Method, apparatus and system for a stackable ethernet switch

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention generally relates to the field of data switching. In particular, the present invention relates to implementing switch stacking capability for a switch device, and methods for stacking said switch device with one or more other switch devices.

00032. Background Art

0004Currently there exists various switch devices (including certain Ethernet switches) which can interconnect the full input/ouput (I/O) bandwidth of a plurality of front panel ports simultaneously. More particularly, a set of ports of such a switching device can be switchably interconnected such that any data traffic (e.g. data packets) received in one port in the set of ports can be switched to any other port in the set of ports as long as the input bandwidth of the set of ports is not exceeded—i.e. without blocking the switching of any incoming data traffic of the set of ports. This behavior is termed non-blocking switching.

0005Stacking switches to create a larger aggregate non-blocking switch is currently achieved, for example, by connecting switches with Ethernet cables and dedicating some of the front panel ports solely for the purpose of switch stacking. For example, <figref idref="DRAWINGS">FIG. 1</figref> illustrates a switch system <b>100</b> including a standalone switch device <b>110</b> stacked with a standalone switch device <b>115</b>. Switch device <b>110</b> includes a plurality of ports <b>120</b><i>a</i>-<b>120</b><i>h </i>to exchange switched data. Similarly, switch device <b>115</b> includes a plurality of ports <b>125</b><i>a</i>-<b>125</b><i>h </i>to exchange switched data. On their own, each of switch devices <b>110</b>, <b>115</b> may support internal non-blocking switching among at least some of their respective sets of ports, e.g. among ports <b>120</b><i>a</i>-<b>120</b><i>h </i>and/or among ports <b>125</b><i>a</i>-<b>125</b><i>h</i>. For example, the respective data switching within switch devices <b>110</b>, <b>115</b> may be via switch chips <b>130</b>, <b>135</b>.

0006According to current practice, standalone switch devices <b>110</b>, <b>115</b> may be stacked, for example, by connecting stacking ports <b>150</b><i>a</i>, <b>150</b><i>b </i>of switch device <b>110</b>, respectively, to stacking ports <b>155</b><i>a</i>, <b>155</b><i>b </i>of switch device <b>115</b>. Configurable switch components such as switch chips <b>130</b>, <b>135</b> may then be configured—e.g. by switch controllers <b>140</b>, <b>145</b>, respectively—to interconnect at least some ports from each of switch devices <b>110</b>, <b>115</b>. However, configuration in order to stack switch devices <b>110</b>, <b>115</b> merely redirects switching bandwidth of switch chips <b>130</b>, <b>135</b> from supporting respective front panel ports (e.g. ports <b>120</b><i>g</i>, <b>120</b><i>h </i>and ports <b>125</b><i>g</i>, <b>125</b><i>h</i>) to supporting respective stacking ports (e.g. stacking ports <b>150</b><i>a</i>, <b>150</b><i>b </i>and stacking ports <b>155</b><i>a</i>, <b>155</b><i>b</i>). The total I/O bandwidth to be directed away from the front ports of stacked switch devices <b>110</b>, <b>115</b> grows with the total number of aggregated ports in stacked switches <b>110</b>, <b>115</b> for which non-blocking switching is to be implemented. This type of stacking is inefficient in that it “burns up” front panel ports in order to support non-blocking switching for fewer remaining front panel ports. This type of stacking both consumes front panel port capacity and uses an excessive number of stacking cables as more stacking connections need to be established to support non-blocking switching for larger aggregations of switch devices at increasingly high bandwidth. The performance and resource costs associated with this type of switch stacking limits the ability to implement non-blocking switching for stacked switches using switches such as switch devices <b>110</b>, <b>115</b>.

BRIEF DESCRIPTION OF THE DRAWINGS

0007The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

0008<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a stacked switch configuration according to existing stacked switch systems.

0009<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating select elements of a switch device according to an embodiment.

0010<figref idref="DRAWINGS">FIG. 3A</figref> is a block diagram illustrating select elements of a plug-in stacking module according to an embodiment.

0011<figref idref="DRAWINGS">FIG. 3B</figref> is a block diagram illustrating select elements of a plug-in stacking module according to an embodiment.

0012<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram illustrating select elements of a switch system according to an embodiment.

0013<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram illustrating select elements of a switch system according to an embodiment.

0014<figref idref="DRAWINGS">FIG. 6</figref> is a flow diagram illustrating an algorithm for implementing switch stacking capability according to an embodiment.

0015<figref idref="DRAWINGS">FIG. 7</figref> is a flow diagram illustrating an algorithm implementing switch stacking capability according to an embodiment.

0016<figref idref="DRAWINGS">FIG. 8</figref> is a diagram illustrating a stacked switch system according to an embodiment.

0017<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram illustrating a switch system according to an embodiment.

DETAILED DESCRIPTION

0018Certain embodiments discussed herein are generally directed to implementing a switch stacking capability for a switch device with a plug-in stacking module (“PISM”) for such a switch device. According to various embodiments, such a switch device may be a standalone switch—e.g. a device which can independently provide switching functionality via its own component switch means. Such switching functionality may include Ethernet switching—e.g. switching which is based on or otherwise compatible with the Institute of Electrical and Electronics Engineers (IEEE) 802.3ae standard (adopted June 2002). According to an embodiment, a switch device may independently support non-blocking switching of data among at least some set of ports of said switch device which are switchably interconnected within said switch device. As used herein, “switchably interconnected” is understood to refer to a characteristic of a set of switch ports—including but not limited to switch ports of multiple switch devices—wherein data received at any one port in the set of ports can be switched to any other port in the set of ports.

0019In an embodiment, a switch device may be coupled to and operate in combination with a PISM to increase a total number of ports in a set of ports for which non-blocking switching is supported (“set of non-blocked ports”) by the switch device. For example, the total number of ports may be increased by adding one or more other ports of the same switch device to the set of ports for which non-blocking switching is supported by the switch device. Alternatively or in addition, the total number of ports may be increased by adding one or more ports of another switch device to the set of ports for which non-blocking switching is supported by the first switch device. This other switch device may, for example, be a standalone switch which is stacked with the first switch device, e.g. wherein each of the stacked switch devices operate to contribute to supporting the non-blocking switching of data among the set of ports which spans the two stacked switch devices.

0020To operate in combination with a PISM as described above, the switch device may, in various embodiments, change a switching configuration of one or more configurable switch components, e.g. to increase a total number of ports in a set of ports for which non-blocking switching is supported. For example, the switch device may include its own internal communications, processing and/or data storage capabilities whereby the switch device changes one or more switching configurations in response to a condition detected by the switch device. As discussed herein, the changing of a switching configuration by the switch device may include changing one or more of (1) a configuration of the switch device itself, and (2) a configuration of the PISM connected to the switch device. According to various embodiments, the switch device may change a switching configuration so that data to be switched from one port of the switch device to another port of the same switch device is switched via the PISM—e.g. in lieu of said switching taking place within the switch device itself. Alternatively or in addition, a switching configuration may be changed to facilitate a combined operation of the switch device and the PISM in a non-stacking configuration—i.e. wherein the switch device is switching data to itself via the PISM even though the switch device is not availing of a capability of the PISM to support stacking of the switch device with any other switch device.

0021<figref idref="DRAWINGS">FIG. 2</figref> illustrates some elements of a switch device <b>200</b> to implement non-blocking switch stacking capability according to various embodiments. Switch device <b>200</b> may include additional elements which are not shown in order to avoid obscuring certain features of various embodiments. Switch device <b>200</b> may include a plurality of ports <b>210</b><i>a</i>-<b>210</b><i>h </i>to exchange switched data. The plurality of ports <b>210</b><i>a</i>-<b>210</b><i>h </i>may include, for example, RJ45 connectors to provide connections for 10 Gigabits per second (Gb/s) Attachment Unit Interface (XAUI) inputs. Although eight ports <b>210</b><i>a</i>-<b>210</b><i>h </i>are shown for illustrative purposes, features discussed herein may be extended to apply either to greater or fewer ports in a plurality of ports of a switch device.

0022The plurality of ports <b>210</b><i>a</i>-<b>210</b><i>h </i>may provide data traffic (e.g. Ethernet data packets) to component switch means within switch device <b>200</b>. By way of illustration and not limitation, the component switch means of switch device <b>200</b> is illustrated at least in part by switch chip <b>220</b> and switch chip <b>230</b>. More particularly, ports <b>210</b><i>a</i>-<b>210</b><i>d </i>may be switchably interconnected by switch chip <b>220</b>, and ports <b>210</b><i>e</i>-<b>210</b><i>h </i>may be switchably interconnected by switch chip <b>230</b>. However, additional and/or alternative switching means may be implemented in various embodiments. In an embodiment, the switch means of switch device <b>200</b> may further support non-blocking switching of data among a set of ports. For example, one or more of switch chips <b>220</b>, <b>230</b> may support non-blocking switching for their respective set of ports <b>210</b><i>a</i>-<b>210</b><i>d </i>and <b>210</b><i>e</i>-<b>210</b><i>h. </i>

0023Certain embodiments of the invention provide one or more channels for exchanging data from the switch means of switch device <b>200</b> to a stacking module interface <b>240</b>, whereby a PISM (not shown) may be coupled to the switch device <b>200</b> to provide switch stacking capability to switch device <b>200</b>. By way of illustration and not limitation, the channels provided from the switching means of switch device <b>200</b> to stacking module interface <b>240</b> are illustrated as data channels <b>222</b>, <b>224</b>, <b>232</b> and <b>234</b>. More particularly, data channels <b>222</b>, <b>224</b> may connect switch device <b>220</b> to stacking module interface <b>240</b>, while data channels <b>232</b>, <b>234</b> may connect switch device <b>230</b> to stacking module interface <b>240</b>. Various embodiments may provide additional or alternative data connections from switching means of a switch device to a stacking module interface. Additionally, switch device <b>200</b> may include a power connection to stacking module interface <b>240</b> (not shown) whereby switch device <b>200</b> provides power required for operation of a PISM.

0024In order to illustrate how switch device <b>200</b> may independently provide non-blocking switching of data among at least some of ports <b>210</b><i>a</i>-<b>210</b><i>h</i>, certain aspects of various embodiments are now discussed with respect to switch chip <b>220</b>. The example of non-blocking switching by switch chip <b>220</b> may be extended to pertain to other additional or alternative switch means of a switch device such as switch chip <b>230</b>, for example. To provide non-blocking switching for ports <b>210</b><i>a</i>-<b>210</b><i>d</i>, switch chip <b>220</b> may have a switching bandwidth which at least equals the total I/O bandwidth of all ports <b>210</b><i>a</i>-<b>210</b><i>d</i>. By way of illustration and not limitation, if each of ports <b>210</b><i>a</i>-<b>210</b><i>d </i>supports a 10 Gb/s XAUI connection to switch chip <b>220</b>, switch ship <b>220</b> may support non-blocking switching of data among the set of ports <b>210</b><i>a</i>-<b>210</b><i>d </i>if a switching bandwidth of switch ship <b>220</b> is not less than 4×10 Gb/s=40 Gb/s. Similarly, if in addition to ports <b>210</b><i>a</i>-<b>210</b><i>d</i>, other ports are added to the set of ports for which switch chip <b>220</b> supports non-blocking switching, such non-blocking switching may be supported if the other added ports are connected to switch chip <b>220</b> via one or more data channels whose total bandwidth is not less than the total I/O bandwidth of ports <b>210</b><i>a</i>-<b>210</b><i>d</i>. By way of illustration and not limitation, if additional ports are to be switchably interconnected with ports <b>210</b><i>a</i>-<b>210</b><i>d </i>via stacking module interface <b>240</b>, non-blocking switching among all of the ports in question may be accommodated if data channels <b>222</b>, <b>224</b> have a total channel bandwidth not less than the total bandwidth of ports <b>210</b><i>a</i>-<b>210</b><i>d. </i>

0025The increasing of a total number of switchably interconnected ports for which non-blocking switching is supported may be implemented, for example, by switch device <b>200</b> changing a switch configuration of one or more configurable switch components—e.g. via a switch controller <b>250</b>. Switch controller <b>250</b> may include any of a variety of processing, data storage, communication and control mechanisms (not all shown) whereby one or more switch configurations may be detected, analyzed and/or changed. For example, switch controller <b>250</b> may receive an indication, e.g. signal <b>260</b> via stacking module <b>240</b>, that additional ports may be added to the set of ports for which non-blocking switching is supported by switch chip <b>220</b>. Besides signal <b>260</b>, other additional or alternative signals may be provided to switch controller <b>250</b>, for example, a signal generated from within switch device <b>200</b> or an explicit input provided by an operator configuring switch device <b>200</b>. In an embodiment, such a received indication may indicate that previously unavailable switching mechanisms have been coupled to switch device <b>200</b>—such as switching mechanisms of a recently connected PISM (not shown). Alternatively or in addition, such a received indication may indicate that a switching condition necessitates a changed configuration to avail of already-available switching mechanisms—e.g. switching mechanisms within switch device <b>200</b> and/or switching mechanisms of a previously detected PISM. Based on the one or more received indications, switch controller <b>250</b> may implement a change in a switching configuration—e.g. via a configuration module <b>270</b>. Depending on the particular change in switch configuration which is to be implemented, control module <b>270</b> may variously provide one or more configuration messages <b>275</b> to one or more of switch chip <b>220</b>, switch chip <b>230</b>, stacking module interface <b>240</b> or various other switch components of switch device <b>200</b> not shown.

0026The particular mechanisms and protocols whereby switch controller <b>250</b> may variously receive switching configuration information and/or send switching configuration instructions are not described in detail herein so as to avoid obscuring features of certain embodiments. It is appreciated that commonly used switch communication and control methods and mechanisms may be adapted to the various embodiments discussed herein. For example, in order for data traffic to be forwarded automatically to the correct switch device, various component switching hardware such as switch chips <b>220</b>, <b>230</b> may need to recognize, and/or make themselves recognizable to, various switching means such as those of a PISM—e.g. based on assigned IDs of the various chips. In an embodiment, a crossbar switch chip of a PISM (not shown) may need to be initialized and configured when connected to switch device <b>200</b> so that the crossbar switch chip “knows” which of switch chips <b>220</b>, <b>230</b> is connected to a particular port of the crossbar switch chip. The particular means by which crossbar switches may be configured to learn switch chip ID information of switch device <b>200</b> is widely varying—e.g. based on chip set manufacturer specification.

0027According to an embodiment of the invention, a switch device having a configuration otherwise similar to that of switch device <b>200</b> may include a total of <b>24</b> ports that provide a set of 12 10 Gb/s XAUI channels to each of two switch chips. Each of the two switch chips, which may correspond functionally to switch chips <b>220</b>, <b>230</b>, may include a 128 Gb/s switching capacity to accommodate full non-blocking switching for the 120 Gs/s I/O bandwidth of their respective 12 10 Gb/s XAUI channels. Furthermore, each of the two switch chips may be connected to a stacking module interface via respective pairs of 64 Gb/s capacity channels functionally corresponding to either pair of channels <b>222</b>, <b>224</b> or <b>232</b>, <b>234</b>. In one embodiment, each of the these 64 Gb/s capacity channels may include 4 lanes of 16 Gb/s channels.

0028<figref idref="DRAWINGS">FIG. 3A</figref> illustrates select features of a PISM <b>300</b> for implementing switch stacking capability according to various embodiments. PISM <b>300</b> may include switching means (e.g. crossbar switch means) to provide a switch stacking capability—for example, when connected to a switch device (not shown) such as switch device <b>200</b>. In an embodiment, the switching means of PISM <b>300</b> may all be integrated on a single circuit board, for example. Alternatively or in addition, the PISM <b>300</b> may include switching means to provide switching functionality conforming to an Ethernet protocol such as IEEE 802.3ae. By way of illustration and not limitation, switching means of PISM <b>300</b> are illustrated at least in part by crossbar switch chip <b>320</b> and crossbar switch chip <b>330</b>. However, features of certain embodiments may be extended to apply to additional or alternative switching means of a PISM such as PISM <b>300</b>.

0029PISM <b>300</b> may include a switch interface connector <b>310</b>, for example, to connect PISM <b>300</b> to a switch device interface (not shown) such as stacking module interface <b>240</b>. PISM <b>300</b> may also include channels such as data channels <b>310</b><i>a</i>-<b>310</b><i>d </i>to connect switch interface connector <b>310</b> to the crossbar switch means of PISM <b>300</b>. In an embodiment, <b>310</b><i>a </i>and <b>310</b><i>d </i>may connect, respectively, to crossbar switch chip <b>320</b> and crossbar switch chip <b>330</b>, and channels <b>310</b><i>b </i>and <b>310</b><i>c </i>may connect, respectively, to crossbar switch chip <b>320</b> and crossbar switch chip <b>330</b>. Crossbar switch chip <b>320</b> may switchably interconnect channels <b>310</b><i>a</i>, <b>310</b><i>b</i>, <b>320</b><i>a </i>and <b>320</b><i>b</i>, while crossbar switch chip <b>330</b> may switchably interconnect channels <b>310</b><i>c</i>, <b>130</b><i>d</i>, <b>320</b><i>c </i>and <b>320</b><i>d</i>. Channels <b>320</b><i>a</i>, <b>320</b><i>b </i>may connect crossbar switch chip <b>320</b>, respectively, to stacking ports <b>340</b><i>a</i>, <b>340</b><i>b </i>of stacking interface <b>340</b>, while channels <b>320</b><i>c</i>, <b>320</b><i>d </i>may connect crossbar switch chip <b>330</b>, respectively, to stacking ports <b>340</b><i>c</i>, <b>340</b><i>d </i>of stacking interface <b>340</b>.

0030In an embodiment, PISM <b>300</b> may be coupled to, and operate in combination with, a switch device (not shown) to enable such a switch device to increase a total number of ports in a set of ports for which the switch device supports non-blocking switching. For example, based on the particular configuration of a stacked switching system in which PISM <b>300</b> is employed, PISM <b>300</b> may provide said switch device with a capability to be stacked with one or more other switch devices as an aggregate non-blocking switch device—e.g. using one or more of stacking ports <b>340</b><i>a</i>-<b>340</b><i>d</i>. The total number of non-blocked ports may be increased by extending the support for non-blocking switching to include at least one of (1) one or more additional ports on the same switch device, and (2) one or more ports on one or more other switch devices with which the switch device is to be stacked via PISM <b>300</b>. In an embodiment, PISM <b>300</b> may support such non-blocking switching by providing sufficient I/O bandwidth throughout crossbar switch chips <b>320</b>, <b>330</b>, channels <b>310</b><i>a</i>-<b>310</b><i>d </i>and channels <b>320</b><i>a</i>-<b>320</b><i>d</i>. As indicated above with reference to switch device <b>200</b>, the sufficiency of I/O bandwidth across switch interface connector <b>310</b> may be determined by the total I/O bandwidth of the ports for which non-blocking switching is supported. Similarly, this total I/O bandwidth may have to be supported in various embodiments by sufficient bandwidth in crossbar switch chips <b>320</b>, <b>330</b>, in channels <b>310</b><i>a</i>-<b>310</b><i>d </i>and in channels <b>320</b><i>a</i>-<b>320</b><i>d. </i>

0031In addition, the operation of PISM <b>300</b> may include one or more of control signals <b>315</b><i>a</i>-<b>315</b><i>c </i>to exchange switching configuration information—e.g. between component switch elements of PISM <b>300</b> and/or via switch interface connector <b>310</b>. Such switching configuration information may include, for example, a configuration command provided from a switch controller such as switch controller <b>250</b> and/or from an explicit configuration instruction of a user/administrator. Alternatively or in addition, such switching configuration information may include configuration information generated within PISM <b>300</b> itself. In various embodiments, PISM <b>300</b> may include various mechanisms whereby PISM <b>300</b> directly controls certain aspects of its own configuration and operation. PISM <b>300</b> may be able to provide an indication of a switching capability such as a switch stacking capability which may be provided to a switch device (not shown) via switch interface connector <b>310</b>. For example, PISM <b>300</b> may include data storage such as an electrically erasable programmable read-only memory or EEPROM (not shown) to store data identifying PISM <b>300</b> or otherwise indicating such switching capability. Additionally or alternatively, PISM <b>300</b> may include processing, data storage, communications and/or control mechanisms (not shown) variously capable of determining, storing, updating and/or providing data indicating a current configuration of PISM <b>300</b>. Additionally or alternatively, similar mechanisms of a switch controller <b>250</b> may generate switch configuration signals to directly configure switch means of PISM <b>300</b> such as one or more of crossbar switch chips <b>320</b>, <b>330</b>.

0032In an embodiment of the invention, a PISM of configuration otherwise similar to that of PISM <b>300</b> may include two pairs of 64 Gb/s capacity channels functionally corresponding to respective pair of channels <b>310</b><i>a</i>, <b>310</b><i>b </i>of <b>310</b><i>c</i>, <b>310</b><i>d</i>. Such 64 Gb/s capacity channels may partially cross connect a switch interface connector to two crossbar switch chips of the PISM, as in the configuration shown with respect to crossbar switch chips <b>320</b>, <b>330</b>. Each of the switch chips may include a 128 Gb/s switching bandwidth in order to support non-blocking switching for the full bandwidth of the pairs of channels to which the switch chips are connected. Furthermore the two 128 Gb/s may be connected to respective pairs of stacking port corresponding functionally to pairs of stacking ports <b>340</b><i>a</i>, <b>340</b><i>b </i>and <b>340</b><i>c</i>, <b>340</b><i>d. </i>

0033<figref idref="DRAWINGS">FIG. 3B</figref> illustrates select features of a PISM <b>350</b> according to various embodiments. PISM <b>350</b> is an example of a stacking module which may be connected to and operate in combination with a switch device for which only limited, if any, non-blocking switching is intended. Accordingly, PISM <b>350</b> may be considered a limited stacking module in comparison to PISM <b>300</b>, for example, insofar as PISM <b>350</b> may provide less switching capacity than that of crossbar switch chips <b>320</b>, <b>330</b>.

0034In an embodiment, PISM <b>350</b> may include a switch interface connector <b>360</b>, for example, to connect to an interface such as stacking module interface <b>240</b>. In one embodiment, PISM <b>350</b> includes channels such as data channels <b>370</b><i>a</i>, <b>370</b><i>b</i>, where switch interface connector <b>360</b> is simply connected to terminal points of data channels <b>370</b><i>a</i>, <b>370</b><i>b</i>. In such an embodiment, PISM <b>350</b> may be is connected to a switch device (not shown) such as switch device <b>240</b>, whereby data channels <b>370</b><i>a</i>, <b>370</b><i>b </i>may provide a new path for one switch means of said switch device to exchange switched data with another switch means of the same switch device. This new path may provide a capacity to interconnect switch means of a switch device which are otherwise not independently available within said switch device. Accordingly, data channels <b>370</b><i>a</i>, <b>370</b><i>b </i>may operate in a larger switching system to support an increase in a total number of ports in a set of ports of a single switch device for which said switch device supports non-blocking switching—e.g. by interconnecting the set of ports of the single switch device to still other ports of the same switch device.

0035Alternatively or in addition, PISM <b>350</b> may include data channels to exchange switched data between switch interface connector <b>360</b> and a stacking interface <b>380</b> of PISM <b>350</b>. More particularly, stacking module <b>380</b> may include one or more stacking ports such as ports <b>380</b><i>a</i>, <b>380</b><i>b </i>to allow for limited switch stacking according to the prior art methods discussed with reference to <figref idref="DRAWINGS">FIG. 1</figref>. Despite the resource cost and inefficiencies of this type of switch stacking, PISM <b>350</b> may provide switch devices with backward compatibility for switch stacking with older switch device types.

0036<figref idref="DRAWINGS">FIG. 4</figref> illustrates select features of a switch system <b>400</b> according to various embodiments. Switch system <b>400</b> may include a switch device <b>405</b> and a PISM <b>440</b>. In an embodiment, switch device <b>405</b> may include any of a variety of features discussed herein with reference to switch device <b>200</b>. Alternatively or in addition, PISM <b>440</b> may include any of a variety of features discussed herein with reference to PISM <b>300</b>. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the front panel of switch device <b>405</b> may incorporate four ports <b>410</b><i>a</i>-<b>410</b><i>d </i>switchably interconnected by a switch chip <b>420</b>, and four ports <b>410</b><i>e</i>-<b>410</b><i>h </i>switchably interconnected by a switch chip <b>430</b>. It is understood that the particular number and/or arrangement of ports <b>410</b><i>a</i>-<b>410</b><i>h </i>and switch chips <b>420</b>, <b>430</b> are not limiting on aspects of the invention, which may be extended to apply to fewer or greater pluralities of front panel ports configured with any of a variety of additional or alternative switch means in switch device <b>405</b>. Switch device <b>405</b> demonstrates an additional feature according to certain embodiments wherein one or more front panel ports (e.g. ports <b>410</b><i>g</i>, <b>410</b><i>h</i>) may optionally be switched back to stacking module interface <b>435</b>—e.g. via channels <b>436</b><i>a</i>, <b>436</b><i>b</i>. The switching of front panel ports to stacking module interface <b>435</b> enables switch device <b>405</b> to be configured for backward compatible switch stacking, as is shown herein in the discussion of <figref idref="DRAWINGS">FIG. 5</figref>.

0037In an illustrative embodiment, ports <b>410</b><i>a</i>-<b>410</b><i>h </i>may include Ethernet ports each with a bandwidth of 10 Gb/s. Each of switch chips <b>420</b> and <b>430</b> connects to and switchably interconnects, respectively, ports <b>410</b><i>a</i>-<b>410</b><i>d </i>and ports <b>410</b><i>e</i>-<b>410</b><i>h</i>. In order to support full non-blocking switching among their respective sets of front panel ports, each of switch chips <b>420</b>, <b>430</b> may have an internal switching bandwidth no less than the total I/O bandwidth of their respective sets of ports—e.g. 4×10 Gb/s=40 Gb/s. Therefore, switch chip <b>420</b> may have a switching bandwidth of 40 Gb/s of Ethernet packet traffic and will route any Ethernet Layer 3 or Layer 2 packet from any port on switch chip <b>420</b> to any other port on switch chip <b>420</b>—e.g. based on standard Ethernet routing rules (e.g. MAC address or IP address based).

0038Data channels <b>422</b>, <b>424</b> may connect switch chip <b>420</b> to stacking module interface <b>435</b>, and data channels <b>432</b>, <b>434</b> may connect switch chip <b>430</b> to stacking module interface <b>435</b>. PISM <b>440</b> is connected to stacking module interface <b>435</b> to provide a stacking capability to switch device <b>400</b>. In an embodiment, switch device <b>405</b> may avail of switch stacking via one or more of crossbar switch chips <b>442</b>, <b>444</b> of PISM <b>440</b> and their respective stacking ports <b>446</b><i>a</i>, <b>446</b><i>b </i>and stacking ports <b>446</b><i>c</i>, <b>446</b><i>d</i>. In order to avail of the switch stacking capacity of PISM <b>440</b>, switch device <b>405</b> may change switching configurations—e.g. via switch controller <b>460</b>. Switch controller <b>460</b> may receive an indication <b>470</b> of a switch capability of PISM <b>440</b> such as a switch stacking capability. Based on the particular switching configurations to be changed on either or both of switch device <b>405</b> and PISM <b>440</b>, a configuration module <b>480</b> of switch controller <b>460</b> may selectively transmit configuration messages to switch components of switch system <b>400</b>.

0039Switch system <b>400</b> may be configured so that PISM <b>440</b> only switches for switch device <b>405</b>. More particularly, crossbar switch chips <b>442</b> and <b>444</b> may only return to switch device <b>405</b> data received at PISM <b>440</b> from switch device <b>405</b>. In such a configuration, the switch device is merely capable of being stacked, and is not actually stacked, with another switch device. Alternatively or in addition, switch system <b>400</b> may be connected to one or more other switch devices (not shown) via stacking ports <b>446</b><i>a</i>-<b>446</b><i>d</i>. Stacking ports <b>446</b><i>a</i>-<b>446</b><i>d </i>may provide for switch stacking using fewer, high capacity stacking connectors than those used for previous stack switching methods.

0040<figref idref="DRAWINGS">FIG. 5</figref> illustrates select features of a switch system <b>500</b> according to various embodiments. Switch system <b>500</b> may include a switch device <b>505</b> and a PISM <b>540</b>. In an embodiment, switch device <b>505</b> may include any of a variety of features discussed herein with reference to switch device <b>200</b>. Alternatively or in addition, PISM <b>540</b> may include any of a variety of features discussed herein with reference to PISM <b>300</b>. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the front panel of switch device <b>505</b> may incorporate four ports <b>510</b><i>a</i>-<b>510</b><i>d </i>switchably interconnected by a switch chip <b>520</b>, and four ports <b>510</b><i>e</i>-<b>510</b><i>h </i>switchably interconnected by a switch chip <b>530</b>. It is understood that the particular number and/or arrangement of ports <b>510</b><i>a</i>-<b>510</b><i>h </i>and switch chips <b>520</b>, <b>530</b> are not limiting on aspects of the invention, which may be extended to apply to fewer or greater pluralities of front panel ports in various additional or alternative configurations of switch means in switch device <b>505</b>. Switch device <b>505</b> demonstrates an additional feature according to certain embodiments wherein one or more front panel ports (e.g. ports <b>510</b><i>g</i>, <b>510</b><i>h</i>) may optionally be switched back to stacking module interface <b>535</b>—e.g. via channels <b>536</b><i>a</i>, <b>536</b><i>b</i>. The switching of front panel ports to stacking module interface <b>535</b> enables switch device <b>505</b> to be configured for backward compatible switch stacking.

0041In an illustrative embodiment, ports <b>510</b><i>a</i>-<b>510</b><i>h </i>may include Ethernet ports each with a bandwidth of 10 Gb/s. Each of switch chips <b>520</b> and <b>530</b> connects to and switchably interconnects, respectively, ports <b>510</b><i>a</i>-<b>510</b><i>d </i>and ports <b>510</b><i>e</i>-<b>510</b><i>h</i>. In order to support full non-blocking switching among their respective sets of front panel ports, each of switch chips <b>520</b>, <b>530</b> may have an internal switching bandwidth no less than the total I/O bandwidth of their respective sets of ports—e.g. 4×10 Gb/s=40 Gb/s. Therefore, switch chip <b>520</b> may have a switching bandwidth of 50 Gb/s of Ethernet packet traffic and will route any Ethernet Layer 3 or Layer 2 packet from any port on switch chip <b>520</b> to any other port on switch chip <b>520</b>—e.g. based on standard Ethernet routing rules (e.g. MAC address or IP address based).

0042Data channels <b>522</b>, <b>524</b> may connect switch chip <b>520</b> to stacking module interface <b>535</b>, and data channels <b>532</b>, <b>534</b> may connect switch chip <b>530</b> to stacking module interface <b>535</b>. PISM <b>540</b> is connected to stacking module interface <b>535</b> to provide a stacking capability to switch device <b>500</b>. In an embodiment, switch device <b>505</b> may avail of switch stacking only via the stacking ports <b>546</b><i>a</i>, <b>546</b><i>b</i>, which may exchange data for backward compatibility channels <b>536</b><i>a</i>, <b>536</b><i>b</i>. Otherwise the switch means of switch device <b>505</b> can only avail of channels <b>524</b>, <b>544</b> of PISM <b>540</b>. According to the configuration shown, channels <b>524</b>, <b>544</b> may provide an additional path for interconnecting switch chip <b>520</b>, <b>530</b>—e.g. to enable non-blocking switching of data between switch chips <b>520</b>. Such a configuration of channels <b>522</b>, <b>524</b>, <b>532</b>, <b>534</b> with respect to stacking module interface <b>535</b> allows PISM <b>540</b> to be replaced with another PISM such as PISM <b>440</b>. This allows users to replace one PISM for another depending on whether a particular ability to stack switches is desired.

0043Since a manufacturer may not know which particular stacking capability may be desired by a user, the routing of data channels from switching means of switch device to stacking module interface <b>535</b> allows a more efficient data channel layout which is incorporated into the PISM <b>540</b> rather than switch device <b>505</b>. This avoids the added cost and complexity of including multiple data channels in switch device <b>505</b>, at least some of which may not be used for a desired switch stacking configuration selected by a user.

0044In order to avail of the switch stacking capacity of PISM <b>540</b>, switch device <b>505</b> may change switching configurations—e.g. via switch controller <b>560</b>. Switch controller <b>560</b> may to receive an indication <b>570</b> of a switch capability of PISM <b>540</b> such as a switch stacking capability. Based on the particular switching configurations to be changed on either or both of switch device <b>505</b> and PISM <b>540</b>, a configuration module <b>580</b> of switch controller <b>560</b> may transmit configuration messages to select switch components of switch system <b>500</b>.

0045Switch system <b>500</b> may be configured so that PISM <b>540</b> only switches data for switch device <b>505</b>. More particularly, channels <b>542</b> and <b>544</b> may only return to switch device <b>505</b> data received at PISM <b>540</b> from switch device <b>505</b>. In such a configuration, the switch device is merely capable of being stacked, and is not actually stacked, with another switch device—e.g. via stacking ports <b>546</b><i>a</i>, <b>546</b><i>b</i>. Alternatively or in addition, switch system may be connected to one or more other switch devices (not shown) via stacking ports <b>546</b><i>a</i>, <b>546</b><i>b</i>, and reconfigured accordingly.

0046<figref idref="DRAWINGS">FIG. 6</figref> illustrates select elements of an algorithm <b>600</b> for a method of implementing switch stacking capability according to an embodiment. Algorithm <b>600</b> may be performed by a switch system such as one or more of switch systems <b>400</b>, <b>500</b>, for example. According to one embodiment, algorithm <b>600</b> may begin at <b>610</b> with a switch device—e.g. switch device <b>200</b>, which includes a stacking module interface to receive a PISM. The switch device may, at <b>620</b>, include a plurality of ports including a set of ports which are switchably interconnected within said switch device. More particularly, said switch device may support non-blocking switching for a set of ports which includes the first set of ports switchably interconnected by said switch device. In various embodiments, there may be one or more other of the ports of the switch device which the switch device itself cannot independently switchably interconnect with any of the first set of ports.

0047According to an embodiment, at <b>630</b>, a PISM such as one of PISMs <b>440</b>, <b>540</b> may be connected to the switch device—e.g. via stacking module interface <b>435</b>. The connected PISM may thereby provide a switch stacking capability to the switch device. It is appreciated that the provided switch stacking capability may be contingent, for example, on changing of one or more switching configurations—e.g. when it is actually determined that the switch is to be stacked with one or more other switching devices. With the PISM connected to the switch device a switching configuration may be changed, at <b>640</b>, to increase a total number of ports in the set of ports for which the switch device supports non-blocking switching. The algorithm <b>600</b> may end at <b>650</b> with a larger total number of switchably interconnected ports for which non-blocking switching is supported.

0048In one embodiment, exchanging data between the switch device and the connected plug-in stacking module according to the changed switching configuration may include the connected plug-in stacking module switching back to the switch device data received at the plug-in stacking module from the switch device. In a more particular embodiment, the connected plug-in stacking module may exchange switched data only with the switch device.

0049<figref idref="DRAWINGS">FIG. 7</figref> illustrates select elements of an algorithm <b>700</b> for a method of implementing switch stacking capability according to an embodiment. Algorithm <b>700</b> may be performed by a switch system such as one or more of switch systems <b>400</b>, <b>500</b>, for example. According to one embodiment, algorithm <b>700</b> may begin at <b>710</b> with a switch device—e.g. switch device <b>200</b>, which includes a stacking module interface to receive a PISM. The switch device may, at <b>720</b>, include a plurality of ports including a set of ports which are switchably interconnected within said switch device. More particularly, said switch device may support non-blocking switching for a set of ports which includes the first set of ports switchably interconnected by said switch device. In various embodiments, there may be one or more other of the ports of the switch device which the switch device itself cannot independently switchably interconnect with any of the first set of ports.

0050According to an embodiment, at <b>730</b>, a PISM such as PISM <b>440</b> may be connected to the switch device—e.g. via stacking module interface <b>435</b>. The connected PISM may thereby provide a switch stacking capability to the switch device. It is appreciated that actual use of the provided switch stacking capability may depend, for example, on changing of one or more switching configurations—e.g. when it is actually determined that the switch is to be stacked with one or more other switching devices. With the PISM connected to the switch device a switching configuration may be changed, at <b>740</b>, to increase a total number of ports in the set of ports for which the switch device supports non-blocking switching.

0051Additionally, at <b>750</b>, another switch device may be connected to the PISM—e.g. for stacking with the switch device which connects to PISM at <b>730</b>. With the two switches connected via the PISM, further switch configuration changes may be made to provide switch stacking. The algorithm <b>700</b> may end at <b>770</b> with a larger total number of switchably interconnected ports for which non-blocking switching is supported, the set of ports spanning a plurality of stacked switches.

0052<figref idref="DRAWINGS">FIG. 8</figref> illustrates select features of a switch system <b>800</b> according to various embodiments. Switch system may include switch devices <b>810</b>, <b>850</b>, which include respective plurality of ports <b>810</b><i>a</i>-<b>810</b><i>n </i>and <b>850</b><i>a</i>-<b>850</b><i>n</i>. One or both of switch devices <b>810</b>, <b>850</b> may include select features described herein with respect to switch device <b>200</b>, for example. Switch devices <b>810</b>, <b>850</b> may be connected, respectively, to PISM <b>820</b> and PISM <b>860</b>. One or both of PISM <b>820</b> and PISM <b>860</b> may include select features described herein with respect to PISM <b>300</b>, for example. In an embodiment, PISM <b>820</b> may include stacking ports <b>820</b><i>a</i>-<b>820</b><i>d</i>, and PISM <b>860</b> may include stacking ports <b>860</b><i>a</i>-<b>860</b><i>d. </i>

0053Switch system <b>800</b> may include stacking cables <b>830</b><i>a</i>, <b>830</b><i>b</i>, <b>830</b><i>c</i>, <b>830</b><i>d </i>to connect stacking ports <b>820</b><i>a</i>, <b>820</b><i>b</i>, <b>820</b><i>c</i>, <b>820</b><i>d</i>, respectively, to stacking ports <b>820</b><i>a</i>, <b>820</b><i>c</i>, <b>820</b><i>b</i>, <b>820</b><i>d</i>. The particular type of cross-connecting of stacking ports <b>820</b><i>a</i>-<b>820</b><i>d </i>to <b>860</b><i>a</i>-<b>860</b><i>c </i>shown in <figref idref="DRAWINGS">FIG. 8</figref> may be consistent with the type of stacking capability provided in switch system <b>400</b>. For example, if switch system <b>400</b> were connected to an identical switch system <b>400</b>—e.g. where stacking ports <b>446</b><i>a</i>-<b>446</b><i>d </i>are connected to corresponding stacking ports of another switch device <b>405</b>/PISM <b>440</b> combination, then the particular cross-connection shown in <figref idref="DRAWINGS">FIG. 8</figref> would provide full non-blocking switching for all front panel ports of both switch devices, provided the hardware of the stacked stitches and the PISMs all support the total I/O bandwidth of all ports.

0054<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram illustrating more particularly select elements of a switch system configuration similar to that of stacked switch system <b>800</b>. Switch system <b>900</b> includes a PISM <b>930</b> connected to a switch device <b>905</b> to provide a switch stacking capability to switch device <b>905</b>. Switch system <b>900</b> also includes a PISM <b>980</b> connected to a switch device <b>955</b> to provide a switch stacking capability to switch device <b>955</b>. One or more of switch devices <b>905</b>, <b>955</b> may include any of a variety of features discussed herein with reference to switch device <b>405</b>, and one or more of PISMs <b>930</b>, <b>980</b> may include any of a variety of features discussed herein with reference to PISM <b>440</b>.

0055Switch device <b>905</b> includes switch chips <b>904</b>, <b>906</b> to provide non-blocking switching for their respective ports <b>902</b>.<b>1</b>-<b>902</b>.<b>8</b> and ports <b>902</b>.<b>9</b>-<b>902</b>.<b>16</b>. Similarly, switch devices <b>955</b> includes switch chips <b>954</b>, <b>956</b> to provide non-blocking switching for their respective ports <b>952</b>.<b>1</b>-<b>952</b>.<b>8</b> and ports <b>952</b>.<b>9</b>-<b>952</b>.<b>16</b>. Switch devices <b>905</b> and <b>955</b> may be stacked via their respective PISMs <b>930</b>, <b>980</b>, wherein stacking modules <b>908</b>, <b>958</b>, switch controllers <b>940</b>, <b>990</b>, and configuration modules <b>945</b>, <b>995</b>, for example, each provide switch device functionality corresponding to that of respective switch device elements discussed with respect to <figref idref="DRAWINGS">FIG. 4</figref>. More particularly, stacking ports <b>936</b><i>a</i>, <b>936</b><i>b</i>, <b>936</b><i>c</i>, <b>936</b><i>d </i>of PISM <b>930</b> may be connected, respectively to stacking ports <b>986</b><i>a</i>, <b>986</b><i>c</i>, <b>986</b><i>b</i>, <b>986</b><i>d </i>of PISM <b>980</b>. This partial cross connection of crossover switch chips <b>932</b>, <b>934</b> with crossover switch chips <b>982</b>, <b>984</b>, which corresponds to the partial cross-connection by stacking ports <b>820</b><i>a</i>-<b>860</b><i>d </i>and <b>860</b><i>a</i>-<b>860</b><i>d</i>, may provide for full non-blocking switching across all ports <b>902</b>.<b>1</b>-<b>902</b>.<b>16</b> and <b>952</b>.<b>1</b>-<b>952</b>.<b>16</b> of switch system <b>900</b>.

0056Techniques and architectures for switching data are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

0057Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

0058Some portions of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

0059It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

0060The present invention also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

0061The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.

0062Besides what is described herein, various modifications may be made to the disclosed embodiments and implementations of the invention without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.