Memory device having wide area phase change element and small electrode contact area

RELATED APPLICATIONS

0001This application is a divisional of co-pending U.S. patent application Ser. No. 11/530,625, filed on 11 Sep. 2006, which application is incorporated by reference as if fully set forth herein.

PARTIES TO A JOINT RESEARCH AGREEMENT

0002International Business Machines Corporation, a New York corporation, Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement

BACKGROUND

00031. Field of the Invention

0004This invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices.

00052. Description of Related Art

0006Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

0007Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

0008The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and by reducing the size of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

0009One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

0010Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure

SUMMARY

0011Generally, the invention features a memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes. In embodiments of a memory cell device of the invention, the top electrode includes a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. The area of electrical contact is defined by the dimensions of the stem of the electrode, near the base, and not by the dimensions of the memory material, which can have a significantly greater area. The dimensions of the stem portion of the top electrode, and of the area of contact of the base of the stem with the memory material can according to the invention be made very small, and are not dependent upon masking technologies.

0012In one general aspect, the invention features a memory cell device including a bottom electrode, a memory material element over the bottom electrode, and a top electrode including a body portion and a stem portion, in which a base of the stem portion of the top electrode is in electrical contact with a small area of a surface of the memory material.

0013In another general aspect the invention features a method for making a memory cell device, by: forming a bottom electrode layer over a surface of a substrate; forming a memory material layer over the bottom electrode layer; forming a cap layer over the memory material layer; patterning the bottom electrode layer, the memory material layer and the cap layer to define a bottom electrode overlain by a memory element overlain by a cap; forming an intermetal dielectric fill layer over the memory material; forming an etch stop layer over the dielectric fill; forming a via through the etch stop layer and the dielectric fill to expose a surface of the cap, the via including an opening in the etch stop layer; removing a quantity of dielectric fill material from walls of the via, forming a cavity and resulting in an undercut beneath the margin of the opening in the etch stop layer; depositing a thermal isolation material in the cavity over the surface of the memory material, whereby a void is formed in the thermal isolation material; anisotropically etching the thermal isolation material and the cap to expose a small area of the surface of the memory material, forming a pore in the thermal isolation material and the cap adjacent the memory element and a wider cavity in the thermal isolation material; and depositing an electrode material in the pore and the wider cavity to form the top electrode.

0014According to the invention, a masking step establishes the openings in the silicon nitride layer over the memory cell vias. The remainder of the process is self-aligning, and highly repeatable. The area of contact between the top electrode and the memory material is determined by width of the stem portion of the top electrode, which in turn is determined by anisotropic etch conditions and by the size and shape of the void in the thermal insulator, which can be readily and repeatably controlled.

BRIEF DESCRIPTION OF THE DRAWINGS

0015<figref idref="DRAWINGS">FIG. 1</figref> is a diagrammatic sketch in a sectional view showing a memory cell device according to an embodiment of the invention.

0016<figref idref="DRAWINGS">FIGS. 2-10</figref> are sketches in a sectional view showing stages in a process for making a phase change memory cell according to an embodiment of the invention.

0017<figref idref="DRAWINGS">FIGS. 11A and 11B</figref> are sketches in a sectional view showing a portion of a memory array according to an embodiment of the invention; <figref idref="DRAWINGS">FIG. 11B</figref> shows a programming current flow.

0018<figref idref="DRAWINGS">FIG. 12</figref> is a schematic diagram for a memory array having phase change memory elements.

0019<figref idref="DRAWINGS">FIG. 13</figref> is a diagrammatic sketch in a layout or plan view showing a part of a memory array having phase change memory elements.

DETAILED DESCRIPTION

0020The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, features corresponding to features shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs.

0021Turning now to <figref idref="DRAWINGS">FIG. 1</figref>, there is shown generally at <b>10</b> a memory cell structure according to an embodiment of the invention. Memory cell structure <b>10</b> includes a bottom electrode <b>12</b> overlain by a memory element <b>14</b>, a top electrode <b>18</b> including a body portion <b>19</b> and a stem portion <b>17</b>. The stem portion <b>17</b> of the top electrode <b>18</b> is in contact with a small area <b>13</b> of the surface <b>15</b> of the memory material layer <b>14</b>. The top electrode may optionally include a core portion <b>21</b> and a liner (heater) portion <b>23</b>. The top electrode <b>18</b> is surrounded by a thermal isolation material <b>16</b>. The top electrode and the surrounding thermal isolation material are formed within a via in an interlayer dielectric fill, or separation layer, <b>11</b>, which is overlain by an electrically insulative layer <b>20</b>.

0022The memory cell structure <b>10</b> is formed over a semiconductor substrate including access transistors, and electrical connection of the surface <b>22</b> of the top electrode <b>18</b> is made by way of patterned metallization, as described for example below with reference to <figref idref="DRAWINGS">FIG. 11A</figref>.

0023The conductive path in the memory cell passes from the surface <b>22</b> of the top electrode <b>18</b> through the top electrode body portion <b>19</b> and the top electrode stem portion <b>17</b> and then into the memory element <b>14</b> at the area of contact <b>13</b> of the base of the stem portion <b>17</b> with the surface of the memory element <b>14</b>, then through the memory element to the bottom electrode <b>12</b>.

0024This memory cell structure according to the invention provides several advantageous features. The top electrode is well isolated thermally from the surrounding dielectric fill. The area of contact of the top electrode with the memory material is small, so that the reset program current can be reduced. The area of contact between the top electrode and the memory material is determined by width of the stem portion of the top electrode, which in turn is determined by anisotropic etch conditions and by the size and shape of the void in the thermal insulator. The size of the void in the thermal insulator is determined by the width of an undercut <b>320</b> at the margin of the opening in the electrically insulative layer, which can be readily and repeatably controlled.

0025Embodiments of memory cell device <b>10</b> include phase change based memory materials, including chalcogenide based materials and other materials, for memory material <b>14</b>. Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

0026Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In the disclosure herein, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory device described herein is Ge₂Sb₂Te₅.

0027With reference again to <figref idref="DRAWINGS">FIG. 1</figref>, access circuitry, such as described with reference to <figref idref="DRAWINGS">FIG. 12</figref>, can be implemented to contact the first electrode <b>12</b> and the second electrode <b>18</b> in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the phase change material <b>14</b> in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state. For example, application of an electrical pulse having a suitable shorter, high amplitude profile, for example, results in changing the phase change material <b>14</b> locally to a generally amorphous state, as indicated at <b>29</b> in <figref idref="DRAWINGS">FIG. 1</figref>.

0028Manufacture of a memory cell device <b>10</b> will be described with reference to <figref idref="DRAWINGS">FIGS. 2-10</figref>, in which various stages in an exemplary process are shown in sectional view.

0029Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a layer <b>212</b> of a material suitable as a bottom electrode is formed over a surface <b>211</b> of a substrate <b>210</b>; a layer <b>214</b> of a phase change memory material is formed over the bottom electrode material layer <b>212</b>; and a layer <b>226</b> of a protective cap material is formed over the layer <b>214</b> of phase change memory material.

0030The bottom electrode material layer <b>212</b> may be formed by a thin film deposition technique such as, for example, sputtering or atomic layer deposition onto surface <b>211</b> of the substrate <b>210</b>. A suitable bottom electrode layer <b>212</b> may include layers of two or more materials, selected for their properties, among others, of adhesion to materials on adjacent layers. The bottom electrode layer <b>212</b> may include, for example, a film of titanium, followed by a film of titanium nitride on the surface of the titanium film. Titanium adheres well to materials in the underlying semiconductor substrate (such as a silicide); and titanium nitride adheres well to the overlying GST phase change material. Additionally, titanium nitride serves as a good diffusion barrier. A wide variety of materials can be used for the bottom electrode, including for example Ta, TaN, TiAlN, TaAlN; or the material of the bottom electrode may include one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru, and alloys thereof; or may include a ceramic. The conditions of the deposition processes are established to provide suitable thickness of, and coverage by, the material(s) of the electrode layer, and to provide good thermal isolation. The bottom electrode at the surface of the substrate may have a thickness in a range about 200 nm to about 400 nm.

0031The layer <b>214</b> of phase change memory material may be formed over the bottom electrode layer <b>212</b> by a thin film deposition technique such as, for example, sputtering or atomic layer deposition. The conditions of the deposition processes are established to provide a suitable thickness of the phase change material layer over the bottom electrode. The phase change material layer at the surface of the bottom electrode over the substrate may have a thickness in a range about 20-200 nm.

0032The protective cap layer <b>226</b> protects the underlying phase change memory material during subsequent processes. Suitable materials for the protective cap layer <b>226</b> include, for example, silicon nitride, SiO₂, Al₂O₃, Ta₂O₅, and the layer may be formed by, for example a CVD or PVD process. The protective cap layer <b>226</b> may have a thickness in the range about 5 nm to about 50 nm. Formation of the bottom electrode layer, the phase change memory material layer, and the protective cap layer results in a structure as shown in <figref idref="DRAWINGS">FIG. 2</figref>

0033Then a mask and etch process is used to define a bottom electrode <b>12</b> overlain by a phase change material element <b>14</b> and a cap <b>326</b> approximately at the site <b>30</b> of the memory cell, resulting in a structure as shown in <figref idref="DRAWINGS">FIG. 3</figref>. The cap <b>326</b>, which has a surface <b>315</b>, protects the phase change material element during the mask and etch process and, particularly, in some embodiments, during removal (stripping) of the photoresist.

0034Then, an interlayer dielectric fill is formed over the surface of the substrate and over the patterned bottom electrode, memory element, and cap, and an etch stop layer is formed over the interlayer dielectric fill. The interlayer dielectric fill may include, for example, a low-K dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, Al₂O₃, or other low K dielectric. Alternatively, the material of the interlayer dielectric fill may include one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. The material of the etch stop layer may include, for example, silicon nitride. Vias are formed through the etch stop layer and the dielectric fill, using a mask and etch process. <figref idref="DRAWINGS">FIG. 4</figref> shows a resulting memory cell via <b>200</b>, formed through the etch stop layer <b>20</b>, and the dielectric fill layer <b>211</b>. The via reaches to the surface <b>315</b> of the cap <b>326</b> over the phase change material element <b>14</b>. Then, a wet etch process, such as, for example, a hydrofluoric acid dip, is applied to undercut the dielectric fill material and to widen the cavity <b>300</b> in the dielectric fill <b>11</b>, as shown in <figref idref="DRAWINGS">FIG. 5</figref>.

0035The dimensions of the completed memory cell will be determined in part by the dimensions of the memory cell via and, particularly, in part by the extent of the undercut, as described with reference particularly to <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, below.

0036The interlayer dielectric fill may have a thickness in a range about 100 nm to about 300 nm, and the silicon nitride layer may have a thickness in a range about 10 nm to about 40 nm. The via <b>200</b> may have a width in a range about 30 nm to about 300 nm. The size of the opening <b>220</b> through the silicon nitride layer is established, within a variation (typically +/− about 20 nm for example), by the design rules for the particular lithographic process used to form the via <b>200</b>. The diameter <b>220</b> of the opening in the silicon nitride layer may be generally circular, for example, with a diameter <b>220</b> about 200 nm +/− about 20 nm, for example. The material of the etch stop layer <b>20</b> is selected to be selectively etched relative to the dielectric fill material; that is, the wet etch process that removes the dielectric material to form the undercut <b>320</b> may have substantially no effect on the etch stop layer <b>20</b>. Where silicon dioxide is the dielectric fill material, for example, silicon nitride provides a suitable material for the etch stop layer. The extent of the undercut can be controlled by timing the wet etch process, within a variation typically +/− about 1.5 nm, for example. The conditions of the wet etch are established to provide an undercut <b>320</b> having a width <b>321</b> in a range about 5 nm to about 50 nm beneath the margin in the opening of the silicon nitride layer, resulting in a width <b>311</b> of the cavity <b>300</b> about the sum of the width <b>220</b> of the opening in the silicon nitride layer plus 2 times the width <b>321</b> of the undercut <b>320</b>.

0037The protective cap layer <b>326</b> may protect the underlying phase change memory element <b>14</b> during the etch process that forms the via <b>200</b>, and during the wet etch process that widens the cavity <b>300</b> in the dielectric fill.

0038Then a suitable thermal isolation material is formed over the structure of <figref idref="DRAWINGS">FIG. 5</figref>, and within the via, using a conformational deposition process such as a chemical vapor deposition (CVD), resulting in a structure as shown <figref idref="DRAWINGS">FIG. 6</figref>. The geometry of the undercut, and the conditions of the deposition process, result in formation of a void <b>610</b> in the thermal isolation material <b>600</b>. The void <b>610</b> is approximately centered within the cavity in the memory cell via. The shape and width <b>613</b> of the void (or diameter, where the void is generally round, for example circular) is related to the width of the undercut <b>320</b>; for example, where the opening <b>220</b> in the etch stop layer <b>20</b> is generally circular, for example, the void can be expected to be generally circular, and can be expected to have a diameter <b>613</b> about two times the width of the undercut <b>321</b>.

0039Suitable thermal isolation materials <b>600</b> include dielectric materials, and may be an oxide, such as a silicon dioxide, for example. Other thermal isolation materials may be preferred, and selection of a thermal oisolation material depends in part on the material of the interlayer dielectric fill; particularly, thermal isolation material <b>600</b> is a better thermal insulator than the interlayer dielectric fill <b>11</b>, preferably at least 10% better. Therefore, when the interlayer dielectric comprises silicon dioxide, the thermal insulator <b>600</b> preferably has a thermal conductivity value “kappa” less than that of silicon dioxide, which is 0.014 J/cm*K*sec. Representative materials for thermal insulator <b>600</b> include low permittivity (low-K) materials, including materials that are a combination of the elements silicon (Si), carbon (C), oxygen (O), fluorine (F), and hydrogen (H). Examples of thermally insulating materials which are candidates for use as thermal insulator <b>600</b> include SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for thermal insulator <b>600</b> include fluorinated SiO₂, silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. A single layer or combination of layers can provide thermal insulation. In other preferred embodiments, the thermal insulator has a thermal conductivity less than that of the amorphous state of the phase change material, that is, less than about 0.003 J/cm*K*sec where the phase change material is a GST.

0040Then an anisotropic etch is performed, such as a reactive ion etch, to remove some of the thermal isolation material. The etch proceeds until an area of the surface of the cap <b>316</b> is exposed, and then proceeds until an area <b>13</b> of the surface <b>15</b> of the phase change element <b>14</b> is exposed. In some embodiments a first etch is performed under conditions that remove the thermal isolation material, and a second etch is performed under conditions that remove a portion of the cap (different etch chemistries may be used, for example). <figref idref="DRAWINGS">FIG. 7</figref> shows a resulting structure. All the thermal isolation material overlying the etch stop layer <b>20</b> has been removed; and some of the thermal isolation material has been removed from the cavity in the memory cell via forming a pore <b>712</b> near the surface of the phase change material, which will define the stem portion of the top electrode; and a wider cavity <b>710</b>, which will define the body portion of the top electrode The undercut <b>320</b> protects the thermal isolation material beneath it, leaving a residual portion <b>720</b> adjacent the wall of the cavity and adjacent the portion of the phase change material next to the wall of the cavity. The etch is stopped when a small area <b>13</b> of the surface of the phase change material is exposed at the bottom of the pore <b>712</b>; a residual portion <b>722</b> remains after the etch is stopped, and this defines the shape and dimensions of the pore <b>712</b>. The dimensions of the stem portion of the top electrode—and, consequently, the area of the contact of the top electrode with the phase change material—are determined in part by the position and the size of the void and by the deposition conformality of the thermal insulator material <b>600</b>. Particularly, the width of the exposed small area <b>13</b> (diameter, if the area is circular, for example) of the phase change material <b>14</b> exposed at the bottom of the pore <b>712</b> results from the shape and width <b>713</b> of the pore <b>712</b>, which in turn results from the shape and size of the void, as well as from the conditions of the etch. As noted above, the width (or diameter) of the void relates to the width of the undercut, and is not dependent upon the width of the via; typically the width of the void is about twice the width of the undercut. The position of the void (and, consequently, the position of the pore <b>712</b>) is approximately at the center of the via and, because the memory material element has a significantly greater area, it is not necessary for the via to be precisely aligned with the memory material element.

0041The exposed small area <b>13</b> need not have any particular shape; it may, for example, be generally round (e.g., circular) or it may have some other shape, or it may have an irregular shape. Where the small area is circular, for example, the small area <b>13</b> may have a diameter in a range about 10 nm to about 100 nm, such as about 20 nm to about 50 nm, for example about 30 nm. Under conditions described herein, these dimensions may be expected where the width of the undercut is in a range about 5 nm to about 50 nm, such as about 10 nm to about 25 nm, for example about 15 nm.

0042Then the top electrode is formed in the memory cell cavity. In embodiments as shown in the FIGs., the top electrode includes a core surrounded by a liner (heater). In such embodiments, the liner is formed by depositing a suitable liner material over the structure of <figref idref="DRAWINGS">FIG. 7</figref>, resulting in a structure as shown in <figref idref="DRAWINGS">FIG. 8</figref>. The liner material fills the pore <b>712</b>, forming the stem portion <b>17</b> of the top electrode; and forms a film <b>723</b> over the other surfaces of the structure. Suitable liner materials include, for example, tantalum nitride, titanium nitride, tungsten nitride, TiW. The conditions of the deposition processes are established to provide suitable thickness of, and coverage by, the material(s) of the electrode layer. Then the core of the top electrode is formed by depositing a suitable electrode material within the cavity and over the structure of <figref idref="DRAWINGS">FIG. 7</figref>, as shown at <b>900</b> in <figref idref="DRAWINGS">FIG. 9</figref>. The core material may be deposited by, for example, chemical vapor deposition (CVD). The top electrode <b>900</b> may be, for example, tungsten. Other suitable top electrode core materials include, for example, other metals such as copper, platinum, ruthenium, iridium, and alloys thereof.

0043A wide variety of materials can be used for the top electrode, including for example Ta, TaN, TiAlN, TaAlN; or the material of the top electrode may include one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru, and alloys thereof; or may include a ceramic.

0044Then a planarizing process is used to remove the upper material, down to the surface <b>922</b> of the silicon nitride layer <b>20</b>, resulting in a completed memory cell structure as shown in <figref idref="DRAWINGS">FIG. 10</figref>.

0045<figref idref="DRAWINGS">FIG. 11A</figref> shows a sectional view of two phase change random access memory cells <b>100</b>, <b>102</b> according to the invention. The cells <b>110</b>, <b>102</b> are formed on a semiconductor substrate <b>110</b>. Isolation structures such as shallow trench isolation (“STI”) dielectric trenches <b>112</b> isolate pairs of rows of memory cell access transistors in the substrate. The access transistors are formed by common source region <b>116</b> in the substrate <b>110</b>, and drain regions <b>115</b> and <b>117</b> in the substrate <b>112</b>. Polysilicon word lines <b>113</b> and <b>114</b> constitute the gates of the access transistors. Common source line <b>119</b> is formed over the source region <b>116</b>. A first dielectric fill layer <b>111</b> is deposited over the polysilicon word lines and the common source line on the substrate <b>110</b>. Contact plugs <b>103</b>, <b>104</b> (e.g., tungsten) are formed in vias in the fill layer <b>111</b> over the drain regions. Memory cells <b>100</b>, <b>102</b> are formed, generally as described above with reference to <figref idref="DRAWINGS">FIGS. 2-10</figref>, and the memory cells <b>101</b>, <b>102</b> are structured generally each like memory cell <b>10</b> as described with reference to <figref idref="DRAWINGS">FIG. 1</figref>: a bottom electrode material layer is deposited over the first dielectric fill layer, a memory material layer is deposited over the bottom electrode material layer, and a protective cap material layer is deposited over the memory material layer; the layers are patterned to form bottom electrode in contact with the contact plug, memory elements over the bottom electrode, and a cap over the memory element; a second dielectric fill layer <b>121</b> is deposited over these structures, an etch stop layer <b>120</b> is deposited over the second dielectric fill layer, and the etch stop layer and second dielectric fill are masked and etched to form vias and then wet etched to form cavities with undercuts beneath the margins of the via openings in the etch stop layer; then the thermal isolation material is deposited in the cavities (forming voids), anisotropic etch is formed through the thermal isolation material and the cap to form a cavity and to expose a small area of the surface of the memory element; the top electrode is formed in the cavity; the upper surface of the structure is planarized, and bit line <b>141</b> is formed over the memory cells, in contact with the upper surfaces of the top electrodes.

0046<figref idref="DRAWINGS">FIG. 11B</figref> shows a programming current path (arrow <b>129</b>) through memory cells according to the invention, as described with reference to <figref idref="DRAWINGS">FIGS. 1 and 11A</figref>. The current flows from the M1 common source line <b>119</b> to the source region <b>116</b>, then to the drain region <b>115</b>, and from the drain region <b>115</b> through the contact plug <b>103</b> to the memory cell <b>100</b> and through the memory cell <b>100</b> to the bit line <b>141</b>.

0047<figref idref="DRAWINGS">FIG. 12</figref> is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration of <figref idref="DRAWINGS">FIG. 2</figref>, a common source line <b>128</b>, a word line <b>123</b> and a word line <b>124</b> are arranged generally parallel in the Y-direction. Bit lines <b>141</b> and <b>142</b> are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block <b>145</b> are coupled to the word lines <b>123</b>, <b>124</b>. An X-decoder and a set of sense amplifiers in block <b>146</b> are coupled to the bit lines <b>141</b> and <b>142</b>. The common source line <b>128</b> is coupled to the source terminals of access transistors <b>150</b>, <b>151</b>, <b>152</b> and <b>153</b>. The gate of access transistor <b>150</b> is coupled to the word line <b>123</b>. The gate of access transistor <b>151</b> is coupled to the word line <b>124</b>. The gate of access transistor <b>152</b> is coupled to the word line <b>123</b>. The gate of access transistor <b>153</b> is coupled to the word line <b>124</b>. The drain of access transistor <b>150</b> is coupled to the bottom electrode member <b>132</b> for memory cell <b>135</b>, which has top electrode member <b>134</b>. The top electrode member <b>134</b> is coupled to the bit line <b>141</b>. Likewise, the drain of access transistor <b>151</b> is coupled to the bottom electrode member <b>133</b> for memory cell <b>136</b>, which has top electrode member <b>137</b>. The top electrode member <b>137</b> is coupled to the bit line <b>141</b>. Access transistors <b>152</b> and <b>153</b> are coupled to corresponding memory cells as well on bit line <b>142</b>. It can be seen that in this illustrative configuration the common source line <b>128</b> is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data.

0048<figref idref="DRAWINGS">FIG. 13</figref> is a layout or plan view of a memory array as shown in the schematic diagram of <figref idref="DRAWINGS">FIG. 12</figref>, showing the structure above the semiconductor substrate layer <b>110</b> of <figref idref="DRAWINGS">FIG. 11A</figref>. Certain of the features are omitted, or are shown as transparent. Word lines <b>123</b>, <b>124</b> are laid out substantially parallel to the source line <b>28</b>. Metal bit lines <b>141</b> and <b>142</b> are laid out over, and substantially perpendicular to, the word lines. The positions of memory cell devices <b>135</b> below the metal bit lines are indicated, although they would not be visible in this view.

0049Embodiments of memory cell device <b>10</b> include phase change based memory materials, including chalcogenide based materials and other materials, for memory material <b>14</b>. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te_aGe_bSb_100−(a+b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, columns 10-11.) Particular alloys evaluated by another researcher include Ge₂Sb₂Te₅, GeSb₂Te₄and GeSb₄Te₇. (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.

0050The invention has been described with reference to phase change materials. However, other memory materials, also sometimes referred to as programmable materials, can also be used. As used in this application, memory materials are those materials having electrical properties, such as resistance, that can be changed by the application of energy; the change can be a stepwise change or a continuous change or a combination thereof. Other programmable resistive memory materials may be used in other embodiments of the invention, including N₂doped GST, Ge_xSb_y, or other material that uses different crystal phase changes to determine resistance; Pr_xCa_yMnO₃, PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene 6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse. Further examples of programmable resistive memory materials include GeSbTe, GeSb, NiO, Nb—SrTiO₃, Ag—GeTe, PrCaMnO, ZnO, Nb₂O₅, Cr—SrTiO₃.

0051For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067, filed 17 Jun. 2005, titled “Thin film fuse phase change RAM and manufacturing method”.

0052Other embodiments are within the scope of the invention.