Computer automated method for manufacturing an integrated circuit pattern layout
Summary by NHIP
Integrated circuit hot spot correction
The method designs layout information by placing marks on pattern contours and merging adjacent discrete areas into isolated groups. It determines candidate hot spots by counting marks within these groups and modifies patterns where the count exceeds a predetermined value before producing masks and forming vias.
Claim Score by NHIP
Abstract
A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.
Term
Term ended
Expired 24 April 2026, 0.4 years ago.
- Priority
- Filed
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- Today
20 claims: 1 independent, 19 dependent
- 1Broadest claimClaim Score 34, narrow(NHIP)A method of manufacturing an integrated circuit comprising:designing layout information including patterns of cells, wires, and vias to be placed on a semiconductor substrate implemented in a graphic image space of a chip area;verifying the layout information in the graphic image space by placing a plurality of marks on each of contours of the patterns, allocating selectively a plurality of discrete areas in a same level with the patterns on the marks taking account of an influence of the optical proximity effect of the patterns, merging adjacent discrete areas overlapping each other into a single polygon so as to define a plurality of isolated groups by the polygon, sorting the marks into the isolated groups so that the adjacent marks are merged in a same group, determining a candidate hot spot by counting a total number of the marks included in each of the isolated groups, extracting a group with the total number of the marks more than a predetermined value, and modifying a corresponding pattern in the candidate hot spot;modifying the layout information by executing a lithography rule check;producing a plurality of masks based on modified layout information;forming an insulating film on the semiconductor substrate;selectively etching a part of the insulating film by using one of the masks;and forming corresponding actual vias and corresponding actual wires, using the modified layout information, connected to the actual vias in the insulating film.
189 paragraphs in 5 sections, as filed
CROSS REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERENCE
This is a division of patent application Ser. No. 11/263,845, filed Oct. 31, 2005, published as US 2006/0123380 A1, now U.S. Pat. No. 7,451,429, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2004-318427, filed on Nov. 1, 2004; the entire contents of all of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit, more specifically to a computer automated method for designing an integrated circuit, a computer automated system for designing an integrated circuit, and an integrated circuit designed by the computer automated method and system.
2. Description of the Related Art
In manufacturing processes of semiconductor integrated circuits, it has become increasingly important to provide measures to counter random defects caused by adhesion of dust because of miniaturization in recent years. In the layout design process of semiconductor integrated circuits, various measures have been implemented. As the measures in the layout design process, (a) insertion of multiple vias and contacts, (b) spreading wires, (c) increasing wire width, (d) designing a fault tolerant circuit, and the like are effective.
On the other hand, the requirements for miniaturization in recent years have made it difficult to form desired patterns on a wafer even using an accurate mask. To improve design fidelity, technologies called optical proximity correction (OPC) and process proximity correction (PPC) are widely used. The OPC and PPC form a mask pattern to form a pattern on a wafer as designed. Hereinafter, the OPC and PPC are generally referred to as OPC.
Verification of the design fidelity is also important as a measure for systematic defects generated due to each process of the manufacturing process. The systematic defects are generated in a lithography process, an etching process. In a case where a half pitch of design patterns is less than 140 nm, some regions are not sufficiently subjected to the OPC process depending on the design patterns even when a predetermined design rule is followed. The correction by the OPC process is therefore not properly performed, and problems with the wafer shape occur, thus increasing problems reducing the yield (hereinafter, referred to as OPC problems). A measure to correct the OPC problems is a check (hereinafter, referred to as lithography rule check) based on a lithography simulation. In the lithography rule check, the lithography simulation is performed for patterns after OPC. The obtained patterns and the respective design patterns are then compared to detect a portion which could be a device problem. Contents of an error are an error type (open, short, and shortening errors and the like), an error level, and the like. The error level is a fatal error with a problem known (hereinafter, referred to as just a fatal error), the OPC problem (gray zone error) which is not fatal but does not have an enough margin for process variation, or the like.
In small-scale cell design, the lithography rule check in design is performed with these cells arbitrarily arranged. Accordingly, the layout can be modified in advance when the layout includes a pattern where the OPC problem could occur.
On the other hand, in chip or macroblock level design, automatic placement and routing tools and the like are widely used. This can implement a layout dominantly composed of wiring patterns extending in one direction. Accordingly, there are a few variations on the wiring patterns, and the probability of occurrence of the OPC problems is not high.
However, when a design for the yield improvement by the random defect measure, a crosstalk measure, and the like fully begin to be carried out in designing chip and macroblock level comparatively large-scale semiconductor integrated circuits, the following problems occur. <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0011">(a) Variations of wire patterns increase, and the probability of occurrence of the OPC problems increases.</li><li id="ul0001-0002" num="0012">(b) Because of the increase in the probability of occurrence of the OPC problems, the lithography rule check becomes necessary. The wire patterns occupy a large area, and the lithography rule check requires a large amount of computer resources and processing time. The verification is therefore difficult to perform for a practical period of time.</li><li id="ul0001-0003" num="0013">(c) In the lithography rule check, many gray zone errors are detected. To improve the yield, measures for the gray zone errors are also important. The gray zone errors are detected more than the fatal errors, and measures thereof are complicated. Accordingly, when many errors are detected, it is more difficult to address all the detected errors for the practical period of time.</li></ul>
SUMMARY OF THE INVENTION
An aspect of the present invention inheres in a computer automated method for designing an integrated circuit encompassing placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.
Another aspect of the present invention inheres in a computer automated system for designing an integrated circuit encompassing a mark module configured to place a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; a grouping module configured to divide the marks into a plurality of groups so that adjacent marks are merged in a same group; a candidate hot spot judgment module configured to judge one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and a modification module configured to modify corresponding pattern in the candidate hot spot.
Still another aspect of the present invention inheres in a method of manufacturing an integrated circuit encompassing designing layout information including patterns of cells, wires, and vias to be placed on a semiconductor substrate implemented in a graphic image space; verifying the layout information by placing a plurality of marks on contours of the patterns, dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group, determining one of the groups as a candidate hot spot according to a total number of marks included in each of the groups, and modifying the layout based on a judged result in the graphic image space; modifying the layout information by executing a lithography rule check; producing a plurality of masks based on modified layout information; forming an insulating film on the semiconductor substrate; selectively etching a part of the insulating film by using one of the masks; and forming corresponding actual vias and corresponding actual wires connected to the actual vias in the insulating film.
BRIEF DESCRIPTION OF DRAWINGS
<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a computer automated system for designing an integrated circuit according to a first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating an OPC verification module according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating a hot spot verification module of <figref idref="DRAWINGS">FIG. 2</figref> according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 4</figref> is a layout example illustrating a method of extracting an OPC hot spot of an OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 5</figref> is a layout example illustrating the method of extracting the OPC hot spot of the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 6</figref> is a layout example illustrating the method of extracting the OPC hot spot of the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 7</figref> is a layout example illustrating the method of extracting the OPC hot spot of the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 8</figref> is a layout example illustrating the method of extracting the OPC hot spot of the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 9</figref> is a layout example illustrating the method of extracting the OPC hot spot of the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 10</figref> is a layout example illustrating a comparative example of the results of the lithography rule check according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 11</figref> is a layout example illustrating a comparative example of the results of the lithography rule check according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 12</figref> is a layout example illustrating the comparative example of the results of the lithography rule check according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 13</figref> is a layout example illustrating the comparative example of the results of the lithography rule check according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 14</figref> is a flowchart illustrating a method of designing an integrated circuit according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 15</figref> is a flowchart illustrating an OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 16A</figref> is a schematic diagram illustrating OPC verification information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 16B</figref> is a schematic diagram illustrating OPC verification information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 16C</figref> is a schematic diagram illustrating OPC verification information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 16D</figref> is a schematic diagram illustrating OPC verification information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 17</figref> is an example of a list of the OPC hot spot judgment information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 18</figref> is an example of geometries of OPC hot spot judgment information used in the OPC verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 19A</figref> is an example of pattern geometry before the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 19B</figref> is an example of pattern geometry after the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 20A</figref> is an example of pattern geometry before the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 20B</figref> is an example of pattern geometry after the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 21A</figref> is an example of pattern geometry before the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 21B</figref> is an example of pattern geometry after the OPC hot spot correction has been executed according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 22</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 23</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 24</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 25</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 26</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 27</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 28</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 29</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 30</figref> is a schematic diagram illustrating layout results of OPC verification according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 31A</figref> is a schematic diagram illustrating detected OPC hot spots when the semiconductor integrated circuit has designed by earlier technique design method;
<figref idref="DRAWINGS">FIG. 31B</figref> is a schematic diagram illustrating detected OPC hot spots when the semiconductor integrated circuit has designed by the computer automated design method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 31C</figref> is a schematic diagram illustrating detected OPC hot spots when the semiconductor integrated circuit has designed by the computer automated design method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 32</figref> is a flowchart illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 33</figref> is a plan view illustrating an example of a mask provided by the method of manufacturing the semiconductor device according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 34</figref> is a plan view illustrating an example of an integrated circuit fabricated by the mask as shown in <figref idref="DRAWINGS">FIG. 33</figref>.
<figref idref="DRAWINGS">FIG. 35</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 36</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 37</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 38</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 39A</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 39B</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 40</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 41</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 42</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 43</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 44</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 45</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 46</figref> is a layout example illustrating the OPC hot spot verification method according to the first embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 47</figref> is a block diagram illustrating a computer automated system for designing an integrated circuit according to a second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 48</figref> is a plan view illustrating layout information designed by a computer automated system for designing an integrated circuit according the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 49</figref> is a layout example illustrating pattern geometries of multiple via cell library according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 50</figref> is a flowchart illustrating a method of designing an integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 51</figref> is a flowchart illustrating the method of designing the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 52</figref> is a layout example illustrating a method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 53</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 54</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 55</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 56</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 57</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 58</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the second embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 59</figref> is a block diagram illustrating an automated design system according to a third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 60A</figref> is a layout example of wire widening information of the computer automated system for designing an integrated circuit according to the third embodiment of the present invention and illustrates a relationship between the distance of wire spaces and correction values;
<figref idref="DRAWINGS">FIG. 60B</figref> is a layout example of wire widening information of the computer automated system for designing an integrated circuit according to the third embodiment of the present invention and illustrates how to measure the wire space;
<figref idref="DRAWINGS">FIG. 61</figref> is a flowchart illustrating a method of designing an integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 62</figref> is a flowchart illustrating a wire spreading method according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 63</figref> is a layout example illustrating a method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 64</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 65</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 66</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 67</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 68</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention;
<figref idref="DRAWINGS">FIG. 69</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention; and
<figref idref="DRAWINGS">FIG. 70</figref> is a layout example illustrating the method of providing multiple vias in the integrated circuit according to the third embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
First Embodiment
—Computer Automated System—
As shown in <figref idref="DRAWINGS">FIG. 1</figref>, a computer automated system for designing an integrated circuit according to the embodiment of the present invention includes an input unit <b>4</b> which inputs information such as data or instructions from an operator, a central processing unit (CPU) <b>1</b>, which executes various arithmetic operations for a layout design and the like, an output unit <b>5</b> which outputs a layout result and the like, a data memory <b>2</b> which stores design information necessary for the layout design of the semiconductor integrated circuit, and a program memory <b>6</b> which stores a layout program of the semiconductor integrated circuit, and the like. The input unit <b>4</b> and the output unit <b>5</b> is connected to the CPU <b>1</b> through an input and output controller <b>3</b>.
The CPU <b>1</b> includes a layout module <b>10</b> to place cells, wires, vias, and the like in a chip area, a verification module <b>20</b> to verify a result of the layout designed by the layout module <b>10</b>, and a layout modification module <b>30</b> to modify the layout based on a result of the verification of the layout. The layout module <b>10</b> includes a floorplan module <b>11</b> to create a floorplan of the semiconductor integrated circuit, a placement module <b>12</b> to place cells in the chip area, and a routing module <b>13</b> to route wires and connect wires with vias and contacts in the chip area.
The verification module <b>20</b> includes a physical verification module <b>21</b>, a timing verification module <b>22</b>, a noise verification module <b>23</b>, a critical area verification module <b>24</b>, and an OPC verification module <b>25</b>. The physical verification module <b>21</b> verifies the layout of each pattern of wires, and vias placed in the chip area using software such as design rule check (DRC) and Layout vs. Schematic (LVS). The timing verification module <b>22</b> verifies timing and crosstalk of cells, power lines, clock lines, signal lines in the chip area. The noise verification module <b>23</b> verifies noise generated from a layout chip, verification regarding power supply, and the like. The critical area verification module <b>24</b> verifies critical areas which are problematic in the manufacturing process, including short, open, and shortening points of wires and vias. The OPC verification module <b>25</b> verifies the OPC problems caused in the layout including wires, vias placed in the chip area.
As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the OPC verification module <b>25</b> includes a candidate hot spot verification module <b>26</b>, an OPC module <b>27</b>, and a lithography check module <b>28</b>. The candidate hot spot verification module <b>26</b> detects to verify an area which could be a candidate for the OPC problem (hereinafter, referred to as a candidate OPC hot spot). The OPC module <b>27</b> processes the OPC for each pattern in the layout. The lithography check module <b>28</b> checks the lithography rule for each pattern in the layout whether or not actual OPC hot spot is generated after the OPC.
As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the candidate hot, spot verification module <b>26</b> includes a mark module <b>261</b>, a grouping module <b>262</b>, a candidate hot spot judgment module <b>263</b>, and a candidate hot spot modification module <b>264</b>. The mark module <b>261</b> places a plurality of marks on contours of closed plane figures forming patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> placed in the chip area as shown in <figref idref="DRAWINGS">FIG. 4</figref>. For example, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the mark module <b>261</b> places marks at vertices of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>. When additional marks placed at positions other than the vertices are necessary for higher accuracy in extracting the candidate OPC hot spots, the mark module <b>261</b> places the additional marks on sides of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> based on additional mark information previously stored in the data memory <b>2</b>.
Examples of the placement of the additional marks are shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>. For example, as shown in <figref idref="DRAWINGS">FIG. 6</figref>, the OPC problems are likely to occur around an inner corner which is formed at an intersection of the patterns <b>51</b><i>a </i>and <b>51</b><i>b</i>. The mark module <b>261</b> then temporarily places a candidate additional mark <b>1</b> at a point of an edge of the pattern <b>51</b><i>a </i>located on an extension of an edge of the pattern <b>51</b><i>b </i>passing through the inner corner and temporarily places a candidate additional mark <b>2</b> at a point of an edge of the pattern <b>51</b><i>b </i>located on an extension of an edge of the pattern <b>51</b><i>a </i>passing through the inner corner.
The mark module <b>261</b> reads additional mark restriction information stored in the data memory <b>2</b> and determines an additional mark finally placed on the patterns <b>51</b><i>a </i>and <b>51</b><i>b </i>out of the candidate additional marks <b>1</b> and <b>2</b>. For example, it is assumed that a condition in the additional mark restriction information is set to “when length between a vertex and the inner corner of a pattern is not less than 400 nm, an additional mark is placed at a point of an edge of the other pattern on an extension of the pattern passing through the inner corner”. Based on the additional mark restriction information, the mark module <b>261</b> determines the additional mark finally placed to be the candidate additional mark <b>2</b> because the length between the vertex of the pattern <b>51</b><i>a </i>and the inner corner is 400 nm. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, the mark module <b>261</b> places the additional mark at a point of an edge on the pattern <b>51</b><i>b </i>located on the extension of the edge of the pattern <b>51</b><i>a </i>passing through the inner corner.
The grouping module <b>262</b> reads area information stored in the data memory <b>2</b> and allocates a plurality of areas <b>201</b>, <b>202</b>, <b>203</b>, <b>204</b>, <b>205</b>, <b>206</b>, <b>207</b>, <b>208</b>, <b>209</b>, <b>210</b>, <b>211</b>, <b>212</b>, and <b>213</b> on the marks given to the individual vertices and additional mark as shown in <figref idref="DRAWINGS">FIG. 8</figref>. Herein, the “areas” <b>201</b>-<b>213</b> are patterns, which are strongly affected by the OPC, and are allocated around the marks and the additional marks placed by the mark module <b>261</b>. As shown in <figref idref="DRAWINGS">FIGS. 8 and 9</figref>, the grouping module <b>262</b> merges overlapping areas <b>201</b>-<b>204</b> into a single polygon <b>220</b> of a group <b>4</b>. The grouping module <b>262</b> also merges the area <b>205</b> to a group <b>1</b>, the area <b>206</b> to a group <b>2</b>, the area <b>207</b> to a group <b>3</b>, overlapping areas <b>208</b>-<b>210</b> to a group <b>5</b>, the area <b>213</b> to a group <b>6</b>, the area <b>212</b> to a group <b>7</b>, and the area <b>211</b> to a group <b>8</b>.
The candidate hot spot judgment module <b>263</b> reads candidate hot spot judgment information stored in the data memory <b>2</b> and judges the candidate OPC hot spot on the patterns included in the layout based on the number of marks included in each group. For example, when the hot spot judgment information is previously set to “a group including seven or more marks is extracted as the candidate OPC hot spot”, the candidate hot spot judgment module <b>263</b> extracts the group <b>4</b> on the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, and <b>52</b> as the candidate OPC hot spot as shown in <figref idref="DRAWINGS">FIG. 9</figref>.
The candidate hot spot modification module <b>264</b> modifies the layout of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, and <b>52</b> based on candidate hot spot modification information stored in the data memory <b>2</b> so that the number of marks in the group judged as the candidate OPC hot spot is reduced. The “modifying the layout so that the number of marks in the group judged as the candidate OPC hot spot” indicates, for example, as shown in <figref idref="DRAWINGS">FIG. 10</figref>, that the candidate hot spot modification module <b>264</b> increases the distance between the patterns <b>51</b><i>a </i>and <b>52</b> for correction such that the marks of the pattern <b>52</b> are not included in the group <b>4</b>.
As shown in <figref idref="DRAWINGS">FIG. 11</figref>, the OPC module <b>27</b> of <figref idref="DRAWINGS">FIG. 2</figref> processes OPC for the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> on the layout. As shown in <figref idref="DRAWINGS">FIG. 12</figref>, the lithography rule check module <b>28</b> of <figref idref="DRAWINGS">FIG. 2</figref> reads lithography rule check information stored in the data memory <b>2</b> and executes the lithography simulation to extract an error mark (an actual OPC hot spot) representing the fatal error, gray zone error, or the like located on the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> as shown in <figref idref="DRAWINGS">FIG. 12</figref>. As shown in <figref idref="DRAWINGS">FIG. 13</figref>, simulation images of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> are thus obtained.
The layout modification module <b>30</b> of <figref idref="DRAWINGS">FIG. 1</figref> extracts the actual OPC hot spot, which is not modified by the OPC verification module <b>25</b> and modifies the layout using software such as mask data preparation (MDP).
The data memory <b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> includes at least a layout memory <b>14</b>, a verification information memory <b>15</b>, a layout modification information memory <b>16</b>, and a design information memory <b>17</b>. The layout memory <b>14</b> stores the information on the floorplan created by the layout module <b>10</b>, the placement information of cells, wires, and vias in the chip area, and the like. The verification information memory <b>15</b> stores various types of information necessary for the verification module <b>20</b> to execute the verification of the layout. The layout modification memory unit <b>16</b> stores layout modification information to modify the layout. The design information memory <b>17</b> stores information necessary for design of the is semiconductor integrated circuit.
The input unit <b>4</b> of <figref idref="DRAWINGS">FIG. 1</figref> includes a keyboard, a mouse, a light pen, a flexible disk unit, and the like. The operator can specify input and output data or set values necessary for automatic design through the input unit <b>4</b>. It is possible to set layout parameters such as a form of output data and to enter instructions to execute and stop operations and the like through the input unit <b>4</b>. The output unit <b>5</b> includes a display, a printer, and the like. The program memory <b>6</b> stores input and output data, the layout parameters, histories thereof, and data during calculation.
—Computer Automated Method—
Using flowcharts shown in <figref idref="DRAWINGS">FIGS. 14 and 15</figref>, a description is given of an example of a method of designing a layout of a semiconductor integrated circuit using the design system shown in <figref idref="DRAWINGS">FIG. 1</figref>.
In step S<b>1</b> of <figref idref="DRAWINGS">FIG. 14</figref>, various types of information necessary for layout design, verification, and modification of the semiconductor integrated circuit are stored in the design information memory <b>17</b> through the input unit <b>4</b> of <figref idref="DRAWINGS">FIG. 1</figref>.
In step S<b>10</b>, layout of the semiconductor integrated circuit is designed. Specifically, in step S<b>11</b>, the floorplan module <b>11</b> reads the design information stored in the design information memory <b>17</b>, creates a floorplan of the semiconductor integrated circuit, and stores information of the floorplan in the layout memory <b>14</b>. In step S<b>12</b>, the placement module <b>12</b> reads the information of the floorplan stored in the layout memory <b>14</b> and places logic cells, macro cells in the chip area. In step S<b>13</b>, the routing module <b>13</b> reads the information of the floorplan stored in the layout memory <b>14</b> and routes wires and connects wires with vias. The placement results of the cells, wires, vias, obtained in the process shown in the steps S<b>12</b> and S<b>13</b> is stored in the layout memory <b>14</b>.
In step S<b>20</b>, various types of verification are performed for the layout designed in the step S<b>10</b>. Specifically, in step S<b>21</b>, the physical verification module <b>21</b> reads the software such as DRC and LVS stored in the verification information memory <b>15</b> and executes the physical verification for each pattern of the obtained layout. In step S<b>22</b>, the timing verification module <b>22</b> reads timing verification information and crosstalk verification information previously stored in the verification information memory <b>15</b> and verifies the timing verification, and crosstalk verification for the laid-out circuit. In step S<b>23</b>, the noise verification module <b>23</b> reads noise verification information and power supply-related verification information previously stored in the verification information memory <b>15</b> and execute noise verification generated from the chip and power supply verification. In step S<b>24</b>, the critical area verification module <b>24</b> reads the critical area information previously stored in the verification information memory <b>15</b> and verifies the portions (critical areas) problematic in the manufacturing process in the layout where the cells, wires, vias, and the like. The result of the verification performed in the process shown in the steps S<b>21</b> to S<b>24</b> is stored in the verification information memory <b>15</b>.
In step S<b>25</b>, the OPC verification module <b>25</b> verifies the OPC problems caused in the layout based on the candidate hot spot verification information, OPC process information, lithography rule check information, and the like. The step S<b>25</b> is described later in detail. The verification information after the OPC verification is stored in the verification information memory <b>15</b>.
In step S<b>30</b>, the layout modification module <b>30</b> reads the layout modification information previously stored in the layout modification memory unit <b>16</b> and judges a transfer image of the layout whether the modification is needed. The layout modification module <b>30</b> reads the layout modification information. When the obtained transfer image includes a pattern problematic in design, the layout modification module <b>30</b> modifies the pattern in the layout and stores the information after the modification in the layout modification memory unit <b>16</b>.
—Detail of OPC Verification Method—
A detailed description is given of the OPC verification method shown in the step S<b>25</b> using the flowchart shown in <figref idref="DRAWINGS">FIG. 15</figref>.
In step S<b>251</b>, various types of information necessary for judgment and modification of the candidate OPC hot spots is inputted through the input unit <b>4</b> of <figref idref="DRAWINGS">FIG. 1</figref> and stored in the verification information memory <b>15</b>. Examples of the information stored in the verification information memory <b>15</b> are: <ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0120">(a) as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the mark information to place the marks on the contours of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>;</li><li id="ul0002-0002" num="0121">(b) as shown in <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, the additional mark information and additional mark restriction information to place the additional mark on the contours of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>;</li><li id="ul0002-0003" num="0122">(c) as shown in <figref idref="DRAWINGS">FIG. 8</figref>, the area information (see <figref idref="DRAWINGS">FIGS. 16A to 16D</figref>) to place the areas on the marks and additional mark taking into account of an influence of the optical proximity effect and the grouping information to divide the areas into a plurality of groups such that adjacent areas are merged;</li><li id="ul0002-0004" num="0123">(d) as shown in <figref idref="DRAWINGS">FIG. 9</figref>, the candidate hot spot judgment information (see <figref idref="DRAWINGS">FIGS. 17 and 18</figref>) to judge the candidate OPC hot spot according to the total number of marks and additional marks included in each group; and</li><li id="ul0002-0005" num="0124">(e) as shown in <figref idref="DRAWINGS">FIG. 10</figref>, the hot spot modification information to modify the candidate OPC hot spot (see <figref idref="DRAWINGS">FIGS. 19A to 21B</figref>). The examples of information shown in <figref idref="DRAWINGS">FIGS. 16A to 21B</figref> are described later in detail.</li></ul>
In step S<b>252</b> of <figref idref="DRAWINGS">FIG. 15</figref>, the mark module <b>261</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> reads the mark information stored in the verification information memory <b>15</b> and, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, places the marks on the vertices of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>. In step S<b>253</b>, when the additional mark is necessary, the mark module <b>261</b> reads the additional mark information stored in the verification information memory <b>15</b> and places the additional marks on the sides of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>. Furthermore, the mark module <b>261</b> reads the additional mark restriction information stored in the verification information memory <b>15</b> and determines the position of the additional mark to be placed on the patterns <b>51</b><i>a </i>and <b>51</b><i>b. </i>
In step S<b>254</b>, the grouping module <b>262</b> of <figref idref="DRAWINGS">FIG. 3</figref> reads the area information stored in the verification information memory <b>15</b> and creates the areas <b>201</b>-<b>213</b> on each of the marks and additional mark. The areas <b>201</b>-<b>213</b> are set to the region strongly affected by the OPC substantially around each of the marks and additional mark placed by the mark module <b>261</b>. The grouping module <b>262</b> divides the areas <b>201</b>-<b>213</b> into the plurality of groups <b>1</b>-<b>8</b> so that overlapping areas <b>201</b>-<b>204</b> are merged in the same polygon <b>220</b> as shown in <figref idref="DRAWINGS">FIGS. 8 and 9</figref>.
In step S<b>255</b>, the candidate hot spot judgment module <b>263</b> reads the candidate hot spot judgment information stored in the verification information memory <b>15</b> and extracts the candidate OPC hot spot as shown in <figref idref="DRAWINGS">FIG. 9</figref>. In step S<b>256</b>, the candidate hot spot judgment module <b>263</b> reads the candidate hot spot modification information stored in the verification information memory <b>15</b> and judges whether the extracted candidate OPC hot spot can be modified based on the candidate hot spot modification information stored in the verification information memory <b>15</b>. When such modification is possible, the procedure proceeds to step S<b>257</b>, and the candidate hot spot modification module <b>264</b> reads the candidate hot spot modification information stored in the verification information memory <b>15</b>. The candidate hot spot modification module <b>264</b> then increases spacing between the patterns <b>51</b><i>a </i>and <b>51</b><i>b </i>and the pattern <b>52</b> to modify the layout such that the number of marks within the group judged as the candidate OPC hot spot is reduced. When such modification is impossible, the procedure proceeds to step S<b>258</b>.
In step S<b>258</b>, the OPC module <b>27</b> of <figref idref="DRAWINGS">FIG. 2</figref> reads the OPC processing information stored in the verification information memory <b>15</b> and, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, executes the OPC process for each of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> on the layout. In step S<b>259</b>, the lithography rule check module <b>28</b> reads the lithography rule check information stored in the verification information memory <b>15</b>. The lithography rule check module <b>28</b> then executes the lithography simulation for a region where the candidate OPC hot spot is not modified to extract errors existing on the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>, including the fatal and gray zone errors, and acquires the simulation images of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>.
With the method of designing the layout of a semiconductor integrated circuit according to the first embodiment, in the OPC verification process shown in the step S<b>25</b> of <figref idref="DRAWINGS">FIG. 14</figref>, the group including more than a specified number of marks out of the marks placed on the contours of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> is extracted as the candidate OPC hot spot. The region extracted as the candidate OPC hot spot is modified based on the candidate hot spot modification information stored in the verification information memory <b>15</b> of <figref idref="DRAWINGS">FIG. 1</figref> by reducing the number of marks included in the group of interest. For example, in the example of the layout shown in <figref idref="DRAWINGS">FIG. 9</figref>, expanding the space between the pattern <b>51</b><i>a </i>and the pattern <b>52</b> eliminates the candidate OPC hot spot as shown in <figref idref="DRAWINGS">FIG. 22</figref>. The lithography rule check is not necessary for the part not including the candidate OPC hot spot. Accordingly, a comparatively large pattern in the chip area does not require a large amount of computer resources and processing time, and the verification can be performed for a practical period of time.
<figref idref="DRAWINGS">FIGS. 24 to 29</figref> show examples of the layout when the candidate OPC hot spots are not modified in the OPC verification process shown in the step S<b>25</b> of <figref idref="DRAWINGS">FIG. 14</figref>. <figref idref="DRAWINGS">FIG. 24</figref> shows a layout example where the marks and additional marks are placed at vertices of patterns <b>59</b><i>a</i>, <b>59</b><i>b</i>, and <b>60</b> by the mark module <b>261</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 25</figref> shows a layout example where the adjacent marks on the patterns <b>59</b><i>a</i>, <b>59</b><i>b</i>, and <b>60</b> are grouped by the grouping module <b>262</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 26</figref> shows a layout example where the candidate OPC hot spot is extracted by the candidate hot spot judgment module <b>263</b>. <figref idref="DRAWINGS">FIG. 27</figref> shows an example where the OPC process is performed without modification of the candidate OPC hot spot.
When the lithography rule check is performed with the candidate hot spots not modified, as shown in <figref idref="DRAWINGS">FIG. 28</figref>, an open hot spot appears at a portion of the pattern <b>60</b> on a longitudinal extension of the pattern <b>59</b><i>b</i>. A simulation image outputted based on the layout example shown in <figref idref="DRAWINGS">FIG. 28</figref> has a shape shown in <figref idref="DRAWINGS">FIG. 29</figref>, which shows that the pattern is narrowed at the open hotspot. As shown in <figref idref="DRAWINGS">FIG. 30</figref>, apparent from the desired pattern shape and a transfer image actually obtained, there is a defect in the pattern <b>60</b>.
On the other hand, with the method of designing a semiconductor integrated circuit shown in the first embodiment, when there is the candidate OPC hot spot which can be modified based on the candidate hot spot modification information, the pattern at the actual OPC hot spot can be modified in advance. The defective pattern shown in <figref idref="DRAWINGS">FIG. 30</figref> can be therefore prevented, thus improving the yield.
Some of the candidate OPC hot spots extracted in the OPC verification shown in <figref idref="DRAWINGS">FIG. 15</figref> are difficult to modify based on the candidate hot spot modification information stored in the verification information memory <b>15</b> of <figref idref="DRAWINGS">FIG. 1</figref>. In each of the spots difficult to modify based on the candidate hot spot modification information, the actual OPC hot spots and regions therearound are selectively extracted by the lithography rule check module <b>28</b>, and the extracted portions are partially subjected to the lithography rule check shown in step S<b>259</b>. The lithography rule check in the step S<b>259</b> only needs to be performed for comparatively small areas including the actual OPC hot spots, which reduces the amount of processed data. Also in the lithography rule check, few gray zone errors are detected, thus allowing verification to be performed for a practical period of time.
<figref idref="DRAWINGS">FIGS. 31A to 31C</figref> show examples of the result of the lithography rule check after the OPC verification. When using an earlier technique design method which does not use the design method according to the first embodiment, as shown in <figref idref="DRAWINGS">FIG. 31A</figref>, a number of actual OPC hot spots appear in the chip area. The example shown in <figref idref="DRAWINGS">FIG. 31A</figref> can be also processed for a short time. However, when using the computer automated method according to the first embodiment, the actual OPC hot spots are previously modified by the processes shown in the steps S<b>251</b> to S<b>258</b>, and, as shown in <figref idref="DRAWINGS">FIG. 31B</figref>, the actual OPC hot spots after the modification are fewer than that shown in <figref idref="DRAWINGS">FIG. 31A</figref>. Accordingly, as shown in <figref idref="DRAWINGS">FIG. 31C</figref>, in the case of carrying out the lithography rule check shown in the step S<b>249</b>, only the remaining OPC hot spots and regions therearound need to be subjected to the verification, and the lithography rule check and check of the OPC hot spots can be performed for a shorter time. It is therefore possible to provide the method of designing a semiconductor integrated circuit which is capable of implementing the measures for random and systematic defects with high speed and high accuracy.
—Examples of Area—
<figref idref="DRAWINGS">FIGS. 16A to 16D</figref> show examples of the area information to add the area taking into account of the optical proximity effect around the mark placed on the layout. Dimensions “a” to “k” of areas <b>61</b> to <b>64</b> vary depending on the action of the OPC process shown in the step S<b>258</b> of <figref idref="DRAWINGS">FIG. 15</figref>. The area information can be therefore determined by properly setting parameters of the dimensions “a” to “k” according to shapes of patterns <b>55</b> and <b>56</b> and positions of the marks. For example, as shown in <figref idref="DRAWINGS">FIG. 16A</figref>, when the marks are located at a line end, the area <b>61</b> is formed so that the dimension “d” of the area <b>61</b> parallel to the longitudinal direction of the pattern <b>55</b> is longer than the dimension “a” and the line end is wider than a dimension “w” of the pattern <b>55</b>. As shown in <figref idref="DRAWINGS">FIG. 16B</figref>, when the mark is located at an outer corner of the pattern <b>56</b>, the area <b>62</b> is formed so that the dimension “f” is longer than the dimension “d”. As shown in <figref idref="DRAWINGS">FIG. 16C</figref>, when the mark is located at the inner corner of the pattern <b>56</b>, the area <b>63</b> is formed so that the dimension “h” is longer than the dimension “g”. As shown in <figref idref="DRAWINGS">FIG. 16D</figref>, when the mark is located on a side of the pattern <b>56</b>, the area <b>64</b> with the dimension “j” longer than the dimension “i” and with a dimension of “2k”.
—Examples of Candidate Hot Spot Judgment Information—
<figref idref="DRAWINGS">FIGS. 17 and 18</figref> show examples of the candidate OPC hot spot judgment information with which the candidate hot spot judgment module <b>263</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> extracts and judges the candidate OPC hot spots on the layout. An example of the candidate hot spot judgment information stored in the verification information memory <b>15</b> of <figref idref="DRAWINGS">FIG. 1</figref> is a numerical list indicating how many marks and additional marks are included in a group extracted as the candidate OPC hot spot. <figref idref="DRAWINGS">FIG. 18</figref> shows examples of a group extracted as the candidate OPC hot spot and a group not extracted as the candidate OPC hot spot based on the numerical list shown in <figref idref="DRAWINGS">FIG. 17</figref>. As shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>), a group <b>81</b><i>a </i>including eight marks on a closed plane <figref idref="DRAWINGS">FIG. 71</figref><i>a </i>matches a condition “for one closed plane figure, the total number of marks is seven or more” shown in <figref idref="DRAWINGS">FIG. 17</figref>. The group <b>81</b><i>a </i>is therefore extracted as the candidate OPC hot spot. As shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>), a group <b>83</b><i>a </i>is placed on two closed plane <figref idref="DRAWINGS">FIGS. 73</figref><i>a </i>and <b>74</b><i>a </i>and includes six marks and one additional mark. In this case, the group <b>83</b><i>a </i>matches a condition “for two closed plane figures, the total number of marks is five or more” shown in the list of <figref idref="DRAWINGS">FIG. 17</figref>. The group <b>83</b><i>a </i>is therefore extracted as the candidate OPC hot spot. As shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>c</i>), a group <b>84</b><i>a </i>is placed on two closed plane <figref idref="DRAWINGS">FIGS. 75</figref><i>a </i>and <b>76</b><i>a </i>and includes two marks and four additional marks. In this case, the group <b>84</b><i>a </i>matches the condition “for two closed plane figures, the total number of marks is five or more” shown in the list of <figref idref="DRAWINGS">FIG. 17</figref>. The group <b>84</b><i>a </i>is therefore extracted as the candidate OPC hot spot.
On the other hand, as shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>d</i>), a group <b>82</b><i>a </i>is placed on a closed plane pattern <b>72</b><i>a </i>and includes four marks and two additional marks. In this case, the group <b>82</b><i>a </i>does not match the condition “for one closed plane figure, the total number of marks is seven or more” shown in the list of <figref idref="DRAWINGS">FIG. 17</figref>. The group <b>82</b><i>a </i>is therefore not extracted as the OPC candidate hot spot. As shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>e</i>), a group <b>85</b><i>a </i>is placed on two closed plane <figref idref="DRAWINGS">FIGS. 77</figref><i>a </i>and <b>78</b><i>a </i>and includes four marks. In this case, the group <b>85</b><i>a </i>does not match the condition “for two closed plane figures, the total number of marks is four and the number of additional marks is two” shown in the list of <figref idref="DRAWINGS">FIG. 17</figref>. The group <b>85</b><i>a </i>is not extracted as the candidate OPC hot spot.
—Examples of Candidate Hot Spot Modification Information—
<figref idref="DRAWINGS">FIGS. 19A to 21B</figref> show examples of the candidate hot spot modification information with which the candidate hot spot modification module <b>264</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> modifies the OPC candidate hot spots on the layout in the step S<b>257</b> of <figref idref="DRAWINGS">FIG. 15</figref>. <figref idref="DRAWINGS">FIGS. 19A</figref>, <b>20</b>A, and <b>21</b>A show patterns before modification, and <figref idref="DRAWINGS">FIGS. 19B</figref>, <b>20</b>B, and <b>21</b>B show patterns after modification.
When the group <b>81</b> includes eight marks as shown in <figref idref="DRAWINGS">FIG. 19A</figref>, a pattern <b>71</b><i>b </i>with extended patterns <b>711</b><i>a </i>and <b>711</b><i>b </i>is formed so that the number of marks included in a group <b>81</b><i>b </i>is reduced as shown in <figref idref="DRAWINGS">FIG. 19B</figref>. When the group <b>83</b><i>a </i>includes six marks and one additional mark as shown in <figref idref="DRAWINGS">FIG. 20A</figref>, a pattern <b>73</b><i>a </i>and a pattern <b>74</b><i>a </i>are separated apart from each other so that the number of marks in the group <b>83</b><i>a </i>is reduced, thus dividing the group <b>83</b><i>a </i>of <figref idref="DRAWINGS">FIG. 20A</figref> into groups <b>83</b><i>b </i>and <b>83</b><i>c </i>as shown in <figref idref="DRAWINGS">FIG. 20B</figref>. When the group <b>84</b><i>a </i>includes two marks and four additional marks as shown in <figref idref="DRAWINGS">FIG. 21A</figref>, as shown in <figref idref="DRAWINGS">FIG. 21B</figref>, a pattern <b>75</b><i>b </i>and a pattern <b>76</b><i>b </i>are separated apart from each other so that the number of marks in the group <b>84</b><i>a </i>is reduced and the additional marks on the pattern <b>76</b><i>b </i>are not included in the group <b>84</b><i>b. </i>
—Method of Manufacturing an Integrated Circuit—
Referring to <figref idref="DRAWINGS">FIG. 32</figref>, a description is given of a method of manufacturing a semiconductor integrated circuit according to the first embodiment. The method of manufacturing a semiconductor integrated circuit according to the first embodiment includes, as shown in <figref idref="DRAWINGS">FIG. 32</figref>, a design process in step S<b>300</b>, a mask manufacturing process in step S<b>400</b>, a semiconductor manufacturing process in step <b>500</b>, and an inspection process in step S<b>600</b>. Products are then conveyed to a shipping process in step S<b>700</b>.
In the step S<b>300</b>, mask data is created based on results of various simulations such as a process simulation. Specifically, in the layout design process of the step S<b>10</b>, the layout information including a plurality of patterns to place cells, wires, vias, and the like in the chip area is created based on the floorplan.
In the layout verification process shown in the step S<b>20</b>, the physical verification, timing verification, crosstalk verification, noise verification, verification regarding power supply, and OPC verification are performed. In the OPC verification, the plurality of marks are placed on contours of patterns included in the layout information and classified into a plurality of groups such that adjacent marks are grouped. Subsequently, candidate hot spots in the patterns are extracted based on the number of marks included in each group. When the candidate hot spots in the patterns can be modified based on the candidate hot spot information stored in the verification information memory <b>15</b>, the layout is modified so that the number of marks included in the group of interest is reduced. In the step S<b>30</b>, transfer images of the patterns included in the layout information are formed. When the transfer images include a pattern problematic in the design process, the layout information is modified.
In the step S<b>400</b>, based on the obtained mask data, a set of masks (reticles) necessary for a substrate process, a wiring process, and the like are manufactured with a predetermined alignment margin by means of a pattern generator such as an electron beam lithography. In the substrate process shown in step S<b>510</b>, a plurality of chip patterns are periodically arranged on a semiconductor wafer by a projection lithography (stepper) using reticles necessary for respective processes (manufacturing process) for microfabrication (substrate process).
Specifically, in step S<b>511</b>, for example, a silicon oxide film is deposited on a silicon substrate. In step S<b>512</b>, a photoresist film is applied to the silicon oxide film. In step S<b>513</b>, a photolithography process is carried out using one of the set of reticles manufactured for the substrate process to delineate the photoresist film. In step S<b>514</b>, the silicon oxide film is selectively etched using the patterned photoresist film as a mask. Using the photoresist film and silicon oxide film as a mask, for example, p+ or n+ impurity ions are selectively implanted into the surface of the silicon substrate. Thereafter, the photoresist used as the mask for the ion implantation is removed. Furthermore, in step S<b>515</b>, the implanted ions are activated and driven (diffused) into a desired depth to form an impurity diffusion region inside the silicon substrate. The various processes shown in the steps S<b>511</b> to S<b>515</b> are carried out serially using reticles in the set of reticles to form transistors and the like of each cell.
In a surface wiring process of step S<b>520</b>, similarly, the substrate surface is subjected to a wiring process by forming a desired pattern with a stepper using a reticle necessary for each process. Specifically, as shown in step S<b>521</b>, for example, an interlayer insulating film is formed on the silicon substrate by means of CVD, PVD, or the like, and the surface thereof is flattened by chemical mechanical polishing (CMP). In step S<b>522</b>, photoresist is applied on an interlayer insulating film, and a photoresist film is patterned by a photolithography process using one of the set of reticles manufactured for the surface wiring process to form an etching mask in step S<b>523</b>. In step S<b>524</b>, using the etching mask, reactive ion etching (RIE) or the like is performed to form vias in the interlayer insulating film. The photoresist is then removed, and the surface is washed. Thereafter, in step S<b>525</b>, metal is deposited in the vias. Another etching mask is then formed by the photolithography process, and the series of processes, including pattering the metallic film, is repeated using the reticles in the set of reticles, thus forming a multi-level interconnect.
When the processes shown in steps S<b>510</b> to S<b>520</b> is completed, in step S<b>530</b>, the wafer is divided into chips of a predetermined chip size by means of dicing equipment such as a diamond blade (dicing process). Each chip is mounted on a packaging material (mount process), and electrode pads of the chip and leads of a lead frame are connected to each other with gold wires or bumps (bonding process). Next, a required package assembly process such as resin sealing is carried out (sealing process).
In step S<b>600</b>, inspections, including a property inspection concerning performances and functions of a semiconductor device, inspection of lead shape and size, and a reliability test, are carried out (inspection process), thus completing the semiconductor device. In step S<b>700</b>, a semiconductor device which has cleared all the above processes is put into a package for protection from moisture, static electricity and the like and then shipped as a product.
With the method of manufacturing a semiconductor integrated circuit according to the first embodiment, regions which could be the actual OPC hot spots (candidate hot spots) are previously extracted and corrected by adding marks to each pattern, grouping adjacent marks, and measuring density of the patterns when the OPC verification is performed for the obtained layout in the layout verification process of the step S<b>20</b>. Accordingly, compared with the case where the judgment of the actual OPC hot spots of the transfer patterns is made after all the layout design and verifications are completed, the actual OPC hot spots are fewer, thus reducing the processing time for the verifications and improving the yield.
<figref idref="DRAWINGS">FIG. 33</figref> shows an example of a mask which can be manufactured using the method of manufacturing a semiconductor integrated circuit according to the first embodiment. <figref idref="DRAWINGS">FIG. 33</figref> is an example of a mask <b>90</b> manufactured using the layout shown in <figref idref="DRAWINGS">FIG. 11</figref>. On the mask <b>90</b>, line patterns <b>91</b> to <b>95</b>, each including a rectangular correction portion at line end portions and the like, are placed. On the other hand, <figref idref="DRAWINGS">FIG. 34</figref> shows an example of a plan view when wires <b>101</b> to <b>105</b> are formed on an interlayer insulating film <b>100</b> using the mask <b>90</b> shown in <figref idref="DRAWINGS">FIG. 33</figref>. As shown in <figref idref="DRAWINGS">FIG. 34</figref>, the desired wires <b>101</b> to <b>105</b> are formed on the interlayer insulating film without errors. Among the OPC hot spots, a spot which is not judged as an error in the lithography rule check is also extracted. The extracted spot could be an error when the process condition changes. However, with the method of manufacturing a semiconductor integrated circuit according to the first embodiment, it is possible to make a design robust to changes in the process, thus making it possible to manufacture desired patterns on the interlayer insulating film <b>100</b> with higher yield.
Modification of the First Embodiment
The method of placing the marks on the layout in the steps S<b>251</b> and S<b>252</b> of <figref idref="DRAWINGS">FIG. 15</figref>, which is carried out by the mark module <b>261</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>, is not limited to the aforementioned method and can be other various methods.
For example, a layout shown in <figref idref="DRAWINGS">FIG. 35</figref> is defined by a plurality of rectangular regions by a plurality of grids extending in two directions orthogonal to each other as shown in <figref idref="DRAWINGS">FIG. 36</figref>. The positions of the grids are shifted little by little with respect to the layout to form a plurality of patterns each defined by the grids. Furthermore, as shown in an enlarged view of <figref idref="DRAWINGS">FIGS. 39A and 39B</figref>, marks are given to regions where vertices of a pattern <b>54</b> are located. The marks are added in each pattern shown in <figref idref="DRAWINGS">FIGS. 36 to 38</figref>. <figref idref="DRAWINGS">FIGS. 40 to 42</figref> shows results of <figref idref="DRAWINGS">FIGS. 36 to 38</figref>. Thereafter, as shown in <figref idref="DRAWINGS">FIG. 43</figref>, the layouts shown in <figref idref="DRAWINGS">FIGS. 40 to 42</figref> are superimposed. Regions where the marks overlap each other are merged and grouped by the grouping module <b>262</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>, and a wide region where the marks overlap each other is extracted as the candidate OPC hot spot.
In another method, as shown in <figref idref="DRAWINGS">FIG. 44</figref>, marks to divide sides of patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b> into several sections are placed on end portions of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, <b>53</b>, <b>54</b>, and <b>55</b>, and as shown in <figref idref="DRAWINGS">FIG. 45</figref>, the areas are placed around the individual marks. Thereafter, as shown in <figref idref="DRAWINGS">FIG. 46</figref>, adjacent marks are classified into a group by the grouping module <b>262</b> shown in <figref idref="DRAWINGS">FIG. 3</figref>, and the candidate OPC hot spots can be extracted in the same manner as the aforementioned method.
Second Embodiment
—Computer Automated System—
As shown in <figref idref="DRAWINGS">FIG. 47</figref>, a computer automated system for designing an integrated circuit according to a second embodiment includes a placement module <b>12</b><i>a </i>and a layout memory <b>14</b><i>a</i>. The placement module <b>12</b><i>a </i>includes a high yield cell placement module <b>121</b>, a multiple via replacement module <b>122</b>, and a placement modification module <b>123</b>. The layout memory <b>14</b><i>a </i>includes a high yield cell library <b>1421</b> and a multiple via cell library <b>1422</b>. The other members are substantially the same as those of the computer automated system for designing an integrated circuit as shown in <figref idref="DRAWINGS">FIG. 1</figref>.
The high yield placement module <b>121</b>, as shown in <figref idref="DRAWINGS">FIG. 48</figref>, places high-yield cells (a SRAM module <b>45</b>, a ROM module <b>46</b>, a CPU <b>47</b>, a bus interface <b>48</b>, a DRAM module <b>49</b>, and the like), in which cells, wires, vias and the like have been already placed and verified, in a region surrounded by I/O cells <b>41</b><i>a </i>to <b>41</b><i>n</i>, <b>42</b><i>a </i>to <b>42</b><i>n</i>, <b>43</b><i>a </i>to <b>43</b><i>n</i>, and <b>44</b><i>a </i>to <b>44</b><i>n</i>, which are placed in the periphery of a chip area <b>40</b>. The multiple via replacement module <b>122</b> replaces one via (single via) placed by the placement module <b>12</b> to connect wires with a plurality of vias (multiple vias). The placement modification module <b>123</b> modifies a region where design violation occurs when the multiple via replacement module <b>122</b> replaces the single via to the multiple vias. The high-yield cell library <b>1421</b> stores information on the high-yield cells with various shapes. The multiple via cell library <b>1422</b> stores information on multiple via cells <b>96</b> to <b>99</b> with various shapes as shown in <figref idref="DRAWINGS">FIG. 49</figref>.
—Computer Automated Method—
A description is given of a computer automated method of designing a semiconductor integrated circuit according to the second embodiment using flowcharts of <figref idref="DRAWINGS">FIGS. 50</figref> and <b>51</b>.
In step S<b>1</b> of <figref idref="DRAWINGS">FIG. 50</figref>, various types of information necessary for layout design, verification, and modification of the semiconductor integrated circuit are inputted into the design information memory <b>17</b> and the program memory <b>6</b> of <figref idref="DRAWINGS">FIG. 1</figref> through the input unit <b>4</b>. In step S<b>2</b>, the information on the high yield cells placed in the chip area and the multiple via cell information to connect wires through the multiple vias are inputted into the high-yield cell library <b>1421</b> and the multiple via cell library <b>1422</b> of <figref idref="DRAWINGS">FIG. 47</figref>, respectively.
In step S<b>10</b>, the layout module <b>10</b> reads the design information stored in the design information memory <b>17</b>, the layout information stored in the layout memory <b>14</b>, and the like and places the cells, wires, vias, and the like in the chip area. In step S<b>11</b>, the floorplan module <b>11</b> reads the design information stored in the design information memory <b>17</b> and creates a floorplan of the semiconductor integrated circuit. The floorplan module <b>11</b> stores information on the floorplan in the layout memory <b>14</b>.
In step S<b>121</b>, the placement module <b>12</b> reads the information of the floorplan stored in the layout memory <b>14</b> and places logical cells in the chip area. In step S<b>122</b>, the high-yield cell placement module <b>121</b> reads the information of the floorplan stored in the layout memory <b>14</b> and places the high-yield cells in the chip area. In step S<b>13</b>, the routing module <b>13</b> reads the information of the floorplan stored in the layout memory <b>14</b> and routes wires in the chip area and connect wires with vias and contacts.
In step S<b>14</b>, the multiple via replacement module <b>122</b> reads the information of the multiple via cell library stored in the multiple via cell library <b>1422</b> and replaces multiple vias for a single via which could cause a design problem out of the single vias placed on the layout patterns. The step S<b>14</b> is described later in detail.
In step S<b>20</b>, the layout verification is performed for the layout designed in the step S<b>10</b>. In step S<b>30</b>, the layout modification module <b>30</b> reads the layout modification information stored in the layout modification memory unit <b>16</b> and performs judgment and modification using a transfer image of the layout.
—Details of Multiple via Replacement—
A description is given of the method of replacing the multiple vias shown in step S<b>14</b> using the flowchart shown in <figref idref="DRAWINGS">FIG. 51</figref>.
In step S<b>142</b><i>a</i>, the multiple via replacement module <b>122</b>, as shown in <figref idref="DRAWINGS">FIG. 52</figref>, extracts a single via <b>87</b>, which causes a design violation and extracted by DRC or the like. In step S<b>142</b><i>b</i>, the multiple via replacement module <b>122</b> reads the information of the multiple via cell library stored in the multiple via cell library <b>1422</b> and determines whether the single via <b>87</b> is replaced with one of multiple via cells <b>96</b> to <b>99</b> shown in <figref idref="DRAWINGS">FIG. 49</figref>. When the single via <b>87</b> is not replaced, the placement of the multiple vias is terminated. When the single via <b>87</b> is replaced, the process goes to step S<b>142</b><i>c</i>. In the step S<b>142</b><i>c</i>, the multiple via replacement module <b>122</b> reads the multiple via cells <b>96</b> to <b>99</b> stored in the multiple via cell library <b>1422</b> of <figref idref="DRAWINGS">FIG. 47</figref> and replaces the single via <b>87</b> shown in <figref idref="DRAWINGS">FIG. 52</figref> with the multiple via cell <b>97</b>.
In step S<b>142</b><i>d</i>, the layout shown in <figref idref="DRAWINGS">FIG. 53</figref> is subjected to the OPC verification. The mark module <b>261</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> reads the mark information stored in the verification information memory <b>15</b> and, as shown in <figref idref="DRAWINGS">FIG. 54</figref>, places the marks on vertices of the patterns <b>51</b><i>a</i>, <b>51</b><i>b</i>, <b>52</b>, and <b>53</b> located around the pattern where the multiple via cell <b>97</b> is placed. When the additional marks are necessary, the mark module <b>261</b> reads the additional mark information stored in the verification information memory <b>15</b> and places the additional marks on sides of the patterns <b>51</b><i>a</i>, <b>52</b>, and <b>53</b>. The grouping module <b>262</b> of <figref idref="DRAWINGS">FIG. 3</figref> reads the area information stored in the verification information memory <b>15</b> and groups adjacent marks to obtain a plurality of groups. Thereafter, the candidate hot spot judgment module <b>263</b> reads the candidate hot spot judgment information stored in the verification information memory <b>15</b> and extracts a candidate OPC hot spot as shown in <figref idref="DRAWINGS">FIG. 54</figref>.
In step <b>142</b><i>e</i>, the placement modification module <b>123</b> of <figref idref="DRAWINGS">FIG. 47</figref> reads the information of the multiple via cell library <b>1422</b> and determines whether to replace the multiple via cell <b>97</b> with one of the different multiple via cells <b>96</b>, <b>98</b>, and <b>99</b>. When the multiple via cell <b>97</b> is not replaced with the multiple via cell <b>96</b>, <b>98</b>, or <b>99</b>, the operation is terminated. When the multiple via cell <b>97</b> is replaced with the different multiple via cell <b>96</b>, <b>98</b>, or <b>99</b>, the procedure proceeds to step S<b>142</b><i>c</i>. As shown in <figref idref="DRAWINGS">FIG. 55</figref>, the multiple via replacement module <b>122</b> then replaces the multiple via cell <b>97</b> with the different multiple via cell <b>96</b>. The mark module <b>261</b> of <figref idref="DRAWINGS">FIG. 3</figref> then places marks at the vertices of the patterns <b>51</b><i>a</i>, <b>52</b>, and <b>53</b> as shown in <figref idref="DRAWINGS">FIG. 5</figref>.
With the design method of a semiconductor integrated circuit according to the second embodiment, when the multiple via cell <b>97</b> is placed as a via to connect wires, the vicinity of the patterns <b>51</b><i>a</i>, <b>52</b>, and <b>53</b> around the multiple via cell <b>97</b> is searched for the candidate OPC hot spot. When the candidate hot spot is extracted, the multiple via cell <b>97</b> is replaced with the different via cell <b>96</b>. As shown in <figref idref="DRAWINGS">FIG. 58</figref>, this prevents occurrence of a short hot spot or the like caused by the multiple via cell <b>97</b> being adjacent to the pattern <b>52</b> as shown in <figref idref="DRAWINGS">FIG. 57</figref> even in the lithography rule check. It is therefore possible to design a semiconductor integrated circuit with higher yield.
Third Embodiment
—Computer Automated System—
As shown in <figref idref="DRAWINGS">FIG. 59</figref>, a design system according to a third embodiment includes a routing module <b>13</b><i>a </i>and a layout memory <b>14</b><i>b</i>. The routing module <b>13</b><i>a </i>includes a spacing module <b>131</b>, a widening module <b>132</b>, and a routing modification module <b>133</b>. The layout memory <b>14</b><i>b </i>includes a routing space memory <b>1431</b> and a wire width information memory <b>1432</b>.
The routing space memory <b>1431</b> stores information to expanding spacing between wires. For example, the critical area (an area including a short defect) of the random defect is used as an indicator. The routing space memory <b>1431</b> stores a rule to reduce the critical area. As shown in <figref idref="DRAWINGS">FIG. 63</figref>, when the patterns <b>31</b> to <b>33</b> having relatively small routing spaces are placed on the layout, the routing space memory <b>1431</b> stores information to increase the routing spaces between the patterns <b>31</b> to <b>33</b> by folding end portions of the patterns <b>31</b> to <b>33</b> as shown in <figref idref="DRAWINGS">FIG. 64</figref>.
The wire width information memory <b>1432</b> of <figref idref="DRAWINGS">FIG. 59</figref> stores information on parameters to increase the wire width according to the distance between adjacent wires as shown in <figref idref="DRAWINGS">FIGS. 60A and 60B</figref>. Examples of the stored width widening information are as shown in <figref idref="DRAWINGS">FIG. 60B</figref>: information to increase the wire width by 0.045 μm as a correction value <b>1</b> of a pattern <b>65</b> when a distance d<b>1</b> between the pattern <b>65</b> and a pattern <b>66</b> is not less than 0.3 μm and less than 0.4 μm; information to widening the wire width by 0.060 μm as the correction value <b>1</b> when a distance d<b>2</b> between the pattern <b>65</b> and a pattern <b>67</b> is not less than 0.6 μm.
The process to increasing the width of wires can be performed also for the purpose of securing a lithography margin. However, the third embodiment provides a system capable of executing the process to further increase the width of patterns of wires as the measure for random defects.
The spacing module <b>131</b> of <figref idref="DRAWINGS">FIG. 59</figref> reads the routing space information of the routing space memory <b>1431</b>. When the layout designed by the layout module <b>10</b> includes adjacent wires which could be problematic in design, the spacing between adjacent wires is increased. The widening module <b>132</b> reads the wire width information in the wire width information memory <b>1432</b> and increase the width of wires in the layout placed by the layout module <b>10</b>. The other members are substantially the same as those of the design systems of a semiconductor integrated circuit according to the first and second embodiments.
—Computer Automated Method—
A description is given of a computer automated method of designing a semiconductor integrated circuit according to the third embodiment using flowcharts of <figref idref="DRAWINGS">FIGS. 61 and 62</figref>.
In step S<b>1</b> of <figref idref="DRAWINGS">FIG. 61</figref>, various types of information necessary for layout design, verification, and modification of a semiconductor integrated circuit are inputted into the design information memory <b>17</b> and program memory unit <b>6</b> of <figref idref="DRAWINGS">FIG. 1</figref> through the input unit <b>4</b> of <figref idref="DRAWINGS">FIG. 1</figref>. In step S<b>3</b>, the routing space information and wire width information of wires placed in the chip area are inputted into the routing space memory <b>1431</b> and the wire width memory <b>1432</b> of <figref idref="DRAWINGS">FIG. 59</figref> through the input unit <b>4</b>.
In step S<b>10</b>, the layout module <b>10</b> reads the design information stored in the design information memory <b>17</b>, the layout information stored in the layout memory <b>14</b>, and the like and places cells, wires, vias, and the like in the chip area. In step S<b>11</b>, the floorplan module <b>11</b> reads the design information stored in the design information memory <b>17</b>, creates a floorplan of the semiconductor integrated circuit, and then stores information on the floorplan in the layout memory <b>14</b>. In step S<b>12</b>, the placement module <b>12</b> reads the information on the floorplan stored in the layout memory <b>14</b> and places logic and macro cells or high-yield cells in the chip area.
In step S<b>13</b>, the routing module <b>13</b> reads the floorplan stored in the layout memory <b>14</b>. The routing module <b>13</b> routes wires and connect wires with vias and contacts in the chip area. In step S<b>15</b>, the routing module <b>13</b> reads the routing space information stored in the layout memory <b>14</b><i>b </i>of <figref idref="DRAWINGS">FIG. 59</figref> and increases the routing space in the layout. The step S<b>15</b> is described later in detail. In step S<b>20</b>, the layout designed in the step S<b>10</b> is verified. In step S<b>30</b>, the layout modification module <b>30</b> reads the layout modification information stored in the layout modification memory unit <b>16</b> and judges hot spots of the layout and modifies the hot spot based on a transfer image of the layout.
—Detail of Method of Increasing Routing Space and Wire Width—
A description is given of a method of increasing the routing space and the wire width shown in the step S<b>15</b> using a flowchart shown in <figref idref="DRAWINGS">FIG. 62</figref>.
In step S<b>151</b> of <figref idref="DRAWINGS">FIG. 62</figref>, the routing spacing module <b>131</b> of <figref idref="DRAWINGS">FIG. 59</figref> reads the placement information of the patterns <b>31</b> to <b>33</b> and vias <b>34</b> to <b>36</b> shown in <figref idref="DRAWINGS">FIG. 63</figref> and the routing space information of the routing space memory <b>1431</b> and expands the routing space of the patterns <b>31</b> to <b>33</b>. In step S<b>152</b>, the physical verification module <b>21</b> of <figref idref="DRAWINGS">FIG. 1</figref> performs the DRC verification for the layout shown in <figref idref="DRAWINGS">FIG. 64</figref> based on the verification information stored in the verification information memory <b>15</b> and modifies a pattern which could cause a fatal design problem.
In step S<b>153</b>, the layout is subjected to the OPC verification. The mark module <b>261</b> shown in <figref idref="DRAWINGS">FIG. 3</figref> reads the mark information stored in the verification information memory <b>15</b> and places the marks at vertices of the patterns <b>31</b> to <b>33</b> around the region with the spacing between wires expanded as shown in <figref idref="DRAWINGS">FIG. 65</figref>. When the additional marks are necessary, the mark module <b>261</b> reads the additional mark information stored in the verification information memory <b>15</b> and places the additional marks at sides of the patterns <b>32</b> and <b>33</b>. The grouping module <b>262</b> reads the area information stored in the verification information memory <b>15</b> and groups adjacent marks to obtain a plurality of groups. Thereafter, the candidate hot spot judgment module <b>263</b> reads the candidate hot spot judgment information stored in the verification information memory <b>15</b> and extracts a group to be the OPC hot spot (candidate hot spot) as shown in <figref idref="DRAWINGS">FIG. 67</figref>.
In step S<b>154</b>, the candidate hot spot judgment module <b>263</b> judges whether the extracted hot spot can be modified based on the hot spot modification information stored in the verification information memory <b>15</b>. When the modification is impossible, the operation is terminated. When the modification is possible, in step S<b>155</b>, the candidate hot spot judgment module <b>263</b> reads the candidate hot spot modification information stored in the verification information memory <b>15</b> and increases spacing between the patterns <b>31</b>, <b>32</b>, and <b>33</b> to modify the layout such that the number of marks included in the group extracted as the OPC hot spot is reduced as shown in <figref idref="DRAWINGS">FIG. 68</figref>.
With the method of designing a semiconductor integrated circuit according to the third embodiment, an area where the spacing between wires is comparatively small, in which the random defects are likely to occur, is subjected to the process to increase the routing space. This can prevent yield reduction due to the random defects and systematic defects. In the method of designing a semiconductor integrated circuit according to the third embodiment, increasing the spacing between wires as shown in <figref idref="DRAWINGS">FIG. 64</figref> by folding the patterns <b>31</b> to <b>33</b> increases the probability of occurrence of the OPC hot spots (see <figref idref="DRAWINGS">FIG. 69</figref>). After the process to expand the spacing between wire patterns, therefore, the OPC hot spots are properly verified and modified as shown in the step S<b>153</b> and <figref idref="DRAWINGS">FIGS. 65 to 68</figref> to prevent the occurrence of the OPC hot spots as shown in <figref idref="DRAWINGS">FIG. 70</figref>. Accordingly, the lithography rule check and the check of the OPC problems can be carried out with high speed and high accuracy even after patterns of wires and the like in a wide area of the chip area are subjected to the measures for the random and systematic defects. It is therefore possible to provide the design method for a semiconductor integrated circuit capable of improving the yield.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
Contents5
43 sheets
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Every citation, both waysCites: the store holds 16 of 17
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US10872817B2 | Cited by | United States of America | Search report |
| US11387144B2 | Cited by | United States of America | Applicant |
| US10762618B1 | Cited by | United States of America | Search report |
| US2019172824A1 | Cited by | United States of America | Search report |
| US8495525B1 | Cited by | United States of America | Applicant |
| US11475202B1 | Cited by | United States of America | Search report |
| US8458625B2 | Cited by | United States of America | Search report |
| JP2000187314A | Cites | Japan | Applicant |
| JP2003162041A | Cites | Japan | Applicant |
| JP2003257842A | Cites | Japan | Applicant |
| JP2004302110A | Cites | Japan | Applicant |
| US6539519B1 | Cites | United States of America | Search report |
| US6553558B2 | Cites | United States of America | Search report |
| US6631307B1 | Cites | United States of America | Applicant |
| US6668367B2 | Cites | United States of America | Search report |
| US6952818B2 | Cites | United States of America | Applicant |
| US7194707B2 | Cites | United States of America | Applicant |
| JPH08137087A | Cites | Japan | Applicant |
| JP8137087 | Cites | Japan | Third party observation |
| JP2000187314 | Cites | Japan | Third party observation |
| JP2003162041 | Cites | Japan | Third party observation |
| JP2003257842 | Cites | Japan | Third party observation |
| JP2004302110 | Cites | Japan | Third party observation |
| Official Office Action Letter issued on Feb. 10, 2009, in Taiwan application No. 094137590, including Japanese language translation thereof. | Non-patent | – | Applicant |
| Official Office Action Letter issued on Feb. 10, 2009, in Taiwan application No. 094137590, including Japanese language translation thereof. | Non-patent | – | Third party observation |
8 members in 3 offices
Priority claims11
| Document | Office | Kind | Date |
|---|---|---|---|
| 2004318427 | Japan | A | |
| 2004318427 | Japan | A | |
| P2004318427 | Japan | – | |
| 26384505 | United States of America | A | |
| 26384505 | United States of America | A | |
| 24283208 | United States of America | A | |
| 11263845 | – | – | – |
| JP20040318427 | – | – | – |
| P2004318427 | – | – | – |
| US20050263845 | – | – | – |
| US20080242832 | – | – | – |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| JP2006126745A | Japan | A | |
| US2006123380A1 | United States of America | A1 | |
| TW200620017A | Taiwan Province of China | A | |
| US7451429B2 | United States of America | B2 | |
| US2009064083A1 | United States of America | A1 | |
| US7958463B2This record | United States of America | B2 | |
| JP4768251B2 | Japan | B2 | |
| TWI353538B | Taiwan Province of China | B |
49 transactions on the USPTO file
Allowed after 1 non-final rejection.
- Non-final rejections
- 1
- Final rejections
- 0
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Expire PatentEXP. | EXP. | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Supplemental ResponseSA.. | SA.. | |
| Response after Non-Final ActionA... | A... | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Preliminary AmendmentA.PE | A.PE | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Sent to Classification ContractorPGPC | PGPC | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Preliminary AmendmentA.PE | A.PE | |
| Request from applicant for the USPTO to retrieve the Priority DocumentPDREQUST | PDREQUST | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Initial Exam Team nnIEXX | IEXX |
5 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Lapse for failure to pay maintenance feesLapsedLAPS | LAPS | |
| Maintenance fee reminder mailedREMI | REMI |
Numbers
- Publication
- 07958463
- Publication, DOCDB
- 7958463
- Publication, EPODOC
- US7958463
- Application
- 12242832
- Application, DOCDB
- 24283208
- Application, EPODOC
- US20080242832
Titles
- English
- Computer automated method for manufacturing an integrated circuit pattern layout
Patent term adjustment
- A delay
- +277 daysthe office missed an examination deadline
- Applicant delay
- −102 days
- Net adjustment
- 175 days
Classification
- CPC, 3
- G06F30/398
- G06F2119/18
- Y02P90/02
- IPC, 7
- G03F1 36
- G06F17 50
- G03F1 68
- G03F1 70
- G03F7 20
- H01L21 027
- H01L21 82
- USPC, 8
- 716054000
- 430005000
- 430030000
- 716050000
- 716051000
- 716052000
- 716053000
- 716055000