Analog-to-digital converter using digital output as dither

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Patent Application No. 61/148,210, entitled ANALOG-TO-DIGITAL CONVERTER USING DIGITAL OUTPUT AS DITHER, filed on Jan. 29, 2009, which is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates to systems having transducers for converting analog signals to digital signals, and more particularly to micromachined analog-to-digital converter systems using their digital outputs as a source of quantization dither.

DESCRIPTION OF RELATED ART

In today's information age, analog-to-digital converter (ADC) devices are often used for converting analog signals into digital signals for use in electronic systems. For example, in order to store audible sound as a music file, a pressure sensor such as a microphone may be used to convert sound waves into an analog voltage signal that is then converted into ones and zeros by an analog-to-digital converter. Those ones and zeros are then compressed and formatted into a music file. At a later time, the music can be played back on a speaker by reversing this process. ADCs are used in many other applications, such as measuring acceleration for an automobile airbag system with an accelerometer, measuring spatial orientation in a video game controller with a gyroscope, measuring temperature in an electronic thermostat with a thermocouple, and measuring brightness in a night light with a photodetector, to name but a few.

Many ADCs use a technique known as delta-sigma modulation (sometimes alternatively referred to as sigma-delta modulation) to convert analog input signals to digital output signals. Generally speaking, delta-sigma modulation works as follows. First, the analog input signal is combined with a feedback signal to produce a difference (delta) signal, which is passed to an integrator that outputs a sum (sigma) of the difference signals over time. Until the sum reaches a predetermined threshold, a logic zero (0) is output. When the threshold is reached, a logic one (1) is output. The feedback signal is driven by the output voltage to ‘reset’ the sum when a logic one is output. In this way, if the analog input signal is large, the threshold will be reached more quickly, and more ones will be output. On the other hand, if the analog signal is small, the threshold will take longer to reach, and more zeros will be output. The ratio between ones and zeros in the output reflects the average value of the analog signal over time, with the ratio becoming more precise over longer periods of time. Logic values zero and one are represented by different voltages. For example, logic one may be a positive voltage while logic zero is zero volts, or logic one may be a voltage V and logic zero may be a matched voltage −V.

<figref idrefs="DRAWINGS">FIG. 1</figref> is a schematic block diagram of an exemplary delta-sigma modulator as is known in the art. The modulator converts an analog input <b>110</b> into a digital output <b>160</b>. A difference element (delta) <b>120</b> subtracts a feedback signal <b>171</b> (described below) from the input <b>110</b> to produce a difference signal <b>121</b>, as will be described in more detail shortly. A summing element (sigma) <b>130</b> produces a sum signal <b>131</b> from the difference signals <b>121</b>.

A quantizer element <b>140</b>, also referred to herein as a comparator, compares the sum signals <b>131</b> from the summing element <b>130</b> (at the terminal marked “+”) to a reference voltage <b>142</b> (at the terminal marked “−”). The reference voltage V_refmay be, for example, 0V (electrical ground) or another fixed reference voltage. If the signals <b>131</b> are greater than the reference voltage, then the output <b>141</b> of the quantizer element <b>140</b> is a logic one (represented by box <b>146</b>), while if the signals are not greater than the reference voltage, the output <b>141</b> of the quantizer element <b>140</b> is a logic zero (represented by box <b>144</b>). The boxes numbered <b>144</b> and <b>146</b> represent the two output logical voltages produced by the quantizer <b>140</b>, and are not necessarily input voltages provided as inputs to the quantizer <b>140</b>.

Output voltage <b>141</b> is stored in a memory device, here depicted as a D-type latch element <b>150</b>. The memory device is clocked so that it can interface with other electrical systems that run on a clock, such as computers. Thus, the memory device only stores voltage <b>141</b> at certain times, such as the edge of a clock pulse defined by a clock signal <b>152</b>. The stored voltage is output at the terminal marked “Q” as digital output <b>160</b>.

Digital output <b>160</b> is fed back to the difference element <b>120</b> through a digital-to-analog converter (D/A) element <b>170</b>, which produces the feedback signal <b>171</b> mentioned above. When the digital output is a logic one (1), D/A element <b>170</b> outputs a voltage V_DA(represented by box <b>172</b>), so that V_DAvolts are effectively subtracted from the analog input <b>110</b> by difference element <b>120</b>. When the digital output <b>160</b> is a logic zero (0), D/A element <b>170</b> outputs a matched negative voltage −V_DAvolts (represented by box <b>174</b>), so that V_DAvolts are effectively added to the analog input <b>110</b> by the difference element <b>120</b>. The voltages within the difference element <b>120</b>, summing element <b>130</b>, and the signals <b>131</b> may remain within required electrical tolerances by choosing appropriate matched outputs of D/A element <b>170</b>. Elements <b>120</b>, <b>130</b>, and <b>140</b> are typically implemented using operational amplifiers. The purpose of dither generator <b>180</b> is explained below.

Delta-sigma modulation may be used to provide a digital output from servomechanisms (e.g., micromachined accelerometers, gyroscopes, and other sensors) having analog error signals. A useful property of the pulse-density modulated output is that it has an analog time average directly proportional to the input signal and can be used as feedback without explicit digital to analog conversion. Another useful property for vibratory gyroscopes is that the modulation with the shuttle frequency can be achieved with minimal circuits as a cross switch or exclusive-or function. The use of delta-sigma modulation with micromachined sensors has been described by Henrion in U.S. Pat. No. 4,922,756.

However, mechanical sensors generally have inherent signal delays due to the inertial effects of masses changing direction and speed. These delays can cause difficulties with lower frequency limit-cycle oscillations in delta-sigma loops containing them. These oscillations generally occur at low frequencies other than those normally determined by the input signal. These limit-cycle oscillations may appear as undesirable ‘tones’. These tones tend to increase noise in measuring instruments and, by their persistence, tend to cause output “locking” around various input values, most notably around null. When an instrument is locked, it generates long sequences of zeros or ones, allowing the output voltage to stabilize over relatively long durations. When this occurs, feedback mechanisms such as the feedback loop including D/A element <b>170</b> may not work properly. This locking therefore tends to reduce a measuring instrument's response to changes in its input, reducing the resolution and linearity of the instrument.

Some advantages of using well-matched drive and feedback elements in micromachined gyroscopes with delta-sigma feedback is taught by Geen in U.S. Pat. No. 6,470,748. Practical implementation is facilitated by exploiting a degree of resonance enhancement to the signal in the Coriolis accelerometer. However, the effective mechanical lag is also increased in proportion to the signal gain so that the difficulties with unwanted delta-sigma limit-cycles can become more severe.

There are several prior-art approaches to solving this locking problem using modified delta-sigma feedback loops. In one approach, the mechanical lag is compensated with an electrical lead forming a match-filter. This approach is described by Geen in U.K. Patent 2,127,637. However, lag may vary considerably between instrument specimens, requiring individual adjustment which may be impractical in mass production.

A second approach (often used in audio applications) uses multistage modulators as, for example, described by Ledzius et al. in U.S. Pat. No. 5,357,252. Having multiple delta-sigma stages, however, introduces impractical complexities in present manufacturing processes integrating mechanical structures with electronics. In particular, the variability of the sensors and their signal gains generally make it very difficult to devise a stable configuration for a higher order delta-sigma modulator.

A third approach applies a dither signal large enough to randomize the locking behavior. Dither is essentially random noise having an average of zero. By adding this noise, a long string of output zeros or ones may be broken up, while still maintaining the same long-term average output signal. Dither is represented in <figref idrefs="DRAWINGS">FIG. 1</figref> by dither generator <b>180</b>, which provides an additive signal to the quantizer <b>140</b>. The use of dither in a multistage delta-sigma modulator is described by Norsworthy in U.S. Pat. No. 5,144,308, and is applied to micromachined sensors by Lemkin et al. in U.S. Pat. No. 6,386,032.

The generation of a dither signal <b>180</b> having sufficient randomness and amplitude generally requires significant circuitry and can consume a substantial proportion of the available signal headroom. In U.S. Pat. No. 6,839,387, Mittel teaches a more economical method of self-dithering a delta-sigma modulator by inserting D-type delays into the loop. However, doing so still utilizes dozens of transistors, and the delays are likely to worsen the difficulties associated with mechanical elements. Zhang uses a pseudo-random dither generator to modulate the threshold windows of a multi-level comparator in U.S. Pat. No. 6,825,784. This circuit is relatively complex and correspondingly expensive, but has the advantage of not consuming much signal headroom.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention address the locking issue discussed above by placing a proportional feedback around the comparator (quantizer element) to modulate the comparator reference voltage based on the comparator output. This proportional feedback may be implemented using as little as one transistor or resistor. In essence, this proportional feedback is a self-dithering mechanism that does not consume signal headroom and that requires little added circuitry and therefore little added cost, particularly in integrated micromachining processes. Because the proportional feedback is independent of the analog input signal, it may be used in delta-sigma modulators generally, so embodiments of the invention are not limited to use with micromachined sensors but may also be used in audio, telecommunications, and other applications.

In a first embodiment of the invention there is provided apparatus comprising an analog-to-digital converter for converting an analog input signal to a digital output signal. Generally speaking, the converter has four main components, namely a delta circuit, a sigma circuit, a quantizer circuit, and a feedback circuit. The delta circuit produces a delta output signal based on the analog input signal and an analog feedback signal derived from the digital output signal. The sigma circuit integrates the delta output signal to form a sigma output signal. The quantizer circuit produces the digital output signal based on the sigma output signal and a reference signal. Finally, the feedback circuit modulates the reference signal based on the digital output signal.

The feedback circuit may include a transistor, a voltage divider, or a voltage amplifier. The quantizer circuit may include a comparator having an output and a digital memory coupled to the comparator output. If so, the digital memory may be a latch, and may store a digital output voltage. The delta circuit may include a digital-to-analog converter for producing the analog feedback signal based on the digital output signal.

A related embodiment may further include a microelectromechanical sensor having a mechanical-to-electrical transducer for providing the analog input signal to the analog-to-digital converter based on mechanical operation of the sensor. In this embodiment, the sensor may be, for example, a gyroscope, an accelerometer, or a pressure sensor. A related embodiment may also include an electrical-to-mechanical transducer for producing a mechanical effect on the sensor based on the digital output signal.

In another embodiment of the invention there is provided a method for dithering an analog-to-digital converter apparatus having a quantizer for comparing a quantizer input voltage to a reference voltage, the quantizer having an output voltage. The method includes two processes: storing the quantizer output voltage in a digital memory, and varying the reference voltage based on the stored output voltage.

Storing the output voltage may include providing the output voltage to a latch, or converting the output voltage substantially into one of two given voltages. The reference voltage may equal the stored output voltage, so that converting the stored output voltage into the reference voltage requires no active or passive circuit elements. Varying the reference voltage based on the stored output voltage may include applying a constant gain to the stored output voltage.

In a related embodiment, the analog-to-digital transducer apparatus includes a microelectromechanical sensor having an analog output. The sensor may be one of: a gyroscope, an accelerometer, and a pressure sensor. In this embodiment, the method may further include determining the quantizer input voltage based on the analog output of the sensor. The method may include actuating the sensor in response to a change in the stored output voltage. In a related embodiment wherein the sensor has a resonance frequency, varying the reference voltage may include varying it according to a clock frequency that is at least a given multiple of the resonance frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the invention will be more readily understood by reference to the following detailed description, taken with reference to the accompanying drawings, in which:

<figref idrefs="DRAWINGS">FIG. 1</figref> is a schematic block diagram of a delta-sigma circuit, as is known in the art;

<figref idrefs="DRAWINGS">FIG. 2</figref> is a schematic block diagram of a delta-sigma modulator in accordance with an embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 3</figref> is a schematic block diagram of a simple feedback circuit for the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 2</figref>, in accordance with an exemplary embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 4</figref> is a schematic diagram of one exemplary embodiment of the quantizing stage of the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 2</figref>;

<figref idrefs="DRAWINGS">FIG. 5</figref> is a schematic block diagram of a sensor system including a mechanical sensor and a delta-sigma modulator, in accordance with an exemplary embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 6</figref> is a graph of experimental output data from a gyroscope incorporating a delta-sigma modulator known in the art;

<figref idrefs="DRAWINGS">FIG. 7</figref> is a set of graphs of experimental output data from the gyroscope of <figref idrefs="DRAWINGS">FIG. 6</figref> after incorporating a delta-sigma circuit in accordance with embodiments of the present invention; and

<figref idrefs="DRAWINGS">FIG. 8</figref> shows the measured non-linearity error percent as a function of input speed for the gyroscope data of <figref idrefs="DRAWINGS">FIG. 7</figref>.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Definitions. As used in this description and the accompanying claims, the following terms shall have the meanings indicated, unless the context otherwise requires:

An analog-to-digital converter (ADC) is an electrical circuit that converts a continuous, analog signal into a representative, discrete, digital signal. The analog signal is commonly an electric potential having a continuous range of voltage, while the digital signal is commonly a stream of logical binary (zero or one) values, each value embodied as one of two given voltages.

Headroom is the amount by which the values representable by a digital output signal (digital full scale) exceed the range of expected input values (analog full scale). Systems having insufficient headroom may suffer from clipping, where an input signal has a value so large that it exceeds the ability of the digital output signal to represent it. Clipping causes a loss of signal information.

Quantization noise is analog error that is introduced in the process of quantizing a signal, i.e., converting a signal from continuous to discrete in an ADC. The error arises because the finite number of values a discrete output signal may have cannot represent all of the values a continuous input signal may have. Quantization noise manifests itself as undesirable frequencies in the digital signal.

Dither is a signal applied to randomize the frequencies of quantization noise in an ADC, thereby reducing or preventing the appearance of tones in the digital signal. Applying an additive dither signal to an analog signal already at an extremum of its signal range results in an input signal exceeding that range, thus decreasing the available headroom. If the dither signal is too large, clipping will result. However, if the dither signal is too small, undesirable quantization noise may still appear in the digital output.

A delta-sigma modulator (sometimes known as a sigma-delta modulator) is an analog-to-digital converter that includes, among other things, a differencing element (delta) and an integrating element (sigma). The modulator integrates the input signal over time, and generates an output signal based on the value of the integrated signal. When the integrated signal is below a given threshold, the modulator outputs a logic zero. When the integrated signal exceeds the threshold, the modulator outputs a logic one, and the threshold value is subtracted from the integrated signal.

<figref idrefs="DRAWINGS">FIG. 2</figref> is a schematic block diagram of a delta-sigma modulator in accordance with an exemplary embodiment of the present invention. This delta-sigma modulator operates similar to the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 1</figref>, but in this exemplary embodiment a feedback circuit <b>200</b> is used to modulate the reference voltage provided to the quantizer <b>140</b> at the terminal marked ‘−’ based on the output of the quantizer <b>140</b>. Specifically, in this embodiment, the feedback circuit <b>200</b> modulates the reference voltage of the quantizer <b>140</b> based on the output of the latch <b>150</b>, which itself is based on the quantizer <b>140</b> output. The feedback circuit <b>200</b> may include as little as a single resistor or transistor, or may include a voltage divider or voltage amplifier providing a fixed or varying gain. In essence, the feedback circuit <b>200</b> provides a self-dithering mechanism. The feedback circuit does not consume signal headroom, because its output does not appear in the analog input signal. Further, the feedback circuit may require little added circuitry and therefore little added cost, both of which are particularly important in integrated micromachining processes.

The feedback circuit <b>200</b> generally operates as follows. Rather than adding dither at the ‘+’ terminal of quantizer <b>140</b> using dither generator <b>180</b> as in <figref idrefs="DRAWINGS">FIG. 1</figref>, the feedback circuit <b>200</b> modulates the reference voltage at the ‘−’ terminal of quantizer <b>140</b> based on the quantizer <b>140</b> output, and more specifically based on the latch <b>150</b> output. For example, increasing the quantizer <b>140</b> reference voltage by V volts requires the ‘+’ signal to increase by V additional volts in order to register an output value of logic one. Similarly, decreasing the quantizer <b>140</b> reference voltage by V volts requires the ‘+’ signal to increase by V fewer volts in order to register an output value of logic one.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a schematic block diagram of a simple feedback circuit for the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 2</figref>, in accordance with an exemplary embodiment of the present invention. In this exemplary embodiment, in which several components are omitted from the figure for clarity, the feedback circuit <b>200</b> is arranged as a simple resistive voltage divider. In this arrangement, a single resistor <b>202</b> is situated between the output of latch <b>150</b> and a connection <b>204</b> (which, in this exemplary embodiment, is referenced at a voltage V_cc/2). In alternative embodiments, the resistor <b>202</b> could be replaced with a capacitor, transistor, another single circuit element, or more complex circuitry.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a schematic diagram of one exemplary embodiment of the quantizing stage (encompassing the quantizer <b>140</b>, the latch <b>150</b>, and the feedback circuit <b>200</b>) of the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 2</figref>. In one embodiment, the digital output of latch <b>150</b> is either +5V (logic 1) or 0V (logic 0), but it will be understood that other output voltages may be employed in accordance with other embodiments. The depicted quantizing stage incorporates a balanced quantizer (comparator) configuration with differential inputs, where resistors <b>362</b>, <b>366</b> provide the common-mode voltage. The circuit works generally as follows.

The digital output value <b>160</b> of the circuit is determined by the voltage at node <b>300</b>. If this voltage is large enough when clock signal <b>152</b> reaches an edge, the latch <b>150</b> will store a logic one (1), which will be presented at the output <b>160</b>. If the voltage is too small, the latch <b>150</b> will store a logic zero (0) and present this value at the output <b>160</b>.

The voltage at node <b>300</b> is controlled by transistors <b>310</b>, <b>312</b>. Transistor <b>310</b> connects node <b>300</b> with voltage V_dd<b>144</b>, while transistor <b>312</b> connects node <b>300</b> with ground voltage <b>146</b>. The current through transistor <b>310</b> must equal the current through transistor <b>312</b>, by Kirchoff's current law. Generally, however, one of the transistors <b>310</b>, <b>312</b> will limit the current that passes through both. If transistor <b>310</b> is the current limiter, then the voltage at node <b>300</b> will tend to the ground voltage <b>146</b>, while if transistor <b>312</b> is the current limiter, the voltage at node <b>300</b> will tend to V_dd<b>144</b>. The currents through transistors <b>310</b>, <b>312</b> are determined, in turn, by the voltages at nodes <b>320</b>, <b>322</b> respectively.

The left half of the circuit is divided into two limbs, with node <b>320</b> in the right limb and node <b>322</b> common to both limbs. The left limb extends between transistor <b>330</b> and transistor <b>370</b>. The right limb extends between transistor <b>332</b> and transistor <b>370</b>. Transistor <b>330</b> is configured as a diode-connected current source. Because transistors <b>330</b>, <b>332</b> share a gate voltage, the current in the left and right limbs is mirrored. Transistor <b>370</b> is configured as a diode-connected current drain for both limbs, and shares its gate voltage with transistor <b>312</b>. The current in both limbs is controlled by transistors <b>340</b>, <b>342</b>, whose respective gate voltages are controlled by the differential input signal. Whichever transistor <b>340</b>, <b>342</b> has a lower gate voltage acts to limit the current passing through both limbs.

The voltage at node <b>320</b> is determined by whichever of the transistors <b>340</b>, <b>342</b> is the current-limiting transistor. If transistor <b>340</b> has the lower gate voltage, it limits the current through the limbs, and the voltage at node <b>320</b> will tend to ground voltage <b>146</b>. This in turn will increase the conductance of transistor <b>310</b>, which has an inverted gate. On the other hand, if transistor <b>342</b> has a lower gate voltage, then the voltage at node <b>320</b> will tend to V_dd<b>144</b>. This will decrease the conductance of transistor <b>310</b>. The difference between the gate voltages of transistors <b>340</b>, <b>342</b> need only be slight for the above effects to occur. Thus, the circuit as described so far acts as a voltage comparator or single-bit quantizer, as is well known in the art.

In accordance with embodiments of the invention, the quantizing stage is modified by a feedback circuit <b>200</b>, consisting of transistors <b>350</b>, <b>352</b> and resistors <b>360</b>, <b>364</b>. The digital output <b>160</b>, which provides the gate voltages for transistors <b>350</b>, <b>352</b>, thus controls the operation of the quantizing stage. If the value of digital output <b>160</b> is a logic zero (0), then transistor <b>350</b> does not conduct between its source and drain, so the left limb includes both resistors <b>360</b>, <b>362</b>. At the same time, a logic one (1) is presented to the gate of transistor <b>352</b>, which conducts. The right limb thus includes only resistor <b>366</b> and not resistor <b>364</b>, which is short-circuited.

Because the currents in the left and right limbs are balanced, the additional resistance in the left limb provides a voltage offset. The voltage at the drain of transistor <b>340</b> is higher than the voltage at the drain of transistor <b>342</b> by the size of this offset. Thus, to maintain the same gate-drain voltage in transistor <b>340</b>, the gate voltage must increase by this offset. Because the input is differential, this in turn requires the input signal to be larger than the induced offset. If the magnitude of the input is smaller than the offset, then the voltage at node <b>320</b> will drop to ground and the voltage at node <b>300</b> will increase. Thus at the next clock cycle, the latch will store a logic one (1), changing state.

Conversely, if the value of output <b>160</b> is a logic one (1), then transistor <b>350</b> conducts and transistor <b>352</b> does not conduct. In this configuration, the left limb includes only resistor <b>362</b> and not resistor <b>360</b>, and the right limb includes both resistors <b>364</b>, <b>366</b>. The right limb thus contains a voltage offset, and the input signal must again exceed the voltage offset (with opposite sign) to maintain the ground voltage at node <b>320</b>. If the magnitude of the input is smaller than the offset, then the voltage at node <b>320</b> will increase, and the voltage at node <b>300</b> will decrease. Thus at the next clock cycle, the latch will store a logic zero (0), changing state.

Combining these two cases, it can be seen that if the input signal remains small in either positive or negative magnitude, the latch will change state between logic one (1) and logic zero (0) each clock cycle. As a result, the feedback circuit <b>200</b> of the embodiment shown in <figref idrefs="DRAWINGS">FIG. 4</figref> essentially forces a quiescent oscillation having frequency equal to half that of clock <b>152</b>, that can be regarded as “dither” to smear lock bands that may appear in the output at frequency CK/2N. Unlike the dither represented in <figref idrefs="DRAWINGS">FIG. 1</figref>, however, this “dither” is not additive and does not consume headroom. The size of the input signal that avoids this effect is controlled by the voltage offset, which in turn is controlled by the resistors <b>360</b>, <b>364</b>.

It is possible to simplify the circuit even further, while retaining its essential properties. For example, a voltage offset may be induced by omitting transistor <b>352</b> and resistor <b>364</b>, and fixing the resistance R₃₆₆of resistor <b>366</b> to be between that of the high and low resistances that appear on the left limb during operation of the circuit. These high and low resistances are given by R₃₆₂+R₃₆₀(when transistor <b>350</b> does not conduct) and R₃₆₂(when transistor <b>350</b> conducts), respectively. In one particularly useful embodiment of this technique, resistor <b>366</b> has a resistance equal to the average of these, or R₃₆₂+0.5 R₃₆₀.

With these values for resistors <b>360</b>, <b>362</b>, and <b>366</b>, when the output <b>160</b> is logic one (1), transistor <b>350</b> conducts and the left limb has less resistance than the right limb. When the output <b>160</b> is logic zero (0), transistor <b>350</b> does not conduct and the left limb has greater resistance than the right limb. The feedback circuit <b>200</b> thus operates according to the basic principle described above, but employs fewer components. In another embodiment, resistor <b>366</b> does not have an average resistance, and the voltage band in which dithering occurs is no longer centered on the common mode voltage.

Numerous variations on this basic principle are contemplated. For example, digital memory <b>150</b> may be implemented using other digital logic. The feedback loop may be implemented with electrical components other than transistors, and the tipping may be accomplished by, e.g., capacitors rather than resistors.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a schematic block diagram of a sensor system including a mechanical sensor <b>520</b> (e.g., a micromachined accelerometer or gyroscope or pressure sensor) coupled to the delta-sigma modulator of <figref idrefs="DRAWINGS">FIG. 2</figref> via transducers <b>510</b> and <b>512</b>. The transducer <b>512</b> performs a mechanical-to-electrical conversion to produce analog signals <b>110</b> from mechanical movements of a component of the sensor <b>520</b>. For example, the transducer <b>512</b> may include one or more fixed sensing electrodes that are capacitively coupled with one or more corresponding electrodes on a movable mass and may be used to sense motion of the mass. The transducer <b>510</b> is coupled to the digital output <b>160</b> and performs an electrical-to-mechanical conversion, e.g., to adjust operation of one or more mechanical components of the sensor <b>520</b>. For example, the transducer <b>510</b> may include one or more fixed drive electrodes that are capacitively coupled with one or more corresponding electrodes on a movable mass and may be used to impart forces to the mass. It should be noted that the transducers <b>510</b>, <b>512</b> may be integral with the sensor <b>520</b> or may be separate elements.

When sensor <b>520</b> is a vibratory gyro, transducer <b>510</b> may incorporate a modulator at the shuttle frequency and transducer <b>512</b> may incorporate a corresponding demodulator. In that case, clock <b>152</b> has a period that is at least a given multiple of the resonance period. Clock <b>152</b> is then advantageously a sub-harmonic of the shuttle frequency such that the modulator applies whole cycles of shuttle excitation for each feedback quantum and avoids residual forces which induce erroneous perturbations to the mechanical motion. In the embodiment shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, the mechanical structure essentially provides the “delta” function and the transducer block <b>510</b> essentially provides the D/A function when used in a force-feedback configuration so that the sensor lag is in the delta-sigma loop; thus, the difference element <b>120</b> and the D/A element <b>170</b> are omitted.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a graph of experimental output data from a gyroscope incorporating a delta-sigma circuit known in the art. This graph was generated from test data taken from observations of a gyroscopic sensor that does not compensate for sensor lag. The horizontal axis represents the number of degrees per second of angular velocity measured by the gyro, as the input signal. The vertical axis represents the output signal as a fraction of the maximum output signal (i.e., the fraction of the full scale signal). The sensor measured angular motion in degrees per second (deg/sec). Rotation was measured relative to a ‘null’ rotation of 70 deg/sec, which can be seen as the center of the 0.00 output signal data. The maximum output signal (full scale) of the sensor is reached at 470 deg/sec in either rotational direction. This corresponds to +400 deg/sec and −540 deg/sec input signal, as the experimental data in the figure show at the −1.00 and +1.00 output signal levels, respectively.

Lock bands can be clearly seen in the figure every ⅓ of the full scale output signal, from full scale in one direction to full scale in the other. Any input signal in a lock band will yield the same output signal, so the lock band represents a range of inputs to which the output is insensitive. For example, the lock band at output 0.00 output contains 10 data points, and extends from −125 deg/sec input to +300 deg/sec input. In an ideal sensor, these lock bands should not exist. Instead, the output should be exactly proportional to the input, and the output data points should lie in a straight line.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a set of graphs of experimental output data from the gyroscope of <figref idrefs="DRAWINGS">FIG. 6</figref> after incorporating a delta-sigma circuit in accordance with embodiments of the present invention. Graph <b>710</b> shows the linearity between the input and output data over the full range of inputs. Here, clusters of measurements were performed near 0%, 50%, and 100% of full scale input in both rotational directions. As can be seen in the figure, the output closely tracks the full scale input. Lock bands are absent. Graphs <b>720</b>, <b>730</b> show the relationship between the input and output signals near negative and positive full scale inputs, respectively. Both show strong linearity in signal. There are no lock bands, even over changes in the input speed that are fractions of one percent of the input range.

<figref idrefs="DRAWINGS">FIG. 8</figref> shows the measured non-linearity error percent as a function of input speed for the gyroscope data of <figref idrefs="DRAWINGS">FIG. 7</figref>. This measured error is the relative magnitude of the deviation between the observed output and a best fit line for the data in <figref idrefs="DRAWINGS">FIG. 7</figref>. As can be seen from the data in <figref idrefs="DRAWINGS">FIG. 8</figref>, the observed output does not deviate from the ideal, linear sensor output by more than 0.5% over the entire input range. As an example, look at the worst deviation of 0.5%, which occurs at +150 deg/sec of input speed. When this input speed is presented to the gyro of this embodiment, the output signal will be measured at a value corresponding to a scaled value of between 142.5 deg/sec and 157.5 deg/sec. Compare this to the same sensor of <figref idrefs="DRAWINGS">FIG. 6</figref>, which is not included in a circuit in accordance with an embodiment of this invention, in which an input speed of +150 deg/sec would register as 0.00 output signal, or 0 deg/sec. At 300 deg/sec input, the error in the present embodiment is approximately 0.0%, and the sensor registers as 300 deg/sec. At 300 deg/sec input, the prior art sensor output would register one-third of full scale. As full scale is 470 deg/sec for that sensor, the output would correspond to about 156 deg/sec, an error of nearly 50%. Even if the output were measured in the ‘best’ lock band for this input (the lock band at two-thirds full scale), such a reading would correspond to about 312 deg/sec, an error of 4%. This error is still nearly an order of magnitude larger than the worst error measured in the sensor output signal after application of design principles according to the invention taught herein.

The present invention may be embodied in many different forms, including, but in no way limited to, programmable logic for use with a programmable logic device (e.g., a Field Programmable Gate Array (FPGA) or other PLD), discrete components, integrated circuitry (e.g., an Application Specific Integrated Circuit (ASIC)), or other appropriate means including any combination thereof.

Hardware logic (including programmable logic for use with a programmable logic device) implementing all or part of the functionality previously described herein may be designed using traditional manual methods, or may be designed, captured, simulated, or documented electronically using various tools, such as Computer Aided Design (CAD), a hardware description language (e.g., VHDL or AHDL), or a PLD programming language (e.g., PALASM, ABEL, or CUPL).

Programmable logic may be fixed either permanently or transitorily in a tangible storage medium, such as a semiconductor memory device (e.g., a RAM, ROM, PROM, EEPROM, or Flash-Programmable RAM), a magnetic memory device (e.g., a diskette or fixed disk), an optical memory device (e.g., a CD-ROM), or other memory device. The programmable logic may be fixed in a signal that is transmittable to a computer using any of various communication technologies, including, but in no way limited to, analog technologies, digital technologies, optical technologies, wireless technologies (e.g., Bluetooth), networking technologies, and internetworking technologies. The programmable logic may be distributed as a removable storage medium with accompanying printed or electronic documentation (e.g., shrink wrapped software), preloaded with a computer system (e.g., on system ROM or fixed disk), or distributed from a server or electronic bulletin board over the communication system (e.g., the Internet or World Wide Web).

The embodiments of the invention described above are intended to be merely exemplary; numerous variations and modifications may become apparent to those skilled in the art based on the teachings of this disclosure. All such variations and modifications are intended to be within the scope of the present invention as defined in any appended claims. Any references to the “invention” are intended to refer to exemplary embodiments of the invention and should not be construed to refer to all embodiments of the invention unless the context otherwise requires.