Stacked integrated circuit package system

TECHNICAL FIELD

0001The present invention relates generally to an integrated circuit package system and more particularly to a stacked integrated circuit package system.

BACKGROUND ART

0002Integrated circuit packaging technology has seen an increase in the number of integrated circuits mounted on a single circuit board or substrate. The new packaging designs are more compact in form factors, such as the physical size and shape of an integrated circuit, and providing a significant increase in overall integrated circuit density. However, integrated circuit density continues to be limited by the “real estate” available for mounting individual integrated circuits on a substrate.

0003Even larger form factor systems, such as personal computers, compute servers, and storage servers, need more integrated circuits in the same or smaller “real estate”. Particularly acute, the needs for portable personal electronics, such as cell phones, digital cameras, music players, personal digital assistants, and location-based devices, have further driven the need for integrated circuit density.

0004This increased integrated circuit density has led to the development of multi-chip packages, a package in package (PIP), a package on package (POP), or a combination thereof in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry.

0005Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a substrate onto which a set of separate integrated circuit components are attached. Such multi-chip packages have been found to increase integrated circuit density and miniaturization, improve signal propagation speed, reduce overall integrated circuit size and weight, improve performance, and lower costs all of which are primary goals of the computer industry.

0006However, PIP and POP products encounter various problems. The process of stacking integrated circuit packages can suffer from yield and reliability issues due to misalignment of connecting electrical contacts. As the pitch of the electrical interconnect such as solder balls or solder bumps, decreases, misalignment of electrical connections becomes an increasing problem affecting the yield, reliability, and cost of the end product.

0007Thus, a need still remains for a stacked integrated circuit package system providing low cost manufacturing, improved yield, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.

0008Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

0009The present invention provides a stacked integrated circuit package system including: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.

0010Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0011<figref idref="DRAWINGS">FIG. 1</figref> is a top view of a stacked integrated circuit package system in a first embodiment of the present invention;

0012<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of the stacked integrated circuit package system along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref>;

0013<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a stacked integrated circuit package system exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a second embodiment of the present invention;

0014<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a stacked integrated circuit package system exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a third embodiment of the present invention;

0015<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of a stacked integrated circuit package system exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a fourth embodiment of the present invention;

0016<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view of a lead frame;

0017<figref idref="DRAWINGS">FIG. 7</figref> is the structure of <figref idref="DRAWINGS">FIG. 6</figref> in forming conductive sites and the mounting structure over the lead frame;

0018<figref idref="DRAWINGS">FIG. 8</figref> is the structure of <figref idref="DRAWINGS">FIG. 7</figref> in connecting the first integrated circuit die and the conductive sites;

0019<figref idref="DRAWINGS">FIG. 9</figref> is the structure of <figref idref="DRAWINGS">FIG. 8</figref> in forming the first encapsulation;

0020<figref idref="DRAWINGS">FIG. 10</figref> is the structure of <figref idref="DRAWINGS">FIG. 9</figref> in forming the recessed integrated circuit package system of <figref idref="DRAWINGS">FIG. 2</figref>;

0021<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of a carrier strip;

0022<figref idref="DRAWINGS">FIG. 12</figref> is the structure of <figref idref="DRAWINGS">FIG. 11</figref> in mounting the second integrated circuit over the carrier strip;

0023<figref idref="DRAWINGS">FIG. 13</figref> is the structure of <figref idref="DRAWINGS">FIG. 12</figref> in connecting the second integrated circuit and the carrier strip, and forming the external interconnects;

0024<figref idref="DRAWINGS">FIG. 14</figref> is the structure of <figref idref="DRAWINGS">FIG. 13</figref> in forming the second encapsulation;

0025<figref idref="DRAWINGS">FIG. 15</figref> is the structure of <figref idref="DRAWINGS">FIG. 14</figref> in forming the stacked integrated circuit package system of <figref idref="DRAWINGS">FIG. 2</figref>; and

0026<figref idref="DRAWINGS">FIG. 16</figref> is a flow chart of a stacked integrated circuit package system for manufacturing of the stacked integrated circuit package system in an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

0027The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.

0028In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGS. Generally, the invention can be operated in any orientation.

0029In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features from one to another will ordinarily be described with like reference numerals. The embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for the present invention.

0030For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.

0031Referring now to <figref idref="DRAWINGS">FIG. 1</figref>, therein is shown a top view of a stacked integrated circuit package system <b>100</b> in a first embodiment of the present invention. The top view depicts a first encapsulation <b>102</b>, such as an epoxy molding compound.

0032Referring now to <figref idref="DRAWINGS">FIG. 2</figref>, therein is shown a cross-sectional view of the stacked integrated circuit package system <b>100</b> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref>. The cross-sectional view depicts a recessed integrated circuit package system <b>206</b> mounted over a mountable integrated circuit package system <b>208</b>.

0033The recessed integrated circuit package system <b>206</b> includes a first integrated circuit <b>210</b>, such as an integrated circuit die, covered by the first encapsulation <b>102</b>. The first integrated circuit <b>210</b> has a first non-active side <b>212</b> and a first active side <b>214</b>, wherein the first active side <b>214</b> includes active circuitry fabricated thereon. In this example, a mounting structure <b>216</b>, such as a die paddle including gold, can be between the first non-active side <b>212</b> of the first integrated circuit <b>210</b> and a die attach layer <b>218</b>, such as a die-attach adhesive.

0034In the central portion of the recessed integrated circuit package system <b>206</b>, an interior cavity <b>220</b> can be underneath the die attach layer <b>218</b>. First internal interconnects <b>222</b>, such as bond wires or ribbon bond wires, can connect between the first active side <b>214</b> of the first integrated circuit <b>210</b> and conductive sites <b>224</b>, also covered by the first encapsulation <b>102</b>.

0035At a periphery portion of the recessed integrated circuit package system <b>206</b>, peripheral cavities <b>226</b> can be underneath the conductive sites <b>224</b>, such as terminals, of the recessed integrated circuit package system <b>206</b>. Walls <b>228</b> of the peripheral cavities <b>226</b> can be in different configurations. For example, the walls <b>228</b> can be vertical or non-vertical sloped, as depicted with dotted lines, with a wider opening at the bottom portion of the peripheral cavities <b>226</b>.

0036The first encapsulation <b>102</b> also cover the first internal interconnects <b>222</b>. The first encapsulation <b>102</b> partially covers the mounting structure <b>216</b> exposing a portion thereof with the interior cavity <b>220</b>. The first encapsulation <b>102</b> also partially covers the conductive sites <b>224</b> exposing a portion thereof with the peripheral cavities <b>226</b>.

0037The mountable integrated circuit package system <b>208</b> includes a second integrated circuit <b>230</b>, such as an integrated circuit die, over a carrier <b>204</b>, such as a laminated substrate. The second integrated circuit <b>230</b> also has a second non-active side <b>234</b> and a second active side <b>232</b>, wherein the second active side <b>232</b> includes active circuitry fabricated thereon. In this example, the second non-active side <b>234</b> faces the carrier <b>204</b>.

0038Second internal interconnects <b>236</b>, such as bond wires or ribbon bond wires, can connect between the second active side <b>232</b> of the second integrated circuit <b>230</b> and a top side <b>238</b> of the carrier <b>204</b>. A second encapsulation <b>240</b>, such as a cover of epoxy molding compound, can cover the second integrated circuit <b>230</b> and the second internal interconnects <b>236</b> over the carrier <b>204</b>. The second encapsulation <b>240</b> of the mountable integrated circuit package system <b>208</b> can be within the interior cavity <b>220</b> of the recessed integrated circuit package system <b>206</b>.

0039Stacking interconnects <b>242</b>, such as solder balls, can connect the recessed integrated circuit package system <b>206</b> and the mountable integrated circuit package system <b>208</b>. The stacking interconnects <b>242</b> can couple the top side <b>238</b> of the carrier <b>204</b> and the conductive sites <b>224</b>. The stacking interconnects <b>242</b> are preferably within the peripheral cavities <b>226</b>. A conductive structure <b>244</b>, such as solder printing or solder paste, can couple the conductive sites <b>224</b> and the stacking interconnects <b>242</b>.

0040As an example, the interior cavity <b>220</b> includes an interior height <b>246</b> from the mounting structure <b>216</b> to the top side <b>238</b> of the carrier <b>204</b>. Also as an example, the peripheral cavities <b>226</b> include a peripheral height <b>248</b> from the conductive structure <b>244</b> to the top side <b>238</b> of the carrier <b>204</b>.

0041For illustrative purposes, the stacked integrated circuit package system <b>100</b> is shown with the interior cavity <b>220</b> different from the peripheral height <b>248</b>, although it is understood that the interior height <b>246</b> and the peripheral height <b>248</b> can be different from shown. For example, the interior height <b>246</b> and the peripheral height <b>248</b> can be the same height or reversed height value relative to each other.

0042The first encapsulation <b>102</b> and the second encapsulation <b>240</b> can expose a bottom side <b>250</b> of the carrier <b>204</b>. External interconnects <b>252</b>, such as solder balls, can be attached below and to the carrier <b>204</b> for connection to the next system level (not shown), such as a printed circuit board or another stacked integrated circuit package system.

0043It has been discovered that the present invention provides thin profile package by placing the second integrated circuit and the second encapsulation within the interior cavity of the first encapsulation. This feature can reduce the total height of the stacked integrated circuit package system.

0044It has also been discovered that in the present invention, the non-vertical walls of the peripheral cavities for the stacking interconnects of the recessed integrated circuit package system can facilitate faster and more reliable inspection of interconnects during the manufacturing process. This feature can further reduce manufacturing cost and increase reliability. The non-vertical walls can also help alignment of the recessed integrated circuit package system and the mountable integrated circuit package system.

0045Referring now to <figref idref="DRAWINGS">FIG. 3</figref>, therein is shown a cross-sectional view of a stacked integrated circuit package system <b>300</b> exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a second embodiment of the present invention. The stacked integrated circuit package system <b>300</b> includes structural similarities to the stacked integrated circuit package system <b>100</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The cross-sectional view depicts a recessed integrated circuit package system <b>306</b> mounted over a mountable integrated circuit package system <b>308</b>.

0046The recessed integrated circuit package system <b>306</b> includes a first integrated circuit <b>310</b>, such as an integrated circuit die, covered by a first encapsulation <b>302</b>. In this example, a mounting structure <b>316</b>, such as a die paddle including gold, can be between the first integrated circuit <b>310</b> and a die attach layer <b>318</b>.

0047In the central portion of the recessed integrated circuit package system <b>306</b>, an interior cavity <b>320</b> can be underneath the die attach layer <b>318</b>. First internal interconnects <b>322</b> can connect between the first integrated circuit <b>310</b> and conductive sites <b>324</b>, also covered by the first encapsulation <b>302</b>.

0048At a periphery portion of the recessed integrated circuit package system <b>306</b>, peripheral cavities <b>326</b> can be underneath the conductive sites <b>324</b>, such as terminals, of the recessed integrated circuit package system <b>306</b>. Walls <b>328</b> of the peripheral cavities <b>326</b> can be in different configurations. For example, the walls <b>328</b> can be vertical or non-vertical sloped, as depicted with dotted lines, with a wider opening at the bottom portion of the peripheral cavities <b>326</b>.

0049The first encapsulation <b>302</b> also cover the first internal interconnects <b>322</b>. The first encapsulation <b>302</b> partially covers the mounting structure <b>316</b> exposing a portion thereof with the interior cavity. The first encapsulation <b>302</b> also partially covers the conductive sites <b>324</b> exposing a portion thereof with the peripheral cavities <b>326</b>.

0050The mountable integrated circuit package system <b>308</b> includes a second integrated circuit <b>330</b>, such as a flip chip, over a carrier <b>304</b>, such as a laminated substrate. Second internal interconnects <b>336</b>, such as solder bumps, can connect between the second integrated circuit <b>330</b> and a top side <b>338</b> of the carrier <b>304</b>. An underfill <b>354</b> can surround the second internal interconnects <b>336</b> between the second integrated circuit <b>330</b> and the carrier <b>304</b>.

0051A second encapsulation <b>340</b>, such as a cover of epoxy molding compound, can cover the second integrated circuit <b>330</b> and the second internal interconnects <b>336</b> over the carrier <b>304</b>. The second encapsulation <b>340</b> of the mountable integrated circuit package system <b>308</b> can be within the interior cavity <b>320</b> of the recessed integrated circuit package system <b>306</b>. The second encapsulation <b>340</b> can be optional in which case, the second integrated circuit <b>330</b> can be within the interior cavity <b>320</b>.

0052Stacking interconnects <b>342</b>, such as solder balls, can connect the recessed integrated circuit package system <b>306</b> and the mountable integrated circuit package system <b>308</b>. The stacking interconnects <b>342</b> can couple the top side <b>338</b> of the carrier <b>304</b> and the conductive sites <b>324</b>. The stacking interconnects <b>342</b> are preferably within the peripheral cavities <b>326</b>. A conductive structure <b>344</b>, such as solder printing or solder paste, can couple the conductive sites <b>324</b> and the stacking interconnects <b>342</b>.

0053As an example, the interior cavity <b>320</b> includes an interior height <b>346</b> from the mounting structure <b>316</b> to the top side <b>338</b> of the carrier <b>304</b>. Also as an example, the peripheral cavities <b>326</b> include a peripheral height <b>348</b> from the conductive structure <b>344</b> to the top side <b>338</b> of the carrier <b>304</b>.

0054For illustrative purposes, the stacked integrated circuit package system <b>300</b> is shown with the interior cavity <b>320</b> different from the peripheral height <b>348</b>, although it is understood that the interior height <b>346</b> and the peripheral height <b>348</b> can be different from shown. For example, the interior height <b>346</b> and the peripheral height <b>348</b> can be the same height or reversed height value relative to each other.

0055The first encapsulation <b>302</b> and the second encapsulation <b>340</b> can expose a bottom side <b>350</b> of the carrier <b>304</b>. External interconnects <b>352</b>, such as solder balls, can be attached below and to the carrier <b>304</b> for connection to the next system level (not shown), such as a printed circuit board or another stacked integrated circuit package system.

0056Referring now to <figref idref="DRAWINGS">FIG. 4</figref>, therein is shown a cross-sectional view of a stacked integrated circuit package system <b>400</b> exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a third embodiment of the present invention. The stacked integrated circuit package system <b>400</b> includes structural similarities to the stacked integrated circuit package system <b>100</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The cross-sectional view depicts a recessed integrated circuit package system <b>406</b> mounted over a mountable integrated circuit package system <b>408</b>.

0057The recessed integrated circuit package system <b>406</b> includes a first integrated circuit <b>410</b>, such as an integrated circuit die, covered by a first encapsulation <b>402</b>. In this example, a mounting structure <b>416</b>, such as a die paddle including gold, can be between the first integrated circuit <b>410</b> and a die attach layer <b>418</b>.

0058In the central portion of the recessed integrated circuit package system <b>406</b>, an interior cavity <b>420</b> can be underneath the die attach layer <b>418</b>. First internal interconnects <b>422</b>, such as bond wires or ribbon bond wires, can connect between the first integrated circuit <b>410</b> and conductive sites <b>424</b>, also covered by the first encapsulation <b>402</b>.

0059The first encapsulation <b>402</b> also cover the first internal interconnects <b>422</b>. The first encapsulation <b>402</b> partially covers the mounting structure <b>416</b> exposing a portion thereof with the interior cavity <b>420</b>. The first encapsulation <b>402</b> also partially covers the conductive sites <b>424</b> exposing a portion thereof with peripheral cavities <b>426</b>. At a periphery portion of the recessed integrated circuit package system <b>406</b>, the conductive sites <b>424</b> can connect the recessed integrated circuit package system <b>406</b> and a carrier <b>404</b> of the mountable integrated circuit package system <b>408</b>. As an example, the recessed integrated circuit package system <b>406</b> can connect onto the carrier <b>404</b>.

0060The mountable integrated circuit package system <b>408</b> includes a second integrated circuit <b>430</b>, such as an integrated circuit die, over the carrier <b>404</b>. Second internal interconnects <b>436</b> can connect between the second integrated circuit <b>430</b> and a top side <b>438</b> of the carrier <b>404</b>. A second encapsulation <b>440</b> can cover the second integrated circuit <b>430</b> and the second internal interconnects <b>436</b> over the carrier <b>404</b>. The second encapsulation <b>440</b> of the mountable integrated circuit package system <b>408</b> can be within the interior cavity <b>420</b>. As an example, the interior cavity <b>420</b> includes an interior height <b>446</b> from the mounting structure <b>416</b> to the top side <b>438</b> of the carrier <b>404</b>.

0061The first encapsulation <b>402</b> and the second encapsulation <b>440</b> can expose a bottom side <b>450</b> of the carrier <b>404</b>. External interconnects <b>452</b>, such as solder balls, can be attached below and to the carrier <b>404</b> for connection to the next system level (not shown), such as a printed circuit board or another stacked integrated circuit package system.

0062Referring now to <figref idref="DRAWINGS">FIG. 5</figref>, therein is shown a cross-sectional view of a stacked integrated circuit package system <b>500</b> exemplified by the top view of <figref idref="DRAWINGS">FIG. 1</figref> along line <b>2</b>-<b>2</b> of <figref idref="DRAWINGS">FIG. 1</figref> in a fourth embodiment. The stacked integrated circuit package system <b>500</b> includes structural similarities to the stacked integrated circuit package system <b>300</b> of <figref idref="DRAWINGS">FIG. 3</figref>. The cross-sectional view depicts a recessed integrated circuit package system <b>506</b> mounted over a mountable integrated circuit package system <b>508</b>.

0063The recessed integrated circuit package system <b>506</b> includes a first integrated circuit <b>510</b>, such as an integrated circuit die, covered by a first encapsulation <b>502</b>. In this example, a mounting structure <b>516</b>, such as a die paddle including gold, can be between the first integrated circuit <b>510</b> and a die attach layer <b>518</b>.

0064In the central portion of the recessed integrated circuit package system <b>506</b>, an interior cavity <b>520</b> can be underneath the die attach layer <b>518</b>. First internal interconnects <b>522</b>, such as bond wires or ribbon bond wires, can connect between the first integrated circuit <b>510</b> and conductive sites <b>524</b>, also covered by the first encapsulation <b>502</b>.

0065The first encapsulation <b>502</b> also cover the first internal interconnects <b>522</b>. The first encapsulation <b>502</b> partially covers the mounting structure <b>516</b> exposing a portion thereof with the interior cavity <b>520</b>. The first encapsulation <b>502</b> also partially covers the conductive sites <b>524</b> exposing a portion thereof with peripheral cavities <b>526</b>. At a periphery portion of the recessed integrated circuit package system <b>506</b>, the conductive sites <b>524</b> can connect the recessed integrated circuit package system <b>506</b> and a carrier <b>504</b> of the mountable integrated circuit package system <b>508</b>. As an example, the recessed integrated circuit package system <b>506</b> can connect onto the carrier <b>504</b>.

0066The mountable integrated circuit package system <b>508</b> includes a second integrated circuit <b>530</b>, such as a flip chip, over the carrier <b>504</b>, such as a laminated substrate. Second internal interconnects <b>536</b>, such as solder bumps, can connect between the second integrated circuit <b>530</b> and a top side <b>538</b> of the carrier <b>504</b>. An underfill <b>554</b> can surround the second internal interconnects <b>536</b> between the second integrated circuit <b>530</b> and the carrier <b>504</b>.

0067A second encapsulation <b>540</b>, such as a cover of epoxy molding compound, can cover the second integrated circuit <b>530</b> and the second internal interconnects <b>536</b> over the carrier <b>504</b>. The second encapsulation <b>540</b> of the mountable integrated circuit package system <b>508</b> can be within the interior cavity <b>520</b> of the recessed integrated circuit package system <b>506</b>. The second encapsulation <b>540</b> can be optional in which case, the second integrated circuit <b>530</b> can be within the interior cavity <b>520</b>. As an example, the interior cavity <b>520</b> includes an interior height <b>546</b> from the mounting structure <b>516</b> to the top side <b>538</b> of the carrier <b>504</b>.

0068The first encapsulation <b>502</b> and the second encapsulation <b>540</b> can expose a bottom side <b>550</b> of the carrier <b>504</b>. External interconnects <b>552</b>, such as solder balls, can be attached below and to the carrier <b>504</b> for connection to the next system level (not shown), such as a printed circuit board or another stacked integrated circuit package system.

0069Referring now to <figref idref="DRAWINGS">FIG. 6</figref>, therein is shown a cross-sectional view of a lead frame <b>602</b>. The cross-sectional view depicts the lead frame <b>602</b> including a central portion <b>654</b> and a periphery portion <b>656</b> extending from a base <b>658</b>. A center height <b>660</b> of the central portion <b>654</b> can be higher than an outer height <b>662</b> of the periphery portion <b>656</b>. The material of the lead frame <b>602</b>, in this example, can be copper.

0070It has been discovered that the present invention provides lower cost manufacturing process by using copper lead frame. Copper lead frame can be removed by a number of low cost means, including chemical etching.

0071Referring now to <figref idref="DRAWINGS">FIG. 7</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 6</figref> in forming the conductive sites <b>224</b> and the mounting structure <b>216</b> over the lead frame <b>602</b>. Conductive material, such as gold, is placed, such as plating, over the periphery portion <b>656</b> to form the conductive sites <b>224</b> and over the central portion <b>654</b> to form the mounting structure <b>216</b>.

0072For illustrative purposes, the conductive material is not shown between the periphery portion <b>656</b> and the central portion <b>654</b>. Although it is understood that the conductive material used for forming the conductive sites <b>224</b> and the mounting structure <b>216</b> can be formed between the periphery portion <b>656</b> and the central portion <b>654</b>.

0073Referring now to <figref idref="DRAWINGS">FIG. 8</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 7</figref> in connecting the first integrated circuit <b>210</b> and the conductive sites <b>224</b>. The first integrated circuit <b>210</b> can mount over the mounting structure <b>216</b> with the die attach layer <b>218</b> in between and over the central portion <b>654</b>. The first internal interconnects <b>222</b> can connect between the first integrated circuit <b>210</b> and the conductive sites <b>224</b> over the periphery portion <b>656</b>.

0074Referring now to <figref idref="DRAWINGS">FIG. 9</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 8</figref> in forming the first encapsulation <b>102</b>. The first encapsulation <b>102</b> can be formed over the lead frame <b>602</b> covering the first integrated circuit <b>210</b> and the first internal interconnects <b>222</b>. The first encapsulation <b>102</b> does not cover the portion of the conductive sites <b>224</b> facing the periphery portion <b>656</b> and the portion of the mounting structure <b>216</b> facing the central portion <b>654</b>.

0075Referring now to <figref idref="DRAWINGS">FIG. 10</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 9</figref> in forming the recessed integrated circuit package system <b>206</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The lead frame <b>602</b> of <figref idref="DRAWINGS">FIG. 9</figref> can be removed by a number of processes, such as chemical etching, to form the interior cavity <b>220</b> in the central portion of the first encapsulation <b>102</b> and to form the peripheral cavities <b>226</b> on the periphery of the first encapsulation <b>102</b>. The interior height <b>246</b> of the interior cavity <b>220</b> can be formed from the center height <b>660</b> of <figref idref="DRAWINGS">FIG. 6</figref> of the central portion <b>654</b> of <figref idref="DRAWINGS">FIG. 6</figref> of the lead frame <b>602</b>. The peripheral height <b>248</b> of the peripheral cavities <b>226</b> can be formed from the outer height <b>662</b> of <figref idref="DRAWINGS">FIG. 6</figref> of the periphery portion <b>656</b> of <figref idref="DRAWINGS">FIG. 6</figref> of the lead frame <b>602</b>.

0076Referring now to <figref idref="DRAWINGS">FIG. 11</figref>, therein is shown a cross-sectional view of a carrier strip <b>1102</b>. The cross-sectional view depicts an adhesive <b>1164</b>, such as a die attach adhesive, over the carrier strip <b>1102</b>. For illustrative purposes, the adhesive <b>1164</b> is shown over the carrier strip <b>1102</b>, although it is understood that the carrier strip <b>1102</b> can have multiple instantiations of the adhesive <b>1164</b>.

0077Referring now to <figref idref="DRAWINGS">FIG. 12</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 11</figref> in mounting the second integrated circuit <b>230</b> over the carrier strip <b>1102</b>. The second integrated circuit <b>230</b> can mount over the carrier strip <b>1102</b> with the adhesive <b>1164</b>. For illustrative purposes, the second integrated circuit <b>230</b> is shown over the carrier strip <b>1102</b>, although it is understood that the carrier strip <b>1102</b> can have multiple instantiations of the second integrated circuit <b>230</b>.

0078Referring now to <figref idref="DRAWINGS">FIG. 13</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 12</figref> in connecting the second integrated circuit <b>230</b> and the carrier strip <b>1102</b>, and forming the external interconnects <b>252</b>. The second internal interconnects <b>236</b> can connect the second integrated circuit <b>230</b> and the carrier strip <b>1102</b>. The external interconnects <b>252</b> can attach below and to the carrier strip <b>1102</b>.

0079Referring now to <figref idref="DRAWINGS">FIG. 14</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 13</figref> in forming the second encapsulation <b>240</b>. The second encapsulation <b>240</b> can be formed over the carrier strip <b>1102</b> to cover the second integrated circuit <b>230</b> and the second internal interconnects <b>236</b>. The second encapsulation <b>240</b> can partially expose the carrier strip <b>1102</b>. The carrier strip <b>1102</b> can be singulated forming the mountable integrated circuit package system <b>208</b> of <figref idref="DRAWINGS">FIG. 2</figref>.

0080Referring now to <figref idref="DRAWINGS">FIG. 15</figref>, therein is shown the structure of <figref idref="DRAWINGS">FIG. 14</figref> in forming the stacked integrated circuit package system <b>100</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The recessed integrated circuit package system <b>206</b>, shown in <figref idref="DRAWINGS">FIG. 10</figref>, can mount over the mountable integrated circuit package system <b>208</b>. An interconnect structure <b>1566</b>, such as solder on pad, solder printing, or solder paste, can be formed under the conductive sites <b>224</b>. The stacking interconnects <b>242</b> can be formed over the carrier <b>204</b>.

0081The recessed integrated circuit package system <b>206</b> can mount over the mountable integrated circuit package system <b>208</b>. The second encapsulation <b>240</b> can mount within the interior cavity <b>220</b> of the recessed integrated circuit package system <b>206</b>. The stacking interconnects <b>242</b> fit within the peripheral cavities <b>226</b> of the recessed integrated circuit package system <b>206</b>. The interconnect structure <b>1566</b> can form the conductive structure <b>244</b> of <figref idref="DRAWINGS">FIG. 2</figref>.

0082Referring now to <figref idref="DRAWINGS">FIG. 16</figref>, therein is shown a flow chart of a stacked integrated circuit package system <b>1600</b> for manufacturing of the stacked integrated circuit package system <b>100</b> in an embodiment of the present invention. The system <b>1600</b> includes forming a recessed integrated circuit package system having a first encapsulation over the first integrated circuit and an interior cavity in the first encapsulation in a block <b>1602</b>; forming a mountable integrated circuit package system having a second integrated circuit over a carrier in a block <b>1604</b>; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier in a block <b>1606</b>.

0083Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.

0084These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.

0085Thus, it has been discovered that the stacked integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, and reducing cost of circuit system. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.

0086While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.