Method and apparatus for rasterizer interpolation

This application is a continuation application of U.S. Application Ser. No. 10/730,864 filed Dec. 8, 2003, now U.S. Pat. No. 7,061,495, which is a continuation application of U.S. application Ser. No. 10/716,590 filed Nov. 18, 2003, now abandoned, which claims priority to U.S. Provisional Application No. 60/427,260, filed Nov. 18, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates computer graphics. More specifically, one or more embodiments of the present invention relate to a rasterizer interpolator.

Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.

2. Background Art

Display images are made up of thousands of tiny dots, where each dot is one of thousands or millions of colors. These dots are known as picture elements, or “pixels”. A raster is a grid of x and y coordinates in a two dimensional display space, and in a three dimensional display space includes a “z” coordinate. A rasterizer is used to operate on pixels or sub-pixels within the raster grid in order to determine a final color values for the pixels. As will be further explained below, current rasterizers are inefficient. This problem can be better understood by reviewing an example of a graphics systems where a rasterizer might be used.

Graphics System

Each pixel in a raster environment has multiple attributes associated with it, including a color and a texture. The color of each pixel being represented by a number value stored in the computer system. A three dimensional display image, although displayed using a two dimensional array of pixels, may in fact be created by rendering of a plurality of graphical objects.

Examples of graphical objects include points, lines, polygons, and three dimensional solid objects. Points, lines, and polygons represent rendering “primitives” which are the basis for most tendering instructions. More complex structures, such as three dimensional objects, are formed from a combination or mesh of such primitives. To display a particular scene, the visible primitives associated with the scene are drawn individually by determining those pixels that fall within the edges of the primitive, and obtaining the attributes of the primitive that correspond to each of those pixels. The obtained attributes are used to determine the displayed color values of applicable pixels.

Sometimes, a three dimensional display image is formed from overlapping primitives or surfaces. A blending function based on an opacity value associated with each pixel of each primitive is used to blend the colors of overlapping surfaces or layers when the top surface is not completely opaque. The final displayed color of an individual pixel may thus be a blend of colors from multiple surfaces or layers.

In some cases, graphical data is rendered by executing instructions from an application that is drawing data to a display. During image rendering, three dimensional data is processed into a two dimensional image suitable for display. The three dimensional image data represents attributes such as color, opacity, texture, depth, and perspective information. The draw commands from a program drawing to the display may include, for example, X and Y coordinates for the vertices of the primitive, as well as some attribute parameters for the primitive (color and depth or “Z” data), and a drawing command. The execution of drawing commands to generate a display image is known as graphics processing.

Rasterizers

Graphics processing is typically performed with a rasterizer. A rasterizer receives pixels as input and may perform a scan conversion process on the pixels, apply textures to the pixels, apply color to the pixels, and shade the pixels by mathematically combining all of the results of the scanning, coloring, and texturing into a single final value for a pixel. This final value is typically output to a frame buffer which is configured to store the value temporarily and to provide it to the display device for drawing at the appropriate time.

The manner in which work is distributed to a rasterizer is currently inadequate. In particular, regions of a display screen are typically arranged into tiles. The tiles are used as a way to organize how and when a screen region of pixels will be passed to the rasterizer. One technique uses a rasterizer and arranges the screen into tiles. As geometric primitives are calculated and it is determined where the geometry falls on the screen, a determination is made as to which tiles have which portions of the geometry.

This is shown by example in <figref idref="DRAWINGS">FIG. 1</figref>. The screen <b>100</b> is divided into four tiles, tile <b>0</b>, tile <b>1</b>, tile <b>2</b>, and tile <b>3</b>. Geometry <b>110</b> (in this instance a triangle) is partially owned by tiles <b>0</b>, <b>1</b>, and <b>2</b>. Rasterizer <b>120</b> receives the tiles (and hence the portions of the geometry) in order (i.e., tile <b>0</b>, then tile <b>1</b>, then tile <b>2</b>). Problems occur, however, because this method is slow since it only rasterizers one tile at a time.

Another common rasterizer implementation uses elongated tiles such as that shown in <figref idref="DRAWINGS">FIG. 2</figref>. Elongated tile <b>200</b> has a 4×2 configuration. Narrow vertical line <b>210</b> (the geometry to be rendered) only passes through sub-tiles <b>220</b> and <b>230</b>. However, this method has its problems because the tile size is not scaleable and, because of the elongated tile size, many empty tiles with no geometry are processed by the rasterizer, causing waste in time and computational power.

What is needed is a rasterization mechanism that is scaleable and efficient in minimizing wasted power spent on processing empty tiles.

SUMMARY OF THE INVENTION

The present invention relates to a rasterizer interpolator. The rasterizer interpolator comprises of a setup unit that computes coverage of incoming graphics primitives, and a plurality of rasterizer pipelines. Based on the calculation using the primitive's (polygon) vertex data against one or more tiles, graphics primitives are distributed to the rasterizers arrayed in parallel. Each rasterizer is configured to perform its operation at the same time as the other rasterizers. In one embodiment, an output screen is divided into a number of regions. For instance, in one embodiment, the screen is sub-divided into four regions, and one of four rasterizers is granted ownership of one quarter of the total screen. The present invention interpolates primitives for various number of parallel rasterizer pipelines in various configurations. In various embodiments, the size of the tiles is configurable. In one embodiment, the tiles are square tiles.

The present invention also comprises of a scan converter working in conjunction with a Hierarchical-Z unit in a z-buffer to perform coarse grain tiling. Coarse grain tiling occurs by a series of iterations performed in parallel. Each region undergoes a tiling process where each tile is reduced to a smaller set of sub-tiles, with the goal of reducing time spent on processing empty tiles and/or non-visible tiles with no graphics primitive coverage. With each successive iteration, a finer level of precision is reached. The scan converter communicates with the Hierarchical-Z unit to calculate the current primitive's visibility, using vertex data from the graphics primitive and z depth information. Briefly, in one embodiment, the process starts with computing a list of tiles that are in a current pipeline and covered by a current graphics primitive. Then a first mask value is generated, with the value specifying which of intermediate (smaller) tiles within each of the tiles on the list are visible. Then the process generates a sub-list containing even smaller quad tiles within the intermediate tiles. Following this, a second mask value is computed, with the value specifying which of quad tiles are visible and a z plane equation. The final result is that primitive's (polygon) coverage is calculated at a detailed level, reducing empty tiles slated for rasterization and thus improving efficiency.

Another embodiment increases raster efficiency by assigning the ownership of tiles in a non-contiguous manner. For instance, a two-raster system might assign every other tile to one of the rasters. This scheme decreases the likelihood that one raster will run out of work (or have no work at all) while the other raster is busy operating on a dense screen region.

Another embodiment of the present invention uses multiple graphics chips, with each chip having multiple parallel rasterizers. The screen is divided into regions and each chip is responsible for a particular region. In one embodiment, a super tiling technique is used to manage the distribution of tiles across multiple graphics chips. In this manner, geometry in each region, adjacent pixels are cached in the chip closest to their neighbors. This embodiment increases cache locality, and hence the efficiency of the tiling process.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where:

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of the operation of a prior art tiling scheme.

<figref idref="DRAWINGS">FIG. 2</figref> shows a problem inherent in one prior art tiling scheme.

<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart showing the operation of a rasterizer interpolator according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart showing the operation of a rasterizer interpolator according to another embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> is an architecture for rasterizer interpolation according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 6</figref> shows a setup unit according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 7</figref> shows a setup unit interfacing with four raster pipes according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8A</figref> shows a tile configuration according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8B</figref> shows a tile configuration according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8C</figref> shows a tile configuration according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8D</figref> shows a tile configuration according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8E</figref> shows a tile configuration according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 9</figref> shows an architecture suitable for super tiling according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10A</figref> shows a scan conversion process according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10B</figref> shows a Hierarchical-Z operation according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10C</figref> shows a second pass of a scan conversion process according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10D</figref> shows the process of coarse grain tiling operation with a scan conversion and Hierarchical-Z unit according to an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 11</figref> is an embodiment of a computer execution environment.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to a rasterizer interpolator. In the following description, numerous specific details are set forth to provide a more thorough description of embodiments of the invention. It will be apparent, however, to one skilled in the art, that the invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the invention.

Rasterizer Interpolation

In one embodiment, multiple parallel rasterizers are used. Each rasterizer is configured to perform its operation at the same time as the other rasterizers, each one executing one or more instructions in each clock cycle. An output screen is divided into a number of regions. For instance, in one embodiment, the screen is sub-divided into four regions and one of four rasterizers is granted ownership of each of the regions. In this way, tiles are interpolated to the appropriate pipelines.

Coarse grain tiling occurs by a series of iterations performed in parallel. Each region undergoes a tiling process where each tile is reduced to a 2×2 set of sub-tiles. With each successive iteration, another 2×2 level of precision is reached. By tiling in this manner, the number of empty tiles is minimized. The operation of this embodiment of the present invention is shown in the flowchart of <figref idref="DRAWINGS">FIG. 3</figref>. At step <b>300</b>, a screen region is divided into a number of regions. At step <b>310</b>, each of the regions is assigned to a rasterizer. At step <b>320</b>, geometry information is determined. The geometry information relates to the slopes and vertices of a geometric figure that is eventually to be rendered on the screen. By obtaining the geometric information, it is known which regions have which portions of the geometry.

Once the geometric information is determined at step <b>320</b>, it is determined whether the tiling process should repeat into smaller sub-tiles at step <b>330</b>. If not, the process is complete and the geometry is drawn to the screen at step <b>350</b>. Otherwise, each tile in the region is subdivided into a set of smaller 2×2 dies at step <b>340</b>. This process repeats at step <b>330</b> until the desired level of granularity is reached, wherein the geometry is eventually drawn to the screen at step <b>350</b>.

Another embodiment increases raster efficiency by assigning the ownership of tiles in a non-contiguous manner. For instance, a two-raster system might assign every other tile to one of the rasters. This scheme decreases the likelihood that one raster will run out of work (or have no work at all) while the other raster is busy operating on a dense screen region. The operation of this embodiment is shown in <figref idref="DRAWINGS">FIG. 4</figref>.

At step <b>400</b>, a screen region is divided into a number of regions. At step <b>410</b>, each of the regions is assigned to a rasterizer in a non-contiguous manner. At step <b>420</b>, geometry information is determined. Once the geometric information is determined at step <b>420</b>, it is determined at step <b>430</b> whether the tiling process should repeat into smaller sub-tiles. If not, the process is complete and the geometry is rendered to the screen at step <b>450</b>. Otherwise, each tile in the region is subdivided into a set of smaller 2×2 tiles at step <b>440</b>. This process repeats until the desired level of granularity is reached, wherein the geometry is eventually drawn to the screen at step <b>450</b>.

Rasterizer Interpolation Architecture

One embodiment of a rasterizer interpolation architecture is shown in <figref idref="DRAWINGS">FIG. 5</figref>. In operation, incoming triangle list data comes in through a data stream <b>512</b> into a set-up unit <b>515</b>. Set-up unit <b>515</b> generates slope and initial value information for each of the texture coordinate, color, or Z parameters associated with the primitive. The resulting set-up information is passed to one or more parallel pipelines. In the current example there are two pipelines, pipeline <b>520</b> and pipeline <b>525</b>, but the present invention contemplates any configuration of parallel pipelines. In this example, each pipeline owns one-half of the screen's pixels. In another example, there are four pipelines and each pipeline would own one-quarter of the screen's pixels. Allocation of work between the pipelines is made based on a repeating square pixel tile pattern. In one embodiment, logic <b>530</b> in the set-up unit <b>515</b> intersects the graphics primitives with the tile pattern such that a primitive is only sent to a pipeline if it is likely that it will result in the generation of covered pixels. The setup unit is thus responsible for determining which of the raster pipes will receive the computed polygon information.

Each pipeline operates on four pixels at a time, the four pixels are arranged in a 2×2 tile (called a “quad”). Each pipeline contains an input FIFO used to balance the load over different pipelines. A scan converter <b>540</b> steps through the geometry (e.g., triangle or parallelogram) within the bounds of the pipeline's tile pattern. In one embodiment, initial stepping is performed at a coarse level. For each of the coarse level tiles, a minimum (i.e., closest) Z value is computed. This is compared with the farthest Z value for the tile stored in a Hierarchical-Z buffer <b>550</b>. If the compare fails, the tile is rejected.

The Hierarchical-Z compare block <b>550</b> passes the coarse level tile and subdivides it into the quad's 2×2 pixel tiles. For each covered quad, the x and y screen coordinate is output, together with a sub-pixel coverage mask, and a z-plane equation (slope and a reference value at the center of the quad). The Z-buffer <b>555</b> copies the incoming quad coordinate, mask, and Z-plane to the output. In one embodiment, if top of pipe Z-buffering is enabled, this block performs Z-buffering on all of the covered samples, and modifies the coverage masks appropriately, discarding the quad if all mask bits are zero. Once the processing is completed, data is forwarded to other back-end components <b>570</b> including the frame buffer for display.

Set-Up Unit

With reference to the set-up unit <b>515</b> shown in <figref idref="DRAWINGS">FIG. 5</figref>, its interfaces and functionalities are described in conjunction with <figref idref="DRAWINGS">FIGS. 6-9</figref>. In <figref idref="DRAWINGS">FIG. 6</figref>, a single stream <b>600</b> is passed to the setup unit <b>610</b>, which generates slope and initial value information for each of the texture coordinate, color, or Z parameters associated with the primitive. The resulting setup information <b>611</b> is then passed to one or more pipelines. In this example there are four pipelines, labeled A-D, which transport the pixels to their associated rasterizers <b>615</b>, <b>620</b>, <b>625</b>, or <b>630</b>.

Each of the pipelines owns a logical screen area. For instance, if two pipelines are activated, then they each own one half of the screen pixels. The SU <b>610</b> contains logic by which it intersects the graphics primitives with the tile pattern that divides the screen so that a primitive is only sent to a pipeline if it is likely that it will result in the generation of covered pixels.

One embodiment of a setup unit interfacing with multiple raster pipes is shown in <figref idref="DRAWINGS">FIG. 7</figref>, where setup unit <b>700</b> communicates with four raster pipes labeled RP0, RP1, RP2, and RP3.

Tiling Scheme in Setup Unit

As mentioned before, the setup unit is responsible for determining which of the raster pipes will receive the computed polygon information. Five possible configurations are shown in <figref idref="DRAWINGS">FIGS. 8A-8E</figref>. <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> show four-pipe configurations <b>800</b> and <b>820</b>. <figref idref="DRAWINGS">FIGS. 8C and 8D</figref> show two-pipe configurations <b>830</b> and <b>840</b> and <figref idref="DRAWINGS">FIG. 8E</figref> shows a single pipe configuration <b>850</b>. The number of pipelines and the configuration of the pipelines (e.g., the configurations of <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> for a four pipe configuration) are dynamically configurable in the control of the setup unit. The actual physical pipelines do not need to be present, unless a pipe configuration setup requires it.

The tile size is also configurable. Tiles are not required to be square, but the sizes of the width (n) and height (m) are powers of 2 to ensure scalablility in the present invention. Each tile has a tile configuration register. The value stored in the tile configuration register will be the log₂of the width and height. Preferably, the size of the screen is an integer multiple of the size of the tile. The Tile RP0's upper coordinates <b>860</b>, <b>861</b>, <b>862</b>, <b>863</b>, and <b>864</b> are the locations (0,0) in (x,y) screen coordinates.

Per polygon, the setup unit will determine which types of tiles are covered in the current configuration for the current polygon. Once a coverage is computed, the computed polygon's values will be sent to the appropriate pipelines or pipelines. Below is an algorithm to compute tile coverage according to one embodiment of the present invention:

Compute V0.x.tile=V0.x&gt;&gt;n

Compute V1.x.tile=V1.x&gt;&gt;n

Compute V2.x.tile=V2.x&gt;&gt;n

Compute V0.y.tile=V0.y&gt;&gt;m

Compute V1.y.tile=V0.y&gt;&gt;m

Compute V2.y.tile=V2.y&gt;&gt;m

Tile (V0.RP) is determined to be the tile where (V0.x.tile, V0.y.tile) is located

Tile (V1.RP) is determined to be the tile where (V1.x.tile, V1.y.tile) is located

Tile (V2.RP) is determined to be the tile where (V2.x.tile, V2.y.tile) is located

Switch(# pipes)

For 1 Pipe:

Done, send polygon to pipe

For 2 Pipes: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0073">Config 0: If max(|v0.x.tile-v1.x.tile|, |v0.x.tile-v2.x.tile|, |v1.x.tile-v2.x.tile|)&gt;1, {RP0, RP1} are covered</li><li id="ul0002-0002" num="0074">Config 1: If max(|v0.y.tile-v1.y.tile|, |v0.y.tile-v2.y.tile|, |v1.y.tile-v2.y.tile|)&gt;1, {RP0, RP1} are covered</li><li id="ul0002-0003" num="0075">Default: If (V0.RP &amp; V1.RP and V2.RP are in same tile), V0.RP is only tile covered else {RP0, RP1} is covered</li></ul></li></ul>

For 4 Pipes:

Config 0:

Switch({(max(|v0.x.tile-v1.x.tile|, |v0.x.tile-v2.x.tile|, |v1.x.tile-v2.x.tile|)&gt;1), (max(|v0.y.tile-v1.y.tile|, |v0.y.tile-v2.y.tile|, |v1.y.tile-v2.y.tile|)&gt;1)})

0 0: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RP})

0 0 0: {RP0, RP1, RP2, RP3} are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP are covered

0 1 0: RP of V1.RP.V2.RP and RP of V0.RP are covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP are covered

default: RP of V0.RP is covered

0 1: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RP})

0 0 0: {RP0, RP1, RP2, RP3} are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP, All vertical tiles too covered

0 1 0: RP of V1.RP/V2.RP and RP of V0.RP, All vertical tiles too covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP, All vertical tiles too covered

default: Tile {RP0, RP2} or {RP1, RP3} based on V0.RP are covered

1 0: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RPI})

0 0 0: {RP0, RP1, RP2, RP3} are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP, All horizon. tiles too covered

0 1 0: RP of V1.RP/V2.RP and RP of V0.RP, All horizon. tiles too covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP, All horizon. tiles too covered

default Tile {RP0, RP1} or (RP2, RP3} based on V0.RP are covered

1 1: Tile {RP0, RP1, RP2, RP3} are covered

Config 1:

Switch({(max(|v0.x.tile-v1.x.tile|, |v0.x.tile-v2.x.tile|, |v1.x.tile-v2.x.tile|)&gt;1), (max(|v0.y.tile-v1.y.tile|, |v0.x.tile-v2.y.tile|, |v1.y.tile-v2.y.tile|)&gt;1)})

0 0: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RP})

0 0 0: {RP0, RP1, RP2, RP3} are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP are covered

0 1 0: RP of V1.RP.V2.RP and RP of V0.RP are covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP are covered

default: RP of V0.RP is covered

0 1: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RP})

0 0 0: {RP0, RP1, RP2, RP3) are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP, All vertical tiles too covered

0 1 0: RP of V1.RP/V2.RP and RP of V0.RP, All vertical tiles too covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP, All vertical tiles too covered

default: Tile {RP0, RP1} or {RP2, RP3} based on V0.RP are covered

1 0: Switch({V0.RP==V1.RP, V2.RP==V1.RP, V0.RP==V2.RP})

0 0 0: {RP0, RP1, RP2, RP3} are covered

0 0 1: RP of V0.RP/V2.RP and RP of V1.RP, All horizontal tiles too covered

0 1 0: RP of V1.RP/V2.RP and RP of V0.RP, All horizontal tiles too covered

1 0 0: RP of V0.RP/V1.RP and RP of V2.RP, All horizontal tiles too covered

default: Tile {RP0, RP2} or {RP1, RP3} based on V0.RP are covered

1 1: Tile {RP0, RP1, RP2, RP3} are covered

Briefly, the algorithm performs pixel coverage calculation by taking into account the various different configurations shown in <figref idref="DRAWINGS">FIGS. 8A-8E</figref>. The algorithm takes into account the vertices of the incoming polygon (encoded V0, V1, and V2), the size of the tiles (encoded m and n), the number of pipes present (switch on the number of pipes), and which configuration to use given the number of pipes (e.g. Config. 0 or Config. 1). The end result is the determination of tile coverage. The coverage mask identifies which of the available tiles in a given configuration are covered, (e.g. within a quad or pair of tiles). For a 2×2 quad of tiles, the possible solutions will be: {RP0}, {RP1}, {RP2}, {RP3}, {RP0, RP1}, {RP0, RP2}, {RP1, RP3}, {RP2, RP3}, {RP1, RP2, RP3, RP4}.

Super Tiling

One embodiment of the present invention uses a super tiling scheme. This scheme may be useful in a larger design, where multiple graphics chips are used in parallel to increase fill rate. Super tiling involves sub-dividing the screen into groups of 2×2 tiles. In one embodiment, each group is drawn by a separate 4-pipe rendering engine. It is the responsibility of the setup unit to discover if the polygon covers one of the 2×2 tiles that any particular chip is responsible for.

The specification of the super tile is an x and y super tile stride value, as well as a super tile x and y start value. The stride will be the integer log 2 number that indicates “how far” two consecutive 2×2 super tiles are in super-tile coordinates (must be power of 2 in a scalable configuration). The location of the start x,y of the super tile will be the location, in super tile coordinates, of the first 2×2 super tile in x and y.

Below is one example of a super-tiling algorithm:

Compute V0.ST=(V0.tile.x&gt;&gt;ST_x_stride, V0.tile.y&gt;&gt;ST_y_stride

Compute V1.ST=(V1.tile.x&gt;&gt;ST_x_stride, V1.tile.y&gt;&gt;ST_y_stride

Compute V2.ST=(V2.tile.x&gt;&gt;ST_x_stride, V2.tile.y&gt;&gt;ST_y_stride

Compute MaxWidth=Max(|V0.ST.x-V1.ST.x|, |V0.ST.x-V2.ST.x|, |V1.ST.x-V2.ST.x|)

Compute MaxHeight=Max(|V0.ST.y-V1.ST.y|, |V0.ST.y-V2.ST.y|, |V1.ST.y-V2.ST.y|)

Compute Vmin.ST.x=mod_ST_x_stride(min(V0.ST.x, V1.ST.x, V2.ST.x))

Compute Vmin.ST.y=mod_ST_y_stride(min(V0.ST.y, V1.ST.y, V2.ST.y)) <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0131">If (((Vmin.ST.x&gt;=ST_x_start) and (Vmin.ST.x+MaxWidth&lt;=ST_x_start)) or (MaxWidth&gt;=ST_x_stride)) and ((Vmin.ST.y&gt;=ST_y_start) and (Vmin.ST.y+MaxHeight&lt;=ST_y_start)) or</li><li id="ul0004-0002" num="0132">(MaxHeight&gt;=ST_y_stride)) accept polygon</li></ul></li></ul>

Else Reject Polygon

It is possible to use only 2 raster chips, in which case either X or Y dominance is used (set ST_x_stride to 1 and ST_y_stride to 0, or vice-versa). For 4 raster chips, the strides should be set to 1 and 1 (or 2 and 0 or 0 and 2).

In this manner, geometry in each region, adjacent pixels are cached in the chip closer to their neighbors. This embodiment increases cache locality, and hence the efficiency of the tiling process. This embodiment is shown in the block diagram of <figref idref="DRAWINGS">FIG. 9</figref>. Screen region <b>900</b> is divided into four regions <b>905</b>, <b>906</b>, <b>907</b>, and <b>908</b> in this example, though alternate configurations are possible. Region <b>905</b> maps to graphics chip <b>910</b>. Region <b>906</b> maps to graphics chip <b>911</b>. Region <b>907</b> maps to graphics chip <b>912</b>. Region <b>908</b> maps to graphics chip <b>913</b>. Graphics chip <b>913</b> is expanded to show more detail but is otherwise the same as the other graphics chips <b>910</b>, <b>911</b>, and <b>912</b>.

Graphics chip <b>913</b> includes a cache <b>920</b> and graphics processing hardware <b>925</b> to control the operation of parallel rasterizers <b>930</b>, <b>931</b>, <b>932</b>, and <b>933</b>. For instance, screen region <b>908</b> might be sub-divided into smaller regions, where each region is mapped to a particular rasterizer. Take, for example, smaller region <b>940</b> that might be mapped in one embodiment, by a setup unit <b>950</b> in the graphics processing hardware <b>925</b> to rasterizer <b>930</b>.

Scan Converter—Coarse Grain Tiling Process

With reference back to <figref idref="DRAWINGS">FIG. 5</figref>, once the instructions are sent by setup unit to the individual pipelines, scan converter <b>540</b> operates on these instructions. Scan converter <b>540</b> steps through the geometry (e.g., triangle or parallelogram) within the bounds of the pipeline's tile pattern. In one embodiment, initial stepping is performed at a coarse level, with sub-division iterations performed with conjunction to Hierarchical-Z component <b>550</b> and Z-buffer <b>555</b>.

The operation of scan converter and Hierarchical-Z unit is shown in <figref idref="DRAWINGS">FIG. 10D</figref>. In one embodiment, the scan converter performs the scan conversion of triangles or parallelograms in two stages (passes). In step <b>1060</b>, the scan converter computes a list of size 8×8 tiles that are both owned by the current pipeline, and covered by the current graphics primitive. This is the first pass. In step <b>1065</b>, the address of these tiles, together with a reduced precision version of the closest z value, is passed to a Hierarchical-Z unit in a Z Buffer (zb). In step <b>1070</b>, the Hierarchical-Z unit returns a 4-bit mask specifying which of four size 4×4 tiles are visible. In step <b>1075</b>, the scan converter then generates a sub-list containing all the size 2×2 quads within the current 8×8 tile which are both visible and covered by the current graphics primitive. This is the second pass. In step <b>1080</b>, for each of these 2×2 quads, the scan converter computes a 32-bit coverage mask (assuming 8 samples per pixel), and a z plane equation. In step <b>1085</b>, these values are then passed back to the Z Buffer for fine grain early Z buffering at high precision.

An example of a scan converter embodiment operating in conjunction with a Z buffer is shown in <figref idref="DRAWINGS">FIGS. 10A-10C</figref>. <figref idref="DRAWINGS">FIG. 10A</figref> shows a plurality of tiles (“A”-“D”) dedicated to respective graphics pipelines, and that each pipeline is dedicated to one portion of an output screen with the setup unit (<b>515</b>) distributing instructions to the pipelines. As shown in <figref idref="DRAWINGS">FIG. 10A</figref>, each portion of the output screen includes a plurality of the tiles that are contiguous and arranged in substantially similar pattern (e.g. 2×2 “A” tiles, 2×2 “B” tiles and so on). The triangle being rasterized (<b>1000</b>) in <figref idref="DRAWINGS">FIG. 10A</figref> is partially hidden by a previously drawn triangle <b>1010</b>. <figref idref="DRAWINGS">FIG. 10A</figref> shows the result from the first pass of the scan conversion (step <b>1060</b> of <figref idref="DRAWINGS">FIG. 10D</figref>). In this example, only the tiles dedicated to the “A” pipeline's operations are illustrated, and so only tiles interpolated to that pipeline (tiles within area <b>1030</b>) and rasterizer are considered. Tiles of size 8×8 are generated during this operation, with the computed coverage within the tiles shown in gray. Note that the 64 sub-tiles with the “A” tile are not illustrated. At this stage, the scan conversion is done at the coarsest level.

Diagram <b>1040</b> of <figref idref="DRAWINGS">FIG. 10B</figref> shows the result of a Hierarchical-Z operation. The computed coverage 4×4 tiles <b>1050</b> generated during this operation are shown in dark gray (step <b>1070</b> of <figref idref="DRAWINGS">FIG. 10D</figref>). Diagram <b>1060</b> of <figref idref="DRAWINGS">FIG. 10C</figref> shows the result of the second pass of Scan Conversion (step <b>1075</b> of <figref idref="DRAWINGS">FIG. 10D</figref>). The computed coverage are done at the level of 2×2 tiles. The computed coverage (quads) <b>1070</b> generated during this operation are shown in dark gray. Note that a total of 25 quads are generated for this triangle (number of dark gray rectangles in <figref idref="DRAWINGS">FIG. 10C</figref>). Without Hierarchical-Z, the count would be 37 (number of dark gray rectangles+light gray rectangles). Thus, the present invention reduces the number of tiles that need to be processed and hence speeds up overall operation. Those skilled in the art can appreciate that the sizes of the tiles can be scaled up or down by in this iterative process, preferably by a factor of 2. The sizes of 2×2, 4×4, and 8×8 are sizes used in just one example.

Multi-Chip Application

In one embodiment, a register is used to specify the tile format for use in a multi-chip system (e.g. a flight simulator). This affects the allocation of tiles among pipelines, and therefore the tile pattern used by each tile for scan conversion. In one embodiment, the register has a field “chip_count” that specifies the total number of chips in the system. It also has a field “chip_id” that specifies the id of the present chip.

Embodiment of Computer Execution Environment (Hardware)

An embodiment of the invention can be implemented as computer software in the form of computer readable program code executed in a general purpose computing environment such as environment <b>1100</b> illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, or in the form of bytecode class files executable within a Java™ run time environment running in such an environment, or in the form of bytecodes running on a processor (or devices enabled to process bytecodes) existing in a distributed environment (e.g., one or more processors on a network). A keyboard <b>1110</b> and mouse <b>1111</b> are coupled to a system bus <b>1118</b>. The keyboard and mouse are for introducing user input to the computer system and communicating that user input to central processing unit (CPU) <b>1113</b>. Other suitable input devices may be used in addition to, or in place of, the mouse <b>1111</b> and keyboard <b>1110</b>. I/O (input/output) unit <b>1119</b> coupled to bidirectional system bus <b>1118</b> represents such I/O elements as a printer, A/V (audio/video) I/O, etc.

Computer <b>1101</b> may include a communication interface <b>1120</b> coupled to bus <b>1118</b>. Communication interface <b>1120</b> provides a two-way data communication coupling via a network link <b>1121</b> to a local network <b>1122</b>. For example, if communication interface <b>1120</b> is an integrated services digital network (ISDN) card or a modem, communication interface <b>1120</b> provides a data communication connection to the corresponding type of telephone line, which comprises part of network link <b>1121</b>. If communication interface <b>1120</b> is a local area network (LAN) card, communication interface <b>1120</b> provides a data communication connection via network link <b>1121</b> to a compatible LAN. Wireless links are also possible. In any such implementation, communication interface <b>1120</b> sends and receives electrical electromagnetic or optical signals which carry digital data streams representing various types of information.

Network link <b>1121</b> typically provides data communication through one or more networks to other data devices. For example, network link <b>1121</b> may provide a connection through local network <b>1122</b> to host <b>1123</b> or to data equipment operated by ISP <b>1124</b>. ISP <b>1124</b> in turn provides data communication services through the world wide packet data communication network now commonly referred to as the “Internet” <b>1125</b>. Local network <b>1122</b> and Internet <b>1125</b> may use electrical, electromagnetic or optical signals which carry digital data streams. The signals through the various networks and the signals on network link <b>1121</b> and through communication interface <b>1120</b>, which carry the digital data to and from computer <b>1100</b>, are exemplary forms of carrier waves transporting the information.

Processor <b>1113</b> may reside wholly on client computer <b>1101</b> or wholly on server <b>1126</b> or processor <b>1113</b> may have its computational power distributed between computer <b>1101</b> and server <b>1126</b>. Server <b>1126</b> symbolically is represented in <figref idref="DRAWINGS">FIG. 11</figref> as one unit, but server <b>1126</b> can also be distributed between multiple “tiers”. In one embodiment, server <b>1126</b> comprises a middle and back tier where application logic executes in the middle tier and persistent data is obtained in the back tier. In the case where processor <b>1113</b> resides wholly on server <b>1126</b>, the results of the computations performed by processor <b>1113</b> are transmitted to computer <b>1101</b> via Internet <b>1125</b>, Internet Service Provider (ISP) <b>1124</b>, local network <b>1122</b> and communication interface <b>1120</b>. In this way, computer <b>1101</b> is able to display the results of the computation to a user in the form of output.

Computer <b>1101</b> includes a video memory <b>1114</b>, main memory <b>1115</b> and mass storage <b>1112</b>, all coupled to bidirectional system bus <b>1118</b> along with keyboard <b>1110</b>, mouse <b>1111</b> and processor <b>1113</b>. As with processor <b>1113</b>, in various computing environments, main memory <b>1115</b> and mass storage <b>1112</b>, can reside wholly on server <b>1126</b> or computer <b>1101</b>, or they may be distributed between the two. Examples of systems where processor <b>1113</b>, main memory <b>1115</b>, and mass storage <b>1112</b> are distributed between computer <b>1101</b> and server <b>1126</b> include the thin-client computing architecture developed by Sun Microsystems, Inc., the palm pilot computing device and other personal digital assistants, Internet ready cellular phones and other Internet computing devices, and in platform independent computing environments, such as those that utilize the Java technologies also developed by Sun Microsystems, Inc.

The mass storage <b>1112</b> may include both fixed and removable media, such as magnetic, optical or magnetic optical storage systems or any other available mass storage technology. Bus <b>1118</b> may contain, for example, thirty-two address lines for addressing video memory <b>1114</b> or main memory <b>1115</b>. The system bus <b>1118</b> may also include, for example, a 32-bit data bus for transferring data between and among the components, such as processor <b>1113</b>, main memory <b>1115</b>, video memory <b>1114</b> and mass storage <b>1112</b>. Alternatively, multiplex data/address lines may be used instead of separate data and address lines.

In one embodiment of the invention, the processor <b>1113</b> is a microprocessor manufactured by Motorola, such as the 680×0 processor or a microprocessor manufactured by Intel, such as the 80×86, or Pentium processor, or a SPARC microprocessor from Sun Microsystems, Inc. However, any other suitable microprocessor or microcomputer may be utilized. Main memory <b>1115</b> may be comprised of dynamic random access memory RAM). Video memory <b>1114</b> may be a dual-ported video random access memory. One port of the video memory <b>1114</b> may be coupled to video amplifier <b>1116</b>. The video amplifier <b>1116</b> may be used to drive a display/output device <b>1117</b>, such as a cathode ray tube (CRT) raster monitor. Video amplifier <b>1116</b> is well known in the art and may be implemented by any suitable apparatus. This circuitry converts pixel data stored in video memory <b>1114</b> to a raster signal suitable for use by display/output device <b>1117</b>. Display/output device <b>1117</b> may be any type of monitor suitable for displaying graphic images.

Computer <b>1101</b> can send messages and receive data, including program code, through the network(s), network link <b>1121</b>, and communication interface <b>1120</b>. In the Internet example, remote server computer <b>1126</b> might transmit a requested code for an application program through Internet <b>1125</b>, ISP <b>1124</b>, local network <b>1122</b> and communication interface <b>1120</b>. The received code may be executed by processor <b>1113</b> as it is received, and/or stored in mass storage <b>1112</b>, or other non-volatile storage for later execution. In this manner, computer <b>1100</b> may obtain application code in the form of a carrier wave. Alternatively, remote server computer <b>1126</b> may execute applications using processor <b>1113</b>, and utilize mass storage <b>1112</b>, and/or video memory <b>1115</b>. The results of the execution at server <b>1126</b> are then transmitted through Internet <b>1125</b>, ISP <b>1124</b>, local network <b>1122</b> and communication interface <b>1120</b>. In this example, computer <b>1101</b> performs only input and output functions.

Application code may be embodied in any form of computer program product. A computer program product comprises a medium configured to store or transport computer readable code, or in which computer readable code may be embedded. Some examples of computer program products are CD-ROM disks, ROM cards, floppy disks, magnetic tapes, computer hard drives and servers on a network.

The computer systems described above are for example only. An embodiment of the invention may be implemented in any type of computer system or programing or processing environment.

Thus, a rasterizer interpolator is described in conjunction with one or more specific embodiments. The invention is defined by the claims and their fill scope of equivalents.