Method of forming a phase change layer and method of manufacturing a storage node having the phase change layer

PRIORITY STATEMENT

0001This application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2006-0102463, filed on Oct. 20, 2006 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

BACKGROUND

00021. Technical Field

0003Example embodiments relate to a method of forming a phase change layer and a method of manufacturing a storage node having the phase change layer.

00042. Description of the Related Art

0005The resistance of a phase change material may vary depending to whether the phase change material is in a crystalline state or in an amorphous state. Additionally, the phase change material may change from a crystalline state to an amorphous state, and vice versa, depending on temperature. A phase change memory device may include a phase change layer made of the above-described phase change material as a means for storing bit data. An example of a phase change memory device may include a PRAM (phase change random access memory), and an example of a phase change material may include Ge₂Sb₂Te₅(GST). A GST layer may be formed using a physical vapor deposition (PVD) method. However, controlling the growth of the GST layer may be difficult when using a PVD method. Additionally, deposition speed may be relatively low, and the density of the GST layer may be decreased. Accordingly, a metal organic chemical vapor deposition (MOCVD) method or a cyclic chemical vapor deposition cyclic-CVD) method may be used to obtain an improved GST layer.

0006A conventional method of forming a GST layer using a conventional CVD method will be briefly described. A substrate, including a layer on which a GST layer is to be formed, may be loaded into a CVD chamber. The substrate may be heated to the appropriate temperature for deposition. Precursors, including metal elements forming the GST layer, may be supplied simultaneously through a shower head to the heated substrate. For example, suitable precursors may be organic metal compounds including germanium (Ge), antimony (Sb), and/or tellurium (Te). As the substrate is heated to the appropriate temperature for deposition, the precursors may decompose and be absorbed onto the layer as a result of the reaction of metallic elements of the precursors with the layer. The precursors not reacted or absorbed onto the layer may be discharged from the CVD chamber.

SUMMARY OF EXAMPLE EMBODIMENTS

0007Example embodiments provide a method of forming a phase change layer and a method of manufacturing a storage node having the phase change layer. The method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), providing a second precursor, and/or providing a third precursor onto a surface on which the phase change layer is to be formed using a deposition process. Additionally, the second precursor may have antimony (Sb), and the third precursor may have tellurium (Te). Furthermore, the phase change layer may be a Ge₂Sb₂Te₅(GST) layer.

0008The deposition process may be performed using chemical vapor deposition (CVD), which may include metal organic chemical vapor deposition (MOCVD) and cyclic chemical vapor deposition (cyclic-CVD). The deposition process may also be performed using atomic layer deposition (ALD). The composition (e.g., Ge, Sb, Te content) of the phase change layer may be controlled by regulating the deposition pressure, the deposition temperature, and/or the supply rate of reaction gas. The deposition pressure may range from about 0.001-10 torr. The deposition temperature may range from about 150-350° C., and the supply rate of the reaction gas may range from about 0-1 slm. The first, second, and/or third precursors may be provided simultaneously, sequentially, or a combination thereof. Additionally, reaction gas may be provided during deposition.

0009The first precursor may be selected from the group consisting of GeCl₂, Ge(N(SiMe₃)₂)₂, Ge(N(Me₃)₂)₂, Ge(CH(SiMe₃)₂)₂, Ge(CH(Me₃)₂)₂, Ge(Cp)₂, and Ge(EtCp)₂, wherein Me, Et, Cp, and denote methyl, ethyl, and cyclopentadienyl, respectively. The second precursor may be Sb(iPr)₃, and the third precursor may be Te(iPr)₂, wherein iPr denotes isopropyl. Additionally, the reaction gas may be hydrogen (H₂).

0010Ge(N(SiMe₃)₂)₂, example first bivalent precursor, may be made by preparing GeCl₂.dioxane. Bis(trimethylsilyl)amine, anhydrous tetrahydrofuran (THF), and an equivalent amount of methyl lithium with respect to bis(trimethylsilyl)amine may be combined to form a solution. Half of the equivalent amount of the GeCl₂.dioxane with respect to the bis(trimethylsilyl)amine may be added to the solution to form Ge(N(SiMe₃)₂)₂and a lithium chloride byproduct. The lithium chloride byproduct may be filtered and removed, and the THF may be removed by vaporizing the THF (e.g., decompression).

0011The above phase change layer may be provided in a storage node. The method of manufacturing a storage node having the above phase change layer may include providing a bottom electrode layer and an insulating interlayer on the bottom electrode layer, the insulating interlayer having a via hole above the bottom electrode layer. The above phase change layer may be formed on the bottom electrode layer by filling the via hole and/or formed on the insulating interlayer surrounding the via hole. A top electrode may be provided on the phase change layer.

0012By forming a phase change (e.g., GST) layer with a CVD or ALD process using a temperature of about 300° C. or lower, increased step coverage may be achieved. Thus, a via hole having a diameter of about 100 nm or less may be filled with a GST layer, and the reset current of the PRAM may be reduced. Consequently, the transistor size may be reduced, thereby increasing the integration of the PRAM.

BRIEF DESCRIPTION OF THE DRAWINGS

0013The scope of example embodiments will become more apparent when viewed together with the accompanying drawings. It should be noted that the thickness of layers or region illustrated in the drawings may have been exaggerated for clarity.

0014<figref idref="DRAWINGS">FIGS. 1 through 4</figref> are cross-sectional views illustrating a method of manufacturing a phase change memory device including a storage node having a phase change layer according to example embodiments, wherein the phase change layer is provided in a via hole.

0015<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view illustrating a phase change memory device including a storage node having a phase change layer according to example embodiments, wherein the phase change layer is provided in a via hole and on the second insulating interlayer surrounding a via hole.

0016<figref idref="DRAWINGS">FIGS. 6 through 8</figref> are graphs showing the variation of the composition of GST layers based on pressure, temperature, and hydrogen gas supply rate, respectively, according to example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

0017Example embodiments will be described below in more detail with reference to the accompanying drawings. However, example embodiments may be embodied in different forms and should not be interpreted as limited to the examples set forth herein.

0018It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “covering” another element or layer, it may be directly on, connected to, coupled to, or covering the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

0019It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

0020Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

0021The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0022Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

0023Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, including those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

0024Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a gate stack <b>46</b> may be provided in an area of an active region defined by a device separation layer (not shown) on a p-type or an n-type substrate <b>40</b>. The gate stack <b>46</b> may include a gate insulating layer (not shown) and a gate electrode (not shown). A first impurity region <b>42</b> and a second impurity region <b>44</b> may be provided in the substrate <b>40</b> between the device separation layer (not shown) and the gate stack <b>46</b>. The first and second impurity regions <b>42</b> and <b>44</b>, respectively, may be formed by ion-injecting doping materials having a conductivity opposite to the doping material of the substrate <b>40</b>. The first impurity region <b>42</b> may be used as a source, and the second impurity region <b>44</b> may be used as a drain, or vice versa. The first and second impurity regions <b>42</b> and <b>44</b>, respectively, may have a variety of shapes. The first and second impurity regions <b>42</b> and <b>44</b>, respectively, and the gate stack <b>46</b> may constitute a semiconductor transistor.

0025A first insulating interlayer <b>48</b> may cover the first and second impurity regions <b>42</b> and <b>44</b>, respectively, and the gate stack <b>46</b>. A contact hole <b>50</b> exposing the first impurity region <b>42</b> may be provided in the first insulating interlayer <b>48</b>. Alternatively, the contact hole <b>50</b> may be provided in the first insulating interlayer <b>48</b> to expose the second impurity region <b>44</b> instead of the first impurity region <b>42</b>. The contact hole <b>50</b> may be filled with a conductive plug <b>52</b>.

0026Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a bottom electrode layer <b>54</b> may be provided on the first insulating interlayer <b>48</b> so as to cover an exposed upper surface of the conductive plug <b>52</b>, and a bottom electrode contact layer <b>60</b> may be provided on the bottom electrode layer <b>54</b>. The bottom electrode layer <b>54</b> and the bottom electrode contact layer <b>60</b> may be formed by sequentially stacking and simultaneously etching the bottom electrode layer <b>54</b> and the bottom electrode contact layer <b>60</b>. A second insulating interlayer <b>56</b> may be provided on the first insulating interlayer <b>48</b> so as to cover the bottom electrode layer <b>54</b> and the bottom electrode contact layer <b>60</b>. The second insulating interlayer <b>56</b> may be made of the same material (e.g., silicon oxide) as the first insulating interlayer <b>48</b>. A via hole <b>58</b> may be provided on the second insulating interlayer <b>56</b> so as to expose an upper surface of the bottom electrode contact layer <b>60</b>. A source material gas <b>61</b> including a bivalent precursor may be supplied to the second insulating interlayer <b>56</b> during a deposition process. Accordingly, a phase change layer <b>62</b> may be formed on the second insulating interlayer <b>56</b> so as to also fill the via hole <b>58</b>. The phase change layer <b>62</b> may be planarized using a planarization method (e.g., chemical mechanical polishing (CMP)) until the second insulating interlayer <b>56</b> is exposed and the only remaining phase change layer <b>62</b> is in the via hole <b>58</b>, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>.

0027Referring to <figref idref="DRAWINGS">FIG. 4</figref>, a top electrode contact layer <b>64</b> may be provided on the second insulating interlayer <b>56</b> so as to cover the phase change layer <b>62</b> in the via hole <b>58</b>, and a top electrode layer <b>66</b> may be provided on the top electrode contact layer <b>64</b>, thus forming a storage node. Alternatively, referring to <figref idref="DRAWINGS">FIG. 5</figref>, the phase change layer <b>62</b> may be formed to a desired thickness and etched so as to additionally cover a portion of the second insulating interlayer <b>56</b> surrounding the via hole <b>58</b>. A top electrode contact layer <b>64</b> may be provided on the phase change layer <b>62</b> and a top electrode layer <b>66</b> may be provided on the top electrode contact layer <b>64</b> to form a storage node.

0028The phase change layer <b>62</b> may be formed using a CVD method or an atomic layer deposition (ALD) method. Examples of the CVD method may include MOCVD and cyclic-CVD. For example, during CVD, a substrate <b>40</b> having the second insulating interlayer <b>56</b> and via hole <b>58</b> may be placed in a deposition chamber and supplied with source material gases <b>61</b>, a transportation gas, and a reaction gas (e.g., H₂). Alternatively, when the phase change layer <b>62</b> is formed by ALD, the H₂gas may be omitted from the gas mixture including the source material gases <b>61</b>.

0029The first, second, and third precursors may be provided simultaneously during deposition (e.g., MOCVD). Alternatively, one of the second precursor or third precursor may be simultaneously provided with the first precursor (e.g., cyclic-CVD, ALD). The first, second, and/or third precursors may also be provided sequentially by providing a precursor and purging the unabsorbed precursor prior to providing the next precursor. Alternatively, the unabsorbed first precursor may be purged prior to providing the second and third precursors. In any event, a precursor that has been supplied but not absorbed may be purged. When ALD is used, reaction gas may be supplied after purging an unabsorbed precursor. The deposition pressure may be maintained at about 0.001-10 torr, and the deposition temperature may be maintained at about 150-350° C. The supply rate of the H₂gas may be maintained at about 0-1000 sccm (˜1 slm).

0030Where the phase change layer <b>62</b> is a GST layer, the source material gas may include a first precursor including Ge, a second precursor including Sb, and a third precursor including Te. The first, second, and third precursors may be organic metal compounds, and the first precursor may additionally be a bivalent compound. The first precursor may be at least one of GeCl₂, Ge(N(SiMe₃)₂)₂, Ge(N(Me₃)₂)₂, Ge(CH(SiMe₃)₂)₂, Ge(CH(Me₃)₂)₂, Ge(Cp)₂, and Ge(EtCp)₂, wherein Me, Et, and Cp denote methyl, ethyl, and cyclopentadienyl, respectively. The second and third precursors may be Sb(iPr)₃and Te(iPr)₂, respectively, wherein iPr denotes isopropyl.

0031Ge(N(SiMe₃)₂)₂, an example first bivalent precursor, may be made by preparing GeCl₂.dioxane. Bis(trimethylsilyl)amine, anhydrous tetrahydrofuran (THF), and an equivalent amount of methyl lithium with respect to bis(trimethylsilyl)amine may be combined to form a solution. Half of the equivalent amount of the GeCl₂.dioxane with respect to the bis(trimethylsilyl)amine may be added to the solution to form Ge(N(SiMe₃)₂)₂and a lithium chloride byproduct. The lithium chloride byproduct may be filtered and removed, and the THF may be removed by vaporizing the THF (e.g., decompression).

0032The above-described synthesis of Ge(N(SiMe₃)₂)₂may be represented by the following chemical formula.

0033<chemistry id="CHEM-US-00001" num="00001"><img file="US7902048B2_D0001.tif" /></chemistry>

0034Referring to <figref idref="DRAWINGS">FIGS. 6 through 8</figref>, experiments were performed to determine the affect of various process factors on the Ge, Sb, and Te content of a GST layer. Ge(N(SiMe₃)₂)₂, Sb(iPr)₃, and Te(iPr)₂were used as the first, second, and third precursors, respectively, in the experiments.

0035In a first experiment, as illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, deposition pressure was varied from about 0-5 torr during the formation of a GST layer while keeping temperature and reaction gas supply rate constant at about 280° C. and about 400 sccm, respectively. Referring to <figref idref="DRAWINGS">FIG. 6</figref>, plots G<b>1</b>, G<b>2</b>, and G<b>3</b> show the content of Ge, Sb, and Te, respectively, in the GST layer. As illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, when deposition pressure was varied from about 0-5 torr, the content of Ge increased by about 20 wt %, the content of Sb decreased by about 15-20 wt %, and the content of Te remained at about 60 wt %.

0036In a second experiment, as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, deposition temperature was varied from about 260-300° C. during the formation of a GST layer while keeping pressure and reaction gas supply rate constant at about 5 torr and about 400 sccm, respectively. Referring to <figref idref="DRAWINGS">FIG. 7</figref>, plots G<b>21</b>, G<b>22</b>, and G<b>23</b> show the content of Ge, Sb, and Te, respectively, in the GST layer. As illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, when the deposition temperature was varied from about 260-360° C., the content of Ge decreased by about 30 wt %, the content of Sb increased by about 10 wt %, and the content of Te increased by about 15-20 wt %. It may be beneficial to use a deposition temperature of about 220-280° C.

0037In a third experiment, as illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, H₂gas supply rate was varied from about 0-500 sccm during the formation of a GST layer while keeping temperature and pressure constant at about 280° C. and about 5 torr, respectively. Referring to <figref idref="DRAWINGS">FIG. 8</figref>, plots G<b>31</b>, G<b>32</b>, and G<b>33</b> show the content of Ge, Sb, and Te, respectively, in the GST layer. As illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, when the H₂gas supply rate was varied from about 0-500 sccm, the content of Ge increased by about 20 wt %, the content of Sb decreased by about 15 wt %, and the content of Te decreased by about 5 wt %.

0038In view of the results illustrated in <figref idref="DRAWINGS">FIGS. 6 through 8</figref>, it may be beneficial to form a GST layer using a deposition temperature of about 280° C., a deposition pressure of about 5 torr, and a H₂gas supply rate of about 500 sccm.

0039Because a bivalent organic metal compound (e.g., Ge) may be used as a precursor in a CVD process (e.g., MOCVD, cyclic-CVD), the deposition temperature may be reduced to about 300° C. or lower, thus providing increased step coverage. As a result, a phase change layer (e.g., GST layer) may be used to fill a via hole having a diameter of about 100 nm or less. Accordingly, the reset current of a phase change memory device may be reduced, thereby reducing transistor size and increasing integration.

0040While example embodiments have been disclosed herein, other variations may be possible. Such variations are not to be regarded as a departure from the spirit and scope of example embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.