Memory bank arrangement for stacked memory
Summary by NHIP
Stacked Memory Bank Arrangement
The device stacks memory core layers over an interface chip using through electrodes to connect layers sequentially. An interface chip supplies common bank addresses and row addresses, where the row address splits into layer selection bits and operation bits to access specific banks.
Claim Score by NHIP
Abstract
In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
Term
3.2 yearsleft in the term
Expires 22 November 2029, including 1,101 days of term adjustment.
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18 claims: 1 independent, 17 dependent
- 1Broadest claimClaim Score 31, narrow(NHIP)A memory device a plurality of memory core layers each including a plurality of through electrodes;and an interface chip including a plurality of electrodes;the memory core layers being stacked over the interlace chip with one another such that the through electrodes of a lower one of the memory core layers are connected respectively to the through electrodes of an upper one of the memory core layers and the through electrodes of a lowest one of the memory core layers are connected respectively to the through electrodes of the interface chip;each of the memory core layers further including a plurality of memory banks each containing a plurality of memory cells;the interface chip generating bank address information and supplying the bank address information in common to the memory core layers via the through electrodes to designate memory banks belonging respectively to the memory core layers;the interface chip further generating row address information and supplying the row address information in common to the memory core layers via the through electrodes, the row address information comprising a more significant bit part and a less significant bit part, one or more bits belonging to the more significant bit part being allocated as layer selection information to select one of the memory core layers;and the interface chip performing, in response at least to the less significant bit part of the row address information, a data read/write operation on a memory bank which is contained in the memory banks designated by the bank address information and which belongs to one of the memory core layers that is selected by the one or more bits belonging to the more significant bit part of the row address information.
77 paragraphs in 6 sections, as filed
0001This application claims priority to prior Japanese patent application JP 2005-334413, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
00021. Field of the Invention
0003The present invention relates to a stacked memory having a plurality of stacked memory chips, and more particularly to a memory arrangement, a bank arrangement, and a refresh control of a stacked memory.
00042. Description of the Related Art
0005Recently, electronic equipment has been miniaturized, and semiconductor devices used in electronic equipment also have been miniaturized. For example, small-sized electronic equipment such as cellular phones employs a three-dimensional stacked semiconductor device. The three-dimensional stacked semiconductor device has a plurality of stacked semiconductor chips, each of which is subjected to wire bonding so as to be housed in a single package. Thus, in order to achieve miniaturization of a semiconductor device, semiconductor chips are stacked so as to form a three-dimensional stacked semiconductor device.
0006In order to achieve further miniaturization and high-speed operation, there has recently been developed a stacked semiconductor device using through electrodes instead of wire bonding. In such a stacked semiconductor device, stacked semiconductor chips are connected to each other by through electrodes, which extend through the semiconductor chips. The use of through electrodes reduces a space and an inductor which would be caused by wire bonding, and allows a semiconductor device to achieve further miniaturization and high-speed operation.
0007A stacked memory with a plurality of stacked memory chips has been developed as one of such stacked semiconductor devices. A stacked memory can be substituted for a memory module by stacking a plurality of semiconductor chips. For example, such a stacked memory includes a stacked dynamic random access memory (DRAM) having stacked DRAM chips which are formed on memory core layers. When a stacked memory is substituted for a currently used memory or memory module, the stacked memory should be arranged so as to match specifications of the currently used memory or memory module. For example, design of memory core layers should be changed for parity operation and for no-parity operation. Specifically, x16-bit products should be changed into x18-bit products when the parity operation is executed. Further, it is to be noted that each of the DRAM chips tends to be divided into a plurality of banks. Under the circumstances, if the DRAM chips are simply stacked one upon another, the number of banks widely varies depending on the number of stacks. This requires preparation of a great number of DRAM specifications for every one of the bank numbers. Furthermore, any refresh control methods corresponding to a stacked structure have not been established yet.
0008With regard to a stacked semiconductor device having stacked semiconductor chips, the following references are known as the prior art. Japanese laid-open patent publication No. 9-265774 (Patent Document 1) discloses an interleave control performed between stacked memory chips in order to shorten access time. Japanese laid-open patent publication No. 2004-327474 (Patent Document 2) discloses a stacked memory that stacks an IO chip and a plurality of DRAM chips together. With this structure, the IO chip converts system data signals and internal data in the DRAM chips and controls the stacked memory.
0009Patent Document 1 discloses an improvement of an access method of a stacked memory but is silent on a bank arrangement or a refresh method of DRAM chips. According to Patent Document 2, it is assumed that each of the DRAM chips has a single bank arrangement. Accordingly, no problems arise with regard to a plural bank arrangement of the DRAM chips. Further, Patent Document 2 is silent on a refresh method of the DRAM chips. Thus, Patent Documents 1 and 2 do not recognize the aforementioned problems to be resolved by the present invention. Patent Documents 1 and 2 are silent on an arrangement of a stacked memory or an address assignment, and fail to teach or suggest any technology to resolve the aforementioned problems.
0010In addition, a stacked memory should also have a structure matched with specifications of the currently used memory or memory module. However, no methods have been established yet so as to be matched with such demands. Accordingly, an arrangement of semiconductor chips should be changed for parity operation and for no-parity operation. Specifically, x16-bit products for no-parity operation should be changed into x18-bit products for parity operation. Further, if stacking is simply conducted, the bank numbers should change according to the number of stacks, as mentioned before. Such a change of the bank numbers needs to change DRAM specifications for the bank numbers. Furthermnore, no optimal refresh control methods corresponding to a stacked structure have been established yet.
SUMMARY OF THE INVENTION
0011The present invention has been made in view of the above drawbacks. It is, therefore, an object of the present invention to provide a stacked memory which can match currently used memory specifications with use of stacked memory chips having the same arrangement, and an arrangement method of such a stacked memory.
0012In order to resolve the above problems, the present invention basically adopts the following technology. As a matter of course, the present invention covers applied technology in which various changes and modifications are made therein without departing from the spirit of the present invention.
0013According to an aspect of the present invention, there is provided a stacked memory including memory core layers each having through electrodes and an interface chip. The stacked memory is operable to perform a parity operation or a no-parity operation in dependency upon absence or presence of a parity layer.
0014In the stacked memory, each of the memory core layers and the parity layer may have the same arrangement of a memory cell array and a peripheral circuit concerned with the memory cell array. The interface chip may have a memory input/output circuit mounted thereon. An interposer may have an external terminal mounted thereon. The layers may be connected by the through electrodes.
0015In the stacked memory, a layer of the memory core layers may be designated by a significant bit of a row address.
0016In the stacked memory, a bank of the stacked memory may be designated by a bank address and is made to correspond to a mat included in the memory core layer to thereby maintain a constant number of banks irrespective of the number of stacks of the memory core layers.
0017In the stacked memory, the parity layer may be designated by an address signal from the interface chip.
0018In the stacked memory, a bank of the parity layer may be designated by a significant bit of a bank address and a bit in which a least significant bit of the bank address is inversed.
0019In the stacked memory, parity information of a specific bank of the memory core layers may be stored in a submat within one mat of the parity layer.
0020In the stacked memory, the submat may be designated by a row address for designating a layer of the memory core layers.
0021In the stacked memory, a layer of the memory core layers maybe designated by a significant bit of a row address and a most significant bit of a bank address.
0022In the stacked memory, a bank of the stacked memory may be designated by specifying non-inversion, inversion, and invalidation of each bit of a bank address for each mat in the memory core layer and judging consistency or inconsistency with an inputted bank address.
0023In the stacked memory, a layer of the memory core layers may be designated by comparing a layer address and a layer selection address. A mat in a memory core layer designated by a mat selection signal from the interface chip may be designated as a bank of the stacked memory.
0024In the stacked memory, banks of the memory core layers may be grouped, and the interface chip may have refresh counters for refreshing each group of the banks of the memory core layers.
0025According to the present invention, by stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, it is possible to perform a refresh control of the stacked memory, such as Hidden Refresh. The above arrangement provides a stacked memory including stacked memory core layers having through electrodes.
0026The above and other objects, features, and advantages of the present invention will be apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
BRIEF DESCRIPTION OF THE DRAWINGS
0027<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing an entire arrangement of a stacked memory according to the present invention with a structure of a usual memory module;
0028<figref idref="DRAWINGS">FIG. 2</figref> is an explanatory diagram showing bank arrangements of stacked memories for parity operation and no-parity operation;
0029<figref idref="DRAWINGS">FIG. 3</figref> is an explanatory diagram showing an 8-bank arrangement and a 16-bank arrangement of a stacked memory for parity operation;
0030<figref idref="DRAWINGS">FIG. 4</figref> is a diagram explanatory of address assignment for a bank select and a layer select in a stacked memory;
0031<figref idref="DRAWINGS">FIG. 5</figref> is a diagram showing conventional bank arrangements;
0032<figref idref="DRAWINGS">FIG. 6</figref> shows: (a) table showing an address assignment for designating a layer and a bank in an 8-bank arrangement and (b) a diagram showing 8-bank arrangements in various cases;
0033<figref idref="DRAWINGS">FIG. 7</figref> shows: (a) a table showing an address assignment for designating a layer and a bank in a 16-bank arrangement and (b) a diagram showing 16-bank arrangements in various cases;
0034<figref idref="DRAWINGS">FIG. 8</figref> shows: (a) a block diagram explanatory of mat selection with use of programmable address decoders, (b) a circuit diagram of the programmable address decoder shown in (a), and (c) a logical table of the programmable address decoder shown in (a);
0035<figref idref="DRAWINGS">FIG. 9</figref> shows: (a) a block diagram explanatory of mat selection with use of comparators, and (b) a circuit diagram of the comparator shown in (a);
0036<figref idref="DRAWINGS">FIG. 10</figref> shows: (a) a diagram showing a stacked memory for explanation of a refresh control method, (b) a diagram showing a bank arrangement in a case of two lines of counters, and (c) a diagram showing a bank arrangement in a case of four lines of counters.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
0037In order to facilitate an understanding of the present invention, a basic arrangement of stacked memories will be described below in detail with reference to <figref idref="DRAWINGS">FIGS. 1 through 4</figref>. At first, the stacked memory according to a preferred embodiment of the present invention includes an external terminal (interposer) layer <b>2</b> for connection with an external terminal, a plurality of memory core layers <b>3</b>, and an input/output circuit (IF chip) layer <b>4</b>, as illustrated in (b) in <figref idref="DRAWINGS">FIG. 1</figref>. Thus, the entire arrangement of the stacked memory according to the present invention is shown in <figref idref="DRAWINGS">FIG. 1</figref>.
0038<figref idref="DRAWINGS">FIG. 2</figref> is an explanatory diagram showing bank arrangements of stacked memories for parity operation and no-parity operation. <figref idref="DRAWINGS">FIG. 3</figref> is an explanatory diagram showing an 8-bank arrangement and a 16-bank arrangement of a stacked memory for parity operation. <figref idref="DRAWINGS">FIG. 4</figref> is an explanatory diagram of address assignment for a bank select and a layer select.
0039Specifically, <figref idref="DRAWINGS">FIG. 1</figref> (<i>a</i>) and (<i>b</i>) show a structure of a usual memory module and the layer arrangement of the stacked memory according to the present invention, respectively. In <figref idref="DRAWINGS">FIG. 1</figref> (<i>a</i>), the usual memory module includes nine semiconductor memories <b>1</b> for parity operation, numbered from first through ninth memories (#<b>1</b> to #<b>9</b>). For no-parity operation, the usual memory module includes eight semiconductor memories <b>1</b>. Each of semiconductor memories <b>1</b> has a portion connected to an external terminal, an input/output circuit, and a plurality of DRAM cell arrays, namely, DRAM banks that are equal in number to four in <figref idref="DRAWINGS">FIG. 1</figref>. Each semiconductor memory <b>1</b> is mounted on a module substrate (not shown). Assuming that each of the semiconductor memories <b>1</b> is an 8-bit product, the memory module has a data width of 64 bits in a case of no-parity operation or a data width of 72 bit in a case of parity operation.
0040The stacked memory according to the present invention is used instead of the structure of the aforementioned memory module. As mentioned before, the stacked memory according to the present invention includes the external terminal (interposer) layer <b>2</b>, the memory core layers <b>3</b>, and the input/output circuit (IF chip) layer <b>4</b>. The stacked layers are connected to each other by through electrodes (not shown in <figref idref="DRAWINGS">FIG. 1</figref> (<i>a</i>)) extending through the respective layers. The interposer layer <b>2</b> is connected to external terminals and serves as a connecting portion for communicating signals from a system bus and signals from the stacked memory between the external terminals and the stacked memory.
0041Each of the memory core layers <b>3</b> serves as a memory portion that has the DRAM cell arrays (namely, DRAM banks) and a peripheral control circuit. The memory core layers <b>3</b> have the same arrangement as one another. In addition, each of the memory core layers <b>3</b> has through electrodes for a power source, through electrodes for a command, and a group of through electrodes for input/output operation with the DRAM banks (memory mats) operable independently of each other. The memory core layers <b>3</b> can perform a parity operation or a no-oparity operation according to the number of the stacked memory core layers <b>3</b>. As shown in <figref idref="DRAWINGS">FIG. 1</figref> (<i>b</i>), if the stacked memory has a parity layer <b>3</b>-<b>1</b>, the memory core layers <b>3</b> perform a parity operation. If the stacked memory has no parity layer <b>3</b>-<b>1</b>, the memory core layers <b>3</b> perform a no-parity operation. The parity layer <b>3</b>-<b>1</b> may have the same arrangement as the memory core layers <b>3</b>. Thus, the parity layer <b>3</b>-<b>1</b> is added to the memory core layers <b>3</b> in the case of parity operation. The memory core layers <b>3</b> and the parity layer <b>3</b>-<b>1</b> are collectively referred to as the memory core layers <b>3</b> unless the parity layer <b>3</b>-<b>1</b> is required to be distinguished from the other memory core layers <b>3</b>.
0042The input/output circuit layer <b>4</b> has an input/output circuit, which may be referred to as the IF chip, for communicating commands, addresses, input data, output data, and the like. The IF chip layer <b>4</b> has a control function of converting external signals from a system bus into signals for the memory core layers and converting signals from the memory core layers into signals for the system bus. Specifically, the IF chip layer <b>4</b> has a function of recognizing the number of the stacked memory core layers and an address assignment function of designating a memory core layer or a bank according to the recognized number of the memory core layers.
0043<figref idref="DRAWINGS">FIG. 2</figref> shows examples of describing a layer arrangement and a bank arrangement. In the following description, each memory core layer <b>3</b> has 8-bit and 8-bank arrangement. However, the numbers of bits and banks are not limited to the illustrated example, and each memory core layer may have desired numbers of bits and banks. Specifically, the memory arrangement for no-parity (normal) operation is illustrated in <figref idref="DRAWINGS">FIG. 2</figref> (<i>a</i>) while the memory arrangement for parity operation is illustrated in <figref idref="DRAWINGS">FIG. 2</figref> (<i>b</i>).
0044In the case of no-parity operation illustrated in <figref idref="DRAWINGS">FIG. 2</figref> (<i>a</i>), the stacked memory includes first to eighth layers of the memory core layers <b>3</b> each of which is divided into first through eighth banks. In the illustrated example, it is assumed that the stacked memory of the first through the eighth layers is used as a DRAM of eight banks determined by the current specification. In order to distinguish between the banks included in each memory core layer and the banks determined by the specification, the banks included in each of the first to eighth memory layers are called mats in the following description. This shows that the bank will be representative of an access unit while the mats will be representative of memory arrays geometrically arranged in each memory core layer later.
0045In the stacked memory of the eight banks, first mats <b>1</b><i>a </i>to <b>1</b><i>h </i>in the respective memory core layers form a first bank in the illustrated example. The through electrodes are determined by positions of the mats in each memory core layer and are assigned to the banks so that no interference takes place among signals for the respective banks. Thus, the banks can operate independently of one another.
0046In the case of parity operation illustrated in <figref idref="DRAWINGS">FIG. 2(</figref><i>b</i>), a parity layer <b>3</b>-<b>1</b> is added as a ninth layer to the first to eighth layers of the memory core layers <b>3</b>. With this structure, the first to eighth layers serve as data memory areas, and the ninth layer serves as a parity memory area for storing parity information. Like in <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>), first mats <b>1</b><i>a </i>to <b>1</b><i>h </i>in the first to eighth layers of the memory core layers <b>3</b> form a first bank. Parity information corresponding to the first mats <b>1</b><i>a </i>to <b>1</b><i>h </i>in the first to eighth layers of the memory core layers <b>3</b> is stored in a second mat in the ninth layer of the parity layer <b>3</b>-<b>1</b>, as illustrated in <figref idref="DRAWINGS">FIG. 2(</figref><i>b</i>). In other words, parity information is not stored in a first mat in the ninth layer, This is because the parity information can not be obtained at the same time as data signals read out of the first through the eighth layers.
0047<figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) and (<i>b</i>) show an 8-bank arrangement with the parity layer <b>3</b>-<b>1</b> and a 16-bank arrangement with the parity layer <b>3</b>-<b>1</b>, respectively. The illustrated 8-bank arrangement is the same as the arrangement in <figref idref="DRAWINGS">FIG. 2(</figref><i>b</i>). In the 16-bank arrangement, the first to eighth layers of the memory core layers <b>3</b> serve as data memory areas, and the ninth layer of the parity layer <b>3</b>-<b>1</b> serves as a parity memory area for storing parity information.
0048Since the memory core layers are composed of eight layers and have the same 8-mat arrangement, the first to eighth mats in the respective memory core layers individually form first to eighth banks when the stacked memory is used as the DRAM of the 8 banks. When the stacked memory is used as the DRAM of the 16-banks, mats in odd numbered layers of the memory core layers form first to eighth banks <b>1</b> to <b>8</b> while mats in even numbered layers of the memory core layers form ninth to sixteenth banks <b>9</b> to <b>16</b>. Specifically, the first mats <b>1</b><i>a</i>, <b>1</b><i>b</i>, <b>1</b><i>c</i>, and <b>1</b><i>d </i>in the odd numbered layers form the first bank while the first mats <b>9</b><i>a</i>, <b>9</b><i>b</i>, <b>9</b><i>c</i>, and <b>9</b><i>d </i>in the even numbered layers form the ninth bank. Parity information corresponding to the first mats in the first to eighth layers of the memory core layers is stored in a second mat in the ninth layer, as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>b</i>).
0049<figref idref="DRAWINGS">FIG. 4</figref> shows an address assignment method of designating a memory core layer and a bank, The example shown in <figref idref="DRAWINGS">FIG. 4</figref> includes first to eighth layers of the memory core layers <b>3</b> and a ninth layer of the parity layer <b>3</b>-<b>1</b> and has an 8-bank structure with parity operation. The layer address assignment of the memory core layer <b>3</b> is defined by 3 bits (Xm, Xm−1, Xm−2) of MSB of the row address. The ninth layer of the parity layer <b>3</b>-<b>1</b> can be designated by the IF chip layer by converting the row address.
0050As shown in <figref idref="DRAWINGS">FIG. 4</figref>, 3 bits (BA<b>2</b>, BA<b>1</b>, BA<b>0</b>) which serves to designate a bank address are used to designate a mat address of each memory layer of the memory core layer <b>3</b>. In this case, a mat of each memory core layer is identical with a bank in the illustrated example. Moreover, LSB (BA<b>0</b>) of 3 bits (BA<b>2</b>, BA<b>1</b>, BA<b>0</b>) of the bank address is inversed to generate an address for designating a mat in the parity layer. By using the address in which LSB (BA<b>0</b>) of the bank address is inversed, any interference in other layers does not take place when parity information is received or transmitted. The mat activation in the parity layer is performed concurrently with activation of the corresponding mats. Accordingly, interactive operation should be limited about banks of the same BA<b>2</b> and BA<b>1</b> in the bank address. In the illustrated example, mats in the memory core layers correspond to banks of the stacked memory, banks and mats might be considered to have the same meaning.
0051In the parity layer <b>3</b>-<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, parity information of the same mat in the memory core layers is stored in one bank of the 8-bank structure. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, one mat in the parity layer <b>3</b>-<b>1</b> is divided into eight regions (submats) corresponding to the eight banks. The regions (submats) are individually accessed by selection addresses (Xm, Xm−1, Xm−2) of the corresponding layers. For example, parity information of the seventh bank of the fourth layer (specified by Xm=0, Xm−1=1,Xm−2=1) of the memory core layers is stored in a fourth region (submat) (Xm=<b>0</b>, Xm-<b>1</b>=<b>1</b>, Xm-<b>2</b>=<b>1</b>) of the eighth mat in the parity layer. Thus, the submat is designated by the selection address (Xm, Xm-<b>1</b>, Xm-<b>2</b>) of the layer.
0052The stacked memory according to the present invention includes an external terminal (interposer) layer <b>2</b> for connection with external terminals, the plurality of memory core layers <b>3</b>, and the IF chip layer <b>4</b>. The memory core layers <b>3</b> have an identical arrangement with one another. In the case of parity operation, a parity layer for parity operation is added as mentioned before in the manner illustrated in <figref idref="DRAWINGS">FIG. 4</figref>. With regard to address assignment, bits of MSB of the row address are assigned to a layer designation of the memory core layers, and a bank address is assigned to a bank designation. The respective banks correspond to mats in the illustrated memory core layers in <figref idref="DRAWINGS">FIG. 4</figref>. Mats in the parity layer are arranged so that a layer and a bank of the parity layer are designated by the IF chip layer and a bank address in which LSB is inversed, respectively. Addresses corresponding to layer designation addresses of the respective memory core layers are assigned to the submat regions in which parity information is stored. The aforementioned address assignment is performed by the IF chip layer.
0053As described above, the stacked memory according to the present invention is formed by stacking a plurality of the same memory core layers <b>3</b> having through electrodes, the interposer (external terminal) layer <b>2</b> for connection with the external terminals, and the IF chip layer <b>4</b>. The parity layer <b>3</b>-<b>1</b> is added to perform a parity operation. By optimizing the address assignment with the IF chip layer, the stacked memory can selectively perform a no-parity operation and a parity operation and can take various bank arrangements.
EXAMPLE 1
0054Example 1 according to the present invention will be described with reference to <figref idref="DRAWINGS">FIGS. 5 through 9</figref>. This example 1 relates to an address assignment method on the assumption that a number of banks is constant and while the memory core layers each of which has eight mats are varied in number, Although the stacked memory having eight memory core layers has thus far been described as a basic form in the above embodiment, description is made about cases in which a stacked memory has different numbers of memory core layers (one, two, four, and eight layers) in Example 1.
0055<figref idref="DRAWINGS">FIG. 5</figref> is a diagram of conventional bank arrangements to show possible problems. <figref idref="DRAWINGS">FIG. 6(</figref><i>a</i>) is a table showing an address assignment for designating a layer and a bank in an 8-bank arrangement. <figref idref="DRAWINGS">FIG. 6(</figref><i>b</i>) is a diagram showing B-bank arrangements in various cases. <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) is a table showing an address assignment for designating a layer and a bank in a 16-bank arrangement. <figref idref="DRAWINGS">FIG. 7(</figref><i>b</i>) is a diagram showing 16-bank arrangements in various cases. <figref idref="DRAWINGS">FIG. 8(</figref><i>a</i>) is a block diagram for explaining mat selection by the use of programmable address decoders. <figref idref="DRAWINGS">FIG. 8(</figref><i>b</i>) is a circuit diagram of the programmable address decoder <b>6</b> shown in <figref idref="DRAWINGS">FIG. 8(</figref><i>a</i>). <figref idref="DRAWINGS">FIG. 8(</figref><i>c</i>) is a logical table of the programmable address decoder <b>6</b> shown in <figref idref="DRAWINGS">FIG. 8(</figref><i>a</i>). <figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>) is a block diagram for explaining mat selection with use of comparators. <figref idref="DRAWINGS">FIG. 9(</figref><i>b</i>) is a circuit diagram of the comparator shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>).
0056<figref idref="DRAWINGS">FIG. 5</figref> shows conventional bank arrangements in which memory core layers having eight banks are simply stacked. As shown in <figref idref="DRAWINGS">FIG. 5(</figref><i>a</i>), one memory core layer has first to eighth mats numbered from 1 to 8 which form first to eighth banks <b>1</b>, respectively. In <figref idref="DRAWINGS">FIG. 5(</figref><i>b</i>), when two memory core layers have each eight mats and are stacked together, mats of the two memory core layers are handled as individual banks. As a result, the bank arrangement has banks <b>1</b> to <b>16</b>. Similarly, in a case of four memory core layers (<figref idref="DRAWINGS">FIG. 5(</figref><i>c</i>), mats of the four memory core layers are handled as individual banks and thus, the bank arrangement has banks <b>1</b> to <b>32</b>. In a case of eight memory core layers, the bank arrangement has banks <b>1</b> to <b>64</b>. Thus, each bank arrangement has banks equal to the total number of banks included in the memory core layer(s). This shows that the number of banks independently operating in the stacked memory widely varies depending on the number of the stacked memory core layers.
0057The number of banks varies according to the number of stacks in a conventional method in which all mats independently operate and correspond to banks. In other words, the mats in the respective memory core layers are in one-to-one correspondence with the banks. This problematically causes unconformity to current DRAM specifications. General DRAM specifications have a constant range of 4 to 16 banks (8 to 16 banks in a case of a large-capacity DRAM). The stacked memory is required to cope with such specifications. In this example, the numbers of the memory core layers are powers of two but may be other values.
0058<figref idref="DRAWINGS">FIG. 6(</figref><i>a</i>) is a table showing an address assignment for designating a layer and a bank in an 8-bank arrangement, and <figref idref="DRAWINGS">FIG. 6(</figref><i>b</i>) is a diagram showing 8-bank arrangements in various cases. In the cases of 8-bank arrangements having one, two, four, and eight layers of the memory core layers <b>3</b>, mats <b>1</b> to <b>8</b> in each memory core layer <b>3</b> are made to correspond to banks <b>1</b> to <b>8</b> of the stacked memory. Since the bank conforms to the mat in each memory core layer, the bank designates each mat in each memory core layer by a bank address BA<b>0</b>, BA<b>1</b>, BA<b>2</b>. In the case of the 8-bank arrangement, a bank address BA<b>3</b> may not be used.
0059Address bit(s) are added to MSB of the row address to designate a layer of the memory core layers <b>3</b> and are specified by R-MSB (+1bit), R-MSB (+2bit), and R-MSB(+3bit) in <figref idref="DRAWINGS">FIG. 6</figref> (<i>a</i>). In a case of two memory core layers, address 1 bit is added to MSB of the row address so as to designate a layer of the memory core layers with the added address 1 bit. In a case of four memory core layers, address 2 bits are added to MSB of the row address so as to designate a layer of the memory core layers with the added address 2 bits. In a case of eight memory core layers, address 3 bits are added to MSB of the row address so as to designate each layer of the memory core layers with the added address 3 bits. Thus, a memory core layer is designated by an address added to MSB of the row address.
0060Thus, each memory core layer is designated by address bit(s) added to MSB of the row address (namely, R-MSB+1, R-MSB+2, R-MSB+3), and a bank is designated by a bank address BA<b>0</b>, BA<b>1</b>, BA<b>2</b> in the stacked memory. Bank arrangements shown in <figref idref="DRAWINGS">FIG. 6(</figref><i>b</i>) are composed of eight banks irrespective of the number of the memory core layers. With such address assignment, all of the memory core layers are designated by addresses under the same conditions. Accordingly, every memory core layer is equally addressed. Thus, the memory cores have the same performance irrespective of positions of the layers. There is no difference in performance between the layers.
0061<figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) is a table showing an address assignment for designating a layer and a bank in a 16-bank arrangement, and <figref idref="DRAWINGS">FIG. 6(</figref><i>b</i>) is a diagram showing 16-bank arrangements in various cases. In the cases of 16-bank arrangements, the number of the mats in the memory core layer (8 mats) does not conform to the number of the banks in the stacked memory (16 banks). Accordingly, a half of the mats (mats <b>1</b> to <b>8</b>) should be assigned to banks <b>1</b> to <b>8</b> while another half of the mats should be assigned to banks <b>9</b> to <b>16</b>. In the following example, addresses are converted so that mats in odd layers of the memory core layers are assigned to banks <b>1</b> to <b>8</b> while mats in even layers of the memory core layers are assigned to banks <b>9</b> to <b>16</b>. An odd layer or an even layer of the memory core layers is designated by a bank address BA<b>3</b>. The bank address BA<b>3</b> thus serves as an address for designating a bank address as well as an address for designating a layer, as shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>).
0062Mats <b>1</b> to <b>8</b> in odd layers are assigned to banks <b>1</b> to <b>8</b> by the bank address BA<b>3</b> while mats <b>1</b> to <b>8</b> in even layers are assigned to banks <b>9</b> to <b>16</b> by adding eight. Each mat in a memory core layer is designated by a bank address BA<b>0</b>, BA<b>1</b>, BA<b>2</b>. Bank arrangements thus addressed are shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>b</i>).
0063Further, address bit(s) are added to MSB of the row address (R-MSB +1, R-MSB+2, R-MSB+3) so as to designate a layer of the memory core layers. In a case of two memory core layers, a layer of the memory core layers is designated by the bank address BA<b>3</b>. In a case of four memory core layers, address 1 bit is added to MSB of the row address so as to designate a layer of the memory core layers by the use of the added address 1 bit and the bank address BA<b>3</b>. In a case of eight memory core layers, address 2 bits are added to MSB of the row address so as to designate a layer of the memory core layers by the use of the added address 2 bits and the bank address BA<b>3</b>. Thus, a memory core layer is designated by the bank address BA<b>3</b> and address bit(s) added to MSB of the row address.
0064For address assignment, the bank address bit BA<b>3</b> and the address bit(s) added to MSB of the row address are assigned to the memory core layer. The bank address is assigned to the bank. With such address assignment, all of the memory core layers are designated by addresses under the same conditions. Accordingly, every memory core layer is equally addressed. Thus, the memory cores have the same performance irrespective of positions of the layers. There is no difference in performance between the layers.
0065Examples in which banks are assigned regularly in the order of the mats have been described above. However, mats and banks may arbitrarily be assigned. <figref idref="DRAWINGS">FIGS. 8 and 9</figref> show such flexible bank arrangements. <figref idref="DRAWINGS">FIG. 8</figref> shows a mat selection method with use of programmable address decoders. <figref idref="DRAWINGS">FIG. 9</figref> shows a mat selection method with use of comparators. A 16-bank arrangement is applied to <figref idref="DRAWINGS">FIGS. 8 and 9</figref>. Four bits are required as address bits.
0066In the mat selection method with use of programmable address decoders, each of the memory core layers <b>3</b> has a plurality of through electrodes <b>5</b> and programmable address decoders <b>6</b> for selecting a corresponding mat. A bank address invalid signal A, a bank address signal B, and a bank address inverse signal C are inputted from the through electrodes <b>5</b> into each programmable address decoder <b>6</b>. <figref idref="DRAWINGS">FIG. 8(</figref><i>b</i>) is a circuit diagram of the programmable address decoder <b>6</b>, and <figref idref="DRAWINGS">FIG. 8(</figref><i>c</i>) is a logical table of the programmable address decoder <b>6</b>.
0067The bank address signal B supplies a common address to the respective chips and mats. The bank address invalid signal A and the bank address inverse signal C are inputted into each mat at the time of initialization. Each of selectors <b>7</b> switches the address invalid signal A and the bank address B by the address inverse signal C at the time of initialization. With the initialization, a potential of an output node N<b>1</b> of each selector <b>7</b> is set and inputted into an EXCLUSIVE-OR circuit <b>8</b>.
0068Each of the EXCLUSIVE-OR circuits <b>8</b> judges consistency and inconsistency of nodes N<b>1</b> and N<b>2</b>. The EXCLUSIVE-OR circuit <b>8</b> outputs an inputted bank address B(n) to an AND circuit <b>9</b> when the address is not inversed, outputs an inversed NOT B(n) to the AND circuit <b>9</b> when the address is inversed, and outputs a low level “0” to the AND circuit <b>9</b> when the address is invalid. The AND circuit <b>9</b> outputs a mat activation signal D. Here, the bank address B(n) represents a bank address B for each bit. The bank address B represents a bank address BA<b>0</b> to BA<b>3</b>.
0069As shown in the logical table, non-inversion, inversion, and invalidation of the bank address B can be specified for each bit of the bank address B by the address inverse signal C and the address invalid signal A. A desired mat can be selected by specifying non-inversion, inversion, and invalidation of the bank address B for each bit, For example, a third mat in an odd layer is to be designated as a fifth bank. At that time, an inputted bank address B is (0, 1, 0, 0). The address is inputted for each bit from an upper side of the decoder circuit shown in <figref idref="DRAWINGS">FIG. 8(</figref><i>b</i>). When a third mat in an odd layer is initialized, the nodes N<b>1</b> are set to be inversion, non-inversion, inversion, and inversion (1, 0, 1, 1). Since the inputted bank address B is (0, 1, 0, 0), all outputs of nodes N<b>3</b> have a high level. Thus, the third mat in the odd layer is selected and activated. With regard to other mats, any of the outputs of the nodes N<b>3</b> has a low level, and the mats are not activated. This selection method allows flexible mat selection and achieves flexible bank arrangements.
0070In the mat selection method with use of comparators shown in <figref idref="DRAWINGS">FIG. 9</figref>, each of the memory core layers <b>3</b> has a plurality of through electrodes <b>5</b> for signals and comparators <b>10</b> for selecting a corresponding mat. A layer address signal E, a layer selection address signal F, and a mat selection signal G, which are common to the respective mats in the respective layers, are inputted from the through electrodes <b>5</b> into each comparator <b>10</b>. <figref idref="DRAWINGS">FIG. 9(</figref><i>b</i>) is a circuit diagram of the comparator <b>10</b>.
0071The layer address signal E and the layer selection address signal F are inputted into each EXCLUSIVE-NOR circuit <b>11</b>. Each of the EXCLUSIVE-NOR circuits <b>11</b> judges consistency and inconsistency of the layer address signal E and the layer selection address signal F and outputs the results to an AND circuit <b>12</b>. The mat selection signal G is additionally inputted into the AND circuit <b>12</b>. The AND circuit <b>12</b> outputs the mat activation signal D. When the layer address signal E and the layer selection address signal F are consistent with each other while the mat selection signal G has a high level, the mat activation signal D is activated so as to select the mat in the layer. The layer address signal E is specified at the time of initialization. Selection of the memory core layer is performed by the layer address, and mat selection of the mat is performed by the mat selection signal G. This selection method allows flexible mat selection and achieves flexible bank arrangements.
0072In the stacked memory of the present example, a plurality of memory core layers having the same arrangement are stacked, and address setting is conducted so as to maintain a constant number of banks. The address setting allows mats in the memory core layers to be designated and selected as banks of the stacked memory. Accordingly, it is possible to achieve a desired constant number of banks in the stacked memory. The memory core layer is designated by the significant address added to the row address and the significant bank address. The bank address sets the mat in the memory core layer with the bank address signal. Further, flexible bank designation can be achieved by the programmable address decoders or the comparators. The stacked memory has a desired number of memory core layers. The mats in the memory core layers are flexibly set as banks of the stacked memory. Thus, the stacked memory can have a constant number of banks.
EXAMPLE 2
0073Example 2 will be described with reference to <figref idref="DRAWINGS">FIG. 10</figref>. This example relates to a refresh control in a stacked memory. <figref idref="DRAWINGS">FIG. 10(</figref><i>a</i>) is a diagram showing a stacked memory for explanation of the refresh control. <figref idref="DRAWINGS">FIG. 10(</figref><i>b</i>) is a diagram showing a group arrangement of banks to be refreshed in a case of two lines of refresh counters. <figref idref="DRAWINGS">FIG. 10(</figref><i>c</i>) is a diagram showing a group arrangement of banks to be refreshed in a case of four lines of refresh counters.
0074The stacked memory includes an interposer <b>2</b>, a plurality of memory core layers <b>3</b>, and an IF chip <b>4</b>. The layers are connected to each other by through electrodes. A refresh control in the stacked memory is performed by the IF chip <b>4</b>. The IF chip <b>4</b> has refresh counters for the refresh control. When the IF chip <b>4</b> has two lines of refresh counters, two groups of banks <b>1</b> to <b>4</b> and banks <b>5</b> to <b>8</b> are designated by 1 bit of MSB of the bank address BA. Each group is refreshed as shown in <figref idref="DRAWINGS">FIG. 10(</figref><i>b</i>). When the IF chip <b>4</b> has four lines of refresh counters, four groups of banks <b>1</b> and <b>2</b>, banks <b>3</b> and <b>4</b>, banks <b>5</b> and <b>6</b>, and banks <b>7</b> and <b>8</b> are designated by 2 bits of MSB of the bank address BA. Each group is refreshed as shown in <figref idref="DRAWINGS">FIG. 10(</figref><i>c</i>).
0075In a case of auto-refresh, refresh is performed for each group. A bank in which data is stored and a bank for the corresponding parity layer are in the same group. This can similarly be applied to other refresh processes. Power-down state of each memory core layer is set or cancelled by a signal from the IF chip <b>4</b>. In a case of self-refresh in the power-down state, the IF chip <b>4</b> controls all of the layers.
0076In the present example, the IF chip has refresh counters for refreshing grouped banks. A desired bank can be selected by the bank address. Accordingly, the stacked memory can automatically perform a refresh process with the refresh counters.
0077Although some examples of the present invention have been described in detail, it should be understood that the present invention is not limited to those examples, and that various changes and modifications may be made therein without departing from the scope of the appended claims.
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Numbers
- Publication
- 7894293
- Application
- 11560898
Titles
- English
- Memory bank arrangement for stacked memory
Patent term adjustment
- A delay
- +817 daysthe office missed an examination deadline
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- +462 dayspendency past three years
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- −147 daysdelays counted once
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- −31 days
- Net adjustment
- 1,101 days
Classification
- CPC, 1
- G11C5/025
- IPC, 3
- G11C8 00
- H10D48 36
- H10D30 01