Multiple access techniques for a wireless communication medium

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to concurrently filed and commonly owned U.S. patent application Ser. No. 11/560,716, entitled “MULTIPLE ACCESS TECHNIQUES FOR A WIRELESS COMMUNICATION MEDIUM,”.

BACKGROUND

1. Field

This application relates generally to communications, and to techniques that enable multiple devices to access a wireless medium.

2. Background

In a wireless communication system multiple wireless devices may communicate with one another via signals having frequencies within a given radio frequency band. Here, provisions may be made to prevent transmissions from one device from interfering with transmissions from another device. For example, some systems employ media access control that allows only one device to use a given medium (e.g., a radio frequency band) at a time. One way of accomplishing this is to require that each device check the medium to determine whether another device is currently transmitting over the medium. If the medium is in use, the device will delay transmitting until a later time when the medium is not in use. Alternatively, some systems use a signaling technique such as spread spectrum that modifies transmitted signals to reduce the likelihood of transmissions from one device interfering with simultaneous transmissions of another device within the same frequency band.

Techniques such as these may be employed in a variety of wireless communication systems. An example of such a wireless communication system is an ultra-wide band system. In some implementations an ultra-wide band system may employ pulse signaling and bandwidths on the order of 500 MHz or more.

Various multiple access schemes have been proposed for use in ultra-wide band systems. One example is code division multiple access (“CDMA”) incorporating direct sequence, time hopping or an appropriate combination of these two schemes. Another example is frequency division multiple access (“FDMA”). Use of the ALOHA family of ad hoc multiple access techniques also have been proposed, for example, for intra-piconet conflict resolution. Chaos-based ultra-wide band systems have been proposed that use length division multiple access (“LDMA”) by varying the time duration of the ultra-wide band pulse.

In a typical application an ultra-wide band system is used for communication over relatively short distances. For example, ultra-wide band technology may be employed in a physical layer implementation for a body area network (“BAN”) or a personal area network (“PAN”). A wide variety of wireless devices having different power and data rate requirements may be deployed in such a BAN or a PAN. Consequently, various ultra-wide band receiver design approaches may be employed. For example, a receiver design may employ a coherent RAKE receiver design, a non-coherent energy detector design, or a transmitted reference design. Given the disparate requirements of applications such as these, a need exists for effective and adaptable multiple access techniques for wireless communications.

SUMMARY

A summary of selected aspects of the disclosure follows. For convenience, one or more aspects may be referred to herein simply as “an aspect” or “aspects.”

In some aspects a multiple access technique for a wireless system defines different time intervals for different channels that concurrently access a common and wireless medium. For example, in a pulse-based wireless system, pulses for one channel are separated by a given time period or periods while pulses for another channel are separated by a different time period or periods. Through the use of such a technique two or more devices (e.g., associated with one or more users) may communicate via two or more concurrently active channels.

In some aspects a multiple access technique is provided for a transmitted reference system. Here, different delay periods may be defined between transmitted reference pulses and associated data pulses for different channels. For example, in a system that utilizes a fixed delay period between a reference pulse and an associated data pulse, one delay period is defined for one channel and a different delay period is defined for another channel. In a system that utilizes multiple delay periods between a reference pulse and an associated data pulse, one set of delay periods is defined for one channel and a different set of delay periods is defined for another channel. In a system that utilizes adjustable delay periods between a reference pulse and an associated data pulse, one delay adjust sequence is defined for one channel and a different delay adjust sequence is defined for another channel.

In some aspects a multiple access technique uses a common reference pulse for multiple channels. For example, a system may generate a reference pulse followed by two data pulses. Here, a first data pulse associated with a first channel may follow the reference pulse by a delay period defined for the first channel. A second data pulse associated with a second channel follows the reference pulse by a different delay period defined for the second channel.

In some aspects a multiple access technique defines different pulse repetition periods for different channels. For example, pulses transmitted over one channel may be separated by one pulse repetition period while pulses transmitted over another channel may be separated by a different pulse repetition period. The pulse repetition period for a given channel may be adjustable. In this case, different pulse repetition period sequences may be assigned to different channels. As an example, one pseudorandom pulse repetition period sequence may be assigned to one channel while a different pseudorandom pulse repetition period sequence may be assigned to another channel.

In some aspects a multiple access technique incorporating different pulse repetition periods may be implemented in a transmitted reference system. Here, one or more of the transmitted reference techniques described above also may be employed. For example, a system may define different channels through the use of different pulse repetition periods and different reference to data pulse delay periods.

In some aspects one or more of the above techniques may be employed in an ultra-wide band system. For example, multiple ultra-wide band channels may be defined by defining different pulse repetition periods and or different reference pulse to data pulse delay periods for each channel.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the disclosure will be more fully understood when considered with respect to the following detailed description, appended claims and accompanying drawings, wherein:

<figref idrefs="DRAWINGS">FIG. 1</figref> is a simplified block diagram of several exemplary aspects of a communication system adapted to provide concurrent channels;

<figref idrefs="DRAWINGS">FIG. 2</figref> is a flowchart of several exemplary aspects of operations that may be performed to establish and communicate via one or more channels;

<figref idrefs="DRAWINGS">FIG. 3</figref> is a simplified diagram illustrating an example of different reference pulse to data pulse delays for different channels;

<figref idrefs="DRAWINGS">FIG. 4</figref> is a simplified diagram illustrating an example of different pulse repetition periods for different channels;

<figref idrefs="DRAWINGS">FIG. 5</figref> is a simplified block diagram of several exemplary aspects of a transmitter for a pulse-based system;

<figref idrefs="DRAWINGS">FIG. 6</figref> is a flowchart of several exemplary aspects of operations that may be performed to transmit pulse-based signals;

<figref idrefs="DRAWINGS">FIG. 7</figref> is a flowchart of several exemplary aspects of operations that may be performed to define delay periods for transmitted or received pulses;

<figref idrefs="DRAWINGS">FIG. 8</figref> is a simplified block diagram of several exemplary aspects of a receiver for a pulse-based system;

<figref idrefs="DRAWINGS">FIG. 9</figref> is a flowchart of several exemplary aspects of operations that may be performed to receive pulse-based signals;

<figref idrefs="DRAWINGS">FIG. 10</figref> is a simplified diagram illustrating an example of the use of a common reference pulse for multiple channels;

<figref idrefs="DRAWINGS">FIG. 11</figref> is a simplified block diagram of several exemplary aspects of a system providing a common reference pulse for multiple channels;

<figref idrefs="DRAWINGS">FIG. 12</figref> is a flowchart of several exemplary aspects of operations that may be performed in conjunction with providing a common reference pulse for multiple channels;

<figref idrefs="DRAWINGS">FIG. 13</figref> is a simplified diagram illustrating an example of different pulse repetition periods for different channels;

<figref idrefs="DRAWINGS">FIG. 14</figref> is a flowchart of several exemplary aspects of operations that may be performed to transmit pulses using different pulse repetition periods;

<figref idrefs="DRAWINGS">FIG. 15</figref> is a simplified diagram illustrating an example of transmitted reference signals implementing binary phase shift keying;

<figref idrefs="DRAWINGS">FIG. 16</figref> is a simplified diagram illustrating an example of transmitted reference signals implementing binary pulse position modulation;

<figref idrefs="DRAWINGS">FIG. 17</figref> is a simplified block diagram of several exemplary aspects of an apparatus adapted to transmit signals;

<figref idrefs="DRAWINGS">FIG. 18</figref> is a simplified block diagram of several exemplary aspects of an apparatus adapted to receive and generate signals; and

<figref idrefs="DRAWINGS">FIG. 19</figref> is a simplified block diagram of several exemplary aspects of an apparatus adapted to provide pulses in accordance with a pulse repetition period.

In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus or method. Finally, like reference numerals may be used to denote like features throughout the specification and figures.

DETAILED DESCRIPTION

Various aspects of the disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure and/or function disclosed herein is merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, an apparatus may be implemented and/or a method practiced using other structure and/or functionality in addition to or other than one or more of the aspects set forth herein.

A multiple access technique employed in a wireless communication system enables two or more devices to communicate over a shared communication medium. As an example, <figref idrefs="DRAWINGS">FIG. 1</figref> illustrates certain aspects of a system <b>100</b> where several wireless communication devices <b>102</b>, <b>104</b>, <b>106</b> and <b>108</b> are adapted to establish wireless communication channels <b>110</b>, <b>112</b>, <b>114</b> and <b>116</b> with one another. To reduce the complexity of <figref idrefs="DRAWINGS">FIG. 1</figref> selected aspects of the devices are only illustrated in conjunction with the device <b>102</b>. It should be appreciated, however, that the devices <b>104</b>, <b>106</b> and <b>108</b> may incorporate similar functionality.

In the example of <figref idrefs="DRAWINGS">FIG. 1</figref>, the devices <b>102</b>, <b>104</b>, <b>106</b> and <b>108</b> communicate via a pulsed-based physical layer. In some aspects the physical layer may utilize ultra-wide band pulses that have a relatively short length (e.g., on the order of a few nanoseconds) and a relatively wide bandwidth. In some aspects an ultra-wide band signal may be defined as a signal having a fractional bandwidth greater than approximately 20% or having a bandwidth greater than approximately 500 MHz.

In some aspects the system <b>100</b> may comprise a transmitted reference system. In this case, a device sends data by transmitting a reference pulse followed by an associated data pulse. A device that receives the pulses may then use the reference pulse as a “noisy matched filter” to detect the data represented by the data pulse.

The device <b>102</b> illustrates several components that may be used to establish and communicate over one or more channels. For example, a processor <b>118</b> may cooperate with a transceiver <b>120</b> to transmit signals over a channel and receive signals from a channel. Here, the processor <b>118</b> implements functionality <b>122</b> to set up a channel. This channel setup component <b>122</b> may be used to define and implement different signaling parameters (e.g., intervals between pulses) for different channels. The processor <b>118</b> also implements functionality <b>124</b> to associate with other devices so that each device will use the same signaling parameters to communicate over a given channel.

Advantageously, through the use of multiple access techniques as taught herein, the devices <b>102</b>, <b>104</b>, <b>106</b> and <b>108</b> may concurrently (e.g., simultaneously) utilize a shared medium. For example, the devices <b>102</b>, <b>104</b>, <b>106</b> and <b>108</b> may concurrently transmit signals within the same ultra-wide band frequency band. As depicted in <figref idrefs="DRAWINGS">FIG. 1</figref>, the device <b>102</b> may communicate with the device <b>104</b> via two or more concurrently operating channels (e.g., channels <b>110</b> and <b>112</b>). In addition, the device <b>102</b> may concurrently communicate with multiple devices (e.g., devices <b>104</b> and <b>106</b>) over different channels (e.g., channels <b>110</b> and <b>114</b>). Furthermore, one set of devices (e.g., devices <b>102</b> and <b>104</b>) may communicate via one channel (e.g., channel <b>110</b>) while another set of devices (e.g., devices <b>106</b> and <b>108</b>) concurrently communicate via another channel (e.g., channel <b>116</b>).

The system <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> is provided as an example of one possible system that may employ a multiple access technique. It should be appreciated that the teachings herein may be incorporated into other types of systems implemented using various types of devices that support various communication techniques and protocols.

Exemplary operations that may be used to establish a channel and communicate over the channel will now be discussed in conjunction with the flowchart of <figref idrefs="DRAWINGS">FIG. 2</figref>. For convenience, the operations of <figref idrefs="DRAWINGS">FIG. 2</figref> (or any other flowchart herein) may be described as being performed by specific components. It should be appreciated, however, that these operations may be performed in conjunction with and/or by other components.

Devices in a wireless communication system may be configured to establish a channel with another device by initially communicating over a known channel. Here, a wireless device seeking to establish a channel may send preliminary messages (e.g., polling messages) over the known channel. In addition, each device in the system may be configured to periodically scan the known channel for any preliminary messages.

Accordingly, as represented by block <b>202</b>, the devices may configure their respective transceivers to initially use default parameter values for sending signals to and receiving signals from the wireless medium. For example, a device may set the pulse repetition period to a value defined for a known channel. In addition, in a transmitted reference system, the device may set the reference pulse to data pulse delay to a value defined for a known channel. Also, in an implementation that uses adjustable intervals for the known channel, the device may configure the transceiver to use a default sequence (e.g., a default pseudorandom sequence) for adjusting the intervals.

As represented by block <b>204</b>, once preliminary communications are established between two or more devices over the known channel, the devices may perform an association procedure whereby the devices learn the respective capabilities of each device. Based on those capabilities, the devices may negotiate to establish a channel for subsequent communication.

As represented by block <b>206</b>, one or more of the devices may select channel parameters to be used for the channel. These channel parameters may include, for example, one or more reference pulse to data pulse delay values, one or more pulse repetition periods, some other suitable parameter(s), or a combination of two or more of these parameters. As will be discussed in more detail below, in general, these channel parameters are selected to avoid or reduce the probability of interference with other channels in the communication system.

In some cases a device may unilaterally define the parameters to be used for a given channel. For example, the device may randomly select the channel parameters. Alternatively, the device may select channel parameters based on a set of one or more device-related parameters (e.g., a device address, a device location, a time of the day, etc.). In other cases a device may select a channel parameter based on information it has regarding the channel parameters of other channels that are or have been defined in the system (e.g., currently active channels). In any case, as represented by block <b>208</b>, the device may send this channel parameter information to each device that will communicate over the channel.

Alternatively, in some cases a device may communicate with one or more other devices to define the channel parameters. For example, a device may select a channel based on information it obtains from other devices regarding the channel parameters of other channels defined in the system. In some cases, in conjunction with the association procedure two or more devices may negotiate to select the channel parameters.

As represented by block <b>210</b>, once all of the devices have generated or obtained the selected channel parameters, the devices may set up their respective transceivers to transmit and receive signals in accordance with the selected channel parameters.

Operations similar to those discussed above may be performed to establish and use other channels in the communication system. In this case, however, a wireless device may select different channel parameters at block <b>206</b> to establish a channel that may be used concurrently with other channels in the system. Here, the channel parameters (e.g., reference to data delay, pulse repetition period, adjustment sequence) for one or more channels may be selected such that concurrent channels may operate with relatively little interference between the signals (e.g., pulses) of the channels. <figref idrefs="DRAWINGS">FIGS. 3 and 4</figref> illustrate two examples of signaling that may be used to establish concurrent channels.

<figref idrefs="DRAWINGS">FIG. 3</figref> illustrates defining different reference pulse to data pulse delay periods for different channels. Referring to channel <b>1</b>, a data pulse <b>302</b> follows a reference pulse <b>304</b> by a delay period <b>306</b>. Referring to channel <b>2</b>, a data pulse <b>308</b> follows a reference pulse <b>310</b> by a delay period <b>312</b>. As shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, the delay period <b>312</b> is different than the delay period <b>306</b>. In this way, the probability of the pulses for channel 1 interfering with the pulses of channel 2 may be reduced or substantially eliminated.

In addition, each delay period <b>306</b> or <b>312</b> may be selected to avoid interference between its respective reference and data pulses. For example, each delay period <b>306</b> or <b>312</b> may be greater than a maximum channel delay spread. This delay spread represents a time interval within which most of the energy from a pulse (e.g., reference pulse <b>304</b> or <b>310</b>) is captured.

<figref idrefs="DRAWINGS">FIG. 4</figref> illustrates defining different pulse repetition periods for different channels. Referring to channel 1, a second set of pulses <b>404</b> follows a first set of pulses <b>406</b> by a pulse repetition period <b>408</b>. Referring to channel 2, a second set of pulses <b>410</b> follows a first set of pulses <b>412</b> by a pulse repetition period <b>414</b>. Again, the pulse repetition period <b>408</b> is different than the pulse repetition period <b>414</b>. Again, this enables interference between the two channels to be reduced or substantially eliminated.

The use of different pulse repetition periods is applicable to a variety of pulse-based communication systems. The specific example of <figref idrefs="DRAWINGS">FIG. 4</figref> relates to a transmitted reference system. Here, the reference pulse to data pulse delay period is represented by the arrows <b>402</b>. As will be discussed in more detail below, the same delay period <b>402</b> or different delay periods <b>402</b> may be defined for the two channels.

Exemplary components and operations of a wireless system will now be described in conjunction with <figref idrefs="DRAWINGS">FIGS. 5-9</figref>. <figref idrefs="DRAWINGS">FIGS. 5 and 6</figref> relate in some aspects to transmitting transmitted reference signals. <figref idrefs="DRAWINGS">FIG. 7</figref> relates to operations that may be performed to define channel delay parameters. <figref idrefs="DRAWINGS">FIGS. 8 and 9</figref> relate in some aspects to receiving transmitted reference signals.

<figref idrefs="DRAWINGS">FIG. 5</figref> depicts a transmitter <b>500</b> including a signal generator (e.g., a pulse generator <b>502</b>), a delay circuit <b>504</b> and a combining circuit (e.g., including a multiplier <b>506</b> and an adder <b>508</b>) adapted to generate pulses. Exemplary operations of the transmitter <b>500</b> will be described in conjunction with the flowchart of <figref idrefs="DRAWINGS">FIG. 6</figref>.

As represented by block <b>602</b> in <figref idrefs="DRAWINGS">FIG. 6</figref>, initially a wireless device including the transmitter <b>500</b> may define channel delay parameters, for example, as discussed in conjunction with <figref idrefs="DRAWINGS">FIG. 2</figref> above. These operations will be treated in some detail with reference to the flowchart of <figref idrefs="DRAWINGS">FIG. 7</figref>

Block <b>602</b> in <figref idrefs="DRAWINGS">FIG. 7</figref> represents that the operations to follow may be performed to define one or more channel delay parameters for each of one or more channels in a communication system. In general, these operations may be performed in conjunction with selecting a reference to data delay, a pulse repetition period or some other parameter that may be used to define a channel. Multiple operations may be performed for each channel. For example, the operations may be performed once to select a fixed or variable reference to data delay and performed another time to select a fixed or variable pulse repetition period for the same channel. These operations may be performed for one or more channels. For example, the parameters for any one channel may be selected as discussed herein to avoid interference with other channels. In addition, the parameters for more than one channel may be selected as discussed herein to avoid interference between these channels or with other channels.

As represented by block <b>702</b>, a delay parameter for a channel may be a fixed delay or an adjustable delay. As an example of the latter, a delay parameter may be continually adjusted through a range of delay values in accordance with a known sequence. In this case, a receiver having information regarding the sequence may recover data sent using the sequence once the receiver synchronizes to the transmitted sequence.

As represented by block <b>704</b>, if the delay is fixed the device selects one or more delay time periods for the channel. For example, as will be discussed in more detail below, in a transmitted reference system that employs binary phase shift keying or some other n-ary phase shift keying, a data pulse will follow a reference pulse by a given delay period. Alternatively, in a transmitted reference system that employs binary pulse position modulation or some other n-ary pulse position modulation, a data pulse will follow a reference pulse by one of a predefined set of different delay periods.

The device may include one or more components adapted to select a delay. For example, the transmitter <b>500</b> may include a fixed delay selector <b>510</b> adapted to select the reference to data delay time period(s). The receiver <b>800</b> may include a similar fixed delay selector <b>808</b>. In addition, the transmitter <b>500</b> may include a fixed delay selector <b>512</b> adapted to select a pulse repetition period and the receiver <b>800</b> may include a similar fixed delay selector <b>810</b>. In practice, common fixed delay selectors may be used by the transmitter <b>500</b> and the receiver <b>800</b>. That is, the selectors <b>510</b> and <b>808</b> may comprise the same selector while the selectors <b>512</b> and <b>810</b> may comprise the same selector. The corresponding selection process or processes may be performed in various ways as represented, for example, by blocks <b>706</b>, <b>708</b> and <b>710</b> of <figref idrefs="DRAWINGS">FIG. 7</figref>.

In general, a device selects the time period(s) to avoid or reduce the probability of interference with other channels (block <b>706</b>). For example, the time period(s) selected for different channels may be orthogonal or substantially orthogonal. In this way, pulses for one channel may be prevented from colliding with pulses for another channel. As discussed above, a device may take into account information regarding the parameters of other active or inactive channels when selecting parameters for a new channel. Such information may be acquired, for example, based on prior channels used by the device or based on information provided by other devices (e.g., a peer device or a central controller device).

As represented by block <b>708</b>, in some applications a device may randomly select the time period(s). This approach may be suitable, for example, in applications where the duty cycle of the signaling is relatively low. Here, there may be a relatively low probability of pulses for one channel colliding with pulses for another channel. Accordingly, random selection of the time period(s) by each device may prove adequate to prevent or reduce the likelihood of collisions.

As represented by block <b>710</b>, in some applications a device may communicate with another device to select the time period(s). As discussed above, a device may select the time period(s) based on information it obtains from other devices regarding the time period(s) of other channels that are currently active or were previously active in the system. In addition, in some cases two or more devices may negotiate to select the time period(s) in conjunction with an association procedure or some other procedure.

In some aspects, as represented by block <b>711</b>, a delay may be selected based on one or more parameters (e.g., a device-related parameter). These parameters may relate to one or more of the devices that will be communicating via the channel. For example, a delay may be selected based on one or more of an address of a device, a location of a device, a time of day, a device type, or some other suitable parameter. In this way, one or more devices may select a delay that is (or has a high probability of being) unique with respect to delays selected based on other parameters.

In a typical application, one or more of these parameters may be stored in a data memory (e.g., a register) in the device. For example, a data memory <b>522</b> in <figref idrefs="DRAWINGS">FIG. 5</figref> may include device parameters <b>524</b>. Similarly a data memory <b>820</b> in <figref idrefs="DRAWINGS">FIG. 8</figref> may include device parameters <b>822</b>. In practice, a common data memory that stores the device parameters may be used by the transmitter <b>500</b> and the receiver <b>800</b>. That is, the data memories <b>522</b> and <b>820</b> may comprise the same data memory and the parameters <b>524</b> and <b>822</b> may comprise the same parameters.

Referring now to block <b>712</b>, in applications that use an adjustable delay, the device may select a type of adjustable delay and, for the selected type, a particular sequence that will be used to adjust the delay. In some applications, a non-random sequence may be selected. This type of sequence may be used, for example, in applications where orthogonality with other channels may be achieved through the selection of the timing and width of the time periods defined by the sequence.

Typically, however, a pseudorandom sequence will be used to adjust the delay. Such a sequence may be implemented as a time hopping sequence or some other suitable type of sequence. To this end, the transmitter <b>500</b> in the receiver <b>800</b> may incorporate one or more pseudorandom sequence generators. As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, a pseudorandom sequence generator <b>514</b> may be used to generate a pseudorandom sequence for the reference to data delay. The receiver <b>800</b> in <figref idrefs="DRAWINGS">FIG. 8</figref> may include a similar pseudorandom sequence generator <b>812</b>. A pseudorandom sequence generator <b>516</b> in the transmitter <b>500</b> may be used to generate a pseudorandom sequence for the pulse repetition period. The receiver <b>800</b> may include a similar pseudorandom sequence generator <b>814</b>. In some implementations a common generator may be used for one or more of the pseudorandom sequence generators depicted as separate components of the transmitter <b>500</b> and the receiver <b>800</b>.

Once a particular type of delay is selected, the device may then select a particular sequence for that delay type. Again, the device may include one or more components adapted to select a delay sequence. For example, the transmitter <b>500</b> may include a variable delay sequence selector <b>518</b> adapted to select the reference to data delay sequence. The receiver <b>800</b> may include a similar variable delay sequence selector <b>816</b>. In addition, the transmitter <b>500</b> may include a variable delay sequence selector <b>520</b> adapted to select a pulse repetition period sequence. The receiver <b>800</b> may include a similar variable delay sequence selector <b>818</b>. In a similar manner as discussed above, common variable delay sequence selectors may be used by the transmitter <b>500</b> and the receiver <b>800</b>.

The corresponding selection process or processes may be performed in various ways as represented, for example, by blocks <b>714</b>, <b>716</b>, <b>718</b> and <b>720</b>. The operations of the blocks <b>714</b>, <b>716</b> and <b>718</b> may be similar to the operations of blocks <b>706</b>, <b>708</b>, and <b>710</b> discussed above.

In some aspects, as represented by block <b>720</b>, a sequence may be selected based on one or more parameters (e.g., a device-related parameter). As discussed above, such parameters may relate to one or more of the devices that will be communicating via the channel. For example, a pseudorandom sequence may be selected based on one or more of an address of a device, a location of a device, a time of day, a device type, or some other suitable parameter.

Again, one or more of these parameters may be stored in a data memory (e.g., a register) in the device. For example, the data memory <b>522</b> in <figref idrefs="DRAWINGS">FIG. 5</figref> may include device parameters <b>524</b> and the data memory <b>820</b> in <figref idrefs="DRAWINGS">FIG. 8</figref> may include device parameters <b>822</b>. In some aspects, a common data memory that stores the device parameters may be used by the transmitter <b>500</b> and the receiver <b>800</b> as discussed above.

Once the device defines the delay parameters, the device may configure appropriate components to enable transmission and reception of signals in accordance with the selected parameters. For example, in <figref idrefs="DRAWINGS">FIG. 5</figref> delay information <b>526</b> may include delay parameters such as reference to data delay(s) and/or pulse repetition period(s). Similarly, in <figref idrefs="DRAWINGS">FIG. 8</figref> delay information <b>824</b> may include the delay parameters. Again, this type of information may be stored in a common data memory and shared by the transmitter <b>500</b> and the receiver <b>800</b>.

Referring again to <figref idrefs="DRAWINGS">FIG. 6</figref>, as represented by block <b>604</b>, the pulse generator <b>502</b> generates a reference pulse in accordance with the defined a pulse repetition period. In applications that support a programmable or an adjustable pulse repetition period, a pulse repetition controller <b>528</b> may provide a control signal <b>530</b> to the pulse generator <b>502</b> to control the time interval between generated pulses. As discussed above, this time interval may be based on the delay information <b>526</b>.

As represented by block <b>606</b>, the delay circuit <b>504</b> delays the reference signal in accordance with the defined reference to data delay. In applications that support a programmable or an adjustable reference to data delay, a reference to data delay controller <b>532</b> may generate a control signal <b>534</b> to control the delay of the delay circuit <b>504</b>. As discussed above, this delay may be based on the delay information <b>526</b>.

At block <b>608</b> the transmitter <b>500</b> derives a data pulse from the delayed reference pulse. For example, the delayed reference pulse may be modulated by data to be transmitted in accordance with a given modulation scheme. In <figref idrefs="DRAWINGS">FIG. 5</figref> a data stream consisting of data bits to be transmitted <b>536</b> is provided to a spreading code generator <b>538</b>. In the binary phase shift keying example shown in <figref idrefs="DRAWINGS">FIG. 5</figref> the multiplier <b>506</b> multiplies the delayed reference pulse with the output (e.g., +1 or −1) of the spreading code generator <b>538</b> representative of the data to be transmitted. Alternatively, a phase shifter may be used to modulate the delayed pulse with the data to be transmitted (e.g., the output of the spreading code generator <b>538</b>) for phase shift keying employing two or more phases (M-PSK with M=2, 3, 4, etc.). In any event, the adder <b>508</b> may be used to couple the resultant data pulse to an output path to a shaping filter (e.g., a bandpass filter) <b>540</b>.

As represented by block <b>610</b>, a transmitter circuit <b>542</b> may then process the transmitted reference signal (including the reference and data pulses) and provide the resultant signal to an antenna <b>544</b> for transmission over the medium. As represented by block <b>612</b> and as discussed above in conjunction with block <b>604</b>, the pulse generator <b>502</b> will wait to generate another pulse until the end of the defined pulse repetition period.

As represented by block <b>614</b>, in applications that support an adjustable reference to data delay and/or an adjustable pulse repetition period, the corresponding time interval may be adjusted in accordance with a corresponding sequence. Again, such an adjustment may be initiated upon application of the appropriate control signal <b>530</b> and/or <b>534</b>.

Referring now to <figref idrefs="DRAWINGS">FIG. 8</figref>, the receiver <b>800</b> includes a receiver circuit <b>802</b> (e.g., a signal generator), a delay circuit <b>804</b> and a combiner circuit (e.g., a multiplier <b>806</b>) adapted to generate received pulses and process the received pulses to recover transmitted data. Exemplary operations of the receiver <b>800</b> will be described in conjunction with the flowchart of <figref idrefs="DRAWINGS">FIG. 9</figref>. Here, it will be assumed that the receiver has already generated or acquired the channel parameters, for example, as discussed above.

As represented by block <b>902</b>, the receiver circuit <b>802</b> receives signals from the channel at intervals corresponding to the pulse repetition period for that channel. To this end, the receiver circuit <b>802</b> includes circuitry (e.g., an amplifier <b>826</b> and a filter <b>828</b>) adapted to receive signals from an antenna <b>830</b> and process the signals to provide received reference pulses and data pulses corresponding to the signals sent over the channel (block <b>904</b>). The circuitry may thus detect pulses in the received signals to generate the received pulses.

As represented by block <b>906</b>, the delay circuit <b>804</b> delays the reference pulse generated at block <b>904</b> in accordance with the defined reference to data delay. In applications that support a programmable or an adjustable reference to data delay, a reference to data delay controller <b>830</b> may generate a control signal <b>832</b> to control the delay of the delay circuit <b>804</b>. As discussed above, this delay may be based on the delay information <b>824</b>.

As represented by block <b>908</b>, the multiplier <b>806</b> multiplies the delayed reference pulse with the data pulse that corresponds to that reference pulse. Here, the reference pulse effectively provides a matched filter for recovering the data from the data pulse. In some applications multiple pulses may have been transmitted for each pulse (e.g., using a spreading code) to improve the accuracy of the data recovery. In addition, in some applications several reference pulses may be averaged to reduce the effects of noise. In this way, the characteristics of the effective matched filter may be improved.

As represented by block <b>910</b>, an integrator <b>834</b> integrates the multiplied signal to provide a detected data pulse. In some aspects the operation of the integrator <b>834</b> may be based, in part, on the pulse repetition period associated with the channel. For example, a pulse repetition period controller <b>838</b> may generate a control signal <b>840</b> that is used to turn the integrator <b>834</b> on and off at the appropriate times to capture only each data pulse.

In some aspects the detected pulse is fed directly to an analog-to-digital converter (“ADC”) <b>836</b> that converts the signal to digital data. Here, the controller <b>838</b> may generate a control signal <b>842</b> that is used to turn the analog-to-digital converter <b>836</b> on and off at appropriate times to capture a signal output by the integrator <b>834</b> at an appropriate time. By turning off the converter <b>836</b> when it is not needed, the power consumed by the converter <b>836</b> may be reduced.

Various mechanisms may be employed to maintain synchronization between a transmitter and the receiver <b>800</b> to generate the control signals <b>840</b> and <b>842</b> at the appropriate times. For example, the transmitter may occasionally send timing signals to the receiver <b>800</b>. Also, a receiver may employ an appropriate time tracking algorithm to maintain synchronization.

In some aspects a peak detector (not shown) may be employed between the integrator <b>834</b> and the converter <b>836</b>. In this case, the converter <b>836</b> may simply convert the detected peaks (e.g., positive and negative peaks) to provide the received data. Such a configuration may be used, for example, when precise timing information is not used to control the integrator <b>834</b> and/or the converter <b>836</b>. This may be the case when the timing of the peaks is not known or is not known with a high degree of certainty. In such a case, the control signals <b>840</b> and <b>842</b> may be much less precise or, in some cases, may not be employed.

It should be appreciated that the components and operations described above in conjunction with <figref idrefs="DRAWINGS">FIGS. 5-9</figref> may be adapted to generate and receive other types of signals. For example, the circuits may be modified as will be discussed in conjunction with <figref idrefs="DRAWINGS">FIGS. 10-12</figref> to provide an implementation where a common reference pulse is used for multiple channels. In addition, by eliminating the delay circuits and associated operations these components may simply generate and process pulses in accordance with the defined pulse repetition period(s) and the data bits as will be discussed in more detail in conjunction with <figref idrefs="DRAWINGS">FIGS. 13 and 14</figref>. Furthermore, the circuits may be adapted to generate and process transmitted reference signals embodying different modulation schemes as will be discussed in more detail in conjunction with <figref idrefs="DRAWINGS">FIGS. 15 and 16</figref>.

Referring now to <figref idrefs="DRAWINGS">FIGS. 10-12</figref>, in some aspects a common reference pulse may be utilized for multiple channels in the case where a transmitter is simultaneously transmitting data over multiple channels. For example, <figref idrefs="DRAWINGS">FIG. 10</figref> depicts a reference pulse <b>1002</b> followed by a data pulse <b>1004</b> associated with a first channel and by a data pulse <b>1006</b> associated with a second channel. Here, a first reference to data delay time period <b>1008</b> is defined for the first channel while a second reference to data delay time period <b>1010</b> is defined for the second channel. In addition, it should be appreciated that this aspect may be used in conjunction with pulse position modulation and/or an adjustable reference to data delay implemented using an adjustment sequence. Furthermore, this aspect may be used in conjunction with any pulse repetition period technique as taught herein.

<figref idrefs="DRAWINGS">FIG. 11</figref> illustrates an example of an adaptation of <figref idrefs="DRAWINGS">FIG. 5</figref> that may be used to generate pulses such as those shown in <figref idrefs="DRAWINGS">FIG. 10</figref>. <figref idrefs="DRAWINGS">FIG. 12</figref> describes corresponding operations that may be performed to generate these pulses.

As represented by block <b>1202</b> in <figref idrefs="DRAWINGS">FIG. 12</figref>, a pulse generator <b>1102</b> (e.g., pulse generator <b>502</b>) generates a single reference pulse for the first channel and a second channel. As represented by block <b>1204</b>, a delay circuit <b>1104</b> (e.g., delay circuit <b>504</b>) delays the reference pulse in accordance with the reference to data delay time period(s) defined for the first channel. As represented by block <b>1206</b>, a multiplier <b>1206</b> (e.g., multiplier <b>506</b>) and, if applicable, other circuitry (not shown) multiplies the data for the first channel with the delayed reference signal to derive a data pulse for the first channel.

As represented by block <b>1208</b>, a delay circuit <b>1108</b> delays the reference pulse in accordance with the reference to data delay time period(s) defined for the second channel. As represented by block <b>1210</b>, a multiplier <b>1110</b> (and other optional circuitry, not shown) multiplies the data for the second channel with the delayed reference signal to derive a data pulse for the second channel.

As represented by block <b>1212</b>, an adder <b>1112</b> (e.g., similar to adder <b>508</b>) couples the reference pulse and the data pulses to the transmit output stream. The pulses are then conditioned as necessary and provided to an antenna for transmission over a wireless medium as discussed above. Advantageously, through the use of the above technique, the power consumption of the transmitter may be reduced since fewer references pulses are transmitted.

It should be appreciated that modifications may not need to be made to the receiver <b>800</b> of <figref idrefs="DRAWINGS">FIG. 8</figref> to process pulses generated in the manner of <figref idrefs="DRAWINGS">FIG. 10</figref>. For example, a receiver <b>800</b> configured to receive pulses on the first channel will configure the delay circuit <b>804</b> to delay a period of time corresponding to delay <b>1008</b>. The data pulse <b>1006</b> may then be ignored. Conversely, a receiver <b>800</b> configured to receive pulses on the second channel will configure the delay circuit <b>804</b> to delay a period of time corresponding to delay <b>1010</b>. In this case, the data pulse <b>1004</b> may be ignored.

Referring now to <figref idrefs="DRAWINGS">FIGS. 13 and 14</figref>, in some aspects multiple access in an ultra-wide band system may be provided by allocating different pulse repetition periods for different channels. <figref idrefs="DRAWINGS">FIG. 13</figref> illustrates an example where two channels use different pulse repetition periods <b>1302</b> and <b>1304</b>. Specifically, channel <b>1</b> pulses <b>1306</b> and <b>1308</b> are transmitted at times separated by the pulse repetition period <b>1302</b>. In channel <b>2</b>, pulses <b>1310</b> and <b>1312</b> are transmitted at times separated by the pulse repetition period <b>1304</b>.

<figref idrefs="DRAWINGS">FIG. 13</figref> also illustrates that the pulses may not be transmitted reference pulses. That is, other pulse modulation schemes may be used in conjunction with this ultra-wide band multiple access technique.

Referring now to the operations of <figref idrefs="DRAWINGS">FIG. 14</figref>, it will be appreciated that the transmitter <b>500</b> of <figref idrefs="DRAWINGS">FIG. 5</figref> or some other suitable transmitter may be readily adapted to generate signals in accordance with this multiple access technique. As represented by block <b>1402</b> a pulse repetition period is defined for a given channel. As represented by block <b>1404</b> a pulse generator (e.g., pulse generator <b>502</b>) generates pulses that may be modulated, for example, by multiplying a data bit stream with the generated pulses (e.g., in a similar manner as discussed above). As represented by block <b>1406</b> the generated pulses are provided to a transmitter output circuit that processes and transmits the pulses over a wireless medium. As represented by block <b>1408</b> the pulse generator may generate the pulses at intervals defined by the pulse repetition period (e.g., under the control of the controller <b>528</b>). In addition, as represented by block <b>1410</b> the pulse repetition period may be adjusted according to a sequence as discussed herein.

In some aspects a device may be configured to support different modulation schemes. <figref idrefs="DRAWINGS">FIGS. 15 and 16</figref> illustrate two examples of modulation schemes for a transmitted reference signal. It should be appreciated that these examples are provided for illustration purposes and that other modulation schemes or modifications of these schemes (e.g., other n-ary modulation such as M-PSK, M-PPM, etc.) may be employed in accordance with the teachings herein.

<figref idrefs="DRAWINGS">FIG. 15</figref> illustrates an example of a binary phase shift keying modulation scheme. Here, a reference pulse <b>1502</b> is followed by a data pulse <b>1504</b> having an opposite polarity thereby representing a binary zero. Alternatively, a reference pulse <b>1506</b> followed by a data pulse <b>1508</b> having the same polarity represents a binary one. To provide data in this format, the transmitter <b>500</b> of <figref idrefs="DRAWINGS">FIG. 5</figref> may be adapted to, for example, multiply the delayed reference pulse by a −1 or a +1 depending on the value of the data bits <b>536</b>. In other n-ary modulation schemes the delayed reference pulse may be phase shifted in accordance with other phase values.

<figref idrefs="DRAWINGS">FIG. 16</figref> illustrates an example of a binary pulse position modulation scheme. Here, a reference pulse <b>1602</b> followed by a data pulse <b>1604</b> at an interval ΔTR represents a binary one. Alternatively, a reference pulse <b>1606</b> followed by a data pulse <b>1608</b> at an interval ΔTR+ΔPPM represents a binary zero. Thus, the reference to data delay is modulated by the ΔPPM value. In other n-ary modulation schemes the reference pulse may be delayed in accordance with other delay values.

To provide data in the format of <figref idrefs="DRAWINGS">FIG. 16</figref>, the transmitter <b>500</b> may be configured to provide different delays for the reference pulse. For example, the transmitter <b>500</b> may be adapted to adjust the delay of the delay circuit <b>504</b> based on the value of the data bits <b>536</b> (and the n-ary scheme). Here, the reference to data delay controller <b>532</b> or some other suitable component may be adapted to generate an appropriate delay control signal for the delay circuit <b>504</b> in accordance with the data bits <b>536</b>. In this case, the portion of the transmitter <b>500</b> related to the multiplier <b>506</b> may be omitted.

To receive data in the format of <figref idrefs="DRAWINGS">FIG. 16</figref>, the receiver <b>800</b> may be configured to detect a received data pulse at different delays with respect to a received reference pulse. For example, the circuit may include a second delay circuit (e.g., with a delay of ΔTR+ΔPPM) and multiplier pair that is connected in parallel with the delay circuit <b>804</b> (e.g., with a delay of ΔTR) and the multiplier <b>806</b>. Thus, one delay circuit and multiplier pair may be used to recover one pulse value (e.g., “−1”) and another delay circuit and multiplier pair used to recover another pulse value (e.g., “+1”). Additional circuitry may be used for other n-ary schemes.

The examples of <figref idrefs="DRAWINGS">FIGS. 15 and 16</figref> illustrate that a system may provide reference and data pulses separated in time by one or more delay periods. For example, the reference and data pulses may be separated in time by at least one first delay period (e.g., separated by a first fixed period, or separated by ΔTR1 or ΔTR1+ΔPPM) for a first channel. In addition, the system may provide reference and data pulses separated in time by at least one second delay period (e.g., separated by a second fixed period or separated by ΔTR2, or ΔTR2+ΔPPM) for a second channel. Moreover, the delay period(s) associated with the first channel are different than the delay period(s) associated with the second channel.

It should be appreciated that the teachings herein may be applicable to a wide variety of applications other than those specifically mentioned herein. For example, the teachings herein may be applicable to systems utilizing different bandwidths, signal types (e.g., shapes), modulation schemes or signal periodicities. Also, the delay circuit may take various forms including, without limitation, a delay line, one or more delay elements, a transmission line, or any other suitable mechanism that imparts a given delay on a signal. The delay circuit may be fixed or adjustable. In the former case the delay circuit may be fixed to provide a given delay value that is different than the delay value assigned for other delay circuits in a device.

The teachings herein also may be incorporated into a variety of devices. For example, one or more aspects taught herein may be incorporated into a phone (e.g., a cellular phone), a personal data assistant (“PDA”), an entertainment device (e.g., a music or video device), a headset, a microphone, a biometric sensor (e.g., a heart rate monitor, a pedometer, an EKG device, etc.), a user I/O device (e.g., a watch, a remote control, etc.) or any other suitable communication device. Moreover, these devices may have different power and data requirements. Advantageously, the teachings herein may be adapted for use in low power applications (e.g., through the use of a pulse-based signaling scheme) and may support a variety of data rates including relatively high data rates (e.g., through the use of high-bandwidth pulses).

The components described herein may be implemented in a variety of ways. For example, referring to <figref idrefs="DRAWINGS">FIG. 17</figref>, an apparatus <b>1700</b> includes components <b>1702</b>, <b>1704</b>, <b>1706</b>, <b>1708</b>, <b>1710</b>, <b>1712</b>, <b>1714</b>, <b>1716</b>, <b>1718</b>, and <b>1720</b> that may correspond to components <b>502</b>, <b>504</b>, <b>506</b> and <b>508</b>, <b>510</b> and <b>518</b>, <b>512</b> and <b>520</b>, <b>514</b>, <b>528</b>, <b>532</b>, <b>532</b>, and <b>540</b> and <b>542</b>, respectively, of transmitter <b>500</b> in <figref idrefs="DRAWINGS">FIG. 5</figref>. In <figref idrefs="DRAWINGS">FIG. 18</figref>, an apparatus <b>1800</b> includes components <b>1802</b>, <b>1804</b>, <b>1806</b>, and <b>1808</b> that may correspond to components <b>802</b>, <b>804</b>, <b>806</b>, and <b>808</b> and <b>816</b>, respectively, in <figref idrefs="DRAWINGS">FIG. 8</figref>. An apparatus <b>1900</b> in <figref idrefs="DRAWINGS">FIG. 19</figref> includes components <b>1902</b>, <b>1904</b>, <b>1906</b>, <b>1908</b>, <b>1910</b>, <b>1912</b>, and <b>1914</b> that may correspond to components <b>502</b>, <b>512</b> and <b>520</b>, <b>516</b>, <b>520</b>, <b>528</b>, <b>528</b>, and <b>528</b>, respectively, in <figref idrefs="DRAWINGS">FIG. 5</figref>. <figref idrefs="DRAWINGS">FIGS. 17-19</figref> illustrate that in some aspects these components may be implemented via appropriate processor components. These processor components may in some aspects be implemented, at least in part, using structure as taught herein. In some aspects the components represented by dashed boxes are optional.

In addition, the components and functions represented by <figref idrefs="DRAWINGS">FIGS. 17-19</figref>, as well as other components and functions described herein, may be implemented using any suitable means. Such means also may be implemented, at least in part, using corresponding structure as taught herein. For example, in some aspects means for providing or generating pulses may comprise a pulse generator, means for delaying may comprise a delay circuit, means for deriving or modulating may comprise a modulator, means for selecting or defining may comprise a selector, means for generating may comprise a generator, means for adjusting may comprise an adjuster, means for communicating may comprise a communication circuit, means for transmitting may comprise a transmitter, means for generating received pulses may comprise a receiver circuit, means for combining may comprise a combiner, and means for controlling a comprise a controller. One or more of such means also may be implemented in accordance with one or more of the processor components of <figref idrefs="DRAWINGS">FIGS. 17-19</figref>.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, various forms of program or design code incorporating instructions (which may be referred to herein, for convenience, as “software” or a “software module”), or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The steps of a method or algorithm described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (e.g., including executable instructions and related data) and other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. An exemplary storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a “processor”) such the processor can read information (e.g., code) from and write information to the storage medium. An exemplary storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in user equipment. In the alternative, the processor and the storage medium may reside as discrete components in user equipment.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.