Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate

CROSS REFERENCE TO RELATED APPLICATIONS

0001This application is a divisional of application Ser. No. 11/502,598, filed Aug. 11, 2006 now U.S. Pat. No. 7,619,250, which is a divisional of application Ser. No. 10/377,875, filed Mar. 4, 2003, now U.S. Pat. No. 7,119,365, which claims priority to Japanese Application Nos. 2002-86999, filed Mar. 26, 2002, 2002-243927, filed Aug. 23, 2002 and 2002-280036, filed Sep. 25, 2002, the entire contents of each of which are hereby incorporated by reference.

FIELD OF THE INVENTION

0002The present invention relates to a semiconductor device and to a manufacturing method thereof, and particularly relates to a semiconductor device having an integrated circuit constituted of plural MOSs and to a manufacturing method thereof.

0003Further, the present invention relates to an SOI substrate constituted by (a) bonding a single crystal silicon thin film in which hydrogen ions have been implanted to a substrate and (b) dividing the single crystal silicon thin film at a hydrogen ion implantation portion, and the present invention further relates to a semiconductor device using the SOI substrate, and to a manufacturing method of the SOI substrate.

0004In addition, the present invention relates to a semiconductor device, used in an active matrix driving liquid crystal display device and the like, that improves circuit performance of a device in which peripheral driving circuits, a control circuit, and the like are integrated.

BACKGROUND OF THE INVENTION

0005Conventionally, so-called active matrix driving has been employed, and the active matrix driving is such that: thin film transistors (hereinbelow referred to as TFT) such as a-Si (amorphous Si) and p-Si (polycrystalline Si) are formed on a glass substrate, so as to drive a liquid crystal display panel, an organic EL panel, and the like. Further, by using the p-Si whose mobility is so high as to operate at a high speed, peripheral drivers have been integrated. Alternately, study has been performed with respect to forming of a device which utilizes higher-performance Si so as to integrate a system constituted of an image processor, a timing controller, and the like, that are required to have higher performance.

0006This is because the polycrystalline Si brings about the following problems: because of (a) a localized state in the band gap that is caused by incomplete crystallization, (b) deficiency in the vicinity of a crystal grain boundary, drop in the mobility that is caused by the presence of the localized state in the band gap, and (d) increase in an S coefficient (sub-threshold coefficient), performance of the transistor is too insufficient to form a high-performance device of Si.

0007Then, in order to form a higher-performance device of Si, not only laser crystallization, but also the following techniques have been proposed: a technique for improving crystallization, for example, further advanced techniques such as SLS (Sequential Lateral Solidification) and the like (for example, a specification of U.S. Pat. No. 6,300,175 (Publication date: Oct. 9, 2001), CLC (CW Laser Lateral Crystallization)(for example, A. Hara et al., “Ultra-high Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, 2001 International Workshop on Active Matrix Liquid Crystal Displays—TFT Technologies and Related Materials—(AM-LCD2001), Digest of Technical Papers, p. 227-230, Jul. 11-13, 2001, Japan Society of Applied Physics). These techniques are to deposit an a-Si film on a glass substrate so as to control the crystallization in a preferable manner, or so as to realize single crystallization.

0008However, in these techniques using laser, a merely Si film is heated to a high temperature so as to perform crystal growth while keeping a temperature of an insulating substrate whose heat resistance is low like glass etc. Thus, generally, a tensile stress of approximately 10⁹Pa is exerted on the Si film, so that there occur such problems: cracks appear in the film, reproducibility in the TFT property is deteriorated, non-uniformity is large, and the like.

0009While, there is a technique in which the single crystal Si is bonded to the insulating substrate so as to make the film thinner (for example, Japanese Laid-Open Patent Application No. 211128/1993 (Tokukaihei 5-211128)(Publication date: Aug. 20, 1993). With this technique, it is possible to form an oxide film on the single crystal Si substrate, and to form the single crystal Si thin film thereon. However, when the single crystal Si thin film is to be bonded to an insulating substrate other than the Si substrate, for example, a glass substrate or a quartz substrate, there occurs such problem that Si is stripped because of a thermal-expansion-coefficient difference between Si and the insulating substrate such as the quartz substrate.

0010In order to prevent the foregoing damage brought about in the thermal-bond-strength-improving process due to the thermal-expansion-coefficient difference between Si and the quartz substrate, there is proposed a method of changing composition of crystallized glass (for example, Japanese Laid-Open Patent Application No. 163363/1999 (Tokukaihei 11-63363) (Publication date: Jun. 18, 1999).

0011Further, as described above, conventionally, there have been brought about dramatic improvements in (a) an integrated circuit element technique such that: the single crystal silicon substrate is processed and hundreds of millions of transistors are formed on the substrate, and (b) a thin film transistor (TFT) liquid crystal display technique such that: after a polycrystal semiconductor thin film such as a silicon film is formed on an amorphous material such as a glass substrate, they are processed into a transistor, so as to make picture elements and drivers of a liquid crystal display, as well as popularization of computers and personal information terminals using liquid crystal displays.

0012In these techniques, the integrated circuit element is made by processing a commercial single crystal silicon wafer whose thickness is scant 1 mm and diameter ranges from 150 mm to 300 mm, and forming a large number of transistors on the processed single crystal silicon wafer. Further, in the TFT liquid crystal display, an amorphous silicon film on an amorphous nonalkali glass is fused/polycrystallized by heat of laser etc., and the amorphous silicon film is processed, so as to form a MOS type transistor which functions as a switching element.

0013In fields of the liquid crystal display and the organic EL display using the TFT, a TFT of an amorphous silicon film or a polysilicon film is formed on a transparent glass substrate, so as to form a device of silicon for driving the picture element, that is, for performing so-called active matrix driving. Further, in order to integrate the peripheral drivers, the timing controller, and the like as a system in terms of the active matrix driving, forming of a higher-performance device of silicon has been studied. This is because the polycrystalline Silicon film brings about the following problem: because of (a) a localized state in the band gap that is caused by incomplete crystal, (b) drop in the mobility, or (c) increase in a sub-threshold coefficient (S coefficient) that are brought about by the presence of the localized state in the band gap in the vicinity of a crystal grain boundary, performance of the transistor is too insufficient to form a high-performance device of silicon.

0014Then, attention is paid to an SOI technique. The SOI is the abbreviation of Silicon on Insulator, and is a technique for forming a single crystal semiconductor thin film on an insulating substrate (this technique is seldom used to form a polycrystalline Silicon film). The technique has been actively studied since around 1981. Further, the SOI substrate used in the field of the integrated circuit is to dramatically improve performance of the semiconductor element by using preferable transistors. Thus, as long as the substrate functions as an insulating film, it does not matter whether the substrate is transparent or not, or it does not matter whether the substrate is crystalline or amorphous. In this field, when the transistor is formed by using the SOI substrate, elements are completely separated, so that there is little restriction in operating, thereby obtaining preferable property as a transistor.

0015Now, as a representative of the SOI substrate, a SIMOX (Separation by Implantation of Oxygen) substrate is on sale. In the SOI substrate, oxygen is implanted into a silicon wafer, and the thus formed silicon oxide layer separates a single crystal silicon thin film from a bulk of the substrate. Thus, oxygen which is an element much heavier than hydrogen is implanted to a predetermined depth so that the implantation is performed at high energy and at high dose. Thus, crystals are severely damaged, so that there occur the following problems: it is impossible to obtain sufficient property of the single crystal, or it is impossible to obtain complete insulating property because of deviation from stoichiometry of a silicon dioxide film portion.

0016Then, Tokukaihei 5-211128 discloses a technique such that: the single crystal silicon is bonded to the substrate, and this is made to be a thin film. This prior art is called “smart cut process”, and is such that: hydrogen ions are implanted into a single crystal silicon substrate in accordance with an ion implantation process, and the resultant is bonded to an enforcing member, and minute bubbles are brought about in a hydrogen ion implanted layer by a heating process, and the single crystal silicon substrate is divided at the hydrogen ion implanted layer, so as to form the single crystal silicon thin film, so that the SOI structure is realized. As a result, it is possible to manufacture a single crystal silicon transistor whose element property is high. From this view point, the technique is superior.

0017However, as to this prior art, Tokukaihei 5-211128 discloses merely that: the oxide film is formed on the single crystal silicon substrate, and the single crystal silicon thin film is formed thereon. The suitability for other substrates such as the glass substrate for display is not taken into consideration. Then, Tokukaihei 11-163363 mentions examples in which other substrates are compared in terms of the bonding suitability. In the prior art, it is recited that: crystallized glass is used to prevent the damages of the substrate in the heating process for improving the bond strength with respect to the substrate, and composition thereof is changed so as to correspond to the silicon piece in terms of the thermal expansion rate.

0018However, the crystallized glass typically contains alkali atoms, and has property contrary to a transistor whose property is stabilized. Further, in the foregoing techniques, the single crystal Si substrate is shaped in a wafer of 6, 8, and 12 inches in diameter, so that the insulating substrate which is to be bonded is limited to a substrate of 6, 8, and 12 inches. Thus, it is impossible to manufacture large size liquid crystal display panel and organic EL panel. In a case of a small size panel, the manufacturing cost becomes high, and it is difficult to use the technique in practice.

0019Moreover, in a case of using a quartz substrate, when the single crystal Si substrate is bonded to the insulating substrate, the bond strength drops because of the thermal expansion rate difference. Further, in a case where a stress is exerted on a bonded interface, the TFT property is deteriorated because of differences and non-uniformity in the stress exerted on the interface.

0020Further, in the prior art, it is considered that: when the single crystal silicon substrate is bonded, it is impossible to obtain the sufficient bond strength unless exposed in a high temperature. Thus, a temperature for performing the heating process is 800° C. to 1200° C. It is considered that a high-heat-resistant crystallized glass whose strain point is not less than 750° C. is suitable, so that there occurs the following problem: the technique cannot be applied to a high-strain-point nonalkali glass, typically used in a liquid crystal panel of the active matrix driving, whose strain point is not more than 700° C.

SUMMARY OF THE INVENTION

0021An object of the present invention is to provide (a) a semiconductor device, having no non-uniformity or differences in a bond strength of the single crystal Si thin film or a stress exerted on a bonded interface, which is constituted of a large size and inexpensive substrate in which a single crystal Si thin film is provided and its property is stabilized, and (b) a manufacturing method of such a semiconductor device.

0022Another object of the present invention is to provide a semiconductor device constituted of a large size and inexpensive substrate in which a single crystal Si thin film is provided and its property is stabilized.

0023Still another object of the present invention is to provide (a) an SOI substrate which can be manufactured without using a crystallized glass whose composition has been adjusted or a high heat resistant glass at low cost, (b) a display device using such SOI substrate, and (c) a manufacturing method of such SOI substrate.

0024In order to achieve the foregoing objects, the semiconductor device of the present invention includes a polycrystalline Si thin film and a single crystal Si thin film are respectively provided on different areas of an insulating substrate.

0025With the foregoing configuration, the polycrystalline Si thin film and the single crystal Si thin film are respectively provided on different areas of the insulating substrate such as a large size glass substrate. The single crystal Si solves the following problems: (a) a localized state in the band gap that is caused by incomplete crystallization, (b) deficiency in the vicinity of a crystal grain boundary, (c) drop in mobility that is caused by the presence of the localized state in the band gap, and (d) increase in an S coefficient (sub-threshold coefficient) etc., peculiar to the polycrystalline Si, all of which make it difficult to form a high performance device. Thus, it is possible to make an arrangement such that: a device of higher performance, such as a timing controller, is formed in an area where the single crystal Si thin film is formed, and other devices are formed in an area where the polycrystalline Si thin film is formed.

0026That is, even when a size of the single crystal Si thin film is limited, the size may be sufficient as long as it is possible to form a high speed logic, a timing generator, a high speed DAC (with current buffer), and the like, that are required to realize a high speed, low power consumption, and little non-uniformity, that are enabled by the single crystal Si. Thus, it is possible to integrate a high performance and well-functioning circuit system, which can be realized only by the single crystal Si, on a substrate, so that it is possible to manufacture a semiconductor device used in a display device such as a liquid crystal panel or an organic EL panel in which a high performance system is integrated at much lower cost compared with a case where all devices are constituted of the single crystal Si.

0027Further, a substrate shape of the single crystal Si is limited to wafer sizes of an LSI manufacturing equipment, such as 6, 8, and 12 inches in diameter, but the polycrystalline Si thin film is formed on the substrate, so that it is possible to manufacture a large size liquid crystal panel or an organic EL panel for example.

0028Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film and an amorphous Si film sequentially on a surface of the insulating substrate; growing a polycrystalline Si layer, by thermally crystallizing the amorphous Si film, so as to form the polycrystalline Si thin film; removing a predetermined area of the polycrystalline Si layer by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; bonding a hydrogen ion implanted surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in an exfoliating manner by performing a heating process, so as to form the single crystal Si thin film.

0029With the foregoing configuration, it is possible to enforce the bond strength by heating the single crystal Si substrate in which the hydrogen ions of the predetermined dose are implanted to the predetermined depth, that is, by heating the single crystal Si substrate having the hydrogen ion implantation portion in which the hydrogen ions have been implanted in advance, and it is possible to obtain the single crystal Si thin film by dividing the single crystal Si substrate at the hydrogen ion implantation portion in an exfoliating manner. Thus, the single crystal Si solves the following problems: (a) a localized state in the band gap caused by incomplete crystallization, (b) deficiency in the vicinity of a crystal grain boundary, (c) drop in mobility that is caused by the presence of the localized state in the band gap, and (d) increase in an S coefficient etc., peculiar to the polycrystalline Si, all of which make it difficult to manufacture a high performance device. Therefore, it is possible to form the single crystal Si thin film and the polycrystalline Si thin film on the insulating substrate, so that devices required to have higher performance can be constituted of the single crystal Si and other devices can be constituted of the polycrystalline Si in accordance with a common manufacturing process after forming the single crystal Si thin film and the polycrystalline Si thin film. Thus, it is possible to manufacture the semiconductor device for a display device etc. such as a liquid crystal panel or an organic EL panel, in which a high performance system is integrated, at low cost.

0030Further, the oxide layer or the SiO₂film is formed in advance, and the single crystal Si substrate is bonded to the insulating substrate such as a glass substrate via the formed oxide layer or SiO₂film, so that it is possible to prevent the following problems: (a) drop in the mobility that is brought about by distortion of the Si crystal caused by a stress exerted on a bonded Si interface, or (b) deficiency in the interface, and an interface fixed charge that is brought about with the deficiency, and (c) a threshold shift that is brought about by a localized state in the interface, and (d) drop in the characteristics stability. Thus, it is not necessary to use a crystallized glass whose composition has been adjusted so as to prevent damages caused by thermal expansion rate difference with respect to a glass substrate when the bond strength is improved and the exfoliation is performed by heat treatment, so that a high-strain-point glass can be used. Thus, there is not such a problem that the crystallized glass is contaminated with the alkali metal, so that it is possible to prevent the damages caused by thermal expansion rate difference with respect to a glass substrate when the bond strength is improved and the exfoliation is performed by heat treatment.

0031Further, for example, the polycrystalline Si film is formed on a large-area high-strain-point glass substrate, and etching removal is performed with respect to the polycrystalline Si thin film so as to cover an area that is to be bonded to the single crystal Si substrate processed into an appropriate size.

0032Further, the single crystal Si substrate is bonded to the area, and the single crystal Si thin film and the SiO₂film are left by exfoliation. Other single crystal Si is removed by exfoliation, so that it is possible to prevent the bias of the stress entirely exerted on the glass substrate by performing exfoliation removal with respect to other single crystal Si.

0033That is, a surface of the area is oxidized or an SiO₂film is deposited on the surface, and the single crystal Si substrate, having the hydrogen ion implantation portion, that has been cut into a predetermined shape so as to partially or substantially entirely cover the area having been subjected to the etching removal, is bonded to the area having been subjected to the etching removal so that a surface close to the hydrogen ion implantation portion is in contact with the area, and the single crystal Si substrate is subjected to a heating process, and the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so that the single crystal Si thin film and the SiO₂film are left, and other single crystal Si is removed by exfoliation, so that it is possible to prevent the bias of the stress entirely exerted on the glass substrate.

0034Thus, it is possible to obtain the substrate, in which an area is constituted of the single crystal Si thin film and other area is constituted of the polycrystalline Si thin film, without bringing about stripping, cracking, and damages of the Si.

0035Further, a shape of the single crystal Si substrate is limited to wafer sizes of an LSI manufacturing equipment, such as 6, 8, and 12 inch disks, but also the polycrystalline Si thin film is formed on the insulating substrate, so that it is possible to manufacture the semiconductor device such as a large size liquid crystal display panel and an organic EL panel.

0036Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film and an amorphous Si film sequentially on a surface of the insulating substrate; growing a polycrystalline Si layer, by thermally crystallizing the amorphous Si film, so as to form the polycrystalline Si thin film; removing a predetermined area of the polycrystalline Si layer by etching, and removing a part of the SiO₂film, that corresponds to the predetermined area, in a direction of thickness of the SiO₂film by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; bonding a hydrogen ion implantation surface (surface of ion implanted side) of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film.

0037With the foregoing configuration, in addition to advantages of the foregoing manufacturing method, the predetermined area of the polycrystalline Si layer is removed by etching, and a part of the SiO₂film of the same area is removed in a direction of thickness of the SiO₂film by etching, so that it is possible to obtain a substrate such that: a bonded surface of the single crystal Si substrate is free from the influence exerted by a thickness of the SiO₂film, and the single crystal Si thin film and the polycrystalline Si thin film formed on the insulating substrate are substantially equal to each other in terms of a height. As a result, it is possible to perform almost all the following processes including the step of etching performed to form the island shape. Further, the foregoing method enables forming of a transistor or a circuit in which a large step is not brought about. Thus, in case of a liquid crystal panel for example, it is possible to obtain an advantage in controlling a cell thickness.

0038Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film on a surface of the insulating substrate; removing a part of the SiO₂film, that corresponds to the predetermined area, in a direction of thickness of the SiO₂film by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; bonding a surface of hydrogen ion implanted side of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in an exfoliating manner by performing a heating process, so as to form the single crystal Si thin film on the insulating substrate; depositing a second SiO₂film and an amorphous Si film sequentially on a surface of the insulating substrate; and growing a polycrystalline Si layer, by thermally crystallizing the amorphous Si film, so as to form the polycrystalline Si thin film.

0039With the foregoing configuration, it is possible to obtain the same advantage as in the foregoing manufacturing methods.

0040Further, in order to achieve the foregoing object, an SOI substrate of the present invention includes: an amorphous nonalkali glass substrate; and a single crystal silicon piece in which hydrogen ions have been implanted, and the single crystal silicon piece is bonded to the amorphous nonalkali glass substrate, wherein the single crystal silicon piece is divided at a hydrogen ion implantation portion in which the hydrogen ions have been implanted, so as to form a single crystal silicon thin film.

0041With the foregoing configuration, hydrogen ions are implanted to the single crystal silicon piece in accordance with an ion implantation process, and hydrogen embrittlement is brought about by the heating process in the layer in which the hydrogen ions have been implanted, and the single crystal silicon thin film is formed by dividing the single crystal silicon piece at the layer (in accordance with a so-called smart cut process), and the single crystal silicon thin film is bonded to the substrate, so as to form the SOI substrate. As to the SOI substrate, the present inventors paid attention to the following fact: the SOI substrate is such that it is possible to obtain the sufficient bond strength even at 300° C. upon bonding the single crystal silicon piece to the substrate. Thus, it is possible to set a heating temperature for improving the bond strength to be lower compared with a conventional method, so that it is possible to use an amorphous nonalkali glass substrate whose strain point is not more than 700° C.

0042The present inventors studied the foregoing point repeatedly, and found that: in a case where hydrogen ions much lighter than oxygen ions in terms of a mass are implanted so as to divide the single crystal silicon piece into the single crystal silicon thin film, approximately 600° C. is sufficient as the heating temperature upon manufacturing the element. By heat treatment at a temperature or temperatures above the hydrogen dissociation temperature from Si, single crystal silicon is separated to form single crystal silicon film, and it is possible to restore a crystalline material of the single crystal silicon thin film to a level, at which the hydrogen ions have not been implanted, so as to perform a process for suppressing the deterioration of the crystalline material at the same time. Thus, by performing the heating process at approximately 600° C., it is possible to improve the bond strength between the single crystal silicon piece and the substrate as well as the separation and the improvement of the crystalline material.

0043That is, as to the SOI substrate manufactured by bonding the single crystal silicon thin film obtained by the so-called smart cut process with the substrate, when the single crystal silicon piece is bonded to the substrate, it is possible to obtain the sufficient bond strength even at approximately above 300° C. From this view point, the single crystal silicon piece is bonded to the substrate and the thin film is separated at approximately 600° C. by using the amorphous nonalkali glass substrate.

0044Thus, it is not necessary to use a crystallized glass or a high heat resistance glass whose composition has been adjusted, so that it is possible to manufacture the SOI substrate at low cost using a high-strain-point nonalkali glass generally used in a liquid crystal display panel etc. based on active matrix driving. Further, since the heating temperature is low, it is possible to prevent the alkaline metal from dispersing into the semiconductor layer. Thus, since the alkaline metal is prevented from dispersing, it is possible to make a thickness of an oxide film formed on the side of the single crystal silicon piece or a silicon dioxide film formed on the side of the substrate thinner, so that it is possible to improve the throughput.

0045Note that, in the present invention, a substrate, containing SOI, in which the single crystal silicon piece is bonded to a part of a large area glass substrate, may be used as the SOI substrate.

0046Further, in order to achieve the foregoing object, the display device of the present invention is arranged so that the amorphous nonalkali glass substrate uses any one of the foregoing SOI substrates made of an amorphous glass which allows transmittance of visible light.

0047With the foregoing configuration, the SOI substrate is made of the amorphous glass which allows the transmittance of the visible light, and a transistor and a separately formed polycrystalline Silicon film are provided on the single crystal silicon thin film, so that it is possible to arrange a liquid crystal display device or an organic EL display device.

0048Thus, it is possible to form a high performance transistor on a specific portion of a large area substrate of the display device.

0049Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the SOI substrate includes the steps of: bonding a single crystal silicon piece, in which hydrogen ions have been implanted, to an amorphous nonalkali glass substrate; and dividing said single crystal silicon piece at a hydrogen ion implantation portion by performing a heating process at a maximum of 600° C., so as to form a single crystal silicon thin film.

0050With the foregoing configuration, as to the manufacturing method of the SOI substrate manufactured by bonding the single crystal silicon thin film that has been obtained by the smart cut process etc. to the substrate, the present inventors paid attention to a fact that it is possible to obtain the sufficient bond strength even at 300° C. upon bonding the single crystal silicon piece to the substrate, so that they think it preferable to set the maximum temperature for the heating process to approximately 600° C. at which the single crystal silicon piece is divided, for example, the heating process is performed at 600° C. for 30 to 60 minutes.

0051Thus, it is not necessary to use a crystallized glass whose composition has been adjusted or a high heat resistance glass, so that it is possible to manufacture the SOI substrate at low cost by using a high-strain-point nonalkali glass generally used in a liquid crystal display panel etc. based on active matrix driving. Further, the heating process temperature is low, so that it is possible to prevent the alkali metal from dispersing into the semiconductor layer. Thus, the alkaline metal is prevented from dispersing, so that the oxide film formed on the side of the single crystal silicon piece and the silicon dioxide film formed on the side of the substrate can be made thinner. As a result, it is possible to improve the throughput.

0052Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the SOI substrate includes the steps of: bonding a single crystal silicon piece, in which hydrogen ions have been implanted, to an amorphous nonalkali glass substrate; and dividing said single crystal silicon piece at a hydrogen ion implantation portion by performing a heating process in accordance with lamp anneal including a peak temperature of not less than 850° C., so as to form a single crystal silicon thin film.

0053With the foregoing configuration, as to the manufacturing method of the SOI substrate manufactured by bonding the single crystal silicon thin film that has been obtained by the smart cut process etc. to the substrate, the present inventors paid attention to a fact that it is possible to obtain the sufficient bond strength even at a maximum of 600° C. upon bonding the single crystal silicon piece to the substrate, so that they think it preferable that the heating process is performed in accordance with the lamp anneal including a peak temperature of approximately 700° C.

0054Thus, it is not necessary to use a crystallized glass whose composition has been adjusted or a high heat resistance glass, so that it is possible to manufacture the SOI substrate at low cost by using a high-strain-point nonalkali glass generally used in a liquid crystal display panel etc. based on active matrix driving. Further, the heating process temperature is low, so that it is possible to prevent the alkaline metal from dispersing into the semiconductor layer. Thus, the alkaline metal is prevented from dispersing, so that the oxide film formed on the side of the single crystal silicon piece and the silicon dioxide film formed on the side of the substrate can be made thinner. As a result, it is possible to improve the throughput.

0055Further, the shrinkage of the glass substrate occurs upon heating in an electric furnace when the glass substrate is heated above the strain point. On the other hand, rapid thermal anneal (hereinbelow referred to as RTA) using lamp etc. or heating anneal using laser (laser anneal) prevents the shrinkage of the entire substrate, and causes an annealed portion to be heated, thereby improving the crystallization or the separating efficiency. Furthermore, it is possible to improve the throughput upon manufacturing the SOT substrate.

0056Note that, as the peak temperature of the lamp anneal is higher, the characteristics of the transistor are further improved, but the substrate largely bends, and largely expands and contracts, so that it is preferable to set an appropriate temperature and an appropriate holding time according to the substrate size and a type of a formed device. For example, as to a substrate of 300 to 400 mm, the heating process is performed at 700° C. for about 5 minutes.

0057Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the SOI substrate includes the steps of: depositing a silicon dioxide film and an amorphous silicon film sequentially on a surface of the amorphous nonalkali glass substrate; growing a polycrystalline Silicon layer, by thermally crystallizing the amorphous silicon film, so as to form the polycrystalline Silicon thin film; removing a predetermined area of the polycrystalline Silicon layer by etching, and removing a part of the silicon dioxide film, that corresponds to the predetermined area, in a direction of thickness of the silicon dioxide film by etching; oxidizing a surface of the single crystal silicon piece or depositing a silicon dioxide film on the surface of the single crystal silicon piece, and implanting the hydrogen ions in the single crystal silicon piece; cutting the single crystal silicon piece, in which the hydrogen ions have been implanted, into a shape so as to cover the predetermined area that has been subjected to the etching; bonding a hydrogen ion implantation surface of the single crystal silicon piece that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching; and dividing the single crystal silicon piece in accordance with hydrogen embrittlement caused by the heating process, so as to form the single crystal silicon thin film on the insulating substrate.

0058With the foregoing configuration, when manufacturing the SOI substrate in which the transistor is formed not only on the single crystal silicon thin film bonded in the foregoing manner but also on the polycrystalline Silicon thin film deposited by CVD etc., the etching removal is performed with respect to the polycrystalline Silicon layer in the predetermined area of the bonded area, and a part of the silicon dioxide film in the same area is subjected to the etching removal in a direction of thickness of the silicon dioxide, before bonding the single crystal silicon piece.

0059Thus, it is possible to obtain the SOI substrate in which a height of the bonded single crystal silicon thin film area and a height of the polycrystalline Silicon thin film area are substantially equal to each other. As a result, it is possible to perform substantially all the steps thereafter, including the etching for forming the island shape, with respect to both the single crystal silicon thin film area and the polycrystal thin film area at the same time. Further, the transistor or the circuit having small step is formed, so that this is advantageous in controlling the cell thickness in a case of a liquid crystal panel for example.

0060Further, in order to achieve the foregoing object, the semiconductor device of the present invention includes a polycrystalline Si thin film and a single crystal Si thin film, that are respectively provided on different areas of an insulating substrate, wherein a difference between the insulating substrate and the single crystal Si thin film in terms of a difference of total linear expansion (normalized) is approximately not more than 250 ppm for temperature range from room temperature to 600° C.

0061Generally, the single crystal Si constitutes the semiconductor thin film used as an activating layer, so that it is possible to solve the following problems: (a) a localized state in the band gap that is caused by incomplete crystallization, (b) deficiency in the vicinity of a crystal grain boundary, (c) drop in mobility that is caused by the presence of the localized state in the band gap, and (d) increase in an S coefficient (sub-threshold coefficient) etc., all of which make it difficult to manufacture a high performance equipment.

0062Then, with the foregoing configuration, the polycrystalline Si thin film and the single crystal Si thin film are formed on the different areas of a large size glass substrate etc. Thus, devices required to have higher performance, for example, a timing controller, a microprocessor, and the like, can be formed on an area where the single crystal Si thin film has been formed, and other devices can be formed on an area where the polycrystalline Si thin film has been formed.

0063That is, even when a size of the single crystal Si thin film is limited, the size may be sufficient as long as it is possible to form a high speed logic, a timing generator, a high speed DAC (with current buffer), and the like, that are required to realize a high speed, low power consumption, and little non-uniformity, that are enabled by the single crystal Si. Thus, it is possible to integrate a high performance and well-functioning circuit system, which can be realized only by the single crystal Si, on a substrate, so that it is possible to manufacture a semiconductor device used in a display device such as a liquid crystal panel or an organic EL panel in which a high performance system is integrated at much lower cost compared with a case where all devices are constituted of the single crystal Si.

0064Further, a substrate shape of the single crystal Si is limited to wafer sizes of an LSI manufacturing equipment, such as 6, 8, and 12 inches in diameter, but the polycrystalline Si thin film is formed on the substrate, so that it is possible to manufacture a large size liquid crystal panel or an organic EL panel for example.

0065Further, it is not necessary to use a crystallized glass whose composition has been adjusted so as to prevent damages caused by thermal expansion rate difference with respect to a substrate when the bond strength is improved by heat treatment. Thus, there is not such a problem that the crystallized glass is contaminated with the alkaline metal, so that it is possible to prevent the damages caused by thermal expansion rate difference with respect to a substrate when the bond strength is improved by heat treatment.

0066Further, a difference between the insulating substrate and the single crystal Si thin film in terms of a difference of total linear expansion is not more than approximately 250 ppm for temperature range from room temperature to 600° C., so that the stress exerted on the insulating substrate and the single crystal Si thin film becomes small. Thus, in the step of forming the single crystal Si thin film on the insulating substrate, it is possible to prevent (a) damages and exfoliation of the bonded surface that are brought about by the difference in terms of the thermal expansion coefficient when the single crystal Si thin film is divided at a hydrogen ion implantation portion in a cleaving manner, or (b) deficiency in the crystal. Further, it is possible to improve the thermal bond strength. Note that, the thermal expansion is variation in the length thereof caused by the temperature variation.

0067Further, in order to achieve the foregoing object, the semiconductor device of the present invention includes a polycrystalline Si thin film and a single crystal Si thin film that are respectively provided on different areas of an insulating substrate, wherein a position of Raman shift peak is within 520.5±1.0 cm⁻¹.

0068With the foregoing configuration, the polycrystalline Si thin film and the single crystal Si thin film are respectively provided on the different areas. Thus, devices required to have higher performance, for example, a timing controller, a microprocessor, and the like, can be formed on an area where the single crystal Si thin film has been formed, and other devices can be formed on an area where the polycrystalline Si thin film has been formed.

0069It is general that large stress remains in the Si thin film in a case where crystallization or crystal growth is performed by using laser.

0070With the foregoing configuration, it is possible to substantially vanish the stress exerted on the Si interface of the single crystal Si thin film, so that the position of Raman shift peak is within 520.5±1.0 cm⁻¹. Thus, in case of forming a TFT, it is possible to prevent the following problems: (a) drop and non-uniformity in the characteristics that are brought about by stress of the Si crystal that is caused by a stress exerted on an Si interface, or (b) deficiency in the interface, and (c) an interface fixed charge brought about with the deficiency, and (d) a threshold shift or non-uniformity brought about by a localized state in the interface, and (e) drop in the property stability.

0071That is, devices required to have higher performance, for example, a timing controller, a microprocessor, and the like, can be formed on an area where the single crystal Si thin film has been formed, and other devices can be formed on an area where the polycrystalline Si thin film has been formed.

0072Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film and an amorphous Si film sequentially on a surface of the insulating substrate; growing a polycrystalline Si layer, by thermally crystallizing the amorphous Si film, so as to form the polycrystalline Si thin film; removing a predetermined area of the polycrystalline Si layer by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; cleaning the insulating substrate and the single crystal Si substrate so as to activate surfaces of both the substrates; bonding a hydrogen ion implantation surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film on the insulating substrate.

0073With the foregoing configuration, by heating the single crystal Si substrate in which hydrogen ions of predetermined dose have been implanted to a predetermined depth, it is possible to improve the bond strength, and by dividing the single crystal Si substrate at the hydrogen ion implantation portion in an exfoliating manner, it is possible to obtain the single crystal Si thin film. Thus, it is possible to solve the following problems: (a) a localized state in the band gap that is caused by incomplete crystallization, (b) deficiency in the vicinity of a crystal grain boundary, (c) drop in mobility caused by the presence of the localized state in the band gap, and (d) increase in an S coefficient (sub-threshold coefficient) etc., all of which make it difficult to manufacture a high performance device. Therefore, it is possible to form the single crystal Si thin film and the polycrystalline Si thin film on the insulating substrate, and steps thereafter are performed as common manufacturing processes, so that devices required to have higher performance can be constituted of the single crystal Si, and other devices can be constituted of the polycrystalline Si. Thus, it is possible to manufacture a semiconductor device used in a display device such as a liquid crystal panel or an organic EL panel, in which a high performance system is integrated at low cost.

0074Further, the SiO₂film is formed in advance, and the single crystal Si substrate is bonded with the insulating substrate such as a glass substrate via the SiO₂film, so that it is possible to prevent the following problems: (a) drop in the mobility that is brought about by distortion of the Si crystal that is caused by a stress exerted on an Si interface, or (b) deficiency in the interface, and (c) an interface fixed charge brought about in combination with the deficiency, or (d) a threshold shift brought about by a localized state in the interface, or (e) drop in the property stability. Thus, it is not necessary to use a crystallized glass whose composition has been adjusted so as to prevent damages caused by thermal expansion rate difference with respect to a substrate when the bond strength is improved by heat treatment and the exfoliation is performed, so that it is possible to use the high-strain-point glass. Thus, there is not such a problem that the crystallized glass is contaminated with the alkaline metal, so that it is possible to prevent the damages caused by thermal expansion rate difference with respect to a substrate when the bond strength is improved by heat treatment and the exfoliation is performed.

0075Moreover, the polycrystalline Si film is formed on a large area high-strain-point glass substrate, and the polycrystalline Si thin film is subjected to etching removal so as to cover an area with which the single crystal Si substrate having been cut into an appropriate size should be bonded, and the single crystal Si substrate is bonded with the area, and the single crystal Si thin film and the SiO₂film are left by exfoliation, and other single crystal Si is removed by exfoliation, so that it is possible to prevent the stress from being biased in the entire glass substrate. Thus, it is possible to obtain a substrate, in which a part is constituted of the single crystal Si thin film and other parts are constituted of the polycrystalline Si thin film, without bring about stripping, cracks, or damages of Si.

0076Further, a substrate shape of the single crystal Si is limited to wafer sizes of an LSI manufacturing equipment, such as 6, 8, and 12 inches in diameter, but the polycrystalline Si thin film is formed on the substrate, so that it is possible to manufacture a large size liquid crystal panel or an organic EL panel for example.

0077Further, the single crystal Si substrate is bonded to an insulating substrate <b>1</b> via the SiO₂film at a room temperature, so that it is possible to substantially vanish the stress exerted on the bonded Si interface. Thus, it is possible to prevent the following problems: (a) drop and non-uniformity in the mobility that is brought about by distortion of the Si crystal that is caused by a stress exerted on an Si interface, or (b) deficiency in the interface, and (c) an interface fixed charge brought about in combination with the deficiency, and (d) a threshold shift brought about by a localized state in the interface, and (e) drop in the property stability.

0078Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film and an amorphous Si film sequentially on a surface of the insulating substrate; growing a polycrystalline Si layer, by thermally crystallizing the amorphous Si film, so as to form the polycrystalline Si thin film; removing a predetermined area of the polycrystalline Si thin film by etching, and removing a part of the SiO₂film, that corresponds to the predetermined area, in a direction of thickness of the SiO₂film by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; cleaning the insulating substrate and the single crystal Si substrate so as to activate surfaces of both the substrates; bonding a hydrogen ion implantation surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film on the insulating substrate.

0079With the foregoing configuration, besides the advantages of the foregoing manufacturing method, a predetermined area of the polycrystalline Si thin film is removed by etching, and a part of the SiO₂film in the predetermined area is removed in a direction of thickness of the SiO₂film by etching, so that it is possible to obtain a substrate such that: a bonded surface of the single crystal Si substrate is free from the influence exerted by a thickness of the SiO₂film, and the single crystal Si thin film and the polycrystalline Si thin film formed on the insulating substrate are substantially equal to each other in terms of a height. As a result, it is possible to perform almost all the following processes including the step of etching performed to form the island shape. Further, the foregoing method enables forming of a transistor or a circuit in which a large step is not brought about. Thus, in case of a liquid crystal panel for example, it is possible to obtain an advantage in controlling a cell thickness.

0080Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film on a surface of the insulating substrate; cutting a single crystal Si substrate into a predetermined shape, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; cleaning the insulating substrate and the single crystal Si substrate so as to activate surfaces of both the substrates; bonding a hydrogen ion implantation surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area at a room temperature; dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film on the insulating substrate; depositing an insulating film and an amorphous Si film sequentially on a surface of the insulating substrate; and growing a polycrystalline Si layer, by heating the amorphous Si film, so as to form the polycrystalline Si thin film.

0081With the foregoing configuration, it is possible to obtain advantages similar to those of the foregoing manufacturing methods.

0082Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing an SiO₂film on a surface of the insulating substrate; removing partially a predetermined area of the SiO₂film in a direction of thickness of the SiO₂film by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; cleaning the insulating substrate and the single crystal Si substrate so as to activate surfaces of both the substrates; bonding a hydrogen ion implantation surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film; depositing an insulating film and an amorphous Si film sequentially on a surface of the insulating substrate; and growing a polycrystalline Si layer, by heating the amorphous Si film, so as to form the polycrystalline Si thin film.

0083With the foregoing configuration, it is possible to obtain advantages similar to those of the foregoing manufacturing methods.

0084Further, in order to achieve the foregoing object, the method of the present invention for manufacturing the semiconductor device, including a polycrystalline Si thin film and a single crystal Si thin film that are provided on an insulating substrate, includes the steps of: depositing sequentially a first SiO₂film, an amorphous Si film, and a second SiO₂film, on a surface of the insulating substrate; removing a predetermined area of the second SiO₂film by etching so as to expose a part of the amorphous Si film; forming a very thin oxide (several nm) by oxidizing the amorphous Si film, that has been exposed, so as to spin-coat the oxide film with Ni acetate aqueous solution; growing a polycrystalline Si layer, in which crystal growth has been promoted in accordance with metal assist, by heating the amorphous Si film, so as to form the polycrystalline Si thin film; removing the second SiO₂film and the oxide film; removing a predetermined area of the polycrystalline Si layer by etching; cutting a single crystal Si substrate into a predetermined shape so as to partially or substantially entirely cover the predetermined area that has been subjected to the etching, said single crystal Si substrate having a surface which has been oxidized or on which an SiO₂film has been deposited, and having a hydrogen ion implantation portion in which hydrogen ions of a predetermined dose have been implanted to a predetermined depth; cleaning the insulating substrate and the single crystal Si substrate so as to activate surfaces of both the substrates; bonding a hydrogen ion implantation surface of the single crystal Si substrate that has been cut into the predetermined shape to the predetermined area that has been subjected to the etching at a room temperature; and dividing the single crystal Si substrate at the hydrogen ion implantation portion in a cleaving manner by performing a heating process, so as to form the single crystal Si thin film on the insulating substrate.

0085With the foregoing configuration, it is possible to obtain advantages similar to those of the foregoing manufacturing methods.

0086For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0087<figref idref="DRAWINGS">FIG. 1(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 1(</figref><i>h</i>) are cross sectional views each of which shows an example of a manufacturing process of a semiconductor device according to the present invention.

0088<figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 2(</figref><i>h</i>) are cross sectional views each of which shows an example of a manufacturing process of another semiconductor device according to the present invention.

0089<figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 3(</figref><i>d</i>) are cross sectional views each of which shows an example of a manufacturing process of still another semiconductor device according to the present invention.

0090<figref idref="DRAWINGS">FIG. 4(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 4(</figref><i>h</i>) are cross sectional views each of which shows an example of a manufacturing process of further another semiconductor device according to the present invention.

0091<figref idref="DRAWINGS">FIG. 5</figref> is a cross sectional view of an SOI substrate of another embodiment of the present invention.

0092<figref idref="DRAWINGS">FIG. 6</figref> is a cross sectional view showing a condition under which a single crystal silicon piece has not been bonded to a high-strain-point nonalkali glass substrate.

0093<figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 7(</figref><i>g</i>) are drawings each of which shows a manufacturing procedure of the SOI substrate shown in <figref idref="DRAWINGS">FIG. 5</figref>.

0094<figref idref="DRAWINGS">FIG. 8</figref> is a pattern diagram showing a condition under which the high-strain-point nonalkali glass substrate according to the present invention and the single crystal silicon piece bonded thereto are curved.

0095<figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>h</i>) are drawings each of which shows a manufacturing procedure of an SOI substrate of still another embodiment of the present invention.

0096<figref idref="DRAWINGS">FIG. 10</figref> is a cross sectional view showing an example of a thin film transistor manufactured based on the SOI substrate shown in <figref idref="DRAWINGS">FIG. 9</figref>.

0097<figref idref="DRAWINGS">FIG. 11(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>) are cross sectional views each of which shows an example of a semiconductor device according to still another embodiment of the present invention.

0098<figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>) are cross sectional views each of which shows an example of a semiconductor device according to further another embodiment of the present invention.

0099<figref idref="DRAWINGS">FIG. 13(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 13(</figref><i>f</i>) are cross sectional views each of which shows an example of a semiconductor device according to further still another embodiment of the present invention.

0100<figref idref="DRAWINGS">FIG. 14(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 14(</figref><i>e</i>) are cross sectional views each of which shows an example of a semiconductor device according to still another embodiment of the present invention.

0101<figref idref="DRAWINGS">FIG. 15(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>) are cross sectional views each of which shows an example of a semiconductor device according to further another embodiment of the present invention.

0102<figref idref="DRAWINGS">FIG. 16</figref> is a graph showing linear expansion of (a) Si which is a material for a single crystal Si substrate, (b) code 1737 which is a material for an insulating substrate, and (c) code 7059 made of barium-boro-silicated glass.

DESCRIPTION OF THE EMBODIMENTS

0103The following description will discuss an active matrix substrate <b>20</b> using a TFT which is one embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 1(</figref><i>h</i>).

0104The active matrix substrate <b>20</b> which functions as a semiconductor device includes: an insulating substrate <b>1</b>; SiO₂(silicon oxide) films <b>2</b> and <b>11</b>; a polycrystalline Si thin film <b>4</b>; a single crystal Si thin film <b>5</b>; a gate oxide film <b>6</b>; a gate electrode <b>21</b>; an interlayer insulating film <b>22</b>; and a metal wiring <b>24</b>.

0105As the insulating substrate <b>1</b>, #1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated), which is a high-strain-point glass, is used, but it is also possible to use the following materials: a barium-alumino boro-silicated glass which is a high-strain-point glass, an alkaline earth-alumino boro-silicated glass, a boro-silicated glass, an alkaline earth-zinc-lead-alumino boro-silicated glass, and an alkaline earth-zinc-alumino boro-silicated glass.

0106The SiO₂film <b>2</b> having an approximately 200 nm thickness is formed on an entire surface of the insulating substrate <b>1</b>.

0107The polycrystalline Si thin film <b>4</b> having an approximately 50 nm thickness is made with the SiO₂film <b>2</b> on the surface of the insulating substrate <b>1</b> so that the polycrystalline Si thin film <b>4</b> are in an island shape. Further, in an area except for the area having the polycrystalline Si thin film <b>4</b>, the SiO₂film <b>11</b> having an approximately 200 nm thickness is formed on the SiO₂film <b>2</b> on the surface of the insulating substrate <b>1</b>, and the single crystal Si thin film <b>5</b>, having an approximately 50 nm thickness, that is shaped into the same form as the SiO₂film <b>11</b>, is formed on an island pattern area of the SiO₂film <b>11</b>. An area of the polycrystalline Si thin film <b>4</b> is separated from an area of the single crystal Si thin film <b>5</b> by at least 0.3 micrometer, preferably not less than 0.5 micrometer. This prevents metal atoms, such as Ni, Pt, Sn, and Pd, that are used in a producing process of the polycrystalline Si thin film <b>4</b> described later, from diffusing into the single crystal Si area, thereby stabilizing its property.

0108The gate oxide film <b>6</b> having an approximately 60 nm is formed on entire surfaces of the SiO₂film <b>2</b>, the polycrystalline Si thin film <b>4</b>, and the single crystal Si thin film <b>5</b>.

0109The gate electrode <b>21</b> constituted of the polycrystalline Si, silicide, or polycide etc. is formed on the gate oxide film <b>6</b> on surfaces of the island-shaped polycrystalline Si thin film <b>4</b> and the single crystal Si thin film <b>5</b>.

0110Further, the interlayer insulating film <b>22</b> constituted of SiO₂is formed on the gate oxide film <b>6</b> having the gate electrode <b>21</b> so as to entirely cover the gate oxide film <b>6</b>. However, the interlayer insulating film <b>22</b> has a contact hole <b>23</b> (see <figref idref="DRAWINGS">FIG. 1(</figref><i>g</i>)) which functions as an opening, and the metal wiring <b>24</b> constituted of metal such as AlSi. The metal wiring <b>24</b> extends from the surfaces of the island-shaped the polycrystalline Si thin film <b>4</b> and the single crystal Si thin film <b>5</b>.

0111The active matrix substrate <b>20</b> further includes SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display. In the polycrystalline Si thin film area, a driver and a TFT used for display are formed. In the single crystal Si thin film area, there is formed a timing controller which controls timing at which driving is performed by the driver.

0112A TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec (N channel). On the other hand, in the liquid crystal display active matrix substrate <b>20</b>, the TFT formed in the single crystal Si area is such that the mobility is approximately 500 cm²/V·sec (N channel).

0113In the liquid crystal display active matrix substrate <b>20</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>4</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film <b>5</b> stably operates at 3.3V.

0114Note that, in a case where the thickness of the single crystal Si thin film <b>5</b> is increased, when the thickness is 50 nm to 100 nm, the condition does not largely change, but when the thickness is 300 nm to 600 nm, a channel portion is not completely depleted, so that an OFF current gradually increases, and an S value (sub-threshold coefficient) increases. Thus, although depending on the doping density of the channel portion, it is necessary to set the thickness of the single crystal Si thin film <b>5</b> to not more than 500 nm, preferably not more than 100 nm, taking coverage for non-uniformity into consideration.

0115Further, in the liquid crystal display active matrix substrate <b>20</b>, transistors are formed in the area of the polycrystalline Si thin film <b>4</b> and in the area of the single crystal Si thin film <b>5</b>, so that transistors, identical to each other in terms of a conductivity type, that are formed in the respective areas, are different from each other, depending on the areas, in terms of at least one of the mobility, the sub-threshold coefficient, and a threshold value. Thus, it is possible to form a transistor, corresponding to required property, in a suitable area.

0116In the liquid crystal display active matrix substrate <b>20</b>, integrated circuits are formed in the area of the polycrystalline Si thin film <b>4</b> and in the area of the single crystal Si thin film <b>5</b>, so that the integrated circuits formed in the respective areas are different from each other, depending on the areas, in terms of at least one of a gate length, a thickness of the gate oxide film, a power supply voltage, and a logic level. Thus, it is possible to form an integrated circuit, corresponding to required property, in a suitable area.

0117In the liquid crystal display active matrix substrate <b>20</b>, integrated circuits are formed in the area of the polycrystalline Si thin film <b>4</b> and in the area of the single crystal Si thin film <b>5</b>, so that it is possible to apply design rules, different from each other depending on the respective areas, with respect to the integrated circuits formed in the respective areas. This is based on the following reason: there is no crystal grain boundary in a single crystal portion particularly in a case of a short channel length, so that the non-uniformity in the TFT property hardly increases, but in the polycrystal portion, the influence of the crystal grain boundary rapidly increases the non-uniformity in the TFT property, so that it is necessary to change the design rules with respect to respective portions. Thus, it is possible to form an integrated circuit, corresponding to the design rules, in a suitable area.

0118Note that, in the present invention, a size of the obtained single crystal Si area is limited due to a wafer size of an LSI manufacturing equipment, but this size is sufficient to form (a) a high speed logic in which high speed, low power consumption, and less non-uniformity are required, (b) a timing generator, a high speed DAC (with current buffer), and the like.

0119The following description will discuss a manufacturing method of the active matrix substrate <b>20</b> described above referring to <figref idref="DRAWINGS">FIG. 1(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 1(</figref><i>h</i>).

0120First, #1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated), which is a high-strain-point glass is used as the insulating substrate <b>1</b>, and the SiO₂film <b>2</b> having an approximately 200 nm thickness is deposited on an entire surface of the insulating substrate <b>1</b>, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>a</i>), in accordance with plasma chemical vapor deposition (hereinbelow referred to as CVD) using mixed gas constituted of SiH₄(silane) and N₂O (dinitrogen monoxide). Further, an amorphous Si film <b>3</b> having an approximately 50 nm thickness is deposited on an entire surface of the SiO₂film <b>2</b>, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>a</i>), in accordance with the plasma CVD using SiH₄gas.

0121Excimer laser is irradiated to heat the amorphous Si film <b>3</b> so that the amorphous Si film <b>3</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>4</b> is formed. Note that, the heating process of the amorphous Si film <b>3</b> is not limited to the irradiation heating based on the excimer laser, but may be irradiation heating based on other laser, or may be a heating process using a furnace. Further, in order to promote the growth of the crystal, at least one of Ni, Pt, Sn, and Pd may be added to the amorphous Si film <b>3</b>.

0122A predetermined area of the polycrystalline Si thin film <b>4</b> is subjected to etching removal as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>b</i>).

0123Next, the SiO₂film <b>11</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>10</b> in advance or depositing an oxide film (SiO₂film) on the surface, and there is prepared the single crystal Si substrate <b>10</b> doped with boron of 3×10¹⁵/cm⁻³, in which there is provided a hydrogen ion implanted layer <b>12</b> obtained by implanting hydrogen ions of a dose amount of not less than 10¹⁶/cm², here 5×10¹⁶/cm², at predetermined energy. The single crystal Si substrate <b>10</b> is cut, in accordance with dicing etc., into a shape smaller, by at least 0.3 micrometer, preferably by more than 0.5 micrometer, than the predetermined area of the polycrystalline Si thin film <b>4</b> that has been subjected to the etching removal.

0124After both the substrate having the polycrystalline Si thin film <b>4</b> and the single crystal Si substrate <b>10</b> are subjected to SC-1 cleaning, a surface of the cut single crystal Si substrate <b>10</b> which faces the hydrogen ion implanted layer <b>12</b> is in contact with the area having been subjected to the etching removal, so as to be bonded thereto. The SC-1 cleaning is one of cleaning methods generally called RCA cleaning, and in the SC-1 cleaning, rinsing solution is constituted of ammonia, hydrogen peroxide, and pure water.

0125Thereafter, a thermal process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implanted layer <b>12</b> of the single crystal Si substrate <b>10</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C., so that the single crystal Si substrate <b>10</b> is divided at the hydrogen ion implanted layer <b>12</b> in an exfoliating manner.

0126A damaged layer of the surface of the single crystal Si substrate that is left on the insulating substrate <b>1</b> after the exfoliation is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid.

0127Thus, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>d</i>), the polycrystalline Si thin film <b>4</b> and the single crystal Si thin film <b>5</b> each of which has an approximately 50 nm thickness are provided on the insulating substrate <b>1</b>. Note that, when the single crystal Si substrate <b>10</b> is thermally divided at approximately 550° C. in an exfoliating manner after the single crystal Si substrate <b>10</b> is heated at 300° C. to 350° C. for approximately 30 minutes after bonding the substrates at a room temperature, the occurrence of stripping is reduced upon the exfoliation.

0128Thereafter, the lamp anneal is performed at approximately 800° C. for a minute. Next, an active area of the device is left, and unnecessary portions of the Si thin films <b>4</b> and <b>5</b> are removed by etching, so that island patterns are obtained as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>e</i>).

0129Next, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with a plasma CVD using mixed gas constituted of TEOS (Tetra Ethoxy Silane, namely, Si (OC₂H₅)₄) and O₂. The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE which is anisotropic etching. Thereafter, as the gate oxide film <b>6</b>, a second SiO₂film <b>6</b> having an approximately 60 nm thickness is formed, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>f</i>), in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O.

0130At this time, a space between the first SiO₂film pattern and the single crystal Si thin film pattern is substantially equalized to a length twice as long as the thickness of the first SiO₂film, so that an oxide film is left in a valley-shaped portion between the polycrystalline Si thin film and the single crystal Si thin film pattern, thereby entirely flattening the substrate.

0131Thereafter, the forming is performed in the same process as in a well-known forming process of a p-Si (polycrystalline Silicon) type TFT matrix substrate. That is, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>g</i>), after the gate electrode <b>21</b> constituted of polycrystalline Si, silicide, or polycide is formed, P⁺ and B⁺ ions are implanted, and the SiO₂film (interlayer insulating film) <b>22</b> is deposited, and the contact hole <b>23</b> is formed. Thereafter, as shown in <figref idref="DRAWINGS">FIG. 1(</figref><i>h</i>), the metal (AlSi) wiring <b>24</b> is formed in the contact hole <b>23</b>.

0132Note that, the single crystal Si thin film <b>5</b> and the polycrystalline Si thin film <b>4</b>, that have been formed on the insulating substrate <b>1</b>, are subjected to patterning based on etching, so as to form a MOS transistor, and P⁺ ion of not less than 10¹⁵/cm²is implanted into at least one part of a source/drain area of an N type MOS transistor and a P type MOS transistor. Thereafter, a heating process is performed in accordance with RTA, laser, and a furnace etc., and gettering of metal atoms is performed with respect not only to the polycrystalline Si thin film <b>4</b> area, but also to the single crystal Si thin film <b>5</b> area, thereby obtaining a TFT in which its property non-uniformity is little and its property is stable.

0133Further, there are sequentially formed SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display, and the timing controller is formed in the single crystal Si thin film <b>4</b> area.

0134Further, in the present embodiment in a case where the thickness of the single crystal Si thin film <b>5</b> is increased by enlarging implantation energy of the hydrogen ion so as to make a peak position of the hydrogen atom deeper, when the thickness is 50 nm to 100 nm, the condition does not largely change, but when the thickness is 300 nm to 600 nm, the S value of the TFT gradually increases, and an OFF current largely increases. Thus, although depending on the doping density of impurities, it is necessary to set the thickness of the single crystal Si thin film S to approximately not more than 600 nm, preferably not more than 500 nm, more preferably not more than 100 nm.

Embodiment 2

0135The following description will discuss an active matrix substrate <b>30</b> using a TFT as another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 2(</figref><i>h</i>). Note that, as to the same members as in the active matrix substrate <b>20</b> of Embodiment 1, description thereof will be omitted.

0136The active matrix substrate <b>30</b> which functions as a semiconductor device includes: an insulating substrate <b>1</b>; SiO₂(silicon oxide) films <b>32</b> and <b>11</b>; a second SiO₂film <b>35</b>; a polycrystalline Si thin film <b>37</b>; a single crystal Si thin film <b>34</b>; a gate oxide film <b>38</b>; a gate electrode <b>21</b>; an interlayer insulating film <b>22</b>; and a metal wiring <b>24</b>.

0137As the insulating substrate <b>1</b>, #1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated) which is a high-strain-point glass is used.

0138The SiO₂film <b>32</b> having an approximately 350 nm is formed on an entire surface of the insulating substrate <b>1</b>.

0139The second SiO₂film <b>35</b> having an approximately 100 nm thickness is formed on the SiO₂film on the insulating substrate, and the polycrystalline Si thin film <b>37</b> having an approximately 50 nm thickness is formed on the second SiO₂film <b>35</b> so as to be respectively deposited on island patterns.

0140Further, in an area except for an area of the polycrystalline Si thin film <b>37</b>, a concaved portion <b>33</b> (see <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>)) having an approximately 150 nm depth is formed in the SiO₂film <b>32</b> on the surface of the insulating substrate <b>1</b>. The SiO₂film <b>11</b> having an approximately 200 nm is formed on a bottom surface of the concaved portion <b>33</b>. The single crystal Si thin film <b>34</b>, having an approximately 50 nm thickness, that is shaped so as to correspond to a shape of the SiO₂film <b>11</b>, is formed on the SiO₂film <b>11</b> so as to be deposited on an island pattern. An area of the polycrystalline Si thin film <b>37</b> is separated from an area of the single crystal Si thin film <b>34</b> by at least 0.3 micrometer, preferably not less than 0.5 micrometer. This prevents metal atoms such as Ni, Pt, Sn, and Pd from diffusing into the single crystal Si area, thereby stabilizing its property.

0141The gate oxide film <b>36</b> having an approximately 60 nm thickness is formed on entire surfaces of the SiO₂film <b>32</b>, the polycrystalline Si thin film <b>37</b>, and the single crystal Si thin film <b>34</b>.

0142The gate electrode <b>21</b> constituted of polycrystalline Si, silicide, or polycide etc. is formed on surfaces of the island-shaped polycrystalline Si thin film <b>37</b> and single crystal Si thin film <b>34</b>.

0143Further, as in the active matrix substrate <b>30</b>, there are formed the interlayer insulating film <b>22</b>, the contact hole <b>23</b> (see <figref idref="DRAWINGS">FIG. 2(</figref><i>g</i>)), and the metal wiring <b>24</b>. Further, likewise, the active matrix substrate <b>30</b> further includes an SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display. In the polycrystalline Si thin film area, a driver and a TFT used for display are formed. In the single crystal Si thin film area, a timing controller is formed.

0144An N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate <b>30</b>, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 500 cm²/V·sec.

0145In the liquid crystal display active matrix substrate <b>30</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>37</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film <b>34</b> stably operates at 3.3V.

0146The following description will discuss a manufacturing method of the active matrix substrate <b>20</b> described above referring to <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 2(</figref><i>h</i>).

0147#1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated) which is a high-strain-point glass is used as the insulating substrate <b>1</b>, and the SiO₂film layer <b>32</b> having an approximately 350 nm thickness is deposited on an entire surface of the insulating substrate <b>1</b> in accordance with plasma CVD using mixed gas constituted of SiH₄and N₂O. As shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>), a predetermined area of the SiO₂film layer <b>32</b> is etched by approximately 150 nm, so as to form the concaved portion <b>33</b>.

0148Next, the SiO₂film <b>11</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>10</b> in advance or depositing an oxide film on the surface, and there is prepared the single crystal Si substrate <b>10</b>, doped with boron of 3×10⁶/cm⁻³, in which there is provided a hydrogen ion implanted layer <b>12</b> obtained by implanting a hydrogen ion of a dose amount of not less than 10¹⁶/cm², at predetermined energy. The single crystal Si substrate <b>10</b> is cut into a shape smaller, by at least 0.5 micrometer, than the area having the concaved portion <b>33</b>.

0149After both the insulating substrate <b>1</b> having the concaved portion <b>33</b> and the cut single crystal Si substrate <b>10</b> are subjected to SC-1 cleaning, a hydrogen ion implantation surface from which the hydrogen ions have been implanted is bonded to the area having been subjected to the etching removal, so as to be bonded thereto, as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>b</i>).

0150Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implanted layer <b>12</b> of the single crystal Si substrate <b>10</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C., so that the single crystal Si substrate <b>10</b> is divided at the hydrogen ion implanted layer <b>12</b> in an exfoliating manner.

0151A damaged layer of the single crystal Si substrate surface that is left on the insulating substrate <b>1</b> after the exfoliation is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid. Thus, as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>c</i>), the single crystal Si thin film <b>34</b> having an approximately 50 nm thickness is provided on the insulating substrate <b>1</b>.

0152Thereafter, a second SiO₂film <b>35</b> having an approximately 100 nm is deposited above an entire surface of the insulating substrate <b>1</b>, as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>d</i>), in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O. Further, an amorphous Si film <b>36</b> having an approximately 50 nm thickness is deposited on an entire surface of the SiO₂film <b>35</b>, as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>d</i>), in accordance with the plasma CVD using SiH₄gas.

0153Excimer laser is irradiated to heat the amorphous Si film <b>36</b> so that the amorphous Si film <b>36</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>37</b> is formed, and the bond strength is improved.

0154Next, an unnecessary portion of the polycrystalline Si thin film <b>37</b> and at least a portion of the second SiO₂film <b>35</b> that exists on the single crystal Si thin film <b>34</b> are removed by etching. Next, an active area of the device is left, and unnecessary portions of the Si thin film are removed by etching, so that an island pattern is obtained as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>e</i>).

0155Next, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with plasma CVD using mixed gas constituted of TEOS and oxide. The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE which is anisotropic etching.

0156Thereafter, as the gate oxide film <b>38</b>, the SiO₂film <b>38</b> having an approximately 60 nm thickness is formed, as shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>f</i>), in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O. Here, a space between the first SiO₂film pattern and the single crystal Si thin film pattern is substantially equalized to a length twice as long as the thickness of the first SiO₂film, so that an oxide film is left in a valley-shaped portion between the polycrystalline Si thin film and the single crystal Si thin film pattern that has not been subjected to the island-shape etching, thereby entirely flattening the substrate.

0157Processes thereafter are performed in the same manner as in Embodiment 1, so that descriptions thereof are omitted.

Embodiment 3

0158The following description will discuss an active matrix substrate using a TFT as still another embodiment of the present invention. A cross sectional structure of the active matrix substrate is arranged in the same manner as in the active matrix substrate <b>20</b> of Embodiment 1, so that only differences between the active matrix substrate of the present embodiment and the active matrix substrate <b>20</b> of Embodiment 1 are described.

0159A polycrystalline Si thin film <b>43</b> (see <figref idref="DRAWINGS">FIG. 3(</figref><i>d</i>)) of the present embodiment is constituted of polycrystalline Si whose crystal-growing directions are uniformed, and are uniformed, that is, so-called continuous grain silicon Si.

0160An N channel TFT formed in a conventional continuous grain silicon Si area was such that its mobility was approximately 200 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 500 cm²/V·sec.

0161In the liquid crystal display active matrix substrate, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>43</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film <b>5</b> stably operates at 3.3V.

0162The following description will discuss a manufacturing method of the active matrix substrate described above referring to <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 3(</figref><i>d</i>).

0163In Embodiment 3 of the present invention, as in Embodiment 1, #1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated) which is a high-strain-point glass is used as the insulating substrate <b>1</b>, and the SiO₂film <b>2</b> having an approximately 200 nm thickness is deposited on an entire surface of the insulating substrate <b>1</b> in accordance with plasma CVD using mixed gas constituted of SiH₄and N₂O. Further, an amorphous Si film <b>3</b> having an approximately 50 nm thickness is deposited on an entire surface of the SiO₂film <b>2</b> in accordance with the plasma CVD using SiH₄gas. As shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>), a second SiO₂film <b>41</b> having an approximately 200 nm thickness is deposited on an entire surface of the amorphous Si film <b>3</b> in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O.

0164An opening portion is formed in a predetermined area of the second SiO₂film <b>41</b> of an upper layer in accordance with etching. Thereafter, in order to control hydrophilicity of a surface of the amorphous Si film <b>3</b> in the opening portion, as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>b</i>), a thin SiO₂film <b>42</b> is formed on the surface of the amorphous Si film <b>3</b>, and a surface of the thin SiO₂film <b>42</b> is spin-coated with Ni acetate aqueous solution.

0165Next, solid-phase growing is performed at 600° C. for 12 hours, and polycrystalline Si whose crystal-growing directions are uniformed, that is, so-called continuous grain silicon is grown, so as to form a polycrystalline Si thin film <b>43</b>. Further, the second SiO₂films <b>41</b> and <b>42</b> on the polycrystalline Si thin film <b>43</b> are removed. Thereafter, a predetermined area of the polycrystalline Si thin film <b>43</b> is removed by etching.

0166Next, the SiO₂film <b>11</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>10</b> in advance or depositing an oxide film on the surface, and there is prepared the single crystal Si substrate <b>10</b>, having a hydrogen ion implanted layer <b>12</b> obtained by implanting the hydrogen ion of the dose amount of 5×10¹⁶/cm²at predetermined energy. The single crystal Si substrate <b>10</b> is cut into a shape smaller, by at least 0.3 micrometer, preferably not less than 0.5 micrometer, than the predetermined area in which the polycrystalline Si thin film <b>43</b> has been subjected to the etching removal.

0167After both the substrate having the polycrystalline Si thin film <b>43</b> and the single crystal Si substrate <b>10</b> are subjected to SC-1 cleaning, a surface of the single crystal Si substrate <b>10</b> which faces the hydrogen ion implanted layer <b>12</b> is in contact with the area having been subjected to the etching removal, so as to be bonded thereto. At this time, the polycrystalline Si thin film <b>43</b> is separated from the single crystal Si substrate <b>10</b> by at least 0.3 micrometer, preferably not less than 0.5 micrometer. This prevents metal atoms such as Ni, Pt, Sn, and Pd from diffusing into the single crystal Si area, thereby stabilizing its property.

0168Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implanted layer <b>12</b> of the single crystal Si substrate <b>10</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C., so that the single crystal Si substrate <b>10</b> is divided at the hydrogen ion implanted layer <b>12</b> in an exfoliating manner.

0169A damaged layer of a surface of the single crystal Si substrate <b>10</b> that is left on the insulating substrate <b>1</b> after the exfoliation is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid. Thus, as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>d</i>), the polycrystalline Si thin film <b>43</b> and the single crystal Si thin film <b>5</b> each of which has an approximately 50 nm thickness are provided on the insulating substrate <b>1</b>.

0170Next, an unnecessary portion on the polycrystalline Si thin film <b>43</b> and at least a portion of the second SiO₂film that exists on the single crystal Si thin film <b>5</b> are removed by etching. Further, unnecessary portions of the polycrystalline Si thin film <b>43</b> and the single crystal Si thin film <b>5</b> are removed by etching in island shapes so as to correspond to a shape of the device. Next, an active area of the device is left, and unnecessary portions of the Si thin film are removed by etching, so that an island pattern is obtained.

0171Next, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with plasma CVD using mixed gas constituted of TEOS and oxygen. The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE which is anisotropic etching. Thereafter, as the gate oxide film, the SiO₂film (not shown) having an approximately 60 nm thickness is formed in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O. Here, a space between the first SiO₂film pattern and the single crystal Si thin film pattern is substantially equalized to a length twice as long as the thickness of the first SiO₂film, so that an oxide film is left in a valley-shaped portion between the polycrystalline Si thin film and the single crystal Si thin film pattern, or side walls are formed on gap portions so that the gap portions are smoothed, thereby entirely flattening the substrate.

0172Next, an opening portion is formed in the SiO₂film in the vicinity of the active area of the devices, and P⁺ ions are implanted with high dose (15 keV, 5×10¹⁵/cm²) so as to perform gettering with respect to Ni added to promote crystal growth of the SiO₂film into a mask, and a heating process is performed in accordance with RTA at approximately 800° C. for one minute. Although a physical space is provided so that Ni atoms are prevented from diffusing into the single crystal Si while processing, there is a possibility that slight amount of Ni atoms may be mixed into the single crystal Si, so that it is preferable to perform the gettering also with respect to the active area of the single crystal Si, but the gettering may be omitted in terms of designing in a case where the space is prioritized.

0173Processes thereafter are performed in the same manner as in Embodiment 1, so that descriptions thereof are omitted.

Embodiment 4

0174The following description will discuss an active matrix substrate <b>50</b> using a TFT as another embodiment of the present invention. The active matrix substrate <b>50</b> is arranged substantially in the same manner as in the active matrix substrate <b>20</b> of Embodiment 1, so that only differences between the active matrix substrate <b>50</b> and the active matrix substrate <b>20</b> are described.

0175A thickness of the SiO₂film <b>2</b> in the active matrix substrate <b>20</b> is approximately 200 nm. On the other hand, a thickness of an SiO₂film <b>52</b> in the active matrix substrate <b>50</b> of the present embodiment is approximately 350 nm, and there is formed a concaved portion <b>55</b> (see <figref idref="DRAWINGS">FIG. 4(</figref><i>b</i>)) having an approximately 150 nm depth.

0176Further, a thickness of the SiO₂film <b>11</b> of the active matrix substrate <b>20</b> is approximately 200 nm. On the other hand, a thickness of an SiO₂film <b>61</b> of the active matrix substrate <b>50</b> of the present embodiment is approximately 400 nm.

0177An N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate <b>50</b>, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 500 cm²/V·sec.

0178In the liquid crystal display active matrix substrate <b>50</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>54</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film <b>55</b> stably operates at 3.3V.

0179Further, the single crystal Si substrate <b>60</b>, on which the SiO₂film <b>61</b> having an approximately 400 nm thickness has been formed, is used in the present embodiment. Compared with a case where non-uniformity of a threshold of a TFT is 0.3V (±σ) in Embodiment 1 in which the single crystal Si substrate <b>10</b> having the SiO₂film <b>11</b> of approximately 200 nm is used, non-uniformity of a threshold of a TFT that has been obtained in the present embodiment is approximately 0.15V (±σ) which is half of the foregoing value, so that stability of operation particularly at a low voltage is improved. This is based on the following reason: the foregoing arrangement reduces influence of a fixed charge that is caused by (a) contamination on an interface between the single crystal Si substrate and a glass substrate that are bonded to each other, or (b) deformation and incompleteness of a lattice. As the SiO₂film <b>61</b> is thicker, the non-uniformity of the threshold is further reduced, but a suitable value is approximately 200 nm to 400 nm in terms of (a) an efficiency of a forming process of the SiO₂film (time taken to oxidize) and (b) trade off with respect to height differences. In a case where the non-uniformity is focused on, the suitable value is approximately 400 nm, and in a case where the differences and the efficiency are focused on, the suitable value is approximately 200 nm.

0180In a case where no problem is brought about with respect to the differences, it is needless to say that not less than 400 nm is more preferable.

0181The following description will discuss a manufacturing method of the active matrix substrate <b>50</b> described above referring to <figref idref="DRAWINGS">FIG. 4(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 4(</figref><i>h</i>).

0182#1737 (trade name, alkaline earth-alumino boro-silicated glass, made by Corning Incorporated) which is a high-strain-point glass is used as the insulating substrate <b>1</b>, and the SiO₂film <b>52</b> having an approximately 350 nm thickness is deposited on an entire surface of the insulating substrate <b>1</b> in accordance with plasma CVD using mixed gas constituted of SiH₄and N₂O. As shown in <figref idref="DRAWINGS">FIG. 4(</figref><i>a</i>), an amorphous Si film <b>53</b> having an approximately 50 nm thickness is deposited on an entire surface of the SiO₂film <b>52</b> in accordance with the plasma CVD using SiH₄gas.

0183Excimer laser is irradiated to heat the amorphous Si film <b>53</b> so that the amorphous Si film <b>53</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>54</b> is formed.

0184The polycrystalline Si thin film <b>54</b> in the predetermined area and the SiO₂film <b>52</b> are partially removed by approximately 150 nm in accordance with etching, so that a concaved portion <b>55</b> having an approximately 200 nm depth is formed, as shown in <figref idref="DRAWINGS">FIG. 4(</figref><i>b</i>).

0185Next, the SiO₂film <b>61</b> having an approximately 400 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>60</b> or depositing an oxide film on the surface, and there is prepared the single crystal Si substrate <b>60</b> having a hydrogen ion implanted layer <b>62</b> into which hydrogen ions of a dose amount of 5×10¹⁶/cm²have been implanted at predetermined energy.

0186The single crystal Si substrate <b>60</b> is cut into a shape smaller than a shape of the concaved portion <b>55</b> by 0.5 micrometer.

0187After both the substrate <b>1</b> having the polycrystalline Si thin film <b>54</b> and the single crystal Si substrate <b>60</b> are subjected to SC-1 cleaning, a surface of the cut single crystal Si substrate <b>60</b> which faces the hydrogen ion implanted layer <b>62</b> is in contact with a bottom surface of the concaved portion <b>55</b>, so as to be bonded thereto.

0188Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 650° C., here, at approximately 550° C., and a temperature of the hydrogen ion implanted layer <b>62</b> of the single crystal Si substrate <b>60</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C., so that the single crystal Si substrate <b>60</b> is divided at the hydrogen ion implanted layer <b>62</b> in an exfoliating manner.

0189A damaged layer of a surface of the single crystal Si substrate <b>10</b> that is left on the insulating substrate <b>1</b> after the exfoliation is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid.

0190Thus, as shown in <figref idref="DRAWINGS">FIG. 4(</figref><i>d</i>), the polycrystalline Si thin film <b>54</b> and the single crystal Si thin film <b>55</b> each of which has an approximately 50 nm thickness are provided on the insulating substrate <b>1</b>.

0191Thereafter, the lamp anneal is performed at approximately 800° C. for a minute. Next, an active area of the device is left, and unnecessary portions of Si thin films <b>54</b> and <b>55</b> are removed by etching, so that island patterns are obtained as shown in <figref idref="DRAWINGS">FIG. 4(</figref><i>e</i>).

0192Next, a first SiO₂film having an approximately 350 nm thickness is deposited in accordance with plasma CVD using mixed gas constituted of TEOS and oxygen. The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE which is anisotropic etching.

0193Thereafter, as the gate oxide film, the SiO₂film <b>56</b> having an approximately 60 nm thickness is formed, as shown in <figref idref="DRAWINGS">FIG. 4(</figref><i>f</i>), in accordance with the plasma CVD using mixed gas constituted of SiH₄and N₂O.

0194Thereafter, a TFT is formed in the same process as in Embodiment 1.

Embodiment 5

0195The following description will discuss an active matrix substrate using a TFT as still another embodiment of the present invention. A structure of the active matrix substrate is arranged in the same manner as in the active matrix substrate of Embodiment 4, so that only differences in the manufacturing method between the active matrix substrate of the present embodiment and the active matrix substrate of Embodiment 4 are described.

0196In Embodiment 4, there is prepared the single crystal Si substrate <b>60</b> in which a hydrogen ion of a dose amount of 5×10¹⁶/cm²has been implanted at predetermined energy. On the other hand, in the present embodiment, there is prepared the single crystal Si substrate in which a hydrogen ion of a dose amount of 3×10¹⁶/cm²has been implanted at predetermined energy.

0197Further, in Embodiment 4, the single crystal Si is divided at the hydrogen ion implantation portion <b>62</b> in an exfoliating manner, and the heating process is performed at approximately 550° C. before obtaining the single crystal Si thin film <b>55</b>. On the other hand, in the present embodiment, a pulse of the excimer laser is irradiated at approximately 60 to 80% energy upon forming the polycrystalline Si layer, and the irradiation is performed with respect to the entire surface as in the growth of the polycrystalline Si layer, so that the surface is entirely heated.

0198An N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 600 cm²/V·sec. Note that, in the liquid crystal display active matrix substrate of Embodiment 4, the TFT formed in a conventional single crystal Si area is such that its mobility is approximately 500 cm²/V·sec. This difference in the mobility is caused by the following reason: since the single crystal Si thin film obtained in the present embodiment is in a condition under which the implantation amount of the hydrogen ion is reduced, it is possible to reduce the damage of the single crystal Si that is brought about upon implanting the hydrogen ion, so that the TFT property is improved.

0199Further, in the liquid crystal display active matrix substrate, not only the driver but also devices formed in the area of the polycrystalline Si thin film require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film stably operates at 3.3V.

Embodiment 6

0200The following description will discuss an active matrix substrate using a TFT as still another embodiment. A structure of the active matrix substrate is the same as that of the active matrix substrate of Embodiment 1, so that description thereof is omitted.

0201In the present embodiment, a gate length of a TFT formed in a polycrystalline Si area is set to 5 micrometer, and a gate length of a TFT formed in a single crystal Si area is set to 0.8 micrometer. A gate oxide film thickness of the TFT formed in the polycrystalline Si area is set to 80 nm, and a gate oxide film thickness of the TFT formed in the single crystal Si area is set to 50 nm. When the TFTs are operated at power supply voltages of 8V and 3V respectively, the operation is stabilized.

0202While, a TFT whose gate length is 0.8 micrometer is formed in the polycrystalline Si area, and is operated at 3V, the TFT property varies and the substrate lacks in the withstand pressure between a source and a drain, so that unusable substrates tend to be manufactured.

0203Further, when a TFT whose gate length is 1.5 micrometer is formed in the polycrystalline Si area, and is operated at 3V, there are practical problems in a threshold voltage and variation thereof.

0204The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art intended to be included within the scope of the following claims.

0205Further, the embodiments of the present invention are not limited to the present content, but it is needless to say that, for example, the forming method of the polycrystalline Si, or materials for the interlayer insulating film, a thickness of the interlayer insulating film, and the like can be realized by means person with ordinary skill in the art knows. Further, it is needless to say that other materials generally used for the same object bring about the same effects.

Embodiment 7

0206The following description will discuss one embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 5</figref> to <figref idref="DRAWINGS">FIG. 8</figref>.

0207<figref idref="DRAWINGS">FIG. 5</figref> is a cross sectional view of an SOI substrate <b>201</b> described as one embodiment of the present invention. The SOI substrate <b>201</b> is manufactured by the smart cut method, and is such that: a silicon dioxide film <b>203</b> is stacked on a surface of a high-strain-point nonalkali glass substrate <b>202</b> which is an amorphous nonalkali glass substrate, and a single crystal silicon thin film <b>205</b> thermally oxidized is bonded to the surface.

0208In <figref idref="DRAWINGS">FIG. 5</figref>, the single crystal silicon thin film <b>205</b> is smaller than the high-strain-point nonalkali glass substrate <b>202</b>, and this results from a size relationship between the high-strain-point nonalkali glass substrate and a silicon wafer that are generally sold. Thus, the single crystal silicon thin film <b>205</b> may be as large as the high-strain-point nonalkali glass substrate <b>202</b>. Further, <figref idref="DRAWINGS">FIG. 5</figref> is only a pattern diagram, so that the thickness relationship is not practical. Generally, a thickness of the high-strain-point nonalkali glass substrate <b>203</b> is approximately 0.7 mm, and a thickness of the silicon dioxide films <b>203</b> and <b>204</b> is approximately 50 to 300 nm.

0209Further, a thickness of the single crystal silicon thin film <b>205</b> is approximately 40 to 200 nm. When the thickness of the single crystal silicon thin film <b>205</b>, namely an implantation depth of the hydrogen ions, is thin such as 200 nm, it is possible to obtain a transistor that has been completely depleted, so that it is possible to improve the property largely, and to facilitate the process. While, when the thickness is less than 40 nm, large non-uniformity is brought about in the thickness, so that the safety coefficient in manufacturing drops. Thus, the foregoing setting enables the safety coefficient to be kept, so that it is possible to obtain a high element property.

0210<figref idref="DRAWINGS">FIG. 6</figref> shows a condition under which a single crystal silicon piece <b>206</b> has not been bonded to the high-strain-point nonalkali glass substrate <b>202</b>. The silicon dioxide film <b>204</b> of the single crystal silicon piece is formed only on a surface of the single crystal silicon piece <b>206</b> as shown in <figref idref="DRAWINGS">FIG. 6</figref> in a case where the film is obtained by a film-forming process such as a chemical vapor deposition (CVD process). In case of forming the film by a thermal oxidation process described later, the films are formed on both front and rear surfaces of the single crystal silicon piece <b>206</b>. Further, when the single crystal silicon piece <b>206</b> is divided by the smart cut process, also the silicon dioxide film on the front surface side is removed, so that this brings about a single crystal silicon thin film <b>205</b> shown in <figref idref="DRAWINGS">FIG. 5</figref>.

0211Each of <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 7(</figref><i>g</i>) shows a manufacturing procedure of the foregoing SOI substrate <b>201</b>. The hydrophilicity of the high-strain-point nonalkali glass substrate <b>202</b> is insufficient as it is, so that the silicon dioxide (SiO₂) film <b>203</b> having an 50 to 300 nm thickness is formed, as shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) and <figref idref="DRAWINGS">FIG. 7(</figref><i>b</i>), so as to increase the hydrophilicity. The film can be formed as follows: TEOS (Tetra Ortho Silicate) gas and oxygen gas are emitted in a vacuum chamber, and plasma discharge is performed, in accordance with plasma chemical vapor deposition (plasma CVD) for example. In the plasma CVD, the film is formed by activating the material gas with the plasma discharge, so that the plasma CVD is suitable for forming the film on the high-strain-point nonalkali glass substrate <b>202</b> whose temperature cannot be increased to not less than 600° C. The film-forming process is concretely detailed as follows.

0212The TEOS gas and the oxygen gas that are used as the material gas are emitted into the vacuum chamber, and the degree of vacuum is adjusted to 133 to 1330 Pa. A substrate temperature is kept to approximately 200° C. to 400° C. A board on which the substrate is placed functions also as one electrode of a high frequency power supply, and a high frequency of 13.56 MHz, which is in a radio frequency band (RF band), is applied between the other electrode and the board, so as to bring about the plasma discharge. The power density of the high frequency is approximately 0.1 W/cm². Due to the plasma discharge, it is possible to form the silicon dioxide film <b>203</b> having an approximately 50 to 300 nm thickness in approximately one minute.

0213Here, the plasma frequency is not necessarily limited to the RF band, but may be in a microwave band (approximately 2.456 GHz). Further, the insufficiency in the hydrophilicity of the high-strain-point nonalkali glass substrate <b>202</b> is caused by a chemical composition thereof. The silicon dioxide (SiO₂) is superior in the hydrophilicity, but is contained in the substrate only by 50%, so that this results in the insufficiency of the hydrophilicity. As described above, the silicon dioxide film <b>203</b> is coated by the foregoing thickness, so that it is possible to obtain the sufficient hydrophilicity.

0214While, the single crystal silicon piece <b>206</b> is in disc shapes of 6, 8, and 12 inches. Further, generally, impurities such as boron and phosphor of certain density are doped, and a resistivity value thereof is set to be low such as 10 Ωcm. A crystal orientation is the most likely to be a (100) face. The silicon dioxide film <b>204</b> having an approximately 50 to 300 nm thickness is formed, as shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>c</i>) to <figref idref="DRAWINGS">FIG. 7(</figref><i>d</i>), by a thermal oxidation etc. so that the impurities are not dispersed from the surface. As the thermal oxidation, dry O₂oxidation may be performed, but an oxidation speed is slow in the process, so that it takes large time to form the oxide film having a 300 nm thickness. Thus, processes such as pyrogenic oxidation or steam oxidation, in which the oxidation speed is fast, may be performed.

0215Thereafter, as shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>e</i>), the hydrogen ion is implanted. An example of how the implantation is performed is as follows: an accelerating voltage is 12 to 36 kV, and an implantation amount is 4 to 6×10¹⁶/cm⁻². As shown by a reference sign <b>210</b>, the implantation of hydrogen ions causes a hydrogen ion implantation portion to be formed on a surface positioned at a predetermined depth by an accelerating voltage (40 to 200 nm as described above) of the single crystal silicon piece <b>206</b>.

0216The high-strain-point nonalkali glass substrate <b>202</b> and the single crystal silicon piece <b>206</b> that have been prepared in this manner are rinsed with so-called SC-1 solution obtained by diluting aqua ammoniae and hydrogen peroxide solution with pure water, and so as to remove particles on the surface thereof and activate the surface. The SC-1 solution is prepared as follows: 28% commercial aqua ammoniae, 35% hydrogen peroxide solution, and pure water whose resistivity is not less than 10M Ωcm are mixed at a content ratio of 1:2:12 and the like. The high-strain-point nonalkali glass substrate <b>202</b> and the single crystal silicon piece <b>206</b> are immersed in the SCI solution for 1 to 10 minutes, so as to remove the particles on the surface. Thereafter, rinsed by flowing pure water for about 10 minutes so as to remove the solution from the surfaces, and the surfaces are dried by a spin dryer etc.

0217When the high-strain-point nonalkali glass substrate <b>202</b> and the single crystal silicon piece <b>206</b> that have been rinsed in this manner come closer to each other, they are bonded to each other by a van der Waals force. This condition is shown in <figref idref="DRAWINGS">FIG. 7(</figref><i>f</i>). At this time, the single crystal silicon piece <b>206</b> is turned upside down, and a hydrogen ion implantation surface from which the hydrogen ions have been implanted is bonded on the high-strain-point nonalkali glass substrate <b>202</b>. A little force is required (for example, several hundreds g) in the bonding in a case where: the rinse is performed in a preferable manner, and the particles on the surface are removed and sufficiently activated. An attraction force based on the van der Waals force varies so as to inversely relate to the 6th power of an interatomic distance. When atoms on the surfaces come closer to each other with a distance that can be compared with an interatomic distance of solids, the surfaces bond to each other. It is possible to recognize a condition, under which the surfaces bond to each other, by seeing a backside in which an interference color vanishes, in a case where the high-strain-point nonalkali glass substrate <b>202</b> is a transparent substrate.

0218The high-strain-point nonalkali glass substrate <b>202</b> and the single crystal silicon piece <b>206</b> are made to bond to each other by coming closer to each other as described above, and they are subjected to a heating process, so that the high-strain-point nonalkali glass substrate <b>202</b> to which the single crystal silicon piece <b>206</b> has been made to bond in this manner becomes chemically-integrated bond. That is, the hydrogen on the surfaces are dissipated by heat, and free hands of the atoms on the substrates are joined to each other, so that the adhesion is strengthened. The inventor of the present invention confirmed that this bonding was performed at not less than 300° C., and a high temperature of 800° C. to 1200° C. was not required unlike Tokukaihei 11•163363 (Japanese Patent). While, a strain point of the high-strain-point nonalkali grass which functions as a substrate is not more than 700° C., so that when the substrate is heated at a higher temperature, the substrate is deformed. Thus, in a case of using the high-strain-point nonalkali glass as the substrate like the present invention, the highest temperature for performing the heating process so as to strengthen the adhesion is limited to approximately 650° C., and the inventor of the present invention confirmed that it was possible to obtain a sufficient bond strength even when the highest temperature was 600° C.

0219The high-strain-point nonalkali grass substrate <b>202</b> and the single crystal silicon piece <b>206</b> that have been bonded to each other have a bond strength of 1×10⁵dyn/cm²in an interface therebetween. This value can be compared with a bond strength of a thin film formed by a CVD device etc. The bond strength is evaluated by performing a test in which the bonded single crystal silicon thin film <b>205</b> is stripped from an end portion. According to “Elasticity Theory” (written by LD Landau and EM Lifshitz, translated by Tsunezo Sato, published by Tokyo Tosyo (In Japan)), when a thin layer (thickness: h) is stripped from an object by an external force resisting to a surface tractional force on a separating surface, α (a bond strength per a unit length) is expressed by the following equation.

0220<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><mi>α</mi><mo>=</mo><mrow><mfrac><msup><mi>Eh</mi><mn>3</mn></msup><mrow><mn>24</mn><mo>⁢</mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><msup><mi>σ</mi><mn>2</mn></msup></mrow><mo>)</mo></mrow></mrow></mfrac><mo>⁢</mo><msup><mrow><mo>(</mo><mrow><mrow><msup><mo>∂</mo><mn>2</mn></msup><mo>⁢</mo><mi>ζ</mi></mrow><mo>/</mo><mrow><mo>∂</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><msup><mi>x</mi><mn>2</mn></msup></mrow></mrow><mo>)</mo></mrow><mn>2</mn></msup></mrow></mrow></math></maths><img file="US7884367B2_D0001.tif" />

0221Here, E is a Young's modulus, σ is a Poisson ratio, h is a thickness of the thin film, x is an axis in a horizontal direction of a flat surface on which the thin film is bonded, and ζ is displacement of a film to be stripped in a normal line direction of the thin film. The bond strength α is obtained by calculating a quadratic partial differential coefficient with respect to an x axis of ζ, the displacement in a normal line direction.

0222Further, when the heating process for enforcing the bond strength is performed, it is important in bonding them stably that a coefficient of thermal expansion of the glass substrate is higher than that of the single crystal silicon piece <b>206</b>. The coefficient of thermal expansion of silicon is approximately 2.6×10⁻⁶deg⁻¹at a room temperature, and is approximately 4.1×10⁻⁶deg⁻¹at 500° C. While, the high-strain-point nonalkali glass substrate is made of materials by which it is possible to obtain a substrate whose coefficient of thermal expansion is as high as or higher than that of the single crystal silicon at a temperature range from a room temperature to 700° C., for example, made of an alkaline earth-alumino boro-silicated glass, a barium-alumino boro-silicated glass, an alkaline earth-zinc-lead-alumino boro-silicated glass, or an alkaline earth-zinc-alumino boro-silicated glass, and the coefficient of thermal expansion is 4.7×10⁻⁶deg⁻¹at a temperature ranging from 50° C. to 300° C. Thus, at the temperature ranging from 50° C. to 300° C., the coefficient of thermal expansion of the high-strain-point nonalkali glass substrate <b>202</b> is higher than that of the single crystal silicon. Note that, in the present invention, the amorphous nonalkali glass substrate contains alkali of not more than 1%, and a concrete example is #1737 glass made by Corning Incorporated.

0223The high-strain-point nonalkali glass substrate <b>202</b> and the single crystal silicon piece <b>206</b> bonded to each other are put into a furnace for the heating process, and they are warped. This state is shown in <figref idref="DRAWINGS">FIG. 8</figref> as a pattern diagram. When they are exposed in a high temperature for performing the heating process under the foregoing relationship of the coefficients of thermal expansion, the high-strain-point nonalkali glass substrate <b>202</b> is warped downward in a convex direction. At this time, a portion of the single crystal silicon piece <b>206</b>, that is positioned in the vicinity of the high-strain-point nonalkali glass substrate <b>202</b> bonded to the single crystal silicon piece <b>206</b> by the van der waals force, is pulled in a horizontal direction, but the high-strain-point nonalkali glass substrate <b>202</b> is warped downward in a convex direction, so that a force exerted when the single crystal silicon piece <b>206</b> is stripped from the end portion is identical to a direction in which the high-strain-point nonalkali glass substrate <b>202</b> is warped. This causes the force exerted when the single crystal silicon piece <b>206</b> is stripped of the bonded surface to be counterbalanced, so that the single crystal silicon piece <b>206</b> is not stripped. This brings about a bond. <figref idref="DRAWINGS">FIG. 8</figref> shows this figure at about 600° C.

0224However, separation of the hydrogen ions on the hydrogen ion implantation portion <b>210</b> that is caused by hydrogen embrittlement is not brought about unless the hydrogen ion implantation portion <b>210</b> is heated at not less than 600° C. Thus, by heating the hydrogen ion implantation portion <b>210</b> at 600° C., it is possible to perform (a) the heating process for strengthening the bond strength and (b) the heating process for separating the single crystal silicon piece <b>206</b> at the same time efficiently. An example of this is as follows: when the heating process is performed at 600° C. for 30 to 60 minutes, the bond strength of the bonded surfaces is enforced, and the single crystal silicon piece <b>206</b> is divided at the hydrogen ion implantation portion <b>210</b>. This state is shown in <figref idref="DRAWINGS">FIG. 5</figref> and <figref idref="DRAWINGS">FIG. 7(</figref><i>g</i>).

0225When evaluation of TDS (Temperature Desorption Spectroscopy) is performed in performing the heating process, it is possible to observe a condition under which the hydrogen comes off the single crystal silicon piece <b>206</b> or the surfaces of the silicon dioxide films <b>203</b> and <b>204</b> substantially above 300° C. When the hydrogen comes off, the hydrogen drastically dissipates from the hydrogen ion implantation portion <b>210</b> of the single crystal piece <b>206</b>, and the single crystal silicon piece <b>206</b> is divided into the single crystal silicon thin film <b>205</b> and a single crystal silicon piece <b>206</b><i>a</i>, so that it is possible to obtain the single crystal silicon thin film <b>205</b> on the high-strain-point nonalkali glass substrate <b>202</b>. By performing the foregoing processes, there is provided the SOI substrate <b>201</b> including the single crystal silicon thin film <b>205</b> having an approximately 40 to 200 nm thickness. It is important that a channel portion of a transistor formed within such a thickness range is completely depleted.

0226Note that, the foregoing description discusses the heating process performed at a single stage, but it is possible to enforce the bond strength by performing the heating process at multiple stages. Particularly, the heating process for enforcing the bond strength (temperature ranges from 300° C. to 550° C.) and the heating process for the division may be separately performed. In this case, the bond strength is enforced at not less than 300° C. as described above. Then, a first heating process for enforcing the bond strength is performed at a temperature of 300° C. to 550° C., at which the single crystal silicon piece <b>206</b> is not divided at the hydrogen ion implantation portion <b>210</b>, for a short time such as not more than 15 minutes. Thereafter, a second heating process is performed at 600° C. to 700° C., so that it is possible to reduce the number of inferior products in which a film is stripped from the bonded surface and the single crystal silicon piece <b>206</b> itself is stripped after the heating process.

0227Further, the foregoing description shows an example where an electric furnace is used so as to perform the heating process, but it is also possible to perform the heating process by means of an instant heating anneal including a peak temperature of approximately not less than 850° C. in accordance with light (lamp) anneal such as laser. The shrinkage of the high-strain-point glass substrate <b>202</b> occurs upon heating in an electric furnace when the high-strain-point glass substrate <b>202</b> is heated above the strain point. On the other hand, rapid thermal anneal using lamp etc. or heating anneal using laser (laser anneal) prevents the shrinkage of the entire substrate, and causes an annealed portion to be heated, thereby improving the crystallization or the separating efficiency. Furthermore, it is possible to improve the throughput upon manufacturing the SOI substrate <b>201</b>.

0228In a case where the high-strain-point nonalkali glass substrate <b>202</b> is made of material allowing transmission of visible light for example, the SOI substrate <b>201</b> manufactured in the foregoing manner is processed as follows: a thin film transistor is formed on a layer of the single crystal silicon thin film <b>205</b>, so as to be used in a TFT liquid crystal display (LCD) device, a TFT organic electroluminescence (OLED: organic light emitting diode), and the like. The SOI substrate <b>201</b> of the present invention is introduced into such a display panel of active matrix driving, so that it is possible to uniform, stabilize, and improve the property of the transistor. As a result, it is also possible to integrate the driver of the active matrix, peripheral drivers, the timing controller, and the like, as a system. Further, the single crystal silicon piece <b>206</b> is bonded to a required portion, so that it s possible to cover a large size substrate.

0229As described above, the SOI substrate <b>201</b> of the present invention is manufactured by bonding the single crystal silicon thin film <b>205</b>, obtained by the smart cut process, to the substrate, and the SOI substrate <b>201</b> is such that it is possible to obtain the sufficient bond strength even at 300° C. upon bonding. Base on such property, the high-strain-point nonalkali glass substrate <b>202</b> which is the amorphous alkali glass substrate is used as that substrate.

0230Thus, it is not necessary to use crystallized glass whose composition has been adjusted or heat-resistance glass, so that it is possible to manufacture the SOI substrate at low cost by using the high-strain-point nonalkali glass generally used in a liquid crystal panel based on active matrix driving, and the like. Further, since a temperature at which the heating process is performed is low, it is possible to keep the alkali metal from diffusing into a semiconductor layer by several digits. Thus, it is possible to make the silicon dioxide films <b>203</b> and <b>204</b> for preventing the dispersion thinner than conventional ones, so that it is possible to improve the throughput.

0231Further, the high-strain-point nonalkali glass substrate whose coefficient of thermal expansion is as high as or higher than that of the single crystal silicon at a temperature ranging from a room temperature to 700° C. is used, so that it is possible to prevent the substrate from braking up and to prevent the single crystal silicon thin film <b>205</b> from being stripped, upon performing the heating process for (a) dividing the single crystal silicon piece <b>206</b> into the single crystal silicon thin film <b>205</b> at the highest temperature of 600° C., and for (b) enforcing the bond strength between the single crystal silicon piece <b>206</b> and the high-strain-point nonalkali glass substrate <b>202</b>.

0232The foregoing description discusses the single crystal silicon piece <b>206</b>, which is the most likely to have a (100) face, but it is possible, in the same manner, to manufacture an SOI substrate, having a silicon film surface which is so flat that it is not necessary to grind the surface from the beginning, that includes other crystal orientation such as a (110) face and a (100) face.

0233Further, compared with the SOI substrate of the (100) face, the SOI substrate of the (110) face is such that the largest number of atoms closest to each other are disposed on the (110) face. Thus, when the single crystal silicon piece <b>206</b> is separated, the separated surface is extremely flattened, so that it is possible to reduce defective fraction of the silicon transistor formed on the SOI substrate <b>201</b>.

0234Further, when the SOI substrate of the (111) face is used, the separated surface is identical to a cleaved surface of the single crystal silicon body, and the atoms closest to each other exist in an angle deviating a little from the (111) face. Thus, when the single crystal silicon piece <b>206</b> is separated, the separated surface is extremely flattened, so that it is possible to reduce defective fraction of the silicon transistor formed on the SOI substrate <b>201</b>.

Embodiment 8

0235The following description will discuss another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>) and <figref idref="DRAWINGS">FIG. 10</figref>.

0236Each of <figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>h</i>) shows a procedure for manufacturing an SOI substrate <b>211</b> as another embodiment of the present invention. The SOI substrate <b>211</b> is similar to the foregoing SOI substrate <b>201</b>, and the same reference signs are given to corresponding portions, and description thereof is omitted. It is noteworthy that the SOT substrate <b>211</b> is such that a single crystal silicon thin film <b>212</b> and the single crystal silicon thin film <b>205</b> are formed on the same high-strain-point nonalkali glass substrate <b>202</b> as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>h</i>).

0237First, as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>b</i>), an insulating film <b>213</b>, having an approximately 300 nm thickness, which functions as an undercoat film, is formed on the high-strain-point nonalkali glass substrate <b>202</b> in accordance with plasma chemical vapor deposition (PECVD). A top layer of the undercoat film is made of the silicon dioxide film which is superior in the hydrophilicity. Next, as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>c</i>), an amorphous silicon film <b>214</b> having an approximately 30 to 200 nm thickness is formed in accordance with the PECVD, and dehydrogenation anneal is performed with respect to the amorphous silicon film <b>214</b> at 400° C. to 500° C., so as to dehydrogenate the amorphous silicon film <b>214</b>. Thereafter, as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>d</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>e</i>), an area <b>214</b><i>a </i>on which a TFT is to be formed using the amorphous silicon film <b>214</b> is fused and crystallized (laser crystallization) by excimer laser, so that the polycrystalline Silicon thin film <b>212</b> is formed. It is important that a thickness of the polycrystalline Silicon thin film <b>212</b> at this time corresponds to a thickness of the single crystal silicon thin film <b>205</b> formed later, for example, 40 to 200 nm.

0238After performing the laser crystallization, as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>e</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>f</i>), a silicon film of an area <b>214</b><i>b </i>with which the single crystal silicon thin film <b>205</b> is bonded is removed by etching. At this time, in a case where there is concern that a surface of the polycrystalline Silicon thin film <b>212</b> is contaminated by being in contact with a photo resist, a silicon dioxide film having an approximately 30 to 100 nm thickness is formed on the surface of the polycrystalline Silicon thin film <b>212</b> before applying the photo resist. Further, if necessary, a part of the polycrystalline Silicon thin film <b>212</b> is subjected to the etching removal in a direction of thickness of the insulating film <b>213</b> so that the thickness of the single crystal silicon thin film <b>205</b> is identical to the thickness of the polycrystalline Silicon thickness <b>212</b>.

0239Next, the single crystal silicon piece <b>206</b> in which the hydrogen ions have been implanted is cut into a shape so as to cover the area <b>214</b><i>b </i>that has been subjected to the etching removal, and as shown in <figref idref="DRAWINGS">FIG. 9(</figref><i>g</i>) to <figref idref="DRAWINGS">FIG. 9(</figref><i>h</i>), the single crystal silicon piece <b>206</b> is bonded to the area <b>214</b><i>b </i>having been subjected to the etching removal as in <figref idref="DRAWINGS">FIG. 7(</figref><i>f</i>) to <figref idref="DRAWINGS">FIG. 7(</figref><i>g</i>), and a heating process is performed at approximately 600° C., so that the single crystal silicon piece <b>206</b> is divided at the hydrogen ion implantation portion <b>210</b>. This brings about the single crystal silicon thin film <b>205</b>.

0240Even when there are both thin films <b>205</b> and <b>212</b>, or when there is only the single crystal silicon thin film <b>205</b> like the SOI substrate <b>201</b>, a process for forming the TFT is as shown in <figref idref="DRAWINGS">FIG. 10</figref>. <figref idref="DRAWINGS">FIG. 10</figref> is a cross sectional view of a thin film transistor <b>221</b> using the SOI substrate <b>211</b> as an example. The following description briefly illustrates a procedure for manufacturing the thin film transistor <b>221</b>. First, the thin films <b>205</b> and <b>212</b> are subjected to patterning corresponding to a size of a formed transistor. Next, a gate insulating film <b>222</b> is formed. As the gate insulating film <b>222</b>, a film made of mainly silicon dioxide is the most appropriate, and its thickness is 30 to 200 nm for example. The gate insulating film <b>222</b> becomes a film inferior in the density when the gate insulating film <b>222</b> is formed at 200° C. to 400° C., so that densifying anneal is performed with respect to the gate insulating film <b>222</b> at 600° C. after forming the film. The densifying anneal also restore a crystalline substance of the single crystal silicon film, in which the hydrogen ions have been implanted, to a crystalline substance having no hydrogen ion.

0241Thereafter, a gate electrode film <b>223</b> having an approximately 300 nm thickness is formed, and patterning is performed with respect to the gate electrode film <b>223</b> so as to be appropriately shaped. Further, the gate electrode film <b>223</b> is used as a mask, and ions are implanted into the thin films <b>205</b> and <b>212</b>, so that an n⁺ or p⁺ area <b>224</b> is formed. At this time, in the present invention, the thickness of the single crystal silicon thin film <b>205</b> is set to not more than 200 nm, so that it is possible to completely deplete the channel area <b>225</b>.

0242Next, after forming an interlayer insulating film <b>226</b> having an approximately 400 nm thickness, a hole is provided in such a position that contact with a source/drain electrode is allowed. Thereafter, a source/drain metal film <b>227</b> having an approximately 400 nm thickness is formed, and patterning is performed with respect to the source/drain metal film <b>227</b>. Depending on cases, an n type MOSTFT is arranged so as to have an LDD structure upon implanting ions, thereby obtaining high reliability.

0243In the thin film transistor <b>221</b> manufactured in this manner, a portion in which the single crystal silicon thin film <b>205</b> is obtained by bonding and dividing is such that a silicon film functioning as a channel portion is single crystal silicon film, so that there is no electric conduction from a grain boundary that is recognized in the polycrystalline Silicon thin film <b>212</b>, thereby obtaining the preferable property. Further, the properties of all the transistors on the single crystal silicon thin film <b>205</b> are uniformed. Thus, in a case of using the foregoing portion in an LCD display, this is used as a source driver portion or a peripheral circuit. On the other hand, a portion of the thin film transistor <b>221</b> that is formed using the polycrystalline crystal silicon thin film <b>212</b> is used as a picture element or a gate driver portion that are comparatively inferior in the property.

0244According to a result of manufacturing that is given by the inventor, the single crystal silicon transistor is such that: in the NMOSTFT, electric field effect mobility is 500 cm²/V·sec, a threshold value is 1.0V, an OFF current is 1×10⁻¹²A, and in a PMOSTFT, the electric field effect mobility is 250 cm²/V·sec, the threshold value is −1.0V, the OFF current is 1×10⁻¹²A, so that thin film transistors each of which is superior in the uniformity are obtained.

0245By the foregoing arrangement, it is possible to obtain the SOI substrate <b>211</b> in which a height of the area <b>214</b><i>b </i>of the bonded single crystal silicon thin film <b>205</b> and a height of the area <b>214</b><i>a </i>of the polycrystalline Silicon thin film <b>212</b> are substantially equal. As a result, it is possible to perform processes thereafter, including the island etching, with respect to the areas <b>214</b><i>a </i>and <b>214</b><i>b </i>at the same time. Further, there are formed a transistor and a circuit whose step is small, so that this method is advantageous in controlling a thickness of a cell in a case of a liquid crystal panel.

Embodiment 9

0246The following description will discuss one embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 11(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>) and <figref idref="DRAWINGS">FIG. 16</figref>.

0247Each of <figref idref="DRAWINGS">FIG. 11(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>) shows an example of a manufacturing process of an active matrix substrate <b>320</b> (semiconductor device) according to the present embodiment. As shown in <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>), the active matrix substrate <b>320</b> includes: an insulating substrate <b>301</b>; SiO₂(oxide silicon) films <b>302</b> and <b>311</b>; a polycrystalline Si thin film <b>304</b>; a single crystal Si thin film <b>305</b>; a gate oxide film <b>306</b>; a gate electrode <b>321</b>; an interlayer insulating film <b>322</b>; and a metal wiring <b>324</b>. The active matrix substrate <b>320</b> further includes a thin film transistor (TFT) which functions as a switching element. The active matrix substrate <b>320</b> is used in a liquid crystal display device an the like for example.

0248The insulating substrate <b>301</b> is made of high-strain-point glass. Here, as the insulating substrate <b>301</b>, code 1737 (trade name, made by Corning Incorporated), which is a high-strain-point glass made of alkaline earth-alumino boro-silicated glass, is used.

0249Note that, the material for the insulating substrate <b>301</b> is not particularly limited, but it is possible to use the following materials: a barium-alumino boro-silicated glass, a boro-silicated glass, an alkaline earth-zinc-lead-alumino boro-silicated glass, and an alkaline earth-zinc-alumino boro-silicated glass, each of which is a high-strain-point glass.

0250The SiO₂film <b>302</b> made of SiO₂is formed on a substantially entire surface of the insulating substrate <b>301</b>. A thickness of the SiO₂film <b>302</b> is approximately 100 nm.

0251The polycrystalline Si thin film <b>304</b> and the SiO₂film <b>311</b> are formed on the SiO₂film <b>302</b>. The polycrystalline Si thin film <b>304</b> is formed so as to be in an island shape, and its thickness is approximately 50 nm. The SiO₂film <b>311</b> is formed on the SiO₂film <b>302</b> so as not to be positioned in an area of the polycrystalline Si thin film <b>304</b> so as to be in an island shape, and its thickness is approximately 200 nm. The single crystal Si thin film <b>305</b> is formed on the SiO₂film <b>311</b> so as to have the same shape as the SiO₂film <b>311</b> so as to be in an island shape. A thickness of the single crystal Si thin film <b>305</b> is approximately 50 nm.

0252An area of the polycrystalline Si thin film <b>304</b> and an area of the single crystal Si thin film <b>305</b>, that are adjacent to each other, are separated from each other by at least 0.3 μm, preferably not less than 0.5 μm.

0253This prevents metal atoms, such as Ni, Pt, Sn, and Pd that are used in a producing process of the polycrystalline Si thin film <b>304</b> described later, from diffusing into the single crystal Si area, thereby stabilizing its property.

0254The gate oxide film <b>306</b> made of SiO₂is formed on an entire surface constituted of surfaces of the SiO₂film <b>302</b>, the polycrystalline Si thin film <b>304</b>, and the single crystal Si thin film <b>305</b>. A thickness of the gate oxide film <b>306</b> is approximately 60 nm.

0255The gate electrode <b>321</b> is formed on the gate oxide film <b>306</b> on surface of the island-shaped polycrystalline Si thin film <b>304</b> and single crystal Si thin film <b>305</b>. The gate electrode <b>321</b> is constituted of the polycrystalline Si and W silicide. Note that, materials for the gate electrode <b>321</b> are not particularly limited, but the polycrystalline Si, other silicide or polycide, high melting point metal, and the like may be used for example.

0256The interlayer insulating film <b>322</b> made of SiO₂is formed on an entire surface of the gate oxide film <b>306</b> having the gate electrode <b>321</b>. However, the interlayer insulating film <b>322</b> has a contact hole <b>323</b> (see <figref idref="DRAWINGS">FIG. 11(</figref><i>g</i>)) as an opening, and the metal wiring <b>324</b> made of metal such as AlSi is formed on the contact hole <b>323</b>. The metal wirings <b>324</b> extends from surfaces of the island-shaped polycrystalline Si thin film <b>304</b> and single crystal Si thin film <b>305</b>.

0257Further, the active matrix substrate <b>320</b> includes SiNx (silicon nitride) (not shown), a resin flattening film, a via hole, a transparent electrode, and the like, that are used for liquid crystal display. Further, there are formed a timing controller and a microprocessor etc. in which a driver and a TFT used for display are formed in the polycrystalline Si thin film area, and the timing controller controls timing at which driving is performed by the driver. Of course, the driver may be made of the single crystal Si. In this case, the performance is further improved, and the device area is made smaller, the preferable unity is obtained, and a low power consumption is realized, but the cost is increased, so that selection is made according to purpose for use.

0258The following description will discuss the manufacturing method of the active matrix substrate <b>320</b> referring to <figref idref="DRAWINGS">FIG. 11(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>).

0259First, the SiO₂film <b>302</b> having an approximately 100 nm thickness is deposited on an entire surface of the insulating substrate <b>301</b> made of code 1737 (made by Corning Incorporated) in accordance with plasma chemical vapor deposition (hereinbelow referred to as P-CVD) using TEOS (Tetra Ethoxy Silane, namely, Si (OC₂H₅)₄) and O₂(oxygen).

0260Next, an amorphous Si film <b>303</b> having an approximately 50 nm thickness is deposited on the SiO₂film <b>302</b> in accordance with the P-CVD using SiH₄gas (<figref idref="DRAWINGS">FIG. 11(</figref><i>a</i>)).

0261Further, excimer laser is irradiated to heat the amorphous Si film <b>303</b> so that the amorphous Si film <b>303</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>304</b> is formed.

0262Note that, the heating process of the amorphous Si film <b>303</b> for forming the polycrystal Si thin film <b>304</b> is not limited to the irradiation heating based on the excimer laser, but may be irradiation heating based on other laser, or may be a heating process using a furnace for example. Further, in order to promote the growth of the crystal, at least one of Ni, Pt, Sn, and Pd may be added to the amorphous Si film <b>303</b>.

0263Next, a predetermined area of the polycrystalline Si thin film <b>304</b> is subjected to etching removal (<figref idref="DRAWINGS">FIG. 11(</figref><i>b</i>)).

0264While, the single crystal Si substrate <b>310</b> is prepared. In the single crystal Si substrate <b>310</b>, the SiO₂film <b>311</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>310</b> in advance or depositing an oxide film (SiO₂film) on the surface. Further, in the single crystal Si substrate <b>310</b>, there is provided a hydrogen ion implantation portion <b>312</b> obtained by implanting hydrogen ions of a dose amount of not less than 10¹⁶/cm², here, a dose amount of 5×10¹⁶/cm², at predetermined energy (here, approximately 24 keV), and boron of 3×10¹⁵/cm⁻³has been doped. In accordance with impurities of the boron density, a threshold of the N channel TFT is set to an appropriate value.

0265Further, the single crystal Si substrate <b>310</b> is cut, in accordance with dicing or anisotropic etching such as KOH, into a shape smaller, by at least 0.3 micrometer, preferably not less than 0.5 micrometer, than the predetermined area of the polycrystalline Si thin film <b>304</b> that has been removed by etching.

0266Next, after both the substrate having the polycrystalline Si thin film <b>304</b> and the single crystal Si substrate <b>310</b> are subjected to SC-1 cleaning so as to remove particles and activate the surfaces, a surface of the cut single crystal Si substrate <b>310</b> that faces the hydrogen ion implantation portion <b>312</b> is bonded (<figref idref="DRAWINGS">FIG. 11(</figref><i>c</i>)) to the area having been subjected to the etching removal (<figref idref="DRAWINGS">FIG. 11(</figref><i>b</i>)) at a room temperature. The SC-1 cleaning is one of cleaning methods generally called RCA cleaning, and in the SC-1 cleaning, rinsing solution is constituted of ammonia, hydrogen peroxide, and pure water.

0267Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implanted layer <b>312</b> of the single crystal Si substrate <b>310</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, so that the single crystal Si substrate <b>310</b> is divided at the hydrogen ion implantation portion <b>312</b> in a cleaving manner.

0268Note that, the heating process is not particularly limited, but the temperature of the hydrogen ion implantation portion <b>312</b> of the single crystal Si substrate <b>310</b> may be increased to not less than the temperature, at which hydrogen is separated from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C.

0269Further, a damaged layer of the single crystal Si substrate surface that is left on the insulating substrate <b>301</b> after the division is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 20 nm based on the wet etching using buffered Hydro fluoric acid. Thus, the polycrystalline Si thin film <b>304</b> and the single crystal Si thin film <b>305</b> each of which has an approximately 50 nm thickness are provided on the insulating substrate <b>301</b> (<figref idref="DRAWINGS">FIG. 11(</figref><i>d</i>)).

0270Note that, when the single crystal Si substrate <b>310</b> is thermally cleaved at approximately 550° C. after the single crystal Si substrate <b>310</b> is heated at 300° C. to 350° C. for approximately 30 minutes after bonding the substrates at a room temperature, the occurrence of stripping is reduced upon the cleavage.

0271Further, at this stage, it is possible to obtain sufficient bond strength between the Si and the substrate, but in order to further improve the bond strength, the lamp anneal is performed at approximately 800° C. for a minute, after performing the foregoing cleavage. This process may be performed also as activation of the implanted impurities of the source/drain.

0272Next, a portion which functions as an activated area of the device is left, and unnecessary portions of Si thin films <b>304</b> and <b>305</b> are removed by etching, so that island patterns are obtained (<figref idref="DRAWINGS">FIG. 11(</figref><i>e</i>)).

0273Next, a SiO₂film (SiO₂film for etching back) having an approximately 350 nm thickness is deposited in accordance with the P-CVD using mixed gas constituted of TEOS and O₂(oxygen). The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE (reactive ion etching) which is anisotropic etching. Thereafter, the gate oxide film <b>306</b> (SiO₂film) having an approximately 60 nm thickness is formed in accordance with the P-CVD using mixed gas constituted of SiH₄and N₂O (<figref idref="DRAWINGS">FIG. 11(</figref><i>f</i>)).

0274At this time, when a space between patterns of the formed polycrystalline Si thin film <b>304</b> and single crystal Si thin film <b>305</b> is small, a step therebetween is filled, and when the space is large, side walls are formed.

0275Thereafter, the forming is performed in the same process as in a well-known forming process of a p-Si (polycrystalline Silicon) type TFT matrix substrate. That is, after the gate electrode <b>321</b> constituted of polycrystalline Si, silicide, or polycide is formed, P⁺ and B⁺ ions are implanted, and the interlayer insulating film (SiO₂film) <b>322</b> is deposited, and the contact hole <b>323</b> is formed (<figref idref="DRAWINGS">FIG. 11(</figref><i>g</i>)). Thereafter, the metal (AlSi) wiring <b>324</b> is formed in the contact hole <b>323</b> (<figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>)).

0276Note that, the single crystal Si thin film <b>305</b> and the polycrystalline Si thin film <b>304</b>, that have been formed on the insulating substrate <b>301</b>, are subjected to patterning based on etching, so as to form a MOS transistor, and P⁺ ions of not less than 10¹⁵/cm²are implanted into at least one part of a source/drain area of an N type MOS transistor and a P type MOS transistor. Thereafter, a heating process is performed in accordance with RTA (Rapid Thermal Anneal, hereinbelow referred to as RTA), laser, and a furnace etc., and gettering of metal atoms is performed with respect not only to the polycrystalline Si thin film <b>304</b> area, but also to the single crystal Si thin film <b>305</b> area, thereby obtaining a TFT in which its property non-uniformity is little and its property is stable.

0277Next, there are sequentially formed SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display. Further, a driver and a TFT for display are formed in the polycrystalline Si thin film <b>304</b> area. Then, the timing controller, a microprocessor, and the like are formed in the single crystal Si thin film <b>305</b> area.

0278Incidentally, after bonding the single crystal Si substrate <b>310</b> with the insulating substrate <b>301</b>, when the single crystal Si substrate <b>310</b> is cleaved from the insulating substrate <b>301</b> (see <figref idref="DRAWINGS">FIG. 11(</figref><i>c</i>) and <figref idref="DRAWINGS">FIG. 11(</figref><i>d</i>)), whether the bonding and the cleavage are performed in a preferable manner or not depends on which material is used to constitute the insulating substrate <b>301</b>.

0279The following description will discuss normalized linear expansion (ΔL/L) of (a) material for the single crystal Si substrate <b>310</b> (Si: Silicon), (b) material for the insulating substrate <b>301</b> (code 1737 (made by Corning Incorporated)), and (b) code 7059 (made by Corning Incorporated) made of barium-boro-silicated glass, referring to <figref idref="DRAWINGS">FIG. 16</figref>. Note that, the normalized linear expansion (hereinbelow referred to as linear expansion) is variation (ppm) of the length that is caused by temperature variation. That is, L is an original length, and ΔL is an expanded (varied) length.

0280Thus, the code 1737 is such that a linear expansion coefficient (° C.⁻¹) is substantially constant by the time it is heated at approximately 600° C., so that there is little difference between the code 1737 and the Si in terms of the linear expansion. Within a range from a room temperature (approximately 25° C. (<figref idref="DRAWINGS">FIG. 16</figref> illustrates a case of not less than approximately 100° C.)) to approximately 600° C., the difference in the linear expansion is within approximately 250 ppm.

0281While, code 7059 is such that the linear expansion coefficient suddenly increases at approximately 600° C., so that the difference in the linear expansion between code 7059 and the Si is increased to approximately 800 ppm at approximately 600° C.

0282Thus, in a case of using code 7059 as the insulating substrate <b>301</b>, even if the substrates could be bonded to each other as in a case of using code 1737, a success rate of the cleavage is extremely low. That is, when the cleavage is performed, damages of the single crystal Si substrate <b>310</b>, stripping of the bonded interface, or deficiency in a crystal is brought about.

0283Thus, the insulating substrate <b>301</b> is made of material which is bonded generally at a temperature ranging from not less than a room temperature to not more than approximately 600° C., here, the insulating substrate <b>301</b> is made of material such that the linear expansion difference with respect to material (Si) of the single crystal Si substrate <b>310</b> is not more than approximately 250 ppm for temperature difference between room temperature to 600° C. Here, the linear expansion is normalized.

0284Further, consideration is given on a stress exerted on the bonded interface of the single crystal Si thin film <b>305</b>. Here, a Raman shift of the single crystal Si thin film <b>305</b> was measured by a microscopic Raman measuring equipment (for example, NR-1800U made by JASCO Corporation). In this case, deviation of peak position of Raman shift was 520.52±0.12 cm⁻¹(σ=0.12 cm⁻¹). Thus, it is found that no stress is exerted on the single crystal Si thin film <b>305</b>.

0285In a case where a crystal is grown by using laser, the deviation of peak position of Raman shift is generally such that a large stress of approximately 3 to 5 cm⁻¹(corresponding to 10⁹Pa) remains.

0286While, the single crystal Si substrate <b>310</b> is bonded to the insulating substrate <b>301</b> such as a glass substrate via the SiO₂film at a room temperature, so that it is possible to substantially vanish the stress exerted on the bonded Si interface. That is, the deviation of peak position of Raman shift is set to be within 520.5±1 (519.5 to 521.5) cm⁻¹, so that it is possible to substantially vanish the stress exerted on the bonded Si interface.

0287Thus, it is possible to prevent (a) drop and non-uniformity in the mobility that is caused by distortion of the Si crystal brought about by non-uniformity and difference in the stress exerted on the interface, or (b) deficiency in the interface and an interface fixed charge brought about in combination with the deficiency, and (c) a threshold shift and threshold non-uniformity that are caused by a localized state in the interface, and (d) drop in the property stability, and the like, without fail, compared with a TFT in a case where crystal growth is performed with respect to the Si film by using laser.

0288Note that, in the present embodiment, in a case where the thickness of the single crystal Si thin film <b>305</b> is increased by enlarging implantation energy of the hydrogen atom so as to make a peak position of the hydrogen atom deeper, when the thickness is 50 nm to 100 nm, the condition does not largely change, but when the thickness is 300 nm to 600 nm, the channel portion is not completely depleted, so that an S value (sub-threshold coefficient) of the TFT gradually increases, and an OFF current largely increases.

0289Thus, although depending on the doping density of impurities in the channel portion, it is necessary to set the thickness of the single crystal Si thin film <b>305</b> to not more than 600 nm, preferably not more than 500 nm, more preferably not more than 100 nm, taking coverage with respect to the non-uniformity into consideration.

0290Further, a TFT formed in a conventional polycrystalline Silicon area was such that its mobility (carrier mobility) was approximately 100 cm²/V·sec (N channel). On the other hand, in the liquid crystal display active matrix substrate <b>320</b>, the TFT formed in the single crystal Si area is such that the mobility is approximately 550 cm²/V·sec (N channel).

0291Moreover, in the liquid crystal display active matrix substrate <b>320</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>304</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller, the microprocessor, and the like, each of which is a device formed in the area of the single crystal Si thin film <b>305</b>, stably operate at 3.3V.

0292Note that, in the liquid crystal display active matrix substrate <b>320</b>, transistors are formed in the area of the polycrystalline Si thin film <b>304</b> and in the area of the single crystal Si thin film <b>305</b>, so that transistors, identical to each other in terms of a conductivity type, that are formed in the respective areas, are different from each other, depending on the areas, in terms of at least one of the mobility, the sub-threshold coefficient, and a threshold value. Thus, it is possible to form a transistor, corresponding to a required property, in a suitable area.

0293Further, in the liquid crystal display active matrix substrate <b>320</b>, integrated circuits are formed in the area of the polycrystalline Si thin film <b>304</b> and in the area of the single crystal Si thin film <b>305</b>, so that it is possible to form integrated circuits, corresponding to a required property, in a suitable area, and it is possible to provide integrated circuits, formed in the respective areas, that are different from each other in terms of the performance such as an operation speed and an operation power supply voltage. That is, it is possible to design the integrated circuits different from each other, depending on the areas, in terms of at least one of the gate length, the thickness of the gate oxide film, the power supply voltage, and the logic level.

0294In the liquid crystal display active matrix substrate <b>320</b>, integrated circuits are formed in the area of the polycrystalline Si thin film <b>304</b> and in the area of the single crystal Si thin film <b>305</b>, so that it is possible to apply design rules, different from each other depending on the respective areas, with respect to the integrated circuits formed in the respective areas. This is based on the following reason: there is no crystal grain boundary in a single crystal portion particularly in a case of a short channel length, so that the non-uniformity of the TFT property hardly increases, but in the polycrystal portion, the influence of the crystal grain boundary rapidly increases the non-uniformity of the TFT property, so that it is necessary to change the design rules with respect to respective portions. Thus, it is possible to form an integrated circuit, corresponding to the design rules, in a suitable area.

0295Note that, in the present invention, a size of the obtained single crystal Si area is limited due to a wafer size of an LSI manufacturing equipment, but this size is sufficient to form (a) a high speed logic in which high speed, low power consumption, and less non-uniformity are required, (b) a timing generator, a high-speed DAC (with current buffer), and the like.

0296Further, the thickness of the single crystal Si thin film <b>305</b> and the thickness of the polycrystalline Si thin film <b>304</b> are substantially equal to each other.

0297Thus, it is possible to perform the processes thereafter, including the island etching, at the same time, so that it is possible to form a transistor or a circuit whose step is small. Thus, this is advantageous in controlling a thickness of a cell in case of a liquid crystal panel for example.

0298Incidentally, in the active matrix substrate <b>320</b>, a gate length of a TFT formed in a polycrystalline Si area (polycrystalline Si thin film <b>304</b>) is set to 5 micrometer, and a gate length of a TFT formed in a single crystal Si area (single crystal Si thin film <b>305</b>) is set to 0.8 micrometer. A gate oxide film thickness of the TFT formed in the polycrystalline Si area is set to 80 nm, and a gate oxide film thickness of the TFT formed in the single crystal Si area is set to 50 nm. When the TFTs are operated at power supply voltages of 8V and 3V respectively, the operation is stabilized.

0299While, a TFT whose gate length is 0.8 micrometer is formed in the polycrystalline Si area, and is operated at 3V, the TFT property varies and the substrate lacks in the withstand pressure between a source and a drain, so that unusable substrates tend to be manufactured.

0300Further, a TFT whose gate length is 1.5 micrometer is formed in the polycrystalline Si area, and is operated at 3V, there are practical problems in a threshold voltage and non-uniformity thereof.

Embodiment 10

0301The following description will discuss another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>). Note that, the same reference signs are given to components having the same functions as the components in Embodiment 9, and description thereof is omitted.

0302Each of <figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>) shows an example of a manufacturing method of an active matrix substrate <b>330</b> (semiconductor device) according to the present embodiment. As shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>), the active matrix substrate <b>330</b> includes: an insulating substrate <b>301</b>; SiO₂(silicon oxide) films <b>332</b>, <b>311</b>, and <b>335</b>; a polycrystalline Si thin film <b>337</b>; a single crystal Si thin film <b>334</b>; a gate oxide film <b>338</b>; a gate electrode <b>321</b>; an interlayer insulating film <b>322</b>; and a metal wiring <b>324</b>. The active matrix substrate <b>330</b> further includes a thin film transistor (TFT) which functions as a switching element.

0303The SiO₂film (first SiO₂film) <b>332</b> is formed on a substantially entire surface of the insulating substrate <b>301</b> as in Embodiment 9. A thickness of the SiO₂film <b>332</b> is approximately 350 nm.

0304The SiO₂film (insulating film) <b>335</b> and the SiO₂film <b>311</b> are formed on the SiO₂film <b>332</b>. A thickness of the SiO₂film <b>335</b> is approximately 100 nm. The SiO₂film <b>311</b> is formed on the SiO₂film <b>332</b> so as not to be positioned in an area of the polycrystalline Si thin film <b>335</b> so as to be in an island shape, and its thickness is approximately 200 nm.

0305The polycrystalline Si thin film <b>337</b> is formed on the SiO₂film <b>335</b> so as to be in an island shape. A thickness of the polycrystalline Si thin film <b>337</b> is approximately 50 nm.

0306In an area except for an area of the polycrystalline Si thin film <b>337</b>, a concaved portion <b>333</b> (see <figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>)) having an approximately 150 nm depth is formed in the SiO₂film <b>332</b>. In the concaved portion <b>333</b>, there are formed the SiO₂film <b>311</b> and the single crystal Si thin film <b>334</b>, having the same shape as the SiO₂film <b>311</b>, which is provided on the SiO₂film <b>311</b> so as to be in an island shape.

0307An area of the polycrystalline Si thin film <b>337</b> and an area of the single crystal Si thin film <b>334</b> are separated from each other by at least 0.3 μm, preferably not less than 0.5 μm. Thus, it is possible to prevent metal atoms such as Ni, Pt, Sn, and Pd from diffusing into the single crystal Si area.

0308The gate oxide film <b>336</b> is formed so as to cover entire surfaces of the SiO₂film <b>332</b>, the polycrystalline Si thin film <b>337</b>, and the single crystal Si thin film <b>334</b>. A thickness of the gate oxide film <b>336</b> is approximately 60 nm.

0309The gate electrode <b>321</b> is formed on the gate oxide film <b>336</b> on upper surfaces of the island-shaped polycrystalline Si thin film <b>337</b> and single crystal Si thin film <b>334</b>.

0310Further, the interlayer insulating film <b>322</b>, a contact hole <b>323</b> (see <figref idref="DRAWINGS">FIG. 12(</figref><i>g</i>)), and the metal wiring <b>324</b> are formed as in the active matrix substrate <b>320</b>. Further, there are formed an SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display. In the polycrystalline Si thin film area, a driver and a TFT used for display are formed. In the single crystal Si thin film area, there are formed a timing controller and a microprocessor.

0311The following description will discuss a manufacturing method of the active matrix substrate <b>330</b> referring to <figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>).

0312First, the SiO₂film <b>332</b> having an approximately 350 nm thickness is deposited on an entire surface of the insulating substrate <b>301</b> constituted of code 1737 (made by Corning Incorporated) in accordance with P-CVD using mixed gas constituted of TEOS (Tetra Ethoxy Silane, namely, Si(OC₂H₅)₄) and O₂(oxygen). Further, a predetermined area of the SiO₂film layer <b>332</b> is etched by approximately 150 nm, so as to form the concaved portion <b>333</b> (<figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>)).

0313While, the single crystal Si substrate <b>310</b> is prepared. On the single crystal Si substrate <b>310</b>, an SiO₂film <b>311</b> having an approximately 200 nm is formed by oxidizing a surface of the single crystal Si substrate <b>310</b> in advance or depositing an oxide film (SiO₂film) on the surface. Further, the single crystal Si substrate <b>310</b> doped with 3×10¹⁵/cm⁻³boron includes a hydrogen ion implantation portion <b>312</b> obtained by implanting hydrogen ions of a dose amount of 5×10¹⁶/cm²at predetermined energy.

0314Further, the single crystal Si substrate <b>310</b> is cut into a shape smaller, by at least 0.3 μm, preferably not less than 0.5 μm, than the concaved portion <b>333</b>, in accordance with dicing or anisotropic etching such as KOH.

0315Next, after both the insulating substrate <b>301</b> having the concaved portion <b>333</b> and the cut single crystal Si substrate <b>310</b> are subjected to SC-1 cleaning so as to remove particles and activate the surfaces, a surface of the single crystal Si substrate <b>310</b> which faces the hydrogen ion implantation portion <b>312</b> is bonded to the concaved portion <b>333</b> at a room temperature (<figref idref="DRAWINGS">FIG. 12(</figref><i>b</i>)).

0316Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implantation portion <b>312</b> of the single crystal Si substrate <b>310</b> is increased to a temperature, above the hydrogen dissociation temperature from Si. Thus, the single crystal Si substrate <b>310</b> is divided at the hydrogen ion implantation portion <b>312</b> in a cleaving manner.

0317Further, a damaged layer of a surface of the single crystal Si substrate <b>310</b> that is left on the insulating substrate <b>301</b> after the division is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid. Thus, the polycrystalline Si thin film <b>343</b> having an approximately 50 nm thickness is provided on the insulating substrate <b>301</b> (<figref idref="DRAWINGS">FIG. 12(</figref><i>c</i>)).

0318Thereafter, an SiO₂film <b>335</b> having an approximately 100 nm thickness is deposited on a substantially entire surface of the insulating substrate <b>301</b> in accordance with P-CVD using mixed gas constituted of SiH₄and N₂O. Further, an amorphous Si film <b>336</b> having an approximately 50 nm thickness is deposited on a substantially entire surface of the SiO₂film <b>335</b> in accordance with the P-CVD using SiH₄gas (<figref idref="DRAWINGS">FIG. 12(</figref><i>d</i>)).

0319Further, excimer laser is irradiated to heat the amorphous Si film <b>336</b> so that the amorphous Si film <b>336</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>337</b> is formed. This heating process improves the bond strength of the single crystal Si thin film <b>334</b>.

0320Next, an unnecessary portion of the polycrystalline Si thin film <b>337</b> and at least portions of the single crystal SiO₂thin film <b>335</b> that are position on the single crystal Si thin film <b>334</b> are removed by etching. Thereafter, an active area of the device is left, and unnecessary portions of the Si thin film are removed by etching, so that an island pattern is obtained (<figref idref="DRAWINGS">FIG. 12(</figref><i>e</i>)).

0321Further, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with P-CVD using mixed gas constituted of TEOS and O₂. The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE which is anisotropic etching. Thereafter, the SiO₂film <b>338</b> having an approximately 60 nm thickness is formed in accordance with the P-CVD using mixed gas constituted of SiH₄and N₂O (<figref idref="DRAWINGS">FIG. 12(</figref><i>f</i>)).

0322At this time, when a space between patterns of the formed polycrystalline Si thin film <b>334</b> and single crystal Si thin film <b>337</b> is small, a step therebetween is filled, and when the space is large, side walls are formed.

0323Thereafter, as in Embodiment 9, the gate electrode <b>321</b> and the interlayer insulating film (SiO₂film) <b>322</b> are formed, and the metal wiring <b>324</b> is formed in the contact hole <b>323</b> (<figref idref="DRAWINGS">FIG. 12(</figref><i>h</i>)) after opening the contact hole <b>323</b> (<figref idref="DRAWINGS">FIG. 12(</figref><i>g</i>)).

0324Here, an N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate <b>330</b>, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 550 cm²/V·sec.

0325In the active matrix substrate <b>330</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>337</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller which is a device formed in the area of the single crystal Si thin film <b>334</b> stably operates at 3.3V.

Embodiment 11

0326The following description will discuss another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 13(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 13(</figref><i>f</i>). Note that, the same reference signs are given to components having the same functions as the components in Embodiment 10, and description thereof is omitted.

0327Each of <figref idref="DRAWINGS">FIG. 13(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 13(</figref><i>f</i>) shows an example of a manufacturing method of an active matrix substrate (semiconductor device) according to the present embodiment. As shown in <figref idref="DRAWINGS">FIG. 13(</figref><i>h</i>), the active matrix substrate includes: an insulating substrate <b>301</b>; SiO₂(silicon oxide) films <b>362</b>, <b>311</b>, and <b>335</b>; a polycrystalline Si thin film <b>367</b>; a single crystal Si thin film <b>364</b>; and a gate oxide film <b>368</b>. The active matrix substrate further includes a thin film transistor (TFT) (not shown); a gate electrode; an interlayer insulating film; and a metal wiring, as in Embodiments 9 and 10 described above.

0328The SiO₂film (first SiO₂film) <b>362</b> constituted of SiO₂is formed on a substantially entire surface of the insulating substrate <b>301</b> as in Embodiment 10. A thickness of the SiO₂film <b>362</b> is approximately 50 nm.

0329An SiO₂film (insulating film) <b>335</b> and an SiO₂film <b>311</b> are formed on the SiO₂film <b>362</b>. A thickness of the SiO₂film <b>335</b> is approximately 100 nm. The SiO₂film <b>311</b> is formed on the SiO₂film <b>336</b> so as not to be positioned in an area of the polycrystalline Si thin film <b>335</b> so as to be in an island shape, and its thickness is approximately 200 nm.

0330The single crystal Si thin film <b>364</b> is formed on the SiO₂film <b>311</b> so as to be formed in the same island shape as the SiO₂film <b>311</b>. A thickness of the single crystal Si thin film <b>364</b> is approximately 100 nm. Further, the polycrystalline Si thin film <b>367</b> is formed on the SiO₂film <b>335</b> so as to be in an island shape. A thickness of the polycrystalline Si thin film <b>367</b> is approximately 50 nm.

0331The gate oxide film <b>368</b> is formed so as to cover entire surfaces of the SiO₂film <b>362</b>, the polycrystalline Si thin film <b>367</b>, and the single crystal Si thin film <b>364</b>. A thickness of the gate oxide film <b>368</b> is approximately 60 nm.

0332Further, a gate electrode (not shown) is formed on the gate oxide film <b>368</b> on surfaces of the island-shaped polycrystalline Si thin film <b>367</b> and single crystal Si thin film <b>364</b>. The gate electrode is constituted in the same manner as in the active matrix substrate <b>330</b> of Embodiment 10, and is made of the polycrystalline Si, silicide, or polycide and the like.

0333Further, as in the active matrix substrate <b>330</b>, there are formed an interlayer insulating film (not shown), a contact hole, and a metal wiring. Likewise, there are formed an SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode that are used for liquid crystal display. In the polycrystalline Si thin film area, a driver and a TFT used for display are formed. In the single crystal Si thin film area, there are formed a timing controller and a microprocessor.

0334The following description will discuss a manufacturing method of the active matrix substrate referring to <figref idref="DRAWINGS">FIG. 13(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 13(</figref><i>f</i>).

0335First, the SiO₂film <b>362</b> having an approximately 50 nm thickness is deposited on an entire surface of the insulating substrate <b>301</b> constituted of code 1737 (made by Corning Incorporated) in accordance with P-CVD using mixed gas constituted of TEOS (Tetra Ethoxy Silane, namely, Si(OC₂H₅)₄) and O₂(oxygen) (<figref idref="DRAWINGS">FIG. 13(</figref><i>a</i>)).

0336While, there is prepared a single crystal Si substrate <b>310</b> that has been cut into an appropriate shape. In the single crystal Si substrate <b>310</b>, an SiO₂film <b>311</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>310</b> in advance or depositing an oxide film (SiO₂film) on the surface. Further, in the single crystal Si substrate <b>310</b> doped with boron of approximately 3×10¹⁵/cm⁻³, there is provided a hydrogen ion implantation portion <b>312</b> obtained by implanting hydrogen ions of a dose amount of 5×10¹⁶/cm², at predetermined energy.

0337Further, after activating both the insulating substrate <b>301</b> and the single crystal Si substrate <b>310</b> in accordance with particle removal and SC-1 cleaning for activating the surface, a surface of the cut single crystal Si substrate <b>310</b> which faces the hydrogen ion implantation portion <b>312</b> is bonded to the insulating substrate <b>301</b> at a room temperature (<figref idref="DRAWINGS">FIG. 13(</figref><i>b</i>)).

0338Thereafter, a heating process is performed with respect to the bonded substrates at 300° C. to 600° C., here, at approximately 550° C., and a temperature of the hydrogen ion implantation portion <b>312</b> of the single crystal Si substrate <b>310</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, so that the single crystal Si substrate <b>310</b> is divided at the hydrogen ion implantation portion <b>312</b> in a cleaving manner.

0339Further, a damaged layer a surface of the single crystal Si substrate that is left on the insulating substrate <b>301</b> after the division is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 20 nm based on the wet etching using buffered Hydro fluoric acid. Thus, the single crystalline Si thin film <b>364</b> having an approximately 80 nm thickness is provided on the insulating substrate <b>301</b> (<figref idref="DRAWINGS">FIG. 13(</figref><i>c</i>)).

0340Next, an SiO₂film <b>335</b> having an approximately 100 nm thickness is deposited on a substantially entire surface of the insulating substrate <b>301</b> in accordance with P-CVD using mixed gas constituted of SiH₄and N₂O. Further, an amorphous Si film <b>366</b> having an approximately 50 nm thickness is deposited on a substantially entire surface of the SiO₂film <b>335</b> in accordance with the P-CVD using SiH₄gas (<figref idref="DRAWINGS">FIG. 13(</figref><i>d</i>)).

0341Further, excimer laser is irradiated to heat the amorphous Si film <b>366</b> so that the amorphous Si film <b>366</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>367</b> is formed. This heating process improves the bond strength of the single crystal Si thin film <b>364</b>.

0342Next, portions which function as an active area of the device is left, and at least unnecessary portions are removed from the single crystal Si thin film <b>364</b> by etching, so that island patterns are formed (<figref idref="DRAWINGS">FIG. 13(</figref><i>e</i>)).

0343Next, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with the P-CVD using mixed gas constituted of TEOS and O₂, and a photo resist having an approximately 350 nm thickness is applied to an entire surface of the SiO₂film as the resin flattening film. Thereafter, the resin flattening film is entirely, and the SiO₂film <b>335</b> is partially etched back, in accordance with RIE using mixed gas constituted of O₂and CF₄.

0344Thereafter, the gate oxide film <b>368</b> having an approximately 60 nm thickness is formed in accordance with the P-CVD using mixed gas constituted of SiH₄and N₂O (<figref idref="DRAWINGS">FIG. 13(</figref><i>f</i>)).

0345Thereafter, the forming is performed in the same process as in a well-known forming process of a p-Si (polycrystalline Silicon) type TFT matrix substrate as in Embodiments 9 and 10. That is, the gate electrode constituted of polycrystalline Si, silicide, or polycide is formed. Then, P⁺ and B⁺ ions are implanted, and the interlayer insulating film (SiO₂film) is deposited, and the contact hole is opened. Thereafter, the metal wiring is formed in the contact hole.

0346Here, an N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the active matrix substrate according to the present embodiment, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 550 cm²/V·sec.

0347In the active matrix substrate, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>367</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller and the microprocessor and the like which are devices formed in the area of the single crystal Si thin film <b>364</b> stably operate at 3.3V.

Embodiment 12

0348The following description will discuss another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 14(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 14(</figref><i>e</i>). Note that, the same reference signs are given to components having the same functions as the components in Embodiment 9, and description thereof is omitted.

0349An active matrix substrate according to the present embodiment is different from the active matrix substrate <b>320</b> according to Embodiment 9 in that a polycrystalline Si thin film <b>343</b> is formed instead of the polycrystalline Si thin film <b>304</b>. Other than this, the active matrix substrate is arranged in the same manner as in the active matrix substrate <b>320</b>. Thus, only differences between the active matrix substrate of the present embodiment and the active matrix substrate <b>320</b> of Embodiment 9 are described.

0350The polycrystalline Si thin film <b>343</b> is constituted of polycrystalline Si whose crystal growth is promoted by metal assist, that is, a so-called continuous grain silicon Si.

0351The following description will discuss a manufacturing method of the active matrix substrate using the polycrystalline Si thin film <b>343</b>, referring to <figref idref="DRAWINGS">FIG. 14(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 14(</figref><i>e</i>).

0352First, the SiO₂film <b>332</b> having an approximately 100 nm thickness is deposited on an entire surface of the insulating substrate <b>301</b> constituted of code 1737 (made by Corning Incorporated) in accordance with P-CVD using mixed gas constituted of TEOS (Tetra Ethoxy Silane, namely, Si(OC₂H₅)₄) and O₂(oxygen).

0353Next, an amorphous Si film <b>303</b> having an approximately 50 nm thickness is deposited on the SiO₂film <b>302</b> in accordance with the P-CVD using SiH₄gas. Thereafter, an SiO₂film <b>341</b> (second SiO₂film) having an approximately 200 nm thickness is deposited on a substantially entire surface of the insulating substrate <b>301</b> in accordance with the P-CVD using mixed gas constituted of SiH₄and N₂O (<figref idref="DRAWINGS">FIG. 14(</figref><i>a</i>)).

0354Further, an opening portion is formed in a predetermined area of the SiO₂film <b>341</b> of an upper layer in accordance with etching. Thereafter, in order to control hydrophilicity of a surface of the amorphous Si film <b>303</b> in the opening portion, an oxide layer <b>342</b> is formed on the surface of the amorphous Si film <b>303</b>, and a surface of the oxide film <b>342</b> is spin-coated with Ni acetate aqueous solution (<figref idref="DRAWINGS">FIG. 14(</figref><i>b</i>)).

0355Next, solid-phase growing is performed at 600° C. for 12 hours, so that polycrystalline Si whose crystal growth has been promoted by the metal assist, that is, so-called continuous grain Si is grown, so as to form a polycrystalline Si thin film <b>343</b> having an approximately 50 nm thickness. Further, the SiO₂films <b>341</b> and <b>342</b> on the polycrystalline Si thin film <b>43</b> are removed. Thereafter, a predetermined area of the polycrystalline Si thin film <b>343</b> is removed by etching (<figref idref="DRAWINGS">FIG. 14(</figref><i>c</i>)).

0356While, a single crystal Si substrate <b>310</b> is prepared. In the single crystal Si substrate <b>310</b>, an SiO₂film <b>311</b> having an approximately 200 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>310</b> in advance or depositing an oxide film (SiO₂film) on the surface. Further, in the single crystal Si substrate <b>310</b> doped with boron of approximately 3×10¹⁵/cm⁻³, there is provided a hydrogen ion implantation portion <b>312</b> obtained by implanting hydrogen ions of a dose amount of 5×10¹⁶/cm², at predetermined energy.

0357Further, the single crystal Si substrate <b>310</b> is cut into a shape smaller, by at least 0.3 μm, preferably not less than 0.5 μm, than the predetermined area in which the polycrystalline Si thin film <b>343</b> has been removed by etching, in accordance with dicing or anisotropic etching such as KOH. Thus, it is possible to prevent metal atoms, such as Ni, Pt, Sn, and Pd that have been used in the latter manufacturing process of the polycrystalline Si thin film <b>343</b>, from diffusing into the single crystal Si area.

0358Next, after activating both the substrate having the polycrystalline Si thin film <b>343</b> and the single crystal Si substrate <b>310</b> in accordance with particle removal and SC-1 cleaning for activating the surface, a surface of the cut single crystal Si substrate <b>310</b> which faces the hydrogen ion implantation portion <b>312</b> is bonded to an area having been subjected to the etching removal (<figref idref="DRAWINGS">FIG. 14(</figref><i>c</i>)) at a room temperature (<figref idref="DRAWINGS">FIG. 14(</figref><i>d</i>)).

0359Thereafter, a temperature of the hydrogen ion implantation portion <b>312</b> of the single crystal Si substrate <b>310</b> is increased to a temperature, above the hydrogen dissociation temperature from Si, in accordance with laser irradiation or a lamp anneal including a peak temperature of approximately not less than 700° C., so that the single crystal Si substrate <b>310</b> is divided at the hydrogen ion implantation portion <b>312</b> in a cleaving manner.

0360Next, a damaged layer of a surface of the single crystal Si substrate <b>310</b> that is left on the insulating substrate <b>301</b> after the division is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid. Thus, the polycrystalline Si thin film <b>305</b> having an approximately 50 nm thickness is provided on the insulating substrate <b>301</b> (<figref idref="DRAWINGS">FIG. 14(</figref><i>e</i>)).

0361Next, an opening portion is formed in the SiO₂film in the vicinity of the active area of the devices, and highly-dense P⁺ ions are implanted (15 keV, 5×10¹⁵/cm²) so as to perform gettering with respect to Ni added to promote crystal growth of the SiO₂film into a mask, and a heating process is performed in accordance with RTA at approximately 800° C. for one minute. Although a physical space is provided so that Ni atoms are not diffused into the single crystal Si, there is a possibility that slight amount of Ni atoms may be mixed into the single crystal Si, so that it is preferable to perform the gettering also with respect to the active area of the single crystal Si, but the gettering may be omitted in terms of designing in a case where the space is prioritized.

0362Next, an active area of the device is left, and unnecessary portions of the polycrystalline Si thin film <b>343</b> and unnecessary portions of the single crystal Si thin film <b>305</b> are removed by etching, so that island patterns are obtained (corresponding to <figref idref="DRAWINGS">FIG. 11(</figref><i>e</i>)).

0363Processes thereafter (corresponding to <figref idref="DRAWINGS">FIG. 11(</figref><i>f</i>) to <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>)) are performed in the same manner as in Embodiment 9, so that description thereof is omitted.

0364Here, an N channel TFT formed in a conventional continuous grain silicon Si area was such that its mobility was approximately 200 cm²/V·sec. On the other hand, in the active matrix substrate according to the present embodiment, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 550 cm²/V·sec.

0365In the active matrix substrate, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>367</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller and the microprocessor and the like which are devices formed in the area of the single crystal Si thin film <b>305</b> stably operate at 3.3V.

0366Note that, although the surface is spin-coated with Ni acetate aqueous solution in the process shown in <figref idref="DRAWINGS">FIG. 14(</figref><i>b</i>), the process is not particularly limited. For example, ethanol and the like may be used.

Embodiment 13

0367The following description will discuss another embodiment of the present invention referring to <figref idref="DRAWINGS">FIG. 15(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>). Note that, the same reference signs are given to components having the same functions as the components in Embodiment 9, and description thereof is omitted.

0368An active matrix substrate <b>350</b> according to the present embodiment is different from the active matrix substrate <b>320</b> according to Embodiment 9 in that an insulating film <b>352</b> and an amorphous Si film <b>353</b> are formed instead of the SiO₂film <b>302</b> and the amorphous Si film <b>303</b>. Other than this, the active matrix substrate <b>350</b> is arranged in the same manner as in the active matrix substrate <b>320</b>. Thus, only differences between the active matrix substrate <b>350</b> and the active matrix substrate <b>320</b> are described.

0369As shown in <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>), the active matrix substrate <b>350</b> includes a concaved portion <b>351</b> having an approximately 150 nm depth in the insulating substrate <b>301</b>, and there are formed an SiO₂film having an approximately 350 nm and an insulating film <b>352</b> constituted of an nitride Si film and the like.

0370On the SiO₂film <b>302</b>, there are formed a polycrystalline Si thin film <b>354</b> and an SiO₂film <b>311</b>. The polycrystalline Si thin film <b>354</b> is formed so as to be in an island shape as in the polycrystalline Si thin film <b>304</b>, and has an approximately 50 nm thickness. The SiO₂film <b>311</b> is formed, so as to be in an island shape, on the SiO₂film <b>352</b> so as not to be positioned on an area of the polycrystalline Si thin film <b>354</b>, and has an approximately 200 nm thickness. On the SiO₂film <b>311</b>, a single crystal Si thin film <b>305</b> shaped in the same manner is formed so as to be in an island shape. A thickness of the single crystal Si thin film <b>305</b> is approximately 50 nm.

0371Note that, in the present embodiment, a thickness of the SiO₂film <b>311</b> is approximately 400 nm.

0372The following description will discuss a manufacturing method of the active matrix substrate <b>350</b> referring to <figref idref="DRAWINGS">FIG. 15(</figref><i>a</i>) to <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>).

0373First, the insulating film <b>352</b> having an approximately 350 nm thickness is deposited on an entire surface of the insulating substrate <b>301</b> constituted of code 1737 (made by Corning Incorporated) in accordance with P-CVD using mixed gas constituted of SiH₄and N₂O. Next, the amorphous Si film <b>353</b> having an approximately 50 nm thickness is deposited on an entire surface of the insulating film <b>352</b> in accordance with P-CVD using SiH₄gas (<figref idref="DRAWINGS">FIG. 15(</figref><i>a</i>)).

0374Further, excimer laser is irradiated to heat the amorphous Si film <b>353</b> so that the amorphous Si film <b>353</b> is crystallized, so as to grow a polycrystalline Si layer, so that the polycrystalline Si thin film <b>354</b> is formed.

0375A predetermined area of the polycrystalline Si thin film <b>354</b> and a part of the insulating film <b>352</b> are removed by etching them by approximately 150 nm, so that the concaved portion <b>351</b> having an approximately 200 nm thickness is formed (<figref idref="DRAWINGS">FIG. 15(</figref><i>b</i>)).

0376While, a single crystal Si substrate <b>310</b> is prepared. In the single crystal Si substrate <b>310</b>, an SiO₂film <b>311</b> having an approximately 400 nm thickness is formed by oxidizing a surface of the single crystal Si substrate <b>310</b> in advance or depositing an oxide film (SiO₂film) on the surface. Further, in the single crystal Si substrate <b>310</b>, there is provided a hydrogen ion implantation portion <b>312</b> obtained by implanting hydrogen ions of a dose amount of not less than 10¹⁶/cm², here, by implanting hydrogen ions of a dose amount of 5×10¹⁶/cm², at predetermined energy (here, approximately 24 keV).

0377Further, the single crystal Si substrate <b>310</b> is cut, in accordance with dicing or anisotropic etching etc., into a shape smaller, by at least 0.5 micrometer, than the predetermined area of the polycrystalline Si thin film <b>345</b> that has been removed by etching.

0378Next, after activating both the substrate having the polycrystalline Si thin film <b>354</b> and the single crystal Si substrate <b>310</b> in accordance with particle removal and SC-1 cleaning for activating the surface, a surface of the cut single crystal Si substrate <b>310</b> which faces the hydrogen ion implantation portion <b>312</b> is bonded to the concaved portion <b>351</b> at a room temperature (<figref idref="DRAWINGS">FIG. 15(</figref><i>c</i>)).

0379Thereafter, a heating process is performed at 300° C. to 600° C., here, the heating process is performed at approximately 500° C., so as to increase a temperature of the hydrogen ion implantation portion <b>312</b> of the single crystal Si substrate <b>310</b> to a temperature, above the hydrogen dissociation temperature from Si, so that the single crystal Si substrate <b>310</b> is divided at the hydrogen ion implantation portion <b>312</b> in a cleaving manner.

0380Further, a damaged layer of a surface of the single crystal Si substrate that is left on the insulating substrate <b>301</b> after the division is removed by isotopic plasma etching or wet etching, here, by performing light etching of approximately 10 nm based on the wet etching using buffered Hydro fluoric acid. Thus, the polycrystalline Si thin film <b>354</b> having an approximately 50 nm thickness and the single crystal Si thin film <b>305</b> are provided on the insulating substrate <b>301</b> (<figref idref="DRAWINGS">FIG. 15(</figref><i>d</i>)).

0381Thereafter, lamp anneal is performed at approximately 800° C. for one minute.

0382Next, an active area of the device is left, and unnecessary portions of the Si thin films <b>354</b> and <b>305</b> are removed by etching, so that island patterns are obtained (<figref idref="DRAWINGS">FIG. 15(</figref><i>e</i>)).

0383Next, an SiO₂film having an approximately 350 nm thickness is deposited in accordance with the P-CVD using mixed gas constituted of TEOS and O₂(oxygen). The deposited SiO₂film is etched back by approximately 400 nm in accordance with RIE (reactive ion etching) which is anisotropic etching. Thereafter, the gate oxide film <b>306</b> (SiO₂film) having an approximately 60 nm thickness is formed in accordance with the P-CVD using mixed gas constituted of SiH₄and N₂O (<figref idref="DRAWINGS">FIG. 15(</figref><i>f</i>)).

0384Processes thereafter (<figref idref="DRAWINGS">FIG. 15(</figref><i>g</i>) and <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>) (corresponding to <figref idref="DRAWINGS">FIG. 11(</figref><i>g</i>) and <figref idref="DRAWINGS">FIG. 11(</figref><i>h</i>)) are performed in the same manner as in Embodiment 9, so that description thereof is omitted.

0385An N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the liquid crystal display active matrix substrate <b>350</b>, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 550 cm²/V·sec.

0386In the active matrix substrate <b>350</b>, not only the driver but also devices formed in the area of the polycrystalline Si thin film <b>354</b> require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller and the microprocessor and the like which are devices formed in the area of the single crystal Si thin film <b>305</b> stably operate at 3.3V.

0387Further, the single crystal Si substrate <b>310</b>, on which the SiO₂film <b>311</b> having an approximately 400 nm thickness has been formed, is used in the active matrix substrate <b>350</b>. Compared with a case where non-uniformity in a threshold of a TFT is 0.3V (±σ) in Embodiment 9 in which the single crystal Si substrate <b>310</b> having the SiO₂film <b>311</b> of approximately 200 nm is used, non-uniformity in a threshold of a TFT that has been obtained in the present embodiment is approximately 0.15V (±σ) which is half of the foregoing value, so that stability of operation particularly at a low voltage is improved.

0388This is based on the following reason: the foregoing arrangement reduces influence of a fixed charge that is caused by (a) a contamination on an interface between the single crystal Si substrate and a glass substrate that are bonded to each other, or (b) deformation and incompleteness of a lattice. As the SiO₂film <b>311</b> is thicker, the non-uniformity in the threshold is further reduced, but a suitable value is approximately 200 nm to 400 nm in terms of (a) an efficiency of a forming process of the SiO₂film (time taken to oxidize) and (b) trade off with respect to differences. In a case where the non-uniformity is focused on, the suitable value is approximately 400 nm, and in a case where the gap and the efficiency are focused on, the suitable value is approximately 200 nm.

0389In a case where no problem is brought about with respect to the differences, it is needless to say that not less than 400 nm is more preferable.

0390Note that, the following processes may be performed. After the concaved portion <b>351</b> is formed, an SiO₂film having a several 10 nm thickness is deposited so as to entirely cover the insulating substrate <b>301</b> in accordance with a PECVD method using TEOS and O₂gas. Thereafter, the single crystal Si substrate <b>310</b> and the insulating substrate <b>301</b> are bonded to each other. Thus, the bond strength is improved, so that it is possible to bond them more steadily and with a good yield.

0391Here, the foregoing description discusses the case of using the single crystal Si substrate <b>310</b> in which hydrogen ions of a dose amount of 5×10¹⁶/cm²are implanted at predetermined energy, and the following description discusses a case of using a single crystal Si substrate in which hydrogen ions of a dose amount of 3×10¹⁶/cm²are implanted at predetermined energy.

0392In the case of the single crystal Si substrate <b>310</b> (dose amount of hydrogen ion: 5×10¹⁶/cm²), the heating process is performed at approximately 550° C. so as to obtain the single crystal Si thin film <b>305</b>, but in the case of the single crystal Si substrate (dose amount of hydrogen ion: 3×10¹⁶/cm²), a pulse of the excimer laser is irradiated at approximately 60% to 80% energy upon forming the polycrystalline Si layer, and the irradiation is performed with respect to the entire surface as in the growth of the polycrystalline Si layer, so that the surface is entirely heated.

0393An N channel TFT formed in a conventional polycrystalline Silicon area was such that its mobility was approximately 100 cm²/V·sec. On the other hand, in the foregoing case, the N channel TFT formed in the single crystal Si area is such that the mobility is approximately 600 cm²/V·sec.

0394Note that, in the active matrix substrate <b>350</b> (see <figref idref="DRAWINGS">FIG. 15(</figref><i>h</i>)) using the single crystal Si substrate <b>310</b>, the N channel TFT formed in the single crystal silicon area is such that the mobility is approximately 550 cm²/V·sec.

0395This difference is caused by the following reason: since the single crystal Si thin film obtained by using the single crystal Si substrate (dose amount of hydrogen ion: 3×10¹⁶/cm²) is in a condition under which the implantation amount of the hydrogen ion is reduced, it is possible to reduce the damage of the single crystal Si that is brought about upon implanting the hydrogen ion, so that the TFT property is improved.

0396Further, in the case of using the single crystal Si substrate (dose amount of hydrogen ion: 3×10¹⁶/cm²), not only the driver but also devices formed in the area of the polycrystalline Si thin film require signals and power supply voltages of 7 to 8V. On the other hand, the timing controller and the microprocessor and the like which are devices formed in the area of the single crystal Si thin film stably operate at 3.3V.

0397The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art intended to be included within the scope of the following claims.

0398Further, the embodiments of the present invention are not limited to the present content, but it is needless to say that, for example, the forming method of the polycrystalline Si, or materials for the interlayer insulating film, a thickness of the interlayer insulating film, and the like can be realized by means person with ordinary skill in the art knows. Further, it is needless to say that other materials generally used for the same object bring about the same effects.

0399Further, in the foregoing Embodiments 9, 10, 12, and 13, the SiO₂film on the surface bonded to the single crystal Si thin film formed on the insulating substrate <b>301</b> may be deposited after etching a part of the polycrystalline Si thin film or the insulating substrate <b>301</b> and forming the concaved portion.

0400In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the single crystal Si thin film has a surface, bonded to the insulating substrate, and the surface is oxidized, or an SiO₂film is deposited on the surface.

0401Further, the insulating substrate may also have an SiO₂film deposited on a surface bonded to the single crystal Si thin film. Note that, the thickness of the SiO₂film deposited on the surface bonded to the single crystal Si thin film should be not less than 100 nm, and further preferably not less than 500 nm. In this arrangement, the single crystal Si film is bonded to the insulating substrate via the oxide layer or the SiO₂film, so that it is possible to prevent the following problems: (a) drop in the mobility that is brought about by distortion of the Si crystal caused by a stress exerted on a bonded Si interface, or (b) deficiency in the interface, and an interface fixed charge that is brought about in combination with the deficiency, and (c) a threshold shift that is brought about by a localized state in the interface, and (d) drop in the property stability.

0402Further, in the foregoing arrangement, it is not necessary to use a crystallized glass, as with the one described in Japanese Laid-Open Patent Application Tokukaihei 11-163363, whose composition has been adjusted so as to prevent damages caused by thermal expansion rate difference with respect to a glass substrate when the bond strength is improved by heat treatment. Thus, there is not such a problem that the crystallized glass is contaminated with the alkali metal, so that it is possible to prevent the damages and the stripping that are caused by thermal expansion rate difference with respect to a glass substrate when the bond strength is improved by heat treatment and the exfoliation is performed even when a general low-cost high-strain-point glass is used.

0403On this account, there is not such a problem that the insulating substrate made of crystallized glass is contaminated with the alkali metal, and also cost reduction can be realized.

0404In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the semiconductor device is an active matrix substrate including integrated circuits each of which is made of a plurality of MOSFETs provided on the insulating substrate.

0405With the foregoing configuration, since the semiconductor device is an active matrix substrate including integrated circuits each of which is made of a plurality of MOS (Metal Oxide Semiconductor) FETs on the insulating substrate, it is possible to obtain an active matrix substrate having the foregoing characteristic.

0406In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the insulating substrate is made of high-strain-point glass in which an SiO₂layer is provided on at least a surface of an area having single crystal Si.

0407As described, since the insulating substrate can be manufactured by using high-strain-point glass, which is generally used for such as an active matrix liquid crystal panel, instead of using a crystallized glass whose composition has been adjusted, it is possible to manufacture the semiconductor device at low cost.

0408In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the insulating substrate is made of at least any one of barium-alumino boro-silicated glass, alkaline earth-alumino boro-silicated glass, boro-silicated glass, alkaline earth-zinc-lead-alumino boro-silicated glass, and alkaline earth-zinc-alumino boro-silicated glass, each of which has an SiO₂film thereon.

0409With the foregoing configuration, since the insulating substrate is made of the described glass, i.e., high-strain-point glass, which is generally used for such as an active matrix liquid crystal panel, it is possible to manufacture the semiconductor device suitable for an active matrix substrate at low cost.

0410In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that an area of the single crystal Si thin film provided on the insulating substrate and an area of the polycrystalline Si thin film provided on the insulating substrate are separated from each other by at least not less than 0.3 micrometer.

0411With the foregoing configuration, since an area of the single crystal Si thin film and an area of the polycrystalline Si thin film are separated from each other by at least not less than 0.3 micrometer, it is possible to prevent diffusion of metal atoms, such as Ni, Pt, Sn, and Pd, from the polycrystalline Si into the single crystal Si, thereby stabilizing the property of the semiconductor device.

0412In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that transistors, identical to each other in terms of a conductivity type, that are respectively provided on the different areas, are different from each other in at least any one of a mobility, a sub-threshold coefficient, and a threshold value.

0413With the foregoing configuration, since transistors, identical to each other in terms of a conductivity type, that are respectively provided on the different areas, are different from each other in terms of at least any one of a mobility, a sub-threshold coefficient, and a threshold value, it is possible to provide those transistors on respective appropriate areas according to the required property.

0414In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the integrated circuits respectively provided on the different areas are different from each other in terms of at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level.

0415With the foregoing configuration, since the integrated circuits respectively provided on the different areas are different from each other in terms of at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level, it is possible to provide those integrated circuits on respective appropriate areas according to the required arrangement and property.

0416In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that the integrated circuits respectively provided on the different areas are different from each other in a design rule.

0417With the foregoing configuration, since the integrated circuits respectively provided on the different areas are different from each other in terms of a design rule, it is possible to provide those integrated circuits on respective appropriate areas according to the design rule.

0418In addition to the foregoing configuration, in the semiconductor device according to the present invention, the thickness d of the single crystal Si thin film can be adjusted to be not more than the upper limit of 600 nm, even when the thickness d has a small value including variation of the maximum depletion length Wm, i.e., its impurity density is practical lower limit of 10¹⁵/cm⁻³. The impurity density is determined according to the amount of impurity Ni.

0419Here, Wm=[4∈s kTln (Ni/ni) q²Ni]^1/2, where ni denotes intrinsic carrier density, k denotes Boltzmann constant, T denotes absolute temperature, ∈ s denotes dielectric constant of Si, q denotes electronic charge, and Ni denotes impurity density.

0420With the foregoing configuration, since a thickness of the single crystal Si thin film is not more than 600 nm, it is possible to further reduce S value of the semiconductor device and also to reduce OFF current.

0421In addition to the foregoing configuration, the semiconductor device according to the present invention may have such an arrangement that a thickness of the single crystal Si thin film is not more than 100 nm.

0422With the foregoing configuration, since a thickness of the single crystal Si thin film is not more than 100 nm, it is possible to further reduce S value of the semiconductor device and also to reduce OFF current.

0423In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that the heating process is performed at a single temperature step ranging from not less than 300° C. to not more than 650° C.

0424With the foregoing configuration, since the heating process is performed at a single temperature step, it is possible to carry out the heating process at a single step.

0425In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that the heating process is performed at multi temperature steps ranging from not less than 300° C. to not more than 650° C.

0426With the foregoing configuration, since the heating process is performed at multi temperature steps, it is possible to reduce occurrence of stripping upon the exfoliation of the single crystal Si.

0427In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film upon growing the polycrystalline Si layer.

0428With the foregoing configuration, since at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film upon growing the polycrystalline Si layer before heating, it is possible to promote crystal growth of the polycrystalline Si layer. Thus, a mobility of the polycrystalline Si layer can be increased, thereby having an advantage at the forming of driving circuit etc.

0429In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that the step of dividing the single crystal Si substrate at the hydrogen ion implantation portion in the exfoliating manner is performed by raising a temperature of the hydrogen ion implantation portion of the single crystal Si substrate to a temperature, at which hydrogen dissociates from Si, in accordance with laser irradiation.

0430With the foregoing configuration, since a temperature of a hydrogen ion implanted layer of the single crystal Si substrate is raised by laser irradiation, it is possible to raise temperature only with respect to a small range of area, thereby suppressing damage of the single crystal Si.

0431In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that the single crystal Si substrate is divided at the hydrogen ion implantation portion in the exfoliating manner by performing lamp anneal including a peak temperature of approximately not less than 700° C.

0432With the foregoing configuration, since the single crystal Si substrate is divided at the hydrogen ion implantation portion in the exfoliating manner by performing lamp anneal (Rapid Thermal Anneal, hereinafter referred to as RTA) including a peak temperature of approximately not less than 700° C., it is possible to further improve the bond strength, and also to improve the property of transistor due to recovery of the exfoliation interface and inside of the single crystal Si thin film, which have been damaged by the hydrogen ion implantation. Note that, the property of the transistor is improved with the increase of the peak temperature of the lamp anneal; however, the increase of the peak temperature also increases bending and expansion/contraction of the substrate. Thus, the temperature and holding time should be appropriately set according to the size of substrate and/or the type of the device.

0433In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a maximum size of the single crystal Si thin film is not more than 10 cm.

0434With the foregoing configuration, by having the single crystal Si thin film of which maximum size is not more than 10 cm, it is possible to prevent breakage such as cracking, or stripping of the Si even when high-strain-point glass is adopted, which is generally used for an active matrix liquid crystal display panel etc. and having greater thermal expansion rate difference with respect to the single crystal Si than that of quartz glass. Note that, the maximum size of the single crystal Si thin film signifies a greatest size among each outline length of the surface of the single crystal Si thin film having low thickness. For example, it signifies its diameter when the single crystal Si thin film has a disc shape, and it signifies the length of the diagonal line of upper surface rectangle when the single crystal Si thin film is a thin rectangular solid.

0435In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a maximum size of the single crystal Si thin film is not more than 5 cm.

0436With the foregoing configuration, by having the single crystal Si thin film of which maximum size is not more than 5 cm, it is possible to more securely prevent breakage such as cracking, or stripping of the Si even when high-strain-point glass is adopted, which is generally used for an active matrix liquid crystal display panel etc. and having greater thermal expansion rate difference with respect to the single crystal Si than that of quartz glass. In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may further include the steps of: removing a damaged layer from a surface of the single crystal Si thin film by isotropic plasma etching or wet etching; patterning the polycrystalline Si thin film and the single crystal Si thin film in island shapes by etching; etching-back partially or entirely a first SiO₂film, that has been deposited on entire surfaces of the polycrystalline Si thin film and the single crystal Si thin film, by anisotropic etching; and depositing a second SiO₂film as a gate insulating film, wherein the steps are performed after the polycrystalline Si thin film and the single crystal Si thin film have been provided on the insulating substrate.

0437In the foregoing configuration, a general polysilicon TFT forming process is adopted, thus manufacturing a TFT having the foregoing characteristic by a conventional process.

0438In the foregoing manufacturing method, it is preferable that a space between the polycrystalline Si thin film and the single crystal Si thin film having not been subjected to island-shape-etching is substantially equalized to a length twice as long as the thickness of the first SiO₂film, so that an oxide film is left in a valley-shaped portion between the polycrystalline Si thin film and the single crystal Si thin film pattern, thereby entirely flattening the substrate.

0439In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a space between (a) a pattern formed on the polycrystalline Si thin film and (b) a pattern formed on the single crystal Si thin film having not been subjected to the etching performed to form the island shape is substantially equal to a length twice as long as a thickness of the first SiO₂film.

0440In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may further includes the steps of: forming a MOS transistor by patterning the single crystal Si thin film and the polycrystalline Si thin film, that have been formed on the insulating substrate, in island shapes, in accordance with etching; and implanting P⁺ ions of not less than 10¹⁵/cm²and not more than 5×10¹⁵/cm²into at least each part of a source area and a drain area of an N type MOS transistor and each part of a source area and a drain area of a P type MOS transistor.

0441With the foregoing configuration, since implantation of P⁺ ions of not less than 10¹⁵/cm²and not more than 5×10¹⁵/cm²is performed into at least each part of a source area and a drain area of an N type MOS transistor and each part of a source area and a drain area of a P type MOS transistor, it is possible to obtain a TFT in which its property non-uniformity is little and its property is stable by performing a heating process in accordance with RTA, laser, and a furnace etc., and also performing gettering of metal atoms with respect not only to the polycrystalline Si thin film area, but also to the single crystal Si thin film area.

0442In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a thickness of the single crystal Si thin film is substantially equal to a thickness of the polycrystalline Si thin film.

0443With the foregoing configuration, since a thickness of the single crystal Si thin film is substantially equal to a thickness of the polycrystalline Si thin film, it is possible to perform almost all the following processes at the same time including the step of etching performed to form the island shape, and to enable forming of a transistor or a circuit in which a large gap is not brought about. Thus, in case of a liquid crystal panel for example, it is possible to obtain an advantage in controlling a cell thickness.

0444In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a thickness of the SiO₂film formed in advance is not less than 200 nm, more preferably, not less than 300 nm.

0445As the SiO₂film is thicker, the non-uniformity of the threshold is further reduced, but a suitable value is approximately 200 nm to 400 nm in terms of (a) an efficiency of a forming process of the SiO₂film (time taken to oxidize) and (b) trade off with respect to differences. In a case where the non-uniformity is focused on, the suitable value is approximately 400 nm, and in a case where the differences and the efficiency are focused on, the suitable value is approximately 200 nm to 400 nm, more preferably, 250 nm to 350 nm. When the SiO₂thin film is thick, stability of operation particularly at a low voltage is improved. This is based on the following reason: the foregoing arrangement reduces influence of a fixed charge that is caused by (a) a contamination on an interface between the single crystal Si substrate and a glass substrate that are bonded to each other, or (b) deformation and incompleteness of a lattice.

0446Accordingly, it is possible to obtain a semiconductor substrate having appropriate balance between non-uniformity of the threshold, and the differences and the efficiency of the forming process of the SiO₂thin film.

0447In addition to the foregoing configuration, the manufacturing method of the semiconductor device according to the present invention may have such an arrangement that a thermal expansion rate of the amorphous nonalkali glass substrate is as high as or higher than that of the single crystal silicon piece.

0448With the foregoing configuration, when the single crystal Si thin film is exposed in a high temperature for performing the heating process for increasing division and bonding force to the substrate, the substrate is warped downward in a convex direction. This is because the thermal expansion of the substrate is greater than that of the single crystal silicon (2.6×10⁻⁶deg⁻¹) in the temperature range of the heating process. At this time, a portion of the single crystal silicon piece, that is positioned in the vicinity of the substrate by the van der waals force, is pulled in a horizontal direction, but the substrate is warped downward in a convex direction, so that a force exerted when the single crystal silicon piece is stripped from the end portion is identical to a direction in which the substrate is warped. This causes the force exerted when the single crystal silicon piece is stripped of the bonded surface to be counterbalanced, so that the single crystal silicon piece is not stripped. This brings about a bond. In this manner, it is possible to prevent the single crystal silicon thin film from being divided from the substrate, or breakage of the substrate.

0449More specifically, at the heating process in the process for dispelling the hydrogen ion which has been implanted in the single crystal silicon piece so as to divide the hydrogen ion from the single crystal silicon piece, and at the heating process in the process for increasing bonding force of the single crystal silicon piece to the substrate, the substrate is warped downward in a convex direction and a force exerted when the single crystal silicon piece is stripped from the end portion is identical to a direction in which the substrate is warped. Thus, the single crystal silicon piece is not stripped. As a result, it is possible to prevent the single crystal silicon thin film from being divided from the substrate, or breakage of the substrate.

0450Further, the SOI substrate according to the present invention may be arranged such that the amorphous nonalkali glass substrate is any one of an alkaline earth-alumino boro-silicated glass, a barium-alumino boro-silicated glass, an alkaline earth-zinc-lead-alumino boro-silicated glass, and an alkaline earth-zinc-alumino boro-silicated glass.

0451With the foregoing configuration, it is possible to obtain a substrate whose coefficient of thermal expansion is as high as or higher than that of the single crystal silicon

0452Further, the SOI substrate according to the present invention may be arranged such that a bonded surface of the single crystal silicon piece is constituted of a (111) face, or a (110) face, or a (100) face.

0453With the foregoing configuration, by using a single crystal silicon piece having the foregoing crystal orientation, it is possible, in the same manner, to manufacture an SOI substrate, having a silicon film surface which is so flat that it is not necessary to grind the surface from the beginning.

0454Further, compared with the SOI substrate having the single crystal silicon piece which is most likely to be oriented to a (100) aspect, the SOI substrate of a (110) aspect is such that the largest number of atoms closest to each other are disposed on the (110) face. Thus, when the single crystal silicon piece is separated, the separated surface is extremely flattened, so that it is possible to reduce defective fraction of the silicon transistor formed on the SOI substrate.

0455Further, when the SOI substrate of a (111) aspect is used, the separated surface is identical to an easy to cleave surface of the single crystal silicon body, and the atoms closest to each other exist in an angle deviating a little from the (111) face. Thus, when the single crystal silicon piece is separated, the separated surface is extremely flattened, so that it is possible to reduce defective fraction of the silicon transistor formed on the SOI substrate.

0456Further, the manufacturing method of the SOI substrate according to the present invention may have such an arrangement that the heating process is performed at multi temperature steps ranging from not less than 300° C. to not more than 700° C.

0457With the foregoing configuration, by performing the heating process at multiple stages, it is possible to reduce stripping of the single crystal Si thin film. Particularly, by performing the two-stages heating process: a first heating process for enforcing the bond strength performed at a temperature at which the single crystal silicon piece is not separated from the application surface, and a second heating process for division, it is possible to reduce the number of inferior products in which a film is stripped of the bonded surface and the single crystal silicon piece itself is stripped after the heating process.

0458Further, the manufacturing method of the SOI substrate according to the present invention may have such an arrangement that a depth to which the hydrogen ions are implanted ranges from 40 nm to 200 nm.

0459With the foregoing configuration, as described, when the thickness of the single crystal silicon thin film, namely an implantation depth of the hydrogen ions, is thin such as 200 nm, it is possible to obtain a transistor that has been completely depleted, so that it is possible to improve the property largely, and to facilitate the process. While, when the thickness is less than 40 nm, the single crystal Si thin film becomes easy to break, so that the safety coefficient in manufacturing drops.

0460The semiconductor device according to the present invention may have such an arrangement that the insulating substrate is constituted of a high-strain-point glass, made of alkaline earth-alumino silicated-glass, which has a surface in which an SiO₂layer has been formed at least on an area containing single crystal Si.

0461With the foregoing configuration, since it is not necessary to use a crystallized glass whose composition has been adjusted, and the insulating substrate can be manufactured by using high-strain-point glass, which is generally used for such as an active matrix liquid crystal panel, it is possible to manufacture the semiconductor device at low cost.

0462The semiconductor device according to the present invention may have such an arrangement that the insulating substrate is made of any one of barium-alumino boro-silicated glass, alkaline earth-alumino boro-silicated glass, boro-silicated glass, alkaline earth-zinc-lead-alumino boro-silicated glass, and alkaline earth-zinc-alumino boro-silicated glass.

0463With the foregoing configuration, since the insulating substrate is manufactured by using the described high-strain-point glass, which is generally used for such as an active matrix liquid crystal panel, it is possible to manufacture the semiconductor device suitable for an active matrix substrate at low cost.

0464The semiconductor device according to the present invention may have such an arrangement that the semiconductor device is an active matrix substrate including an integrated circuit constituted of a plurality of MOSFETs, a bipolar transistor, or an SIT, that are provided on the insulating substrate.

0465With the foregoing configuration, since the semiconductor device is an active matrix substrate including integrated circuits each of which is made of a plurality of MOS (Metal Oxide Semiconductor) FETs on the insulating substrate, it is possible to obtain an active matrix substrate having the foregoing characteristic.

0466The semiconductor device according to the present invention may have such an arrangement that an area of the single crystal Si thin film formed on the insulating substrate is separated from an area of the polycrystalline Si thin film formed on the insulating substrate by not less than 0.3 μm.

0467The semiconductor device according to the present invention may have such an arrangement that an area of the single crystal Si thin film formed on the insulating substrate is separated from an area of the polycrystalline Si thin film formed on the insulating substrate by not less than 0.5 μm.

0468With the foregoing configuration, it is possible to prevent diffusion of metal atoms, such as Ni, Pt, Sn, and Pd, from the polycrystalline Si into the single crystal Si, thereby stabilizing the property of the semiconductor device.

0469The semiconductor device according to the present invention may have such an arrangement that transistors, identical to each other in terms of a conductivity type, that are respectively provided on the different areas, are different from each other in terms of at least any one of a mobility, a sub-threshold coefficient, and a threshold value.

0470With the foregoing configuration, since transistors, identical to each other in terms of a conductivity type, that are respectively provided on the different areas, are different from each other in at least any one of a mobility, a sub-threshold coefficient, and a threshold value, it is possible to provide those transistors on respective appropriate areas according to the required property.

0471The semiconductor device according to the present invention may have such an arrangement that integrated circuits respectively provided on the different areas are different from each other in terms of at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level.

0472With the foregoing configuration, since the integrated circuits respectively provided on the different areas are different from each other in at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level, it is possible to provide those integrated circuits on respective appropriate areas according to the required arrangement and property.

0473The semiconductor device according to the present invention may have such an arrangement that integrated circuits respectively provided on the different areas are different from each other in terms of a design rule.

0474With the foregoing configuration, since the integrated circuits respectively provided on the different areas are different from each other in a design rule, it is possible to provide those integrated circuits on respective appropriate areas according to the design rule.

0475In the semiconductor device according to the present invention, the thickness d of the single crystal Si thin film can be adjusted to be not more than the upper limit of 600 nm, even when the thickness d has a small value including variation of the maximum depletion length Wm, i.e., its impurity density is practical lower limit of 10¹⁵/cm⁻³. The impurity density is determined according to the amount of impurity Ni.

0476Here, Wm=[4∈skTln (Ni/ni) q²Ni]^1/2, where ni denotes intrinsic carrier density, k denotes Boltzmann constant, T denotes absolute temperature, ∈ s denotes dielectric constant of Si, q denotes electronic charge, and Ni denotes impurity density.

0477With the foregoing configuration, since a thickness of the single crystal Si thin film is not more than 600 nm, it is possible to further reduce S value (sub-threshold coefficient) of the semiconductor device and also to reduce OFF current.

0478The semiconductor device according to the present invention may have such an arrangement that a thickness of the single crystal Si thin film is approximately not more than 100 nm.

0479With the foregoing configuration, it is possible to further reduce S value (sub-threshold coefficient) of the semiconductor device and also to reduce OFF current.

0480The semiconductor device according to the present invention may have such an arrangement that the heating process is performed at a single temperature step or multi temperature steps which ranges from not less than 300° C. to not more than 650° C.

0481With the foregoing method, since the heating process is performed at a single temperature step, it is possible to carry out the heating process at a single step.

0482The semiconductor device according to the present invention may have such an arrangement that at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film upon growing the polycrystalline Si layer.

0483With the foregoing method, since at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film upon growing the polycrystalline Si layer before heating, it is possible to promote crystal growth of the polycrystalline Si layer. Thus, a mobility of the polycrystalline Si layer can be increased, thereby having an advantage at the forming of driving circuit etc.

0484The semiconductor device according to the present invention may have such an arrangement that the step of dividing the single crystal Si substrate at the hydrogen ion implantation portion in the cleaving manner is performed by raising a temperature of the hydrogen ion implantation portion of the single crystal Si substrate to a temperature, at or above which hydrogen dissociates from Si, in accordance with laser irradiation.

0485With the foregoing method, since a temperature of a hydrogen ion implanted layer of the single crystal Si substrate is raised by laser irradiation, it is possible to raise temperature only with respect to a small range of area, thereby suppressing damage of the single crystal Si.

0486The semiconductor device according to the present invention may have such an arrangement that the single crystal Si substrate is divided at the hydrogen ion implantation portion in the cleaving manner by performing tamp anneal including a peak temperature of approximately not less than 700° C.

0487With the foregoing method, since the single crystal Si substrate is divided at the hydrogen ion implantation portion in the cleaving manner by performing lamp anneal (Rapid Thermal Anneal) including a peak temperature of approximately not less than 700° C., it is possible to further improve the bond strength, and also to improve the property of transistor due to recovery of the exfoliation interface and inside of the single crystal Si thin film, which have been damaged by the hydrogen ion implantation. Note that, the property of the transistor is improved with the increase of the peak temperature of the lamp anneal; however, the increase of the peak temperature also increases bending and expansion/contraction of the substrate. Thus, the temperature and holding time should be appropriately set according to the size of substrate and/or the type of the device.

0488The method for manufacturing the semiconductor device according to the present invention may further includes the steps of: removing a damaged layer from a surface of the single crystal Si thin film by isotropic plasma etching or wet etching; patterning the polycrystalline Si thin film and the single crystal Si thin film in island shapes by etching; etching-back partially or entirely a first SiO₂film, that has been deposited on entire surfaces of the polycrystalline Si thin film and the single crystal Si thin film, by anisotropic etching; and depositing an SiO₂film so as to form a gate insulating film, wherein the steps are performed after the polycrystalline Si thin film and the single crystal Si thin film have been provided on the insulating substrate.

0489With the foregoing method, a typical polysilicon TFT forming step is performed, so that it is possible to manufacture a TFT having the foregoing mobility by using the conventional steps.

0490The method for manufacturing the semiconductor device according to the present invention may further includes the steps of: removing a damaged layer from a surface of the single crystal Si thin film by isotropic plasma etching or wet etching; patterning the polycrystalline Si thin film and the single crystal Si thin film in island shapes by etching; applying a resin flattening film to an entire surface of the SiO₂film for etching back that has been deposited on entire surfaces of the polycrystalline Si thin film and the single crystal Si thin film; etching-back entirely the resin flattening film and partially the SiO₂film for etching back, by anisotropic etching; and depositing the SiO₂film so as to form a gate insulating film, wherein the steps are performed after the polycrystalline Si thin film and the single crystal Si thin film have been provided on the insulating substrate.

0491With the foregoing method, an oxide film (SiO₂film) is left in a valley-shaped portion between the polycrystalline Si thin film and the single crystal Si thin film pattern, thereby entirely flattening the substrate.

0492The semiconductor device according to the present invention may further includes the steps of: forming a MOS transistor by patterning the single crystal Si thin film and the polycrystalline Si thin film, that have been formed on the insulating substrate, in island shapes, in accordance with etching; and implanting P⁺ ions of not less than 10¹⁵/cm²and not more than 5×10¹⁵/cm²into at least each part of a source area and a drain area of an N type MOS transistor and each part of a source area and a drain area of a P type MOS transistor.

0493With the foregoing method, since implantation of P⁺ ions of not less than 10¹⁵/cm²and not more than 5×10¹⁵/cm²is performed into at least each part of a source area and a drain area of an N type MOS transistor and each part of a source area and a drain area of a P type MOS transistor, it is possible to obtain a TFT in which its property non-uniformity is little and its property is stable by performing a heating process in accordance with RTA, laser, and a furnace etc., and also performing gettering of metal atoms with respect not only to the polycrystalline Si thin film area, but also to the single crystal Si thin film area.

0494The semiconductor device according to the present invention may have such an arrangement that a thickness of the single crystal Si thin film is substantially equal to a thickness of the polycrystalline Si thin film.

0495With the foregoing method, it is possible to perform almost all the following processes at the same time including the step of etching performed to form the island shape, and to enable forming of a transistor or a circuit in which a large step is not brought about. Thus, in case of a liquid crystal panel for example, it is possible to obtain an advantage in controlling a cell thickness.

0496The semiconductor device according to the present invention may have such an arrangement that a thickness of the SiO₂film formed by oxidizing a surface of the single crystal Si substrate in advance or depositing the SiO₂film on the surface is not less than 200 nm.

0497Generally, as the SiO₂film is thicker, the non-uniformity of the threshold is further reduced, but a suitable value is approximately 200 nm to 400 nm in terms of (a) an efficiency of a forming process of the SiO₂film (time taken to oxidize) and (b) trade off with respect to differences. In a case where the non-uniformity is focused on, the suitable value is approximately 400 nm, and in a case where the differences and the efficiency are focused on, the suitable value is approximately 200 nm to 400 nm, more preferably, 250 nm to 350 nm. When the SiO₂thin film is thick, stability of operation particularly at a low voltage is improved. This is based on the following reason: the foregoing arrangement reduces influence of a fixed charge that is caused by (a) a contamination on an interface between the single crystal Si substrate and a glass substrate that are bonded to each other, or (b) deformation and incompleteness of a lattice.

0498Accordingly, with the foregoing method, it is possible to obtain a semiconductor substrate having appropriate balance between non-uniformity of the threshold, and the differences and the efficiency of the forming process of the SiO₂thin film.

0499The semiconductor device according to the present invention may have such an arrangement that a maximum size of the single crystal Si thin film is not more than 10 cm.

0500With the foregoing method, by having the single crystal Si thin film of which maximum size is not more than 10 cm, it is possible to prevent breakage such as cracking, or stripping of the Si even when high-strain-point glass is adopted, which is generally used for an active matrix liquid crystal display panel etc. and having greater thermal expansion rate difference with respect to the single crystal Si than that of quartz glass. Note that, the maximum size of the single crystal Si thin film signifies a greatest size among each outline length of the surface of the single crystal Si thin film having low thickness. For example, it signifies its diameter when the single crystal Si thin film has a disc shape, and it signifies the length of the diagonal line of upper surface rectangle when the single crystal Si thin film is a thin rectangular solid.

0501The semiconductor device according to the present invention may have such an arrangement that a maximum size of the single crystal Si thin film is not more than 5 cm.

0502With the foregoing method, by having the single crystal Si thin film of which maximum size is not more than 5 cm, it is possible to prevent breakage such as cracking, or stripping of the Si even when high-strain-point glass is adopted, which is generally used for an active matrix liquid crystal display panel etc. and having greater thermal expansion rate difference with respect to the single crystal Si than that of quartz glass.

0503The semiconductor device according to the present invention may have such an arrangement that a difference between the insulating substrate and the single crystal Si thin film in terms of a normalized linear expansion is not more than approximately 250 ppm at a temperature ranging from a room temperature to not more than 600° C.

0504With the foregoing method, a difference between the insulating substrate and the single crystal Si thin film is small in terms of the linear expansion coefficient. Thus, in the step of forming the single crystal Si thin film on the insulating substrate, it is possible to prevent (a) damages and exfoliation of the bonded surface that are brought about by the difference in terms of the thermal expansion coefficient when the single crystal Si thin film is divided at a hydrogen ion implantation portion in a cleaving manner, or (b) deficiency in the crystal. Further, it is possible to improve the thermal bond strength.

0505The method for manufacturing the semiconductor device may have such an arrangement that a dose amount of the hydrogen ions implanted into the hydrogen ion implantation portion is not less than 10¹⁶/cm², or is approximately 3×10¹⁶/cm².

0506With the foregoing method, it is possible to improve the mobility etc. of the TFT formed in the area of the single crystal Si thin film.

0507The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art intended to be included within the scope of the following claims.