Bus system, bus slave and bus control method

BACKGROUND OF THE INVENTION

p-00021. Field of the Invention

p-0003The present invention relates to a bus system and, particularly, to a technique of controlling a wait operation of a bus master.

p-00042. Description of Related Art

p-0005Various methods for improving the performance of computers have been introduced. Pipelining is used as a technique to improve the performance by executing a plurality of instruction processing in parallel. Specifically, one instruction processing is broken into two or more stages so that each stage of a plurality of instructions can be processed in parallel.

p-0006In a bus system using the pipeline, an access from a bus master such as a processor and a DMAC (Direct Memory Access Controller) to a resource of a bus slave is also composed of a plurality of stages. <figref idrefs="DRAWINGS">FIG. 6</figref> shows an example of the stages of processing that a bus master performs reading (loading) from a register of a bus slave. A bus master is described as a CPU by way of illustration.

p-0007As shown in the example of <figref idrefs="DRAWINGS">FIG. 6</figref>, the processing that a CPU executes the instruction of loading data from a bus slave is composed of six stages: IF, ID, EX, DF, CM and WB. These stages are: a stage to fetch an instruction into a CPU, a stage to decode the instruction, a stage to execute the instruction (in this example, to send a data loading request as an access request to a bus slave), a stage to obtain an operation result (in this example, to receive a response from a bus slave), a stage to complete the execution, and a stage to write back or to update a resource such as a register of the CPU, respectively.

p-0008A bus slave is not always able to perform the processing in response to an access request from a bus master. Thus, in the DF stage to obtain a response from a bus slave, the CPU can receive a ready response indicating that a bus slave is ready to process a request or a wait response indicating that it is not ready. If the CPU receives the wait response, it suspends the execution of an instruction until the stage of the bus slave becomes ready.

p-0009In addition to the above two responses, a bus slave can send a response indicating the occurrence of an exception. If the exception is detected in the CM stage to complete the execution, a CPU interrupts the processing prior to the CM stage and performs the exception handling. The processing is not interrupted in the WB stage to perform write-back because the execution of an instruction is fixed in this stage.

p-0010The CPU operation after receiving the wait response until the state of the bus slave becomes ready is either a non-blocking wait operation or a blocking wait operation. These two operations are described hereinafter in detail with reference to <figref idrefs="DRAWINGS">FIGS. 7 and 8</figref>.

p-0011In the non-blocking wait operation, the execution of an instruction for which a wait response is made is suspended until the wait is released, and other instructions subsequent to this instruction are executed without being suspended. <figref idrefs="DRAWINGS">FIG. 7</figref> shows a case where the wait response is received in the DF stage of the instructions <b>1</b> and <b>4</b> out of the instructions <b>1</b> to <b>5</b>, and the CPU performs the non-blocking wait operation in response thereto. For simplification of the description, the non-blocking wait operation and the blocking wait operation are also referred to hereinafter simply as non-blocking operation and blocking operation, respectively.

p-0012The charts A, B, C and D in <figref idrefs="DRAWINGS">FIG. 7</figref> show the timing for a CPU to execute each stage of the instructions <b>1</b> to <b>5</b>, the timing of signals related to an access request output from the CPU in the EX stage of the instructions <b>1</b> and <b>4</b>, the timing for the CPU to retrieve data when a ready response is sent from a bus slave or an exception (exp) occurs in the DF stage of the instructions <b>1</b> and <b>4</b>, and the timing of a response from a bus slave in the DF stage of the instructions <b>1</b> and <b>4</b>, respectively. In these charts, the first stage (IF) in the instruction <b>1</b> is shown as the first cycle. Each timing in the charts B, C and D corresponds to each cycle shown in the chart A.

p-0013As shown in the chart A of <figref idrefs="DRAWINGS">FIG. 7</figref>, the CPU executes the EX stage of the instruction <b>1</b> in the third cycle and sends an access request to a bus slave. The access request contains a signal REQ to request processing to a the bus slave, an address ADS to be accessed, and a content CMD of the processing requested to the bus slave, which is loading for a load instruction, as shown in the chart B of <figref idrefs="DRAWINGS">FIG. 7</figref>. In the boxes of REQ in the chart B, the High-level line indicates that a REQ signal is active.

p-0014The bus slave responds to the access request in the EX stage of the instruction <b>1</b> where the REQ signal in the chart B is active. In this example, the bus slave sends a wait response (WAIT) in the fourth and fifth cycles and then sends a ready response (RDY) in the sixth cycle (cf. the chart D). The CPU suspends the execution of the instruction and then retrieves data D<b>0</b> from the bus slave in the sixth cycle in response to the ready response (cf. the chart C). After that, the CPU carries out the CM stage to complete the execution and the WB stage to write-back, thereby ending the instruction <b>1</b>.

p-0015The execution of the instructions <b>2</b> and <b>3</b> is started with a delay of one cycle each from the start of the execution of the instruction <b>1</b> (the first cycle). As shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, while the wait response is made in the DF stage of the instruction <b>1</b> (the fourth and fifth cycles), the EX stage and the DF stage of the instruction <b>2</b> and the ID stage and the EX stage of the instruction <b>3</b> are executed. Because the CPU performs the non-blocking operation when the wait response is made in the DF stage of the instruction <b>1</b>, the subsequent instructions <b>2</b> and <b>3</b> are executed.

p-0016This is the same for the instructions <b>4</b> and <b>5</b>, and the IF stage and the ID stage of the instruction <b>4</b> and the IF stage of the instruction <b>5</b> are executed in the fourth and fifth cycles.

p-0017For the instruction <b>4</b>, the CPU sends an access request (cf. the chart B) to a bus slave in the EX stage of the sixth cycle and receives a wait response (cf. the chart D) in DF stage of the seventh and eighth cycles. Then, an exception response (cf. EXP in the chart D) is sent from the bus slave in the ninth cycle. Although the CPU retrieves the data D<b>1</b> from the bus slave at the same time as receiving the exception response, it performs the exception handling for “abnormal completion due to an exception” in the CM stage of the tenth cycle. In such a case, the WB stage of the instruction <b>4</b> is not executed as shown in the chart A, and no write-back of the data D<b>1</b> which is retrieved in the ninth cycle is performed in the WB stage of the eleventh cycle.

p-0018In the DF stage of the instruction <b>4</b>, because the CPU performs the non-blocking operation, the stage of the subsequent instruction <b>5</b> is executed in the seventh and eighth cycles where a wait response is made.

p-0019As described above, if the CPU performs the non-blocking operation, the subsequent instruction is executed, which contributes to higher processing performance of the entire processing system.

p-0020However, if exception handling occurs by the execution of the instruction <b>4</b> as shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, the execution of the subsequent instruction <b>5</b> is completed already when the exception handling is completed in the tenth cycle. Accordingly, if the instruction <b>4</b> is executed again, the instruction <b>5</b> is executed twice. Thus, if the CPU performs the non-blocking operation, the reexecution of the instruction <b>4</b> where an exception occurs is difficult.

p-0021On the other hand, in the blocking wait operation, the execution of the instruction for which a wait response is made is suspended until the wait is released, and other instructions subsequent to that instruction are also suspended. <figref idrefs="DRAWINGS">FIG. 8</figref> shows a case where the wait response is made in the DF stage of the instructions <b>1</b> and <b>4</b> out of the instructions <b>1</b> to <b>5</b>, and the CPU performs the blocking operation in response thereto.

p-0022The charts A, B, C and D in <figref idrefs="DRAWINGS">FIG. 8</figref> are the timing charts when the CPU executes each stage of the instructions <b>1</b> to <b>5</b>, the contents of a request which is output from the CPU in the EX stage of the instructions <b>1</b> and <b>4</b>, data that is retrieved by the CPU when the bus slave becomes ready or exception (exp) in the DF stage of the instructions <b>1</b> and <b>4</b>, and a response from the bus slave in the DF stage of the instructions <b>1</b> and <b>4</b>, respectively.

p-0023A bus slave responds to the access request in the EX stage of the instruction <b>1</b>. In this example, like the example in <figref idrefs="DRAWINGS">FIG. 7</figref>, the bus slave sends a wait response in the fourth and fifth cycles and then sends a ready response (RDY in the chart D) in the sixth cycle. The CPU suspends the execution of the instruction and then retrieves data D<b>0</b> from the bus slave in the sixth cycle in response to the ready response (cf. the chart C). After that, the CPU carries out the CM stage for completion and the WB stage for write-back in the seventh and eighth cycles, respectively, thereby ending the instruction <b>1</b>.

p-0024The execution of the instructions <b>2</b> and <b>3</b> is started with a delay of one cycle each from the start of the execution of the instruction <b>1</b> (the first cycle). As shown in <figref idrefs="DRAWINGS">FIG. 8</figref>, while the wait response is made in the DF stage of the instruction <b>1</b> (the fourth and fifth cycles), the EX stage of the instruction <b>2</b> and the ID stage of the instruction <b>3</b> are also suspended without being executed. Because the CPU performs the blocking operation in the fourth and fifth cycles until the wait is released in the DF stage of the instruction <b>1</b>, the subsequent instructions <b>2</b> and <b>3</b> are also suspended.

p-0025This is the same for the instruction <b>4</b>, and the IF stage is suspended in the fourth and fifth cycles.

p-0026For the instruction <b>4</b>, the CPU sends an access request (cf. the chart B) to a bus slave in the EX stage of the eighth cycle and receives a wait response (cf. the chart D) in DF stage of the ninth and tenth cycles. Then, an exception response (cf. the chart D) is sent from the bus slave in the eleventh cycle. Although the CPU retrieves the data D<b>1</b> at the same time as receiving the exception response, it performs the exception handling for “abnormal completion due to an exception” in the CM stage of the twelfth cycle. In such a case, the WB stage of the instruction <b>4</b> is not executed as shown in the chart A.

p-0027In the DF stage of the instruction <b>4</b>, because the CPU performs the blocking operation, the EX stage of the subsequent instruction <b>5</b> is suspended until the wait is released in the ninth and tenth cycles where a wait response is made.

p-0028As described above, if the CPU performs the blocking operation, the subsequent instruction is not executed, which results in lower processing performance of the entire processing system compared with the case where the CPU performs the non-blocking operation.

p-0029However, if exception handling occurs as in the instruction <b>4</b> of the example shown in <figref idrefs="DRAWINGS">FIG. 8</figref>, the execution of the subsequent instruction <b>5</b> is not yet completed when the exception handling is completed in the twelfth cycle. Therefore, even if the instruction <b>4</b> is reexecuted, the instruction <b>5</b> is not executed twice. Thus, if the CPU performs the blocking operation, it is possible to reexecute the instruction where an exception occurs.

p-0030As described above, there are both advantages and disadvantages when a CPU performs the blocking operation or the non-blocking operation upon receiving a wait response.

p-0031A known technique to determine whether a CPU performs the blocking operation or the non-blocking operation, which is referred to hereinafter as a first technique, is as follows.

p-0032As shown in <figref idrefs="DRAWINGS">FIG. 9</figref>, according to this technique, an address space of a bus master is divided into an address space for blocking operation (which is referred to hereinafter as a blocking operation space) and an address space for non-blocking operation (hereinafter as a non-blocking operation space). The bus master performs the blocking operation for an access to a bus slave which is connected with the blocking operation space and performs the non-blocking operation for an access to a bus slave which is connected with the non-blocking operation space. Because the bus slave illustrated in <figref idrefs="DRAWINGS">FIG. 9</figref> is connected with the blocking operation space of the bus master, the bus master performs the blocking operation when accessing a resource, which is a register in the example of <figref idrefs="DRAWINGS">FIG. 9</figref>, of the bus slave.

p-0033Another technique, which is referred to hereinafter as a second technique, is disclosed in Japanese Unexamined Patent Application Publication No. 04-372018. According to this technique, a flag indicating whether or not to accept a wait signal is set in an instruction structure of a processor. Upon receiving a wait signal during the pipeline operation, a flag in the instruction structure corresponding to the wait signal is referred. If it is the instruction which accepts a wait signal, the next cycle is executed without waiting for the completion of the current cycle. If it is the instruction which does not accept a wait signal, the next cycle is executed after the completion of the current cycle.

p-0034We have now discovered that one bus slave does not always have one resource only. Further, not all of a plurality of resources of one bus slave always require the blocking operation. For example, if only the register D out of the four registers A to D of the bus slave shown in <figref idrefs="DRAWINGS">FIG. 9</figref> requires the blocking operation, it is necessary to connect the bus slave to the blocking operation space of the bus master in spite that the other three registers do not require the blocking operation according to the first technique described above. As a result, the bus master carries out the blocking operation when accessing the other three registers also, which decreases the performance of the system as a whole.

p-0035We have also discovered that the second technique divides the instruction of the bus master into the blocking operation instruction and the non-blocking operation instruction in essential. The bus master refers to a flag which is set in an instruction to indicate whether the instruction is a blocking instruction or a non-blocking instruction and performs the blocking operation when executing the blocking instruction and performs the non-blocking operation when executing the non-blocking instruction.

p-0036Because this technique sets a flag indicating whether an instruction is a blocking instruction or a non-blocking instruction into the instruction structure to be executed by a bus master to thereby determine if the bus master performs the blocking operation or the non-blocking operation, it is necessary to rewrite program codes in order to switch the two operations. Thus, it costs for the operation to find a switching point to rewrite program codes and also costs for the operation to check the occurrence of degradation due to a change to the program codes. For these reasons, it is necessary to modify program codes for the switching of the blocking operation and the non-blocking operation of a bus master, which hinders the dynamic switching.

SUMMARY

p-0037In one embodiment, there is provided a bus system to execute pipeline processing. The bus system includes a bus slave, a bus master to output an access request to the bus slave, and a response unit to output a wait response to cause the bus master to perform a wait operation in response to the access request. As the wait response, the response unit outputs either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation to the bus master.

p-0038In another embodiment, there is provided a bus control method. The method outputs, as a wait response in response to an access request to a resource of a bus slave from a bus master, either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation in a bus system to execute pipeline processing.

p-0039In still another embodiment, there is provided a bus slave in a bus system to execute pipeline processing. The bus slave includes one or more resources and a response unit that is capable of outputting, in response to an access request to one of the resources from a bus master, a wait response that is either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation.

p-0040A bus system and a bus system control method of the present invention are effective in controlling whether a bus master performs a blocking operation or a non-blocking operation.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0041The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

p-0042<figref idrefs="DRAWINGS">FIG. 1</figref> is a block diagram showing the configuration of a bus system according to an embodiment of the present invention;

p-0043<figref idrefs="DRAWINGS">FIG. 2</figref> is a view showing a detail of the connection between a bus master and a bus slave in the bus system shown in <figref idrefs="DRAWINGS">FIG. 1</figref>;

p-0044<figref idrefs="DRAWINGS">FIG. 3</figref> is a block diagram showing the configuration of a bus slave in the bus system shown in <figref idrefs="DRAWINGS">FIG. 1</figref>;

p-0045<figref idrefs="DRAWINGS">FIG. 4</figref> is a flowchart showing the process in the bus slave <b>50</b> shown in <figref idrefs="DRAWINGS">FIG. 3</figref>;

p-0046<figref idrefs="DRAWINGS">FIG. 5</figref> is a view to describe a detail of the processing performed in the bus system shown in <figref idrefs="DRAWINGS">FIG. 1</figref>;

p-0047<figref idrefs="DRAWINGS">FIG. 6</figref> is a view to describe a pipeline processing;

p-0048<figref idrefs="DRAWINGS">FIG. 7</figref> is a view to describe a non-blocking wait operation:

p-0049<figref idrefs="DRAWINGS">FIG. 8</figref> is a view to describe a blocking wait operation; and

p-0050<figref idrefs="DRAWINGS">FIG. 9</figref> is a view to describe a technique according to a related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

p-0051The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

p-0052An exemplary embodiment of the present invention is described hereinafter with reference to the drawings.

p-0053<figref idrefs="DRAWINGS">FIG. 1</figref> shows a bus system <b>100</b> according to a first embodiment of the present invention. The bus system <b>100</b> includes bus masters <b>10</b>, <b>20</b>, . . . , a bus <b>30</b>, and bus slaves <b>50</b>, <b>60</b>, . . . . The bus masters <b>10</b>, <b>20</b>, . . . and the bus slaves <b>50</b>, <b>60</b>, . . . are connected to be communicable with each other through the bus <b>30</b>.

p-0054The bus masters <b>10</b>, <b>20</b>, . . . are the units which are capable of accessing a resource of a bus slave, such as CPU and DMAC. The bus slaves <b>50</b>, <b>60</b>, . . . are the units which are capable of receiving an access request to its resource from a bus master and sending a response thereto, such as I/O device. The DMAC may serve as both a bus master and a bus slave. Alternatively, some CPU may serve as a bus slave in the bus system where a plurality of CPUs are connected. Although <figref idrefs="DRAWINGS">FIG. 1</figref> illustrates two bus masters, <b>10</b> and <b>20</b>, and two bus slaves, <b>50</b> and <b>60</b>, the number of bus masters and bus slaves may be any arbitrary number or one of above.

p-0055The bus system <b>100</b> is described hereinafter with the bus master <b>10</b> and the bus slave <b>50</b> taken as examples.

p-0056<figref idrefs="DRAWINGS">FIG. 2</figref> shows a detail of the connection between the bus master <b>10</b> and the bus slave <b>50</b>. The bus <b>30</b> includes a control signal line <b>31</b>, an address line <b>32</b>, a command line <b>33</b>, a data line <b>34</b>, and a response signal line <b>35</b>. In the following description, the case where the bus master <b>10</b> accesses the bus slave <b>50</b> for the execution of a load instruction is described by way of illustration.

p-0057The bus master <b>10</b> sends a request signal REQ to request processing to the bus slave <b>50</b> through the control signal line <b>31</b>. When sending the request signal, it also sends an address ADS and a command CMD (which is a load command in this example) indicating the contents of the processing requested to the bus slave through the address line <b>32</b> and the command line <b>33</b>, respectively.

p-0058The bus slave <b>50</b> receives the request signal REQ through the control signal line <b>31</b> and obtains the address ADS and the command CMD through the address line <b>32</b> and the command line <b>33</b>, respectively. The bus slave <b>50</b> decodes the obtained address ADS and determines whether it is the address of a resource of its own. If it is the address of a resource of its own, the bus slave <b>50</b> sends a response RESP through the response signal line <b>35</b>.

p-0059The response RESP which is sent from the bus slave <b>50</b> is either a ready (RDY) response indicating that the bus slave <b>50</b> is ready to perform the requested processing or a wait response indicating that it is not ready. In this embodiment, the wait response from the bus slave <b>50</b> further falls into two types, which are described in detail later.

p-0060The bus slave <b>50</b> executes the requested command CMD when it is in the RDY state. Because the command CMD is a load command in this example, the bus slave <b>50</b> loads data DAT at the address which is designated by the address ADS and outputs it through the data line <b>34</b>.

p-0061When the bus master <b>10</b> receives the RDY response from the bus slave <b>50</b> through the response signal line <b>35</b>, it retrieves the data DAT which is output from the bus slave <b>50</b> through the data line <b>34</b>.

p-0062The operation when the bus master <b>10</b> receives the wait response through the response signal line <b>35</b> is described later in conjunction with the detail of the bus slave <b>50</b>.

p-0063<figref idrefs="DRAWINGS">FIG. 3</figref> shows the configuration of the bus slave <b>50</b>. The bus slave <b>50</b> includes an address decoder <b>52</b>, a response unit <b>54</b>, and a register group <b>58</b>. The response unit <b>54</b> includes a response generator <b>55</b> and a controller <b>56</b>. The signals REQ ADS and CMD in <figref idrefs="DRAWINGS">FIG. 3</figref> are input from a corresponding signal line of the bus <b>30</b> shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, which is the control signal line <b>31</b>, the address line <b>32</b>, and the command line <b>33</b>. The signals DAT and RESP are output to the corresponding data line <b>34</b> and the response signal line <b>35</b> of the bus <b>30</b> shown in <figref idrefs="DRAWINGS">FIG. 2</figref>.

p-0064<figref idrefs="DRAWINGS">FIG. 4</figref> is a flowchart showing the operation when the bus slave <b>50</b> receives a request signal REQ from the bus master <b>10</b>.

p-0065The address decoder <b>52</b> decodes the address ADS which is sent with the request signal REQ from the bus master <b>10</b>, determines if the address indicates a resource of the bus slave <b>50</b> to which it belongs, and outputs the determination result to the response unit <b>54</b> (S<b>10</b>, S<b>20</b>).

p-0066In the example of <figref idrefs="DRAWINGS">FIG. 3</figref>, the bus slave <b>50</b> includes the register group <b>58</b> that includes a plurality of registers, which serve as resources of the bus slave <b>50</b>.

p-0067The response generator <b>55</b> of the response unit <b>54</b> ends the process if the signal from the address decoder <b>52</b> does not indicate an access request to the resource of its own (No in S<b>20</b>). If, on the other hand, the signal from the address decoder <b>52</b> indicates an access request to the resource of its own, the response generator <b>55</b> receives the request signal REQ, the address ADS and the command CMD and checks the type of the register corresponding to the address ADS (Yes in S<b>20</b>, S<b>30</b>).

p-0068There are two types of registers; one is a register which requires the blocking wait operation and the other is a register which does not require the blocking wait operation.

p-0069A technique for the response generator <b>55</b> to check the type of a register may be any mechanism as long as it can determine whether a register requires the blocking wait operation or not. For example, a table which correlates a register with whether the register requires the blocking wait operation may be prepared, so that the response generator <b>55</b> can make a decision by referring to the table. Alternatively, when an address contains 16 bits, the low-order 4 bits may be used to indicate whether a register requires the blocking wait operation, so that the response generator <b>55</b> make a decision by referring to the low-order 4 bits of the address which is sent from the address decoder <b>52</b>.

p-0070The response generator <b>55</b> outputs a check result in the step S<b>30</b>, which is information indicating the type of a register to which an access is requested, the address ADS and the command CMD to the controller <b>56</b> (Yes in S<b>20</b>, S<b>30</b>, S<b>40</b>).

p-0071The controller <b>56</b> determines if the requested processing is executable (S<b>50</b>). The determination is made by referring to a counter (not shown) indicating the number of commands which are currently processed. If the requested processing is executable (Yes in S<b>50</b>), the controller <b>56</b> outputs a RDY response indicating that the processing is executable through the response signal line <b>35</b> and executes the requested processing on the relevant register (S<b>60</b>). For example, if CMD is a load command, the controller <b>56</b> loads data from the relevant register and, upon completing the data loading, outputs a signal indicating the processing completion to the bus master <b>10</b>. The controller <b>56</b> outputs the loaded data to the data line <b>34</b> and also outputs a RDY response to the response signal line <b>35</b>.

p-0072The bus master <b>10</b> retrieves data from the data line <b>34</b> in response to the RDY response from the controller <b>56</b> of the bus slave <b>50</b>. Upon receiving the signal indicating the processing completion, the bus master <b>100</b> performs the execution completion process and write-back to its own resource and thereby ends the instruction.

p-0073On the other hand, if the requested processing is not executable (No in S<b>50</b>), the controller <b>56</b> sends a blocking wait response or a non-blocking wait response to the bus master <b>10</b> according to the type of a resource sent from the response generator <b>55</b>. Specifically, if the register to which an access request is made is a register that requires the blocking wait operation, the controller <b>56</b> sends a blocking wait response (Yes in S<b>70</b>, S<b>80</b>). If, on the other hand, the register to which an access request is made is a register that does not require the blocking wait operation, the controller <b>56</b> sends a non-blocking wait response (No in S<b>70</b>, S<b>90</b>).

p-0074The bus master <b>10</b> performs the blocking wait operation when it receives the blocking wait response and performs the non-blocking wait operation when it receives the non-blocking wait response.

p-0075Although it is not shown in the flowchart of <figref idrefs="DRAWINGS">FIG. 4</figref>, if an exception occurs during the execution of the requested processing, the bus slave <b>50</b> sends an exception response (exp) indicating abnormal completion to the bus master <b>10</b>. When the bus master <b>10</b> receives the exception response, it does not carry out write-back to its own resource in order to perform the exception processing even though it obtains the data which is retrieved during the execution of the processing by the bus slave <b>50</b> prior to the exception response.

p-0076<figref idrefs="DRAWINGS">FIG. 5</figref> shows a detailed example of the processing which is performed in the bus system <b>100</b> shown in <figref idrefs="DRAWINGS">FIG. 1</figref>.

p-0077The charts A, B, C and D in <figref idrefs="DRAWINGS">FIG. 5</figref> are the timing charts when the bus master <b>10</b> executes each stage of the instructions <b>1</b> to <b>5</b>, the contents of a request which is sent from the bus master <b>10</b> in the EX stage of the instructions <b>1</b> and <b>4</b>, data that is retrieved by the bus master <b>10</b> when the bus slave <b>50</b> becomes ready in the DF stage of the instructions <b>1</b> and <b>4</b>, and a response from the bus slave <b>50</b> in the DF stage of the instructions <b>1</b> and <b>4</b>, respectively.

p-0078The bus slave <b>50</b> responds to the access request in the EX stage of the instruction <b>1</b>. In this example, like the examples in <figref idrefs="DRAWINGS">FIGS. 7 and 8</figref>, the bus slave <b>50</b> sends a wait response in the fourth and fifth cycles and then sends a ready response in the sixth cycle. As an example, consider the case where the bus slave <b>50</b> sends the non-blocking (NBW) response. Receiving the NBW response, the bus master <b>10</b> suspends the execution of the instruction and then retrieves data D<b>0</b> from the bus slave <b>50</b> in the sixth cycle in response to the ready response (cf. the chart C). After that, the bus master <b>10</b> executes the CM stage for completion and the WB stage for write-back in the seventh and eighth cycles respectively, thereby ending the instruction <b>1</b>.

p-0079The execution of the instructions <b>2</b> and <b>3</b> is started with a delay of one cycle each from the start of the execution of the instruction <b>1</b> (the first cycle). As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, while the non-blocking wait response is made in the DF stage of the instruction <b>1</b> (the fourth and fifth cycles), the EX stage and the DF stage of the instruction <b>2</b> and the ID stage and the EX stage of the instruction <b>3</b> are executed. Because the bus master <b>10</b> performs the non-blocking operation, the subsequent instructions <b>2</b> and <b>3</b> are executed in the fourth and fifth cycles when the wait response (NBW in this case) is made in the DF stage of the instruction <b>1</b>.

p-0080This is the same for the instruction <b>4</b>, and the IF stage and the ID stage are executed in the fourth and fifth cycles.

p-0081For the instruction <b>4</b>, the bus master <b>10</b> sends an access request (cf. the chart B) to the bus slave <b>50</b> in the EX stage of the sixth cycle and receives a wait response (cf. the chart D) in DF stage of the seventh and eighth cycles. Consider the case where the blocking wait operation (BLW) is sent as an example. As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, because the bus master <b>10</b> performs the blocking operation in the seventh and eighth cycles in response to BLW, the EX stage of the instruction <b>5</b> is suspended.

p-0082After that, the wait response to the instruction <b>4</b> is released in the ninth cycle, and the bus master <b>10</b> retrieves the data D<b>1</b> from the bus slave <b>50</b>. With the release of the wait response, the EX stage of the instruction <b>5</b> is also executed.

p-0083As described above, the bus system <b>100</b> of this embodiment checks if each register of the register group <b>58</b> of the bus slave <b>50</b> is a register which requires the blocking wait operation or not and, only when the register requires the blocking wait operation, it sends a wait response to make the bus slave <b>50</b> perform the blocking wait operation. It is thereby possible to minimize the blocking wait operation of the bus master <b>10</b> in the bus system <b>100</b>, which enhances higher performance of the bus system <b>100</b>.

p-0084Further, the bus system <b>100</b> of this embodiment causes the bus master to perform the blocking wait operation or the non-blocking wait operation by sending a blocking wait response or a non-blocking wait response. It is thereby possible to switch the operation of the bus master without rewriting the program of the bus master. This has a large advantage in program debugging.

p-0085In the process of debugging a program, a certain instruction may be reexecuted for checking in some cases. Therefore, the reexecution of an instruction is sometimes necessary even for a bus slave which does not require the blocking wait operation in actual use. To implement this, a bit indicating whether an exception of a bus slave is enabled or disabled may be used, so that the blocking wait response or the non-blocking wait response is sent as a wait response according to the value of this bit. For example, the blocking wait response is sent when a bus slave is in the state to enable an exception, and the non-blocking wait response is sent when a bus slave is in the state to disable an exception. Then, a bit value is set such that a bus slave is in the state to enable an exception during debugging of a program, thereby causing a bus master to perform the blocking wait operation. This permits the reexecution of an instruction in the event of an exception during debugging. On the other hand, a bit value is set such that a bus slave is in the state to disable an exception during actual use, thereby causing a bus master to perform the non-blocking wait operation. This achieves higher performance of the bus system during actual use.

p-0086An exemplary embodiment of the present invention is described in the foregoing. The embodiment is given by way of illustration only, and various changes and modifications may be made without departing from the scope of the present invention. All such changes and modifications as would be obvious to those skilled in the art are intended for inclusion within the scope of the present invention.

p-0087For example, although the response unit <b>54</b> is placed inside each bus slave in the bus system <b>100</b> of the above-described embodiment, the response unit <b>54</b> or part of the response unit <b>54</b> may be placed outside a bus slave, or a single response unit or part of a response unit may be placed in common among a plurality of bus slaves. When using a response unit which is common among a plurality of bus slaves, the response unit may include a table which correlates each register of each bus slave with its type (whether it requires the blocking wait operation or not), so that the response unit determines if each register of a plurality of bus slaves requires the blocking wait operation by referring to the table and then sends a blocking wait response or a non-blocking wait response according to the determination result.

p-0088Further, although the address decoder <b>52</b> is placed inside each bus slave in the bus system <b>100</b> of the above-described embodiment, the address decoder <b>52</b> may be placed outside a bus slave, or an address decoder may be placed in common among a plurality of bus slaves. When using an address decoder which is common among a plurality of bus slaves, a table which correlates an address with a bus slave to which a register corresponding to the address belongs may be placed, so that the address decoder outputs a selection signal to a bus slave to which a register corresponding to an address designated by an access request from a bus master belongs to indicate that the bus slave is designated by referring to the table.

p-0089Furthermore, although a wait response is sent in the next cycle of the request signal REQ, and the bus master <b>10</b> suspends the execution in the DF stage which is subsequent to the EX stage where the request signal REQ is issued in the example of <figref idrefs="DRAWINGS">FIG. 5</figref> for easy implementation and high-speed processing, a system may be configured to send a wait response during the cycle where the request signal REQ is issued.

p-0090It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.