Semiconductor device having metal lines with slits

CROSS-REFERENCE TO RELATED APPLICATIONS

0001The present application is a continuation-in-part of pending application Ser. No. 11/806,562, filed on Jun. 1, 2007, which is a continuation application based on Ser. No. 10/885,971, filed Jul. 8, 2004, now U.S. Pat. No. 7,233,070 B2, which in turn is a divisional application based on Ser. No. 10/035,247, filed Jan. 4, 2002, now U.S. Pat. No. 6,777,806 B2, which claims the priority of Korean Patent Application No. 10-2001-8480, filed Feb. 20, 2001, in the Korean Intellectual Property Office. The disclosures of all of the above applications are hereby incorporated herein in their entirety by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003Embodiments relate to a semiconductor device and a method of manufacturing the same. More specifically, embodiments are directed to the techniques which may prevent a crack from occurring in the layers underlying a metal line layer using slits in the metal lines or a space between adjacent metal line layers.

00042. Description of the Related Art

0005Semiconductor devices generally have a multi-layered structure. When manufacturing such semiconductor devices having a multi-layered structure, only a metal line pattern is inspected, but stresses that are applied to, for example, an insulation layer beneath the metal layer are not considered. Such stresses (e.g., a thermal stress) may cause cracks in a (the) layer(s) underlying the metal layer, for example, the insulation layer. As a result, characteristics of a semiconductor device may deteriorate.

0006<figref idref="DRAWINGS">FIG. 1</figref> illustrates a schematic cross-sectional view of a conventional semiconductor device having a multi-layered structure. The semiconductor memory device includes a first insulation layer <b>12</b>, a resistive layer <b>13</b>, a second insulation layer <b>14</b>, a barrier layer <b>15</b>, and a metal line layer <b>16</b>, which are sequentially formed on a substrate <b>11</b>.

0007In the semiconductor device having such a multi-layered structure of <figref idref="DRAWINGS">FIG. 1</figref>, when a subsequent annealing process is performed after forming the metal line layer <b>16</b>, the stress structure is changed. In other words, due to a thermal stress, the stress direction in one or more of the layers <b>13</b> to <b>16</b> is changed as shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>. <figref idref="DRAWINGS">FIG. 2A</figref> illustrates a cross-sectional view of a stress direction before an annealing process is performed, and <figref idref="DRAWINGS">FIG. 2B</figref> illustrates a cross-sectional view of a stress direction in underlying layers after an annealing process is performed. In <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>, the arrows denote the stress direction.

0008As the direction of a stress is changed, the stress is accumulated and, thus, a crack <b>17</b> may occur in a portion of the second insulation layer <b>14</b> corresponding to a gap in the metal line layer <b>16</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>. <figref idref="DRAWINGS">FIGS. 4A to 4D</figref> are photographs illustrating cracks that occur due to a stress in the conventional semiconductor device. Furthermore, when a crack is deepened, as shown in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, the resistive layer <b>13</b> may be destroyed, thereby causing a low reliability. <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are photographs illustrating a crack that occurs in the resistive layer <b>13</b>.

0009Japanese Patent Publication No. 10-84059 describes a technique that relaxes the concentration of stress on the peripheral edge of a metal board to prevent an underlying ceramic board from deteriorating in mechanical strength and to protect it against cracking. In this technique a groove is provided inside the peripheral edge of one of the surfaces of the metal plate whose other surface is bonded to a high-thermal conductivity silicon nitride board (ceramic board).

0010U.S. Pat. No. 5,229,642 describes a technique that forms slits or rows of small holes in corner portions of a guard ring to prevent a passivation film on the guard ring from being cracked by stresses caused by a resin mold package concentrating in the four corners of the semiconductor substrate.

0011However, the prior art as described above does not suggest a technique that prevents a crack from occurring in one or more layers underlying the metal line layer due to the size of the metal line or a gap between two adjacent metal line layers.

SUMMARY OF THE INVENTION

0012Embodiments of the present invention are directed to a semiconductor device, which overcome one or more of the problems associated with the related art.

0013It is a feature of an embodiment to provide a semiconductor device that reduces or prevents a crack from occurring in a (the) layer(s) underlying a metal line layer.

0014It is another feature of an embodiment to provide a semiconductor device that may be highly reliable and readily manufacturable.

0015At least one of the above and other features of an embodiment may be realized by providing semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.

0016The space may be less than about 10 μm. The slits may be less than about 4 μm away from the space. The slits may be parallel to the space.

0017The integrated circuit may include at least one of a memory device, a logic device and a embedded memory logic device, and wherein at least one of the first and second metal line patterns is a ground line or a power supply line.

0018The integrated circuit may include the memory device, and the memory device may be one of a static random access memory (SRAM) device, a flash memory device and a phase change memory device.

0019The integrated circuit may include the SRAM device, and the SRAM device may include a CMOS SRAM cell including a pair of driver transistors, a pair of load transistors and a pair of transfer transistors, and wherein the first metal line pattern is electrically connected to source regions of the pair of driver transistors and the second metal line pattern is electrically connected to source regions of the pair of load transistors. The integrated circuit may include the flash memory device, and the flash memory device may include a NAND string including a ground selection transistor, a plurality of cell transistors and a string selection transistor which are serially connected to one another, and wherein the first metal line pattern is electrically connected to a source region of the ground selection transistor. The NAND string may correspond to a lower NAND string, and the semiconductor device may include an upper NAND string stacked over the lower NAND string, wherein the first metal line pattern is electrically connected to the upper NAND string.

0020The integrated circuit includes the logic device, and the logic device may include an N-channel MOS transistor having an N-type source region and an N-type drain region formed in the semiconductor substrate, and a P-channel MOS transistor having a P-type source region and a P-type drain region formed in the semiconductor substrate, wherein the first metal line pattern is electrically connected to the N-type source region of the N-channel MOS transistor, and the second metal line pattern is electrically connected to the P-type source region of the P-channel MOS transistor.

0021At least one of the above and other features of an embodiment may be realized by providing a semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, first and second metal line patterns on the insulation layer, the first and second metal line patterns being parallel and spaced apart from each other, each of the first and second metal line patterns having at least one slit, and a third metal line pattern on the insulation layer, the third metal line pattern being perpendicular to the first and second metal line pattern, the third metal line pattern having at least one slit.

0022The third metal line pattern may be adjacent to the second metal line pattern and opposite to the first metal line pattern, and wherein the third metal line pattern is spaced apart from the second metal line pattern. The third metal line pattern may be spaced less than about 1 μm apart from the second metal line pattern.

0023The third metal line pattern is connected to the second metal line pattern and opposite to the first metal line pattern.

0024The integrated circuit may include at least one of a memory device, a logic device and a embedded memory logic device, and wherein at least one of the first and second metal line patterns is a ground line or a power supply line.

0025The integrated circuit may include the memory device, and the memory device may be one of a static random access memory (SRAM) device, a flash memory device and a phase change memory device.

0026The integrated circuit may include the SRAM device, and the SRAM device may include a CMOS SRAM cell including a pair of driver transistors, a pair of load transistors and a pair of transfer transistors, and wherein the first metal line pattern is electrically connected to source regions of the pair of driver transistors and the second metal line pattern is electrically connected to source regions of the pair of load transistors.

0027The integrated circuit may include the flash memory, and the flash memory device may include a NAND string including a ground selection transistor, a plurality of cell transistors and a string selection transistor which are serially connected to one another, and wherein the first metal line pattern is electrically connected to a source region of the ground selection transistor. The NAND string may correspond to a lower NAND string, and the semiconductor device further may include an upper NAND string stacked over the lower NAND string, wherein the first metal line pattern is electrically connected to the upper NAND string.

0028The integrated circuit may include the logic device, and the logic device may include an N-channel MOS transistor having an N-type source region and an N-type drain region formed in the semiconductor substrate, and a P-channel MOS transistor having a P-type source region and a P-type drain region formed in the semiconductor substrate, wherein the first metal line pattern is electrically connected to the N-type source region of the N-channel MOS transistor, and the second metal line pattern is electrically connected to the P-type source region of the P-channel MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

0029The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

0030<figref idref="DRAWINGS">FIG. 1</figref> illustrates a schematic cross-sectional view of a conventional semiconductor device having a multi-layered structure according to the prior art;

0031<figref idref="DRAWINGS">FIG. 2A</figref> illustrates a schematic cross-sectional view of the direction of a stress before an annealing process is performed according to the prior art;

0032<figref idref="DRAWINGS">FIG. 2B</figref> illustrates a schematic cross-sectional view of the direction of a stress after an annealing process is performed according to the prior art;

0033<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are SEM micrographs illustrating a crack that occurs in the resistive layer;

0034<figref idref="DRAWINGS">FIGS. 4A to 4D</figref> are SEM micrographs illustrating cracks that occur due to a stress in the conventional semiconductor device;

0035<figref idref="DRAWINGS">FIG. 5</figref> is a SEM micrograph illustrating a front surface of a semiconductor device according to a first preferred embodiment of the present invention;

0036<figref idref="DRAWINGS">FIG. 6</figref> is a SEM micrograph illustrating an occurrence of a crack due to a width of a space between the metal line patterns;

0037<figref idref="DRAWINGS">FIG. 7</figref> is a SEM micrograph illustrating a front surface of the semiconductor device having metal line patterns according to the first preferred embodiment of the present invention;

0038<figref idref="DRAWINGS">FIGS. 8 to 10</figref> are SEM micrographs illustrating a background art related to the second preferred embodiment of the present invention;

0039<figref idref="DRAWINGS">FIG. 11</figref> is a SEM micrograph illustrating another background art related to the second preferred embodiment of the present invention;

0040<figref idref="DRAWINGS">FIG. 12</figref> is a SEM micrograph illustrating a front surface of a semiconductor device according to the second preferred embodiment of the present invention;

0041<figref idref="DRAWINGS">FIG. 13</figref> illustrates slits further from the space between the metal lines;

0042<figref idref="DRAWINGS">FIG. 14</figref> is a SEM micrograph illustrating the slits formed to prevent a crack from occurring according to the second preferred embodiment of the present invention;

0043<figref idref="DRAWINGS">FIG. 15</figref> is a SEM micrograph illustrating a conventional semiconductor device having a crack;

0044<figref idref="DRAWINGS">FIG. 16</figref> is a SEM micrograph illustrating a semiconductor device having no cracks according to the preferred embodiments of the present invention;

0045<figref idref="DRAWINGS">FIG. 17</figref> illustrates a plan view of metal line patterns according to another embodiment of the present invention;

0046<figref idref="DRAWINGS">FIG. 18</figref> illustrates a plan view of metal line patterns according to still another embodiment of the present invention;

0047<figref idref="DRAWINGS">FIG. 19</figref> illustrates a plan view of an exemplary semiconductor device having metal line patterns according to embodiments of the present invention;

0048<figref idref="DRAWINGS">FIG. 20</figref> illustrates an equivalent circuit diagram of a complementary metal-oxide-semiconductor static random access memory (CMOS SRAM) cell employed in a CMOS SRAM device;

0049<figref idref="DRAWINGS">FIG. 21</figref> illustrates a perspective view of a portion of a CMOS SRAM cell having metal line patterns according to embodiments of the present invention;

0050<figref idref="DRAWINGS">FIG. 22</figref> illustrates a perspective view of a portion of another CMOS SRAM cell having metal line patterns according to embodiments of the present invention;

0051<figref idref="DRAWINGS">FIG. 23</figref> illustrates a perspective view of a portion of a cell array region of a flash memory device having metal line patterns according to embodiments of the present invention; and

0052<figref idref="DRAWINGS">FIG. 24</figref> illustrates a perspective view of a portion of a logic device having metal line patterns according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0053The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

0054In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

0055<figref idref="DRAWINGS">FIG. 5</figref> is a SEM micrograph illustrating the front surface of a semiconductor device according to a first preferred embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, two adjacent metal line patterns <b>41</b> and <b>42</b> are spaced apart from each other, and two adjacent metal line patterns <b>42</b> and <b>43</b> are spaced apart from each other. A space between the two adjacent metal line patterns <b>41</b> and <b>42</b> has a width W<b>11</b>, and a space between the two adjacent metal line patterns <b>42</b> and <b>43</b> has a width W<b>12</b>. The metal line patterns <b>41</b> to <b>43</b> may have a relatively large surface area size of, e.g., greater than 30 μm×30 μm. This is because, if the metal line patterns <b>41</b> to <b>43</b> have a relatively small surface area size of, e.g., less than 30 μm×30 μm, few cracks may occur in one or more layers underlying the metal line layer, e.g., the insulating layer. However, the surface area size of the metal line patterns is not limited to the above value in the present invention.

0056Even though not shown, the semiconductor device of <figref idref="DRAWINGS">FIG. 5</figref> may have a multi-layered structure. For example, as in <figref idref="DRAWINGS">FIG. 1</figref>, the semiconductor memory device includes a first insulation layer, a resistive layer, a second insulation layer, a barrier layer, and a metal line layer, which are sequentially formed in this order on a substrate.

0057The widths W<b>11</b> and W<b>12</b> are sufficiently wide to prevent a crack from occurring in one or more layers underlying the metal line patterns. Preferably, the widths W<b>11</b> and W<b>12</b> are greater than 1.0 μm. To accommodate a high stress resulting from a process parameter, it is more preferable that the widths W<b>11</b> and W<b>12</b> are at least 1.5 μm. However, if the widths W<b>11</b> and W<b>12</b> are very wide, the integration level of the semiconductor device is lowered, and thus it is undesirable that the widths W<b>11</b> and W<b>12</b> are very wide.

0058<figref idref="DRAWINGS">FIG. 6</figref> is a SEM micrograph illustrating an occurrence of a crack due to a width of the space between the metal line patterns. In <figref idref="DRAWINGS">FIG. 6</figref>, the black portion denotes a space between two adjacent metal line patterns <b>51</b> and <b>52</b>. A width W<b>21</b> of the space is 0.75 μm, and a width W<b>22</b> of the space is 1.31 μm. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, a crack occurs not in a portion of one or more layers (e.g., the insulating layer) underlying the metal layers which correspond to the width W<b>22</b>, but in one or more layers underlying the metal layers which correspond to the width W<b>21</b>.

0059<figref idref="DRAWINGS">FIG. 7</figref> is a SEM micrograph illustrating a front surface of a semiconductor device having an alternate metal line pattern according to a first preferred embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, the metal line patterns <b>63</b> and <b>64</b> have a bent space therebetween. As described above, it is preferred that a space between two adjacent metal line patterns <b>61</b> and <b>62</b> or <b>62</b> and <b>63</b> is at least 1.0 μm in width. However, if the bent space between the metal line patterns <b>63</b> and <b>64</b> is 1.0 μm, a crack is likely to occur in one or more layers underlying the metal line layer. Therefore, if a space between two metal line patterns has one or more bent portions or one or more step portions, it is preferable that the width of the bent space is greater than 1.5 μm.

0060Meanwhile, it is difficult to form a space having a width of greater than 1.0 μm or 1.5 μm between two adjacent metal line patterns and still achieve high integration. In order to solve such a problem, a second preferred embodiment of the present invention forms a slit at a distance of within, preferably, 4.0 μm from a space between two adjacent metal line patterns.

0061<figref idref="DRAWINGS">FIGS. 8 to 10</figref> provide the background art related to the second preferred embodiment of the present invention. <figref idref="DRAWINGS">FIG. 8</figref> is a SEM micrograph illustrating a portion of a conventional semiconductor device, and <figref idref="DRAWINGS">FIG. 9</figref> is an enlarged view illustrating a portion D of <figref idref="DRAWINGS">FIG. 8</figref>. <figref idref="DRAWINGS">FIG. 10</figref> is a SEM micrograph illustrating a progressive state of a crack for an area size of the metal line patterns and a space width between the metal line patterns. In <figref idref="DRAWINGS">FIGS. 8 to 10</figref>, reference numerals <b>32</b> to <b>36</b> denote metal line patterns, and black lines denote spaces between the two adjacent metal line patterns. In <figref idref="DRAWINGS">FIG. 8</figref>, a portion defined by a dotted line denotes a region where a crack occurs.

0062Referring to <figref idref="DRAWINGS">FIGS. 8 and 9</figref>, a crack does not occur in a portion of a space SP<b>1</b> corresponding to the metal line patterns <b>36</b>, whereas a crack does occur in a portion of the space SP<b>1</b> between the metal line patterns <b>33</b> and <b>35</b>. At this point, the generated crack stops at a position P<b>1</b>. This is because the growth of a crack is hindered by a space SP<b>2</b> between a portion <b>35</b><i>a </i>of the metal line pattern <b>35</b> and an upper portion of the metal line pattern <b>34</b>.

0063For more detail, as shown in <figref idref="DRAWINGS">FIG. 10</figref>, a crack does not occur in a portion A of the space SP<b>1</b> having a width of 1.43 μm, but a crack occurs in portion B of the space SP<b>1</b> having a width of 0.8 μm. The crack that occurs in a portion B of the space SP<b>1</b> goes through a portion C of the space SP<b>1</b> having a width of 1.43 μm, and then stops at a position P<b>1</b> before a portion D of the space SP<b>1</b> having a width of 0.72 μm. The reason for this is that the space SP<b>2</b> serves to stop growth of a crack. That is, it is understood that if a slit is formed that exposes a layer underlying the metal layer, e.g., the insulation layer, a crack no longer occurs.

0064<figref idref="DRAWINGS">FIG. 11</figref> provides further background art related to the second preferred embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 11</figref>, a metal line pattern P<b>1</b> is interposed between metal line patterns having a relatively large surface area size, while a metal line pattern P<b>2</b> is interposed between metal line patterns having a relatively small surface area size. Spaces SP<b>3</b> and SP<b>4</b> have a width of 0.7 μm. Even though the space SP<b>4</b> has a width of 0.7 μm, which is less than 1.0 μm, since the metal line pattern P<b>2</b> is interposed between the long slim metal line patterns that are formed to be parallel to each other, a crack does not occur in the space SP<b>4</b>. On the other hand, since the metal line pattern P<b>1</b> is interposed between the metal line patterns having a relatively large surface area, a crack occurs in the space SP<b>3</b>. In other words, since a space SP<b>5</b> serves as a slit that prevents a crack from occurring, a crack does not occur in one or more of the layers underlying the metal line pattern that correspond to the space SP<b>4</b>. It is understood that the slit has to be formed parallel to the space between the metal line patterns in order to prevent a crack from occurring.

0065<figref idref="DRAWINGS">FIG. 12</figref> is a SEM micrograph illustrating a front surface of a semiconductor device according to the second preferred embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 12</figref>, a space SP<b>6</b> between metal line patterns <b>71</b> and <b>72</b> and a space SP<b>7</b> between metal line patterns <b>72</b> and <b>73</b> are straight, whereas a space between two adjacent metal line patterns <b>73</b> and <b>74</b> is bent. The spaces SP<b>6</b> to SP<b>8</b> between two adjacent metal line patterns <b>71</b> and <b>72</b>, <b>72</b> and <b>73</b>, and <b>73</b> and <b>74</b>, respectively have a width of less than 1.0 μm to achieve high integration. The metal line patterns <b>71</b> to <b>74</b> have a relatively large surface area size of, e.g., greater than 30 μm×30 μm. However, the surface area size of the metal line patterns is not limited to this value in the present invention.

0066In order to prevent a crack from occurring in one or more layers underlying the metal line layer, slits SL are formed at a predetermined distance from the space between the metal line patterns, and the slits SL are arranged in a direction parallel to the space between the metal line patterns. Preferably, the slit SL has a width of greater than 1.0 μm. The distances d<b>1</b> and d<b>2</b> between the slit SL and the corresponding space between the metal line patterns have a maximum value of, preferably, 4.0 μm. The length of the slit SL is selected such that the metal line patterns are not broken. In the case of the space SP<b>8</b> that is bent, it is preferred that the slits SL are formed to correspond to straight portions of the bent space SP<b>8</b>. In other words, the slits SL are formed at a location adjacent to any portion of the space having a possibility to cause a crack.

0067A process of forming the slit in the metal line pattern according to the second preferred embodiment of the present invention does not require an additional mask process. The slit may be formed by patterning a portion of the metal line layer adjacent to the space between two adjacent metal line patterns concurrently with patterning the metal line layer.

0068<figref idref="DRAWINGS">FIG. 13</figref> shows slits that are further from the space between the metal line patterns than 4.0 μm, e.g., about 10 μm.

0069<figref idref="DRAWINGS">FIG. 14</figref> is a SEM micrograph illustrating the slits formed to prevent a crack from occurring according to the second preferred embodiment of the present invention.

0070<figref idref="DRAWINGS">FIG. 15</figref> is a SEM micrograph illustrating a conventional semiconductor device having a crack, and <figref idref="DRAWINGS">FIG. 16</figref> is a SEM micrograph illustrating the semiconductor device having no cracks according to the preferred embodiments of the present invention.

0071<figref idref="DRAWINGS">FIG. 17</figref> illustrates a plan view of a pair of adjacent metal line patterns according to another embodiment of the present invention. Although the present embodiment is described in conjunction with two adjacent metal line patterns as shown in <figref idref="DRAWINGS">FIG. 17</figref>, the present embodiment is equally applicable to three or more adjacent metal line patterns.

0072Referring to <figref idref="DRAWINGS">FIG. 17</figref>, first and second metal line patterns <b>102</b> and <b>104</b> may be disposed on an underlying layer <b>101</b>, e.g., an insulating layer. That is, the first and second metal line patterns <b>102</b> and <b>104</b> may be disposed on a same level. The first and second metal line patterns <b>102</b> and <b>104</b> may be separated from each other by a space S′. The space S′ has a width WS′ and the width WS′ may have a single value. Alternatively, the width WS′ may have two or more different values along the length direction of the metal line patterns <b>102</b> and <b>104</b>. The first metal line pattern <b>102</b> may include a first inner wall <b>102</b>W′ facing the space S′ and a first outer wall <b>102</b>W″ opposite the first inner wall <b>102</b>W′. Similarly, the second metal line pattern <b>104</b> may include a second inner wall <b>104</b>W′ facing the space S′ and a second outer wall <b>104</b>W″ opposite the second inner wall <b>104</b>W′.

0073The first metal line pattern <b>102</b> may have a plurality of first slits therein, and the second metal line pattern <b>104</b> may have a plurality of second slits therein. In more detail, the first slits may include first inner slits <b>102</b>S′ disposed adjacent to the first inner wall <b>102</b>W′ and first outer slits <b>102</b>S″ adjacent to the first outer wall <b>102</b>W″. The first inner slits <b>102</b>S′ may be disposed to be parallel with the space S′, and each of the first inner slits <b>102</b>S′ may be separated from the first inner wall <b>102</b>S′ by a first inner distance <b>102</b>DT′. In addition, the first outer slits <b>102</b>S″ may be disposed to be parallel with the space S′, and each of the first outer slits <b>102</b>S″ may be separated from the first outer wall <b>102</b>W″ by a first outer distance <b>102</b>DT″. The first inner distance <b>102</b>DT′ may be equal to the first outer distance <b>102</b>DT″. Alternatively, the first inner distance <b>102</b>DT′ may be different from the first outer distance <b>102</b>DT″. For example, the first inner distance <b>102</b>DT′ may be less than the first outer distance <b>102</b>DT″. Furthermore, the first inner slits <b>102</b>S′ may face the first outer slits <b>102</b>S″, respectively. In other words, one of the first inner slits <b>102</b>S′ and the first outer slit <b>102</b>S″ adjacent thereto may be disposed to have center points which are located on a straight line STL crossing the first and second metal line patterns <b>102</b> and <b>104</b>.

0074Similarly, the second slits may include second inner slits <b>104</b>S′ disposed adjacent to the second inner wall <b>104</b>W′ and second outer slits <b>104</b>S″ adjacent to the second outer wall <b>104</b>W″. The second inner slits <b>104</b>S′ may be disposed to be parallel with the space S′, and each of the second inner slits <b>104</b>S′ may be separated from the second inner wall <b>104</b>S′ by a second inner distance <b>104</b>DT′. In addition, the second outer slits <b>104</b>S″ may be disposed to be parallel with the space S′, and each of the second outer slits <b>104</b>S″ may be separated from the second outer wall <b>104</b>W″ by a second outer distance <b>104</b>DT″. The second inner distance <b>104</b>DT′ may be equal to the second outer distance <b>104</b>DT″. Alternatively, the second inner distance <b>104</b>DT′ may be different from the second outer distance <b>104</b>DT″. For example, the second inner distance <b>104</b>DT′ may be less than the second outer distance <b>104</b>DT″. Furthermore, the second inner slits <b>104</b>S′ may face the second outer slits <b>104</b>S″, respectively. In other words, one of the second inner slits <b>104</b>S′ and the second outer slit <b>104</b>S″ adjacent thereto may be disposed to have center points which are located on the straight line STL. As a result, the first inner slits <b>102</b>S′ may be disposed to face the second inner slits <b>104</b>S′, respectively.

0075<figref idref="DRAWINGS">FIG. 18</figref> illustrates a plan view of a pair of adjacent metal line patterns according to still another embodiment of the present invention. Although the present embodiment is described in conjunction with two adjacent metal line patterns as shown in <figref idref="DRAWINGS">FIG. 18</figref>, the present embodiment is also applicable to three or more adjacent metal line patterns.

0076Referring to <figref idref="DRAWINGS">FIG. 18</figref>, first and second metal line patterns <b>106</b> and <b>108</b> may be disposed on an underlying layer <b>105</b>, e.g., an insulating layer. That is, the first and second metal line patterns <b>106</b> and <b>108</b> may be disposed on a same level. The first and second metal line patterns <b>106</b> and <b>108</b> may be separated from each other by a space S″. The space S″ has a width WS″ and the width WS″ may have a single value. Alternatively, the width WS″ may have two or more different values along the length direction of the metal line patterns <b>106</b> and <b>108</b>.

0077The first metal line pattern <b>106</b> may include a first inner wall <b>106</b>W′ facing the space S″ and a first outer wall <b>106</b>W″ opposite the first inner wall <b>106</b>W′. Similarly, the second metal line pattern <b>108</b> may include a second inner wall <b>108</b>W′ facing the space S″ and a second outer wall <b>108</b>W″ opposite the second inner wall <b>108</b>W′.

0078The first metal line pattern <b>106</b> may have a plurality of first slits therein, and the second metal line pattern <b>104</b> may have a plurality of second slits therein. In more detail, the first slits may include odd-numbered first slits <b>106</b>S′ and even-numbered first slits <b>106</b>S″ disposed between the odd-numbered first slits <b>106</b>S′. The odd-numbered first slits <b>106</b>S′ may be disposed adjacent to the first inner wall <b>106</b>W′, and the even-numbered first slits <b>106</b>S″ may be disposed adjacent to the first outer wall <b>106</b>W″. The first slits <b>106</b>S′ and <b>106</b>S″ may be parallel to the space S″. Further, each of the odd-numbered first slits <b>106</b>S′ may be separated from the first inner wall <b>106</b>W′ by a first inner distance <b>106</b>DT′, and each of the even-numbered first slits <b>106</b>S″ may be separated from the first outer wall <b>106</b>W″ by a first outer distance <b>106</b>DT″. Accordingly, all of the first slits <b>106</b>S′ and <b>106</b>S″ may not be located on a single straight line which is parallel to the space S″. The first inner distance <b>106</b>DT′ may be equal to or different from the first outer distance <b>106</b>DT″ as described with reference to <figref idref="DRAWINGS">FIG. 17</figref>.

0079Similarly, the second slits may include odd-numbered second slits <b>108</b>S″ and even-numbered second slits <b>108</b>S′ disposed between the odd-numbered second slits <b>108</b>S″. The odd-numbered second slits <b>108</b>S″ may be disposed adjacent to the second outer wall <b>108</b>W″, and the even-numbered second slits <b>108</b>S′ may be disposed adjacent to the second inner wall <b>108</b>W′. The second slits <b>108</b>S′ and <b>108</b>S″ may be parallel to the space S″. Further, each of the odd-numbered second slits <b>108</b>S″ may be separated from the second outer wall <b>108</b>W″ by a second outer distance <b>108</b>DT″, and each of the even-numbered second slits <b>108</b>S′ may be separated from the second inner wall <b>108</b>W′ by a second inner distance <b>108</b>DT′. Accordingly, all of the second slits <b>108</b>S′ and <b>108</b>S″ may not be located on a single straight line which is parallel to the space S″. The second inner distance <b>108</b>DT′ may be equal to or different from the second outer distance <b>108</b>DT″ as described with reference to <figref idref="DRAWINGS">FIG. 17</figref>.

0080In the aforementioned embodiments, the widths W<b>11</b>, W<b>12</b>, W<b>21</b>, W<b>22</b>, W<b>31</b>, W<b>32</b>, WS′ and WS″ of the spaces between the metal line patterns may be appropriately designed according to the process conditions for forming the metal line patterns and the underlying layer below the metal line patterns. Further, the distances d<b>1</b>, d<b>2</b>, <b>102</b>DT′, <b>102</b>DT″, <b>104</b>DT′, <b>104</b>DT″, <b>106</b>DT′, <b>106</b>DT″, <b>108</b>DT′ and <b>108</b>DT″ may also be appropriately designed according to the process conditions for forming the metal line patterns and the underlying layer below the metal line patterns. For example, even though some embodiments describe that the slits in the metal line patterns prevent the cracks from occurring in the underlying insulation layer when the space between the metal line patterns is less than about 1.5 μm, the space is not limited to the above value of about 1.5 μm. For example, slits may be provided in metal line patterns to prevent the cracks from occurring in the underlying insulation layer even when the space between the metal line patterns is greater than about 1.5 μm. This is because the stress applied to the underlying insulation layer may be changed according to the process conditions for forming the metal line patterns or the underlying insulation layer. The process conditions may include various factors such as thickness of the metal line patterns, material of the metal line patterns, material of the underlying insulation layer, and deposition techniques of the metal line patterns and the underlying insulation layer.

0081Similarly, even though some embodiments describe that the distance between the space and slit is preferably less than 4 μm to prevent the cracks from occurring in the underlying insulation layer when the space between the metal line patterns is less than about 1.5 μm, the distance is not limited to the above value of about 4 μm. For example, the distance may be greater than about 4 μm according to the process conditions for forming the metal line patterns and the underlying layer below the metal line patterns even when the space between the metal line patterns is less than about 1.5 μm.

0082The embodiments described above may be applicable to various semiconductor devices including integrated circuits. For example, the above embodiments of the present invention may be applicable to a volatile memory device such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device, a non-volatile memory device such as a flash memory device, a non-memory device (e.g., a logic device) such as an application specific integrated circuit (ASIC) device, or an embedded memory logic (EML) device including volatile memory cells or non-volatile memory cells.

0083<figref idref="DRAWINGS">FIG. 19</figref> illustrates a plan view of an exemplary semiconductor device to which the metal line patterns according to the embodiments shown in <figref idref="DRAWINGS">FIGS. 17 and 18</figref> may be applied. However, it will be apparent to those skilled in the art that the other metal line patterns according to the embodiments shown in <figref idref="DRAWINGS">FIGS. 5</figref>, <b>6</b>, <b>7</b>, <b>12</b>, <b>13</b> and <b>14</b> may also be applicable to the semiconductor device of <figref idref="DRAWINGS">FIG. 19</figref>.

0084Referring to <figref idref="DRAWINGS">FIG. 19</figref>, the semiconductor device <b>100</b> may include a first region <b>100</b>A and a second region <b>100</b>B surrounding the first region <b>100</b>A. In the event that the semiconductor device <b>100</b> is a memory device, the first region <b>100</b>A may correspond to a cell array region and the second region <b>100</b>B may correspond to a peripheral circuit region. Alternatively, when the semiconductor device <b>100</b> is a non-memory device, the first region <b>100</b>A may correspond to a logic cell array region including logic gates, e.g., inverters, NAND gates or NOR gates, and the second region <b>100</b>B may correspond to a peripheral circuit region including data input/output circuits.

0085The metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref> or the metal line patterns <b>106</b> and <b>108</b> shown in <figref idref="DRAWINGS">FIG. 18</figref> may be disposed in at least one of the first and second regions <b>100</b>A and <b>100</b>B, as shown in <figref idref="DRAWINGS">FIG. 19</figref>.

0086In an exemplary embodiment, the metal line patterns <b>102</b> and <b>104</b> may be employed in the SRAM device including a CMOS SRAM cell shown in <figref idref="DRAWINGS">FIG. 20</figref>. However, it will be apparent to those skilled in the art that the metal line patterns according to the present invention may be applied to the other SRAM device including a load resistor SRAM cell that employs a pair of resistors as load devices.

0087<figref idref="DRAWINGS">FIG. 20</figref> illustrates an equivalent circuit diagram of a CMOS SRAM cell, e.g., a bulk CMOS SRAM cell or a thin film transistor (TFT) CMOS SRAM cell. The bulk CMOS SRAM cell may include six bulk transistors formed at a semiconductor substrate, and the TFT CMOS SRAM cell may include at least two TFTs stacked over the semiconductor substrate.

0088Referring to <figref idref="DRAWINGS">FIG. 20</figref>, the CMOS SRAM cell may include a pair of driver transistors TD<b>1</b> and TD<b>2</b>, a pair of transfer transistors TT<b>1</b> and TT<b>2</b>, and a pair of load transistors TL<b>1</b> and TL<b>2</b>. The pair of driver transistors TD<b>1</b> and TD<b>2</b> and the pair of transfer transistors TT<b>1</b> and TT<b>2</b> may be N-channel MOS transistors, while the pair of load transistors TL<b>1</b> and TL<b>2</b> may be P-channel MOS transistors.

0089The first driver transistor TD<b>1</b> and the first transfer transistor TT<b>1</b> may be serially connected to each other. A source region of the first driver transistor TD<b>1</b> may be electrically connected to a ground line Vss, and a drain region of the first transfer transistor TT<b>1</b> may be electrically connected to a first bit line BL<b>1</b>. Similarly, the second driver transistor TD<b>2</b> and the second transfer transistor TT<b>2</b> may be serially connected to each other. A source region of the second driver transistor TD<b>2</b> may be electrically connected to the ground line Vss, and a drain region of the second transfer transistor TT<b>2</b> may be electrically connected to a second bit line BL<b>2</b>.

0090Source and drain regions of the first load transistor TL<b>1</b> may be electrically connected to a power supply line Vcc and a drain region of the first driver transistor TD<b>1</b>, respectively. Similarly, source and drain regions of the second load transistor TL<b>2</b> may be electrically connected to the power supply line Vcc and a drain region of the second driver transistor TD<b>2</b>, respectively. The drain region of the first load transistor TL<b>1</b>, the drain region of the first driver transistor TD<b>1</b> and the source region of the first transfer transistor TT<b>1</b> may constitute a first node N<b>1</b>. In addition, the drain region of the second load transistor TL<b>2</b>, the drain region of the second driver transistor TD<b>2</b> and the source region of the second transfer transistor TT<b>2</b> may constitute a second node N<b>2</b>. Gate electrodes of the first driver transistor TD<b>1</b> and the first load transistor TL<b>1</b> may be electrically connected to the second node N<b>2</b>, and gate electrodes of the second driver transistor TD<b>2</b> and the second load transistor TL<b>2</b> may be electrically connected to the first node N<b>1</b>. Further, gate electrodes of the first and second transfer transistors TT<b>1</b> and TT<b>2</b> may be electrically connected to a word line WL.

0091As shown in <figref idref="DRAWINGS">FIG. 20</figref>, the CMOS SRAM cell may be divided into two half cells, e.g., a first half cell HC<b>1</b> and a second half cell HC<b>2</b>. The first half cell HC<b>1</b> may include the first driver transistor TD<b>1</b>, the first load transistor TL<b>1</b> and the first transfer transistor TT<b>1</b>, and the second half cell HC<b>2</b> may include the second driver transistor TD<b>2</b>, the second load transistor TL<b>2</b> and the second transfer transistor TT<b>2</b>.

0092<figref idref="DRAWINGS">FIG. 21</figref> illustrates a perspective view of a portion of an exemplary bulk CMOS SRAM cell with a pair of metal line patterns according to the embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref>.

0093Referring to <figref idref="DRAWINGS">FIG. 21</figref>, a P-type well <b>123</b> and an N-type well <b>125</b> may be provided in a semiconductor substrate <b>121</b>. An isolation layer <b>127</b> may be disposed at a predetermined region of the semiconductor substrate <b>121</b> to define a first active region <b>127</b><i>a </i>in the P-type well <b>123</b> and a second active region <b>127</b><i>b </i>in the N-type well <b>125</b>. First to third N-type impurity regions <b>131</b><i>a</i>, <b>131</b><i>b </i>and <b>131</b><i>c </i>may be disposed in the first active region <b>127</b><i>a</i>. A first driver gate electrode <b>129</b><i>a </i>may be disposed over the first active region <b>127</b><i>a </i>between the first and third N-type impurity regions <b>131</b><i>a </i>and <b>131</b><i>c</i>, and a second driver gate electrode <b>129</b><i>b </i>may be disposed over the first active region <b>127</b><i>a </i>between the second and third N-type impurity regions <b>131</b><i>b </i>and <b>131</b><i>c</i>. The first driver gate electrode <b>129</b><i>a</i>, the first N-type impurity region <b>131</b><i>a </i>and the third N-type impurity region <b>131</b><i>c </i>may act as the gate electrode, the drain region and the source region of the first driver transistor TD<b>1</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively. Similarly, the second driver gate electrode <b>129</b><i>b</i>, the second N-type impurity region <b>131</b><i>b </i>and the third N-type impurity region <b>131</b><i>c </i>may act as the gate electrode, the drain region and the source region of the second driver transistor TD<b>2</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively.

0094First to third P-type impurity regions <b>133</b><i>a</i>, <b>133</b><i>b </i>and <b>133</b><i>c </i>may be disposed in the second active region <b>127</b><i>b</i>. A first load gate electrode <b>129</b><i>c </i>may be disposed over the second active region <b>127</b><i>b </i>between the first and third P-type impurity regions <b>133</b><i>a </i>and <b>133</b><i>c</i>, and a second load gate electrode <b>129</b><i>d </i>may be disposed over the second active region <b>127</b><i>b </i>between the second and third P-type impurity regions <b>133</b><i>b </i>and <b>133</b><i>c</i>. The first load gate electrode <b>129</b><i>c</i>, the first P-type impurity region <b>133</b><i>a </i>and the third P-type impurity region <b>133</b><i>c </i>may act as the gate electrode, the drain region and the source region of the first load transistor TL<b>1</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively. Similarly, the second load gate electrode <b>129</b><i>d</i>, the second P-type impurity region <b>133</b><i>b </i>and the third P-type impurity region <b>133</b><i>c </i>may act as the gate electrode, the drain region and the source region of the second load transistor TL<b>2</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively.

0095The substrate having the driver transistors TD<b>1</b> and TD<b>2</b>, as well as the load transistors TL<b>1</b> and TL<b>2</b>, may be covered with a first insulation layer <b>135</b>. First and second pads <b>139</b><i>a </i>and <b>139</b><i>b </i>may be disposed on the first insulation layer <b>135</b>. The first pad <b>139</b><i>a </i>may be electrically connected to the third N-type impurity region <b>131</b><i>c </i>though a first pad contact plug <b>137</b><i>a </i>that penetrates the first insulation layer <b>135</b>, and the second pad <b>139</b><i>b </i>may be electrically connected to the third P-type impurity region <b>133</b><i>c </i>though a second pad contact plug <b>137</b><i>b </i>that penetrates the first insulation layer <b>135</b>. The first and second pads <b>139</b><i>a </i>and <b>139</b><i>b</i>, as well as the first insulation layer <b>135</b>, may be covered with a second insulation layer <b>141</b>.

0096The plurality of metal line patterns described in the above embodiments, for example, the first and second metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref> may be disposed on the second insulation layer <b>141</b>. The first metal line pattern <b>102</b> may be electrically connected to the first pad <b>139</b><i>a </i>through a first metal line contact plug <b>143</b><i>a </i>that penetrates the second insulation layer <b>141</b>, and the second metal line pattern <b>104</b> may be electrically connected to the second pad <b>139</b><i>b </i>through a second metal line contact plug <b>143</b><i>b </i>that penetrates the second insulation layer <b>141</b>. As a result, the first metal line pattern <b>102</b> may act as the ground line Vss shown in <figref idref="DRAWINGS">FIG. 20</figref>, and the second metal line pattern <b>104</b> may act as the power supply line Vcc shown in <figref idref="DRAWINGS">FIG. 20</figref>.

0097Although not shown in <figref idref="DRAWINGS">FIG. 21</figref>, the metal line patterns <b>102</b> and <b>104</b> may extend so that they are disposed on a peripheral circuit region adjacent to the SRAM cell of <figref idref="DRAWINGS">FIG. 21</figref>.

0098According to the above embodiment, cracks may be prevented from being formed in the insulation layers <b>135</b> and <b>141</b> due to the presence of at least the inner slits <b>102</b>S′ in the first metal line pattern <b>102</b> or the inner slits <b>104</b>S′ in the second metal line pattern <b>104</b>.

0099<figref idref="DRAWINGS">FIG. 22</figref> illustrates a perspective view of a first half cell (HC<b>1</b> of <figref idref="DRAWINGS">FIG. 20</figref>) of an exemplary TFT CMOS SRAM cell with a pair of metal line patterns according to the embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref>.

0100Referring to <figref idref="DRAWINGS">FIG. 22</figref>, an isolation layer <b>153</b> may be disposed at a predetermined region of a semiconductor substrate <b>151</b> to define a first active region <b>153</b><i>a</i>. First and second N-type impurity regions <b>157</b><i>a </i>and <b>157</b><i>b </i>may be disposed in the first active region <b>153</b><i>a</i>. A first driver gate electrode <b>155</b> may be disposed over the first active region <b>153</b><i>a </i>between the first and second N-type impurity regions <b>157</b><i>a </i>and <b>157</b><i>b</i>. The first driver gate electrode <b>155</b>, the first N-type impurity region <b>157</b><i>a </i>and the second N-type impurity region <b>157</b><i>b </i>may act as the gate electrode, the source region and the drain region of the first driver transistor TD<b>1</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively.

0101The substrate having the first driver transistor TD<b>1</b> may be covered with a first insulation layer <b>158</b>. A first semiconductor body <b>159</b> may be disposed on the first insulation layer <b>158</b>. The first semiconductor body <b>159</b> may be a single crystalline semiconductor pattern. Third and fourth N-type impurity regions <b>163</b><i>a </i>and <b>163</b><i>b </i>may be disposed in the first semiconductor body <b>159</b>, and a first transfer gate electrode <b>161</b> may be disposed over the first semiconductor body <b>159</b> between the third and fourth N-type impurity regions <b>163</b><i>a </i>and <b>163</b><i>b</i>. The first transfer gate electrode <b>161</b>, the third N-type impurity region <b>163</b><i>a </i>and the fourth N-type impurity region <b>163</b><i>b </i>may act as the gate electrode, the drain region and the source region of the first transfer transistor TT<b>1</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively. As a result, the first transfer transistor TT<b>1</b> of this embodiment may correspond to a thin film transistor.

0102The substrate having the first transfer transistor TT<b>1</b> may be covered with a second insulation layer <b>165</b>. A second semiconductor body <b>167</b> may be disposed on the second insulation layer <b>165</b>. The second semiconductor body <b>167</b> may be a single crystalline semiconductor pattern. First and second P-type impurity regions <b>171</b><i>a </i>and <b>171</b><i>b </i>may be disposed in the second semiconductor body <b>167</b>, and a first load gate electrode <b>169</b> may be disposed over the second semiconductor body <b>167</b> between the first and second P-type impurity regions <b>171</b><i>a </i>and <b>171</b><i>b</i>. The first load gate electrode <b>169</b>, the first P-type impurity region <b>171</b><i>a </i>and the second P-type impurity region <b>171</b><i>b </i>may act as the gate electrode, the source region and the drain region of the first load transistor TL<b>1</b> shown in <figref idref="DRAWINGS">FIG. 20</figref>, respectively. As a result, the first load transistor TL<b>1</b> of this embodiment may also correspond to a thin film transistor.

0103The substrate including the first load transistor TL<b>1</b> may be covered with a third insulation layer <b>173</b>. The second N-type impurity region <b>157</b><i>b</i>, the fourth N-type impurity region <b>163</b><i>b </i>and the second P-type impurity region <b>171</b><i>b </i>may be electrically connected to a first node plug <b>175</b> that passes through the first, second and third insulation layers <b>158</b>, <b>165</b> and <b>173</b>. The first node plug may be a metal plug, e.g., a tungsten plug. The first node plug <b>175</b> and the third insulation layer <b>173</b> may be covered with a fourth insulation layer <b>177</b>.

0104The plurality of metal line patterns described in the above embodiments, e.g., the first and second metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref>, may be disposed on the fourth insulation layer <b>177</b>. The first metal line pattern <b>102</b> may be electrically connected to the first N-type impurity region <b>157</b><i>a </i>through a first metal line contact plug <b>179</b><i>a </i>that penetrates the first to fourth insulation layers <b>158</b>, <b>165</b>, <b>173</b> and <b>177</b>, and the second metal line pattern <b>104</b> may be electrically connected to the first P-type impurity region <b>171</b><i>a </i>through a second metal line contact plug <b>179</b><i>b </i>that penetrates the third and fourth insulation layers <b>173</b> and <b>177</b>. As a result, the first metal line pattern <b>102</b> may act as the ground line Vss shown in <figref idref="DRAWINGS">FIG. 20</figref>, and the second metal line pattern <b>104</b> may act as the power supply line Vcc shown in <figref idref="DRAWINGS">FIG. 20</figref>.

0105Alternatively, the TFT including the first semiconductor body <b>159</b> may act as the first load transistor TL<b>1</b>, and the TFT including the second semiconductor body <b>167</b> may act as the first transfer transistor TT<b>1</b>. In this case, the impurity regions <b>163</b><i>a </i>and <b>163</b><i>b </i>are P-type impurity regions and the impurity regions <b>171</b><i>a </i>and <b>171</b><i>b </i>are N-type impurity regions. Hence, the second metal line pattern <b>104</b> may be electrically connected to the impurity region <b>163</b><i>a. </i>

0106Although not shown in <figref idref="DRAWINGS">FIG. 22</figref>, the metal line patterns <b>102</b> and <b>104</b> may extend so that they are disposed on a peripheral circuit region adjacent to the SRAM cell of <figref idref="DRAWINGS">FIG. 22</figref>.

0107According to the above embodiment, cracks may be prevented from being formed in the fourth insulation layer <b>177</b> due to the presence of at least the inner slits <b>102</b>S′ in the first metal line pattern <b>102</b> or the inner slits <b>104</b>S′ in the second metal line pattern <b>104</b>.

0108The plurality of metal line patterns described in the above embodiments, e.g., the metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref>, may also be employed in the flash memory device including NAND strings, as shown in <figref idref="DRAWINGS">FIG. 23</figref>. However, it will be apparent to those skilled in the art that the metal line patterns according to the embodiments of the present invention may be applicable to all of non-volatile memory devices such as NOR-type flash memory devices, magnetic random access memory (MRAM) devices, phase change memory devices, resistive random access memory (RRAM) devices or the like. Further, although each of flash memory cells shown in <figref idref="DRAWINGS">FIG. 23</figref> employs a stacked gate structure including a conductive floating gate and a control gate electrode which are sequentially stacked, embodiments of the present invention is not limited to the flash memory devices having the stacked gate structure. For example, embodiments of the present invention may also be applicable to the flash memory device employing silicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells.

0109Referring to <figref idref="DRAWINGS">FIG. 23</figref>, an isolation layer <b>203</b> may be disposed at a predetermined region of a semiconductor substrate <b>201</b> to define a cell active region <b>203</b><i>a</i>. A lower ground selection line GSL′ and a lower string selection line SSL′ may be disposed to cross over the cell active region <b>203</b><i>a</i>. Further, a plurality of lower word lines WL<b>1</b>′, WL<b>2</b>′, WL<b>3</b>′, . . . and WLn′ may be disposed between the lower ground selection line GSL′ and the lower string selection line SSL′. A plurality of lower floating gates FG′ may be disposed between the cell active region <b>203</b><i>a </i>and the lower word lines WL<b>1</b>′, WL<b>2</b>′, WL<b>3</b>′, . . . and WLn′, respectively. A lower ground impurity region <b>205</b><i>s </i>may be provided in the cell active region <b>203</b><i>a</i>, adjacent to the lower ground selection line GSL′ and opposite the lower string selection line SSL′. A lower bit line impurity region <b>205</b><i>b </i>may be provided in the cell active region <b>203</b><i>a</i>, adjacent to the lower string selection line SSL′ and opposite the lower ground selection line GSL′. A plurality of lower source/drain regions <b>205</b> may be provided in the cell active region <b>203</b><i>a </i>between the lower ground impurity region <b>205</b><i>s </i>and the lower bit line impurity region <b>205</b><i>b</i>. The lower word lines WL<b>1</b>′, . . . and WLn′, the lower floating gates FG′, the lower ground selection line GSL′, the lower string selection line SSL′, the lower source/drain regions <b>205</b>, the lower ground impurity region <b>205</b><i>s</i>, and the lower bit line impurity region <b>205</b><i>b </i>may constitute a lower NAND string STR<b>1</b>.

0110The lower ground selection line GSL′, the lower ground impurity region <b>205</b><i>s</i>, and the lower source/drain region <b>205</b> adjacent to the lower ground selection line GSL′ may constitute a lower ground selection transistor of the lower NAND string STR<b>1</b>. Similarly, the lower string selection line SSL′, the lower bit line impurity region <b>205</b><i>b</i>, and the lower source/drain region <b>205</b> adjacent to the lower string selection line SSL′ may constitute a lower string selection transistor of the lower NAND string STR<b>1</b>. The lower ground impurity region <b>205</b><i>s </i>may act as a source region of the lower ground selection transistor, and the lower bit line impurity region <b>205</b><i>b </i>may act as a drain region of the lower string selection transistor. In addition, the lower word lines WL<b>1</b>′, . . . , WLn′, the lower floating gates FG′, and the lower source/drain regions <b>205</b> may constitute a plurality of lower cell transistors which are serially connected to one another.

0111The substrate including the lower NAND string STR<b>1</b> may be covered with a first insulation layer <b>207</b>. A semiconductor body <b>209</b> may be disposed on the first insulation layer <b>207</b>. The semiconductor body <b>209</b> may be a single crystalline semiconductor pattern. An upper ground selection line GSL″ and an upper string selection line SSL″ may be disposed to cross over the semiconductor body <b>209</b>. Further, a plurality of upper word lines WL<b>1</b>″, WL<b>2</b>″, WL<b>3</b>″, . . . and WLn″ may be disposed between the upper ground selection line GSL″ and the upper string selection line SSL″. A plurality of upper floating gates FG″ may be disposed between the semiconductor body <b>209</b> and the upper word lines WL<b>1</b>″, WL<b>2</b>″, WL<b>3</b>″, . . . and WLn″, respectively. An upper ground impurity region <b>211</b><i>s </i>may be provided in the semiconductor body <b>209</b> adjacent to the upper ground selection line GSL″ and opposite the upper string selection line SSL″. An upper bit line impurity region <b>211</b><i>b </i>may be provided in the semiconductor body <b>209</b> adjacent to the upper string selection line SSL″ and opposite the upper ground selection line GSL″. A plurality of upper source/drain regions <b>211</b> may be provided in the semiconductor body <b>209</b> between the upper ground impurity region <b>211</b><i>s </i>and the upper bit line impurity region <b>211</b><i>b</i>. The upper word lines WL<b>1</b>″, . . . and WLn″, the upper floating gates FG″, the upper ground selection line GSL″, the upper string selection line SSL″, the upper source/drain regions <b>211</b>, the upper ground impurity region <b>211</b><i>s</i>, and the upper bit line impurity region <b>211</b><i>b </i>may constitute an upper NAND string STR<b>2</b>.

0112The upper ground selection line GSL″, the upper ground impurity region <b>211</b><i>s</i>, and the upper source/drain region <b>211</b> adjacent to the upper ground selection line GSL″ may constitute an upper ground selection transistor of the upper NAND string STR<b>2</b>. Similarly, the upper string selection line SSL″, the upper bit line impurity region <b>211</b><i>b</i>, and the upper source/drain region <b>211</b> adjacent to the upper string selection line SSL″ may constitute an upper string selection transistor of the upper NAND string STR<b>2</b>. The upper ground impurity region <b>211</b><i>s </i>may act as a source region of the upper ground selection transistor, and the upper bit line impurity region <b>211</b><i>b </i>may act as a drain region of the upper string selection transistor. In addition, the upper word lines WL<b>1</b>″, . . . , WLn″, the upper floating gates FG″, and the upper source/drain regions <b>211</b> may constitute a plurality of upper cell transistors which are serially connected to one another.

0113The substrate including the upper NAND string STR<b>2</b> may be covered with a second insulation layer <b>213</b>. The lower and upper bit line impurity regions <b>205</b><i>b </i>and <b>211</b><i>b </i>may be electrically connected to a bit line contact plug <b>215</b> that penetrates the first and second insulation layers <b>207</b> and <b>213</b>. A third insulation layer <b>217</b> may be disposed on the second insulation layer <b>213</b>.

0114The plurality of metal line patterns described in the above embodiments, e.g., the first and second metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref>, may be disposed on the third insulation layer <b>217</b>. The first metal line pattern <b>102</b> may be electrically connected to the lower ground impurity region <b>205</b><i>s </i>and the upper ground impurity region <b>211</b><i>s </i>through a first metal line contact plug <b>219</b> that penetrates the first to third insulation layers <b>207</b>, <b>213</b> and <b>217</b>. Accordingly, the first metal line pattern <b>102</b> may correspond to a ground line Vss of a flash memory device. Further, the second metal line pattern <b>104</b> may correspond to a power supply line Vcc of a flash memory device.

0115Although not shown in <figref idref="DRAWINGS">FIG. 23</figref>, the metal line patterns <b>102</b> and <b>104</b> may extend so that they are disposed on a peripheral circuit region adjacent to the NAND strings of <figref idref="DRAWINGS">FIG. 23</figref>.

0116According to the above embodiment, cracks may be prevented from being formed in the third insulation layer <b>217</b> due to the presence of at least the inner slits <b>102</b>S′ in the first metal line pattern <b>102</b> or the inner slits <b>104</b>S′ in the second metal line pattern <b>104</b>.

0117The plurality of metal line patterns described in the above embodiments, e.g., the metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref>, may also be employed in the logic device including logic gates, as shown in <figref idref="DRAWINGS">FIG. 24</figref>.

0118Referring to <figref idref="DRAWINGS">FIG. 24</figref>, a P-type well <b>253</b> and an N-type well <b>255</b> may be provided in a semiconductor substrate <b>251</b>. An isolation layer <b>257</b> may be disposed at a predetermined region of the semiconductor substrate <b>251</b> to define a first active region <b>257</b><i>a </i>in the P-type well <b>253</b> and a second active region <b>257</b><i>b </i>in the N-type well <b>255</b>. An N-type source region <b>261</b><i>s </i>and an N-type drain region <b>261</b><i>d </i>may be disposed in the first active region <b>257</b><i>a</i>, and a P-type source region <b>263</b><i>s </i>and a P-type drain region <b>263</b><i>d </i>may be disposed in the second active region <b>257</b><i>b</i>. A first gate electrode <b>259</b><i>a </i>may be disposed over the first active region <b>257</b><i>a </i>between the N-type source region <b>261</b><i>s </i>and the N-type drain region <b>261</b><i>d</i>, and a second gate electrode <b>259</b><i>b </i>may be disposed over the second active region <b>257</b><i>b </i>between the P-type source region <b>263</b><i>s </i>and the P-type drain region <b>263</b><i>d</i>. The first gate electrode <b>259</b><i>a</i>, the N-type source region <b>261</b><i>s </i>and the N-type drain region <b>261</b><i>d </i>may constitute an N-channel MOS (NMOS) transistor TN, and the second gate electrode <b>259</b><i>b</i>, the P-type source region <b>263</b><i>s </i>and the P-type drain region <b>263</b><i>d </i>may constitute a P-channel MOS (PMOS) transistor TP.

0119The NMOS transistor TN and the PMOS transistor TP may be covered with a first insulation layer <b>265</b>. A local interconnection <b>269</b> may be disposed on the first insulation layer <b>265</b>. One end of the local interconnection <b>269</b> may be electrically connected to the N-type drain region <b>261</b><i>d </i>through a first drain contact plug <b>267</b><i>a </i>that penetrates the first insulation layer <b>265</b>, and the other end of the local interconnection <b>269</b> may be electrically connected to the P-type drain region <b>263</b><i>d </i>through a second drain contact plug <b>267</b><i>b </i>that penetrates the first insulation layer <b>265</b>. As a result, the local interconnection <b>269</b> electrically connects the N-type drain region <b>261</b><i>d </i>to the P-type drain region <b>263</b><i>d</i>. The local interconnection <b>269</b> and the first insulation layer <b>265</b> may be covered with a second insulation layer <b>271</b>.

0120The plurality of metal line patterns described in the above embodiments, for example, the first and second metal line patterns <b>102</b> and <b>104</b> shown in <figref idref="DRAWINGS">FIG. 17</figref>, may be disposed on the second insulation layer <b>271</b>. The first metal line pattern <b>102</b> may be electrically connected to the N-type source region <b>261</b><i>s </i>through a first metal line contact plug <b>271</b><i>a </i>that penetrates the first and second insulation layers <b>265</b> and <b>271</b>, and the second metal line pattern <b>104</b> may be electrically connected to the P-type source region <b>263</b><i>s </i>through a second metal line contact plug <b>271</b><i>b </i>that penetrates the first and second insulation layers <b>265</b> and <b>271</b>. As a result, the first metal line pattern <b>102</b> may act as a ground line Vss of the logic device, and the second metal line pattern <b>104</b> may act as a power supply line Vcc of the logic device.

0121According to the above embodiment, cracks may be prevented from forming in the second insulation layer <b>271</b> due to the presence of at least the inner slits <b>102</b>S′ in the first metal line pattern <b>102</b> or the inner slits <b>104</b>S′ in the second metal line pattern <b>104</b>.

0122As described above, by providing an appropriate space between two adjacent metal line patterns or by forming a slit at a location adjacent to the space between two adjacent metal line patterns according to the embodiments of the present invention, an occurrence of a crack may be prevented or reduced, thereby leading to high reliability and a high manufacturing yield.

0123Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.