Semiconductor substrate, and semiconductor device and method of manufacturing the semiconductor device
Summary by NHIP
MEMS substrate with selective grooves
The semiconductor substrate contains multiple MEMS elements separated by intersecting division lines, featuring grooves exclusively on the first direction lines. These grooves are V-shaped or U-shaped and formed by anisotropic etching, while a laser-formed modified region exists along both line directions without intersecting the grooves.
Claim Score by NHIP
Abstract
In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

Term
1.9 yearsleft in the term
Expires 2 August 2028, including 458 days of term adjustment.
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10 claims: 1 independent, 9 dependent
- 1Broadest claimClaim Score 56, average(NHIP)A semiconductor substrate comprising:a plurality of semiconductor elements each comprising a MEMS device, and each including a thinned portion of the semiconductor substrate;first direction division lines;second direction division lines intersecting the first direction division lines;a groove formed on each first direction division line;and a modified region formed along each of the first direction division lines and second direction division lines, wherein each semiconductor element is surrounded by first direction division lines and second direction division lines and the grooves do not intersect each other.
64 paragraphs in 5 sections, as filed
0001The present application claims priority to Japanese Patent Application No. 2006-133160, filed May 12, 2006, which application is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
0002The present invention relates to a semiconductor substrate having a diaphragm structure and a beam structure formed by thinning a part of the semiconductor substrate, which is typified by MEMS (Micro Electro Mechanical System), and a semiconductor device manufactured by dividing the semiconductor substrate and a manufacturing method of the semiconductor device.
BACKGROUND OF THE INVENTION
0003In the semiconductor devices which are manufactured by the above described MEMS and have diaphragm structures and beam structures that are partially thinned, MEMS pressure sensors and MEMS acceleration sensors are included. Such sensors are generally manufactured by dividing a plurality of the above described diaphragm structures and beam structures individually after the diaphragm structures and beam structures are simultaneously formed in the semiconductor wafer process. For the division, the method for performing crushing by rotating a ring-shaped dicing saw in which particles of diamond and CBN are held by a bond material at a high speed is most commonly used. Since the machining by the dicing saw is performed while cutting water is run for washing out crushed chips and cooling down the frictional heat, and the diaphragm structures and the beam structures are brittle structures, there has been the problem that the diaphragm structures and the beam structures are broken due to the pressure of the cutting water during machining by the dicing saw.
0004In recent years, as a method for solving such a problem, machining by laser light has attracted attention, and an example of such machining is disclosed in, for example, Japanese Patent No. 3408805.
0005In the manufacturing method by laser light disclosed in Japanese Patent No. 3408805, a modified region by multiphoton absorption is formed in a semiconductor wafer, and the semiconductor wafer is divided by cleavage with the modified region as the starting point. Multiphoton absorption is the phenomenon in which even when energy of photon is smaller than the band gap of absorption of the material, namely, even when photon is optically transmitted, by making the intensity of light very high, absorption occurs in the material. By aligning the focusing point of laser light with the inside of the semiconductor wafer, the phenomenon of multiphoton absorption is caused, and the modified region is formed inside the semiconductor wafer. Then, by easily breaking the substrate along the dicing lane, with the modified region formed as the starting point, division without requiring cutting water is enabled.
0006The above described method for machining by laser light will be described based on the drawings. <figref idref="DRAWINGS">FIG. 9</figref> is a plane view showing the division lines and the periphery of the semiconductor substrate which is a lased machining workpiece, and <figref idref="DRAWINGS">FIG. 10</figref> is a sectional view taken along the line C-C′ shown in <figref idref="DRAWINGS">FIG. 9</figref> during laser processing. In <figref idref="DRAWINGS">FIGS. 9 and 10</figref>, reference numeral <b>101</b> denotes a semiconductor substrate, reference numeral <b>102</b> denotes a semiconductor element which constitutes the semiconductor device formed in the semiconductor substrate <b>101</b>, reference numeral <b>104</b> denotes the division line of the semiconductor element <b>102</b>, reference numeral <b>108</b> denotes laser light, reference numeral <b>109</b> denotes a modified region, and reference numeral <b>110</b> denotes a cut portion (crack) occurring with the modified region <b>109</b> as the starting point.
0007The process of the method of machining by laser light will be described hereinafter.
0008First, the focusing point of the laser light <b>108</b> is aligned with the inside of the semiconductor substrate <b>101</b>, and multiphoton absorption is caused in a predetermined thickness direction.
0009Next, by scanning the laser light <b>108</b> along the center of the division line <b>104</b> while causing multiphoton absorption continuously or intermittently, the modified region <b>109</b> along the division line <b>104</b> is formed inside the semiconductor substrate <b>101</b>, and the cut portion <b>110</b> is formed.
0010Next, an external force is simultaneously applied to both ends of the semiconductor substrate <b>101</b>, the semiconductor substrate <b>101</b> is split with the modified region <b>109</b> as the starting point, and the semiconductor device is formed. Since at this time, the cut portion <b>110</b> is formed with the modified region <b>109</b> as the starting point, the semiconductor substrate <b>101</b> can be easily broken with a relatively small external force. Especially when the semiconductor substrate <b>101</b> is thin, the semiconductor substrate <b>101</b> splits naturally in the thickness direction even if the external force is not especially applied to the semiconductor substrate <b>101</b>.
0011Other than the above described method for machining by laser light, as the method for solving the problem in which diaphragm structures and beam structures are broken by the pressure of cutting water, reducing the thickness of the machined portion by forming in advance a groove on the division line by anisotropic etching or the like is performed. This method is disclosed in, for example, Japanese Patent Laid-Open No. 2001-127008.
0012In the manufacturing method disclosed in Japanese Patent Laid-Open No. 2001-127008, an etching protection film is formed on the semiconductor substrate of an orientation plane (100) so as to open the division line in the longitudinal direction and the lateral direction first, and thereafter, anisotropic etching is performed. Herein, etching is stopped on an orientation plane (111), and therefore, a V-groove with the angle of inclination of 54.7 degrees is formed. Next, an external force is applied to the semiconductor substrate so that the V-groove is enlarged to divide the semiconductor substrate along the V-groove, and the individual semiconductor devices are formed.
0013However, in the above-described known laser machining method disclosed in Patent Document 1, the following problem arises.
0014When the semiconductor substrate is thick, the semiconductor substrate cannot be divided with the modified region by one scanning. Therefore, a plurality of modified regions are required to be formed parallel to the thickness direction by carrying out laser machining a plurality of times, and this leads to increase in tact required for machining.
0015In the above-described known method of manufacturing in which the V-groove is formed, disclosed in Patent Document 2, the following problem arises.
0016Since in the portion where the V-grooves intersect with each other in the longitudinal direction and the lateral direction of the division lines, erosion of anisotropic etching differs from that in the other portions, etching does not stop in the orientation plane (111) if etching is performed excessively, and etching advances into an orientation plane (211), for example. In other words, when the V-groove is to be formed simultaneously with the step of forming the diaphragm structure requiring etching which is deeper than, for example, the V-groove, the intersection portions of the V-grooves are excessively etched, and the semiconductor substrate is penetrated. Therefore, the strength of the semiconductor substrate is extremely reduced, and the semiconductor substrate is broken at the time of handling the semiconductor substrate.
DISCLOSURE OF THE INVENTION
0017The present invention has an object to solve these problems and provide a semiconductor substrate capable of improving machining tact without degrading quality of division when dividing the semiconductor substrate into individual semiconductor devices, a semiconductor device and a method of manufacturing the semiconductor device.
0018In order to attain this object, the semiconductor substrate of the present invention includes grooves continuously formed on only the division lines formed parallel in one direction, out of the division lines in the longitudinal direction and the lateral direction to individually divide a plurality of semiconductor elements formed in a shape of cells in the longitudinal direction and the lateral direction.
0019With this configuration, the grooves are formed on only the division lines formed parallel in one direction, out of the division lines orthogonal to each other in the longitudinal direction and the lateral direction, whereby, the thickness of the semiconductor substrate in the division line portions where the grooves are formed is thin and is notched, and can have the structure in which stress easily concentrates when division by cleavage or the like is performed.
0020The method of manufacturing the semiconductor device of the present invention comprises a step of forming grooves by etching continuously on only division lines formed parallel in one direction, out of the division lines in the longitudinal direction and the lateral direction in order to individually divide a plurality of semiconductor elements formed in the form of cells in the longitudinal direction and the lateral direction in the semiconductor substrate, a step of forming modified regions inside the semiconductor substrate by irradiating laser light along the division lines in the aforesaid longitudinal direction and lateral direction respectively with the focal points aligned with the inside of the aforesaid semiconductor substrate, and a step of forming individual semiconductor devices by dividing the semiconductor substrate along the division lines in the longitudinal direction and lateral direction by applying an external force to the aforesaid semiconductor substrate.
0021By this manufacturing method, the grooves are formed by etching so as to be in series on only the division lines formed parallel in one direction, out of the division lines orthogonal to each other in the longitudinal direction and the lateral direction, and thus, the intersection portions of the grooves for which control of etching is extremely difficult are not formed. Therefore, stable grooves can be formed extremely easily. The substrate is divided into the individual semiconductor devices along the division lines where the continuous grooves are formed, so that as compared with the case where the grooves are not formed, division with excellent straightness can be performed easily.
0022The semiconductor device of the present invention is a semiconductor device manufactured by the above described method, wherein chamfering is performed for only two sides opposed to each other in a back surface side of each of the individual semiconductor devices.
0023With this configuration, chamfering is performed for the two sides opposed to each other on the back surface side, and therefore, during substrate mounting which is the post process thereof, the die bond material used in bonding of the semiconductor device and the substrate can be restrained from creeping up to the side surface of the semiconductor device. Since chamfering is not performed to the other two sides, the area of the back surface of the semiconductor device is not reduced, and bond area during tie bonding can be secured.
BRIEF DESCRIPTION OF THE DRAWINGS
0024<figref idref="DRAWINGS">FIG. 1</figref> is a plane view of a semiconductor substrate in one embodiment of the present invention;
0025<figref idref="DRAWINGS">FIG. 2</figref> is a plane view showing a periphery of division lines of the semiconductor substrate;
0026<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are a sectional view taken along the line A-A′ and a sectional view taken along the line B-B′ in <figref idref="DRAWINGS">FIG. 2</figref>;
0027<figref idref="DRAWINGS">FIG. 4</figref> is a flow chart of a method of manufacturing a semiconductor device in one embodiment of the present invention;
0028<figref idref="DRAWINGS">FIGS. 5A to 5F</figref> are sectional views of the semiconductor substrate showing the process steps of the method of manufacturing the semiconductor device in sequence by using the sectional views taken along the line B-B′ shown in <figref idref="DRAWINGS">FIG. 4</figref>;
0029<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are sectional views showing the method of manufacturing the semiconductor device;
0030<figref idref="DRAWINGS">FIG. 7</figref> shows a plane view, a cross-sectional view and a longitudinal sectional view of the semiconductor device after being divided from the semiconductor substrate in one embodiment of the present invention;
0031<figref idref="DRAWINGS">FIG. 8</figref> is a sectional view of a semiconductor substrate on which the semiconductor device is mounted;
0032<figref idref="DRAWINGS">FIG. 9</figref> is a plane view of a conventional semiconductor substrate; and
0033<figref idref="DRAWINGS">FIG. 10</figref> is a sectional view showing a method of manufacturing a conventional semiconductor device.
DESCRIPTION OF THE EMBODIMENT(S)
0034An embodiment of the present invention will now be described with reference to the drawings.
0035With reference to <figref idref="DRAWINGS">FIGS. 1 to 3</figref>, a semiconductor substrate of the present invention will be described. In <figref idref="DRAWINGS">FIGS. 1 to 3</figref>, reference numeral <b>1</b> denotes a semiconductor substrate made of Si single crystal, reference numeral <b>2</b> denotes a semiconductor element constituting a semiconductor device, reference numeral <b>3</b> denotes a V-groove (one example of a groove), reference numeral <b>4</b> denotes a division line and reference numeral <b>5</b> denotes a diaphragm.
0036A plurality of semiconductor elements <b>2</b> are formed in the form of cells in the longitudinal direction and the lateral direction in the semiconductor substrate <b>1</b> as shown in <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.
0037A plurality of semiconductor elements <b>2</b> are divided by the division lines <b>4</b> as shown in <figref idref="DRAWINGS">FIG. 2</figref>. In this case, the division lines <b>4</b> are division regions set when the semiconductor elements <b>2</b> are divided individually from the semiconductor substrate <b>1</b>. The division lines <b>4</b> are formed so as to be orthogonal (cross) in the longitudinal direction and the lateral direction, and as shown in <figref idref="DRAWINGS">FIGS. 1 to 3</figref>, out of the division lines orthogonal to each other, on only the division lines parallel with one of the longitudinal direction and the lateral direction (in the drawing, on the division lines in the longitudinal direction), the V-grooves <b>3</b> are formed. These V-grooves <b>3</b> are formed by the orientation planes (111) with the inclination angle of 54.7 degrees, for example.
0038As shown in <figref idref="DRAWINGS">FIG. 3B</figref>, the diaphragm <b>5</b> is formed in each of the semiconductor elements <b>2</b>.
0039As described above, the V-grooves <b>3</b> are formed on only the division lines parallel in one direction, out of the division lines <b>4</b> orthogonal to each other in the longitudinal direction and the lateral direction, so that the semiconductor substrate <b>1</b> in the portions of the division lines <b>4</b> where the V-grooves <b>3</b> are formed is small in thickness, is in a notched shape, and can have the structure where stress easily concentrates when division by cleavage or the like is performed. Therefore, when the modified region to be the starting point for dividing the semiconductor substrate <b>1</b> into the individual semiconductor elements <b>2</b> is formed inside the semiconductor substrate <b>1</b>, in the step of dividing the semiconductor substrate <b>1</b> into the individual semiconductor elements <b>2</b> which is a post process, the number of times of laser light scanning can be made smaller as compared with that in the case of the division line in which no groove is formed, as a result of which, machining tact can be made short, and stable division with favorable straightness is enabled.
0040Next, with reference to <figref idref="DRAWINGS">FIG. 4</figref> and <figref idref="DRAWINGS">FIGS. 5A to 5F</figref>, a method of manufacturing the semiconductor device of the present invention will be described. In <figref idref="DRAWINGS">FIGS. 5A to 5F</figref>, reference numeral <b>6</b> denotes an etching mask, reference numeral <b>7</b> denotes an expanded tape, reference numeral <b>8</b> denotes laser light, reference numeral <b>9</b> denotes a modified region, reference numeral <b>10</b> denotes a crack (cut portion) with the modified region as a starting point, and reference numeral <b>11</b> denotes a semiconductor device after individual semiconductor elements <b>2</b> are cut out from the semiconductor substrate <b>1</b>.
0041As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the method of manufacturing the semiconductor device of the present invention comprises the following steps of: “forming V-grooves continuously on only division lines parallel in the longitudinal direction by anisotropic etching” (forming grooves by etching); “forming modified regions inside the semiconductor substrate by irradiating laser light along the orthogonal division lines with the focal points aligned with the inside of the semiconductor substrate” (forming the modified regions inside the semiconductor substrate); and “dividing the semiconductor substrate into individual semiconductor devices along the orthogonal division lines by applying an external force to the semiconductor substrate” (forming the individual semiconductor devices) in this sequence.
0042First, “the step of forming the V-grooves continuously on only the division lines parallel in the longitudinal direction by anisotropic etching” will be described.
0043Namely, as shown in <figref idref="DRAWINGS">FIG. 5A</figref>, first, the etching mask <b>6</b> is formed on the semiconductor substrate <b>1</b> on which a plurality of semiconductor elements <b>2</b> are formed, and division lines (not shown) for dividing the individual semiconductor elements <b>2</b> are set. The etching mask <b>6</b> is formed so that the regions where the diaphragms <b>5</b> and the V-grooves <b>3</b> are desired to be formed are opened. At this time, the openings of the etching mask <b>6</b> for forming the V-grooves <b>3</b> are formed on only the division lines <b>4</b> parallel in one direction.
0044In this case, for example, the etching mask <b>6</b> is formed by forming a material such as a silicon oxide film by using a CVD method, and then, patterning the material with a lithography technique. Though not shown, the etching mask is left on the entire surface where the semiconductor elements <b>2</b> are formed.
0045Next, as shown in <figref idref="DRAWINGS">FIG. 5B</figref>, the diaphragms <b>5</b> and the V-grooves <b>3</b> are formed by anisotropic etching. In this case, as an anisotropic etching solution, for example, a KOH solution, and a TMAH (tetramethylammonium hydroxide) solution are used. At this time, the V-grooves <b>3</b> are formed on only the division lines <b>4</b> parallel in one direction, and thus, the V-grooves <b>3</b> do not have the intersecting patterns. Therefore, etching of the semiconductor substrate <b>1</b> comprised of the Si single crystal substrate does not cause abnormal erosion in the intersecting patterns, and reliably stops the process of etching on the orientation plane (111). Therefore, even when the diaphragms <b>5</b> and the V-grooves <b>3</b> differing in etching depth are simultaneously formed, they can be stopped in the depth at an inclination angle of 54.7 degrees. In other words, the depth and width of the V-groove <b>3</b> can be determined by the opening width of the etching mask <b>6</b>.
0046Next, as shown in <figref idref="DRAWINGS">FIG. 5C</figref>, the etching mask <b>6</b> is removed. For removing the etching mask <b>6</b>, for example, a BHF solution is used. Herein, the etching mask <b>6</b> is removed, but unless removal is especially necessary, the etching mask <b>6</b> may be left.
0047Subsequently, “the step of forming the modified region inside the semiconductor substrate by irradiating laser light along the orthogonal division lines respectively with the focal points aligned with the inside of the semiconductor substrate” will be described.
0048That is, as shown in <figref idref="DRAWINGS">FIG. 5D</figref>, the semiconductor substrate <b>1</b> is mounted to the expanded tape <b>7</b> first.
0049Next, as shown in <figref idref="DRAWINGS">FIG. 5E</figref>, laser light <b>8</b> is irradiated along the division lines <b>4</b> orthogonal to each other respectively with the focal points aligned with the inside of the semiconductor substrate <b>1</b>, and the modified regions <b>9</b> are formed inside the semiconductor substrate <b>1</b>. At this time, scanning of the laser light <b>8</b> in the longitudinal direction is carried out along the lines of the V-grooves <b>3</b> and is carried out so that micro-cracks occurring from the modified regions <b>9</b> develop into the V-grooves <b>3</b>.
0050Subsequently, “the step of dividing the semiconductor substrate into the individual semiconductor devices along the division lines orthogonal to each other by applying an external force to the semiconductor substrate” which is carried out finally will be described.
0051Specifically, as shown in <figref idref="DRAWINGS">FIG. 5F</figref>, by applying the external force to the expanded tape <b>7</b>, the cracks <b>10</b> are developed from the modified regions <b>9</b> formed respectively along the division lines <b>4</b> orthogonal to each other to divide the semiconductor substrate <b>1</b>, whereby the individual semiconductor devices <b>11</b> are formed.
0052Here, when the semiconductor substrate <b>1</b> is thick, division can be facilitated by forming a plurality of modified regions <b>9</b> by carrying out scanning of the laser light <b>8</b> a plurality of times, but as shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, division is possible if the number of times of scanning the laser light <b>8</b> along the division lines <b>4</b> where the V-grooves <b>3</b> are formed is smaller than the number of times of scanning the laser light <b>8</b> along the division lines <b>4</b> where the V-grooves <b>3</b> are not formed.
0053<figref idref="DRAWINGS">FIG. 6A</figref> is an enlarged sectional view taken along the B-B′ line of the above described semiconductor substrate <b>1</b>, and shows modified regions <b>9</b><i>a </i>and <b>9</b><i>b </i>in the depth direction formed along the division line <b>4</b> where the V-groove <b>3</b> is formed when the number of times of scanning of the laser light <b>8</b> is two. <figref idref="DRAWINGS">FIG. 6B</figref> is an enlarged sectional view taken along the line C-C′ of the semiconductor substrate <b>1</b> in the longitudinal direction along the semiconductor element <b>2</b> with the diaphragm <b>5</b> formed therein, and shows modified regions <b>9</b><i>a</i>, <b>9</b><i>b </i>and <b>9</b><i>c </i>in the depth direction formed along the division line <b>4</b> where the V-groove <b>3</b> is not formed when the number of times of scanning of the laser light <b>8</b> is three.
0054As described above, with the configuration of the semiconductor substrate <b>1</b> and by the method of manufacturing the semiconductor device <b>11</b>, when forming the modified region <b>9</b> to be the starting point for dividing the semiconductor substrate <b>1</b> into the individual semiconductor devices <b>11</b>, the number of times of scanning the laser light <b>8</b> along the division line <b>4</b> where the V-groove <b>3</b> is formed can be made smaller than the number of times of scanning the laser light <b>8</b> along the division line <b>4</b> without the V-groove <b>3</b>, the machining tact can be shortened, and stable division with favorable straightness is enabled.
0055Since the V-grooves <b>3</b> are formed by etching so as to be in series on only the division lines formed parallel in one direction, out of the division lines <b>4</b> orthogonal to each other, the intersection portions of the V-grooves <b>3</b> for which control of etching is extremely difficult are not produced, and thereby, the stable V-grooves <b>3</b> can be formed extremely easily. Since the semiconductor substrates <b>1</b> is divided into the individual semiconductor devices <b>11</b> along the division lines <b>4</b> where the continuous V-grooves <b>3</b> are formed, division with excellent straightness can be made easily as compared with the case where the V-grooves <b>3</b> are not formed.
0056Formation of the V-grooves <b>3</b> is performed simultaneously with the anisotropic etching step of forming the diaphragm structure. Therefore, the step is not especially increased, and increases in cost and in lead time can be avoided.
0057The semiconductor devices <b>11</b> individually divided from the semiconductor substrate <b>1</b> by the above described method of manufacturing the semiconductor device <b>11</b> becomes the semiconductor devices each having the diaphragm structure as shown in <figref idref="DRAWINGS">FIG. 7</figref>. In <figref idref="DRAWINGS">FIG. 7</figref>, reference numeral <b>11</b> denotes the semiconductor device after being individually divided, reference numeral <b>12</b> denotes a chamfer which is made when the semiconductor device is divided with the vertex of the V-groove as the starting point, and the chamfers <b>12</b> are formed at only two sides opposed to each other in the back surface side of the individual semiconductor device <b>11</b>.
0058As shown in <figref idref="DRAWINGS">FIG. 7</figref>, the portion of the chamfer <b>12</b> corresponding to the portion where the V-groove <b>3</b> is formed is disposed at the long side of the semiconductor device <b>11</b>. That is, as the division line <b>4</b> where the V-groove <b>3</b> is formed, the division line along the long side of the semiconductor device <b>11</b> is selected, and the V-groove <b>3</b> is formed thereon.
0059Semiconductor devices are generally broken easily when they are slim, and the starting point of breakage is a crack formed at the long side. Thus, by chamfering the long side, the crack to be the starting point is eliminated, and therefore, the transverse strength of the semiconductor device is remarkably increased. In other words, chipping of the long side which leads to reduction in the transverse strength of the semiconductor device <b>11</b> is suppressed, and the semiconductor device <b>11</b> with excellent mechanical strength can be obtained. Since chamfering is not performed for the short sides, the area of the back surface of the semiconductor device <b>11</b> at the short side is not reduced, and the bond area during die bonding can be secured.
0060<figref idref="DRAWINGS">FIG. 8</figref> shows a sectional view of the state in which the semiconductor device of the present invention is mounted on a substrate. In <figref idref="DRAWINGS">FIG. 8</figref>, reference numeral <b>13</b> denotes a mounting substrate, and reference numeral <b>14</b> denotes a die bond material for bonding the mounting substrate <b>13</b> and the semiconductor device <b>11</b>.
0061Bonding of the semiconductor device <b>11</b> and the mounting substrate <b>13</b> is usually performed with the die bond material <b>14</b>. When the bonding is performed, the coating amount of the die bond material <b>14</b> needs to be strictly controlled in order to control creeping-up to the side surface of the semiconductor device <b>11</b>. As shown in <figref idref="DRAWINGS">FIG. 8</figref>, when the chamfer <b>12</b> is applied to the semiconductor device <b>11</b>, creeping-up of the die bond material to the side surface of the semiconductor device <b>11</b> is suppressed by the surface tension of the chamfer <b>12</b>, and therefore, control can be made extremely easy as compared with the conventional unit. Since chamfering is not performed for the other two sides (the short sides), the area of the back surface of the semiconductor device <b>11</b> at the short side is not reduced, and the bond area during die bonding can be secured.
0062In this embodiment, the semiconductor substrate <b>1</b> and the semiconductor device <b>11</b> include the diaphragm structures formed therein, but may not be especially limited to the diaphragm structure.
0063In this embodiment, the grooves formed on only the division lines formed parallel in one of the longitudinal direction and the lateral direction, out of the division lines orthogonal to each other, are formed in the V-grooves, but the grooves are not limited to the V-grooves, and may be formed in the U-shaped grooves. The grooves are formed by anisotropic etching, but can be formed by dry etching.
0064The semiconductor substrate, and the semiconductor device and the method of manufacturing the semiconductor device of the present invention are suitable for manufacturing the semiconductor device without increasing the machining cost and reducing the quality of machining in division of the silicon substrate and the compound semiconductor substrate, and are useful for division especially when manufacturing an MEMS sensor and the like having diaphragm structures.
Contents5
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Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| JP2001127008A | Cites | Japan | Applicant |
| JP2004363517A | Cites | Japan | Applicant |
| JP2005116844A | Cites | Japan | Applicant |
| JP3408805B2 | Cites | Japan | Applicant |
| US5314844A | Cites | United States of America | Search report |
| US7211526B2 | Cites | United States of America | Applicant |
| US7468310B2 | Cites | United States of America | Applicant |
| JPH05285935A | Cites | Japan | Applicant |
| JP5285935 | Cites | Japan | Third party observation |
| JP2001127008 | Cites | Japan | Third party observation |
| JP3408805 | Cites | Japan | Third party observation |
| JP2004363517 | Cites | Japan | Third party observation |
| JP2005116844 | Cites | Japan | Third party observation |
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| Document | Office | Kind | Date |
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| 2006133160 | Japan | – | |
| 2006133160 | Japan | A |
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| CN101071790A | China | A | |
| US2007264803A1 | United States of America | A1 | |
| JP2007305810A | Japan | A | |
| JP4372115B2 | Japan | B2 | |
| US2010015781A1 | United States of America | A1 | |
| US7754584B2 | United States of America | B2 | |
| US7808059B2This record | United States of America | B2 |
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| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Ex Parte Quayle ActionA.QU | A.QU | |
| Mail Ex Parte Quayle Action (PTOL - 326)MCTEQ | MCTEQ | |
| Quayle actionCTEQ | CTEQ | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Response to Election / Restriction FiledELC. | ELC. | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail Restriction RequirementMCTRS | MCTRS | |
| Restriction/Election RequirementCTRS | CTRS | |
| Mail Miscellaneous Communication to ApplicantMM327 | MM327 | |
| Miscellaneous Communication to Applicant - No Action CountM327 | M327 | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Sent to Classification ContractorPGPC | PGPC | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Request for Foreign Priority (Priority Papers May Be Included)RQPR | RQPR | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Preliminary AmendmentA.PE | A.PE | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Initial Exam Team nnIEXX | IEXX |
12 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| AssignmentAS | AS | |
| Fee paymentFPAY | FPAY | |
| AssignmentAS | AS | |
| Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS |
Numbers
- Publication
- 7808059
- Application
- 11797292
Titles
- English
- Semiconductor substrate, and semiconductor device and method of manufacturing the semiconductor device
Patent term adjustment
- A delay
- +330 daysthe office missed an examination deadline
- B delay
- +156 dayspendency past three years
- Applicant delay
- −28 days
- Net adjustment
- 458 days
Classification
- CPC, 5
- B81C1/00873
- B23K26/40
- B23K26/53
- B23K2103/50
- H10P54/00
- IPC, 8
- H01L29 78
- B23K26 00
- B23K26 364
- B23K26 38
- B81B3 00
- H01L29 84
- H10P14 40
- H10P95 00