US7777459B2

High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator

Summary by NHIP

Capacitive-Inductive DC Converter

The DC/DC converter combines a switched capacitive pre-converter with a switched inductive post-regulator to adjust voltage levels. The post-regulator utilizes a high-side switch, a low-side switch, and an inductor arranged in a specific series path to step down voltage.

Claim Score by NHIP

Read claim 12, the broadest

Abstract

A DC/DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC/DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios.

US7777459B2, drawing sheet 1 — Sheet 1 of 75

Term

1.3 yearsleft in the term

Expires 19 January 2028, including 164 days of term adjustment.

27 claims: 2 independent, 25 dependent

1
A DC/DC voltage converter comprising:a pre-converter comprising a switched capacitive circuit, the switched capacitive circuit comprising at least one capacitor, a terminal of the at least one capacitor being coupled through a first switch to an input terminal of the pre-converter and through a second switch to a reference voltage;and a post-regulator comprising a switched inductive circuit;wherein an output terminal of the pre-converter is coupled to an input terminal of the post-regulator, an input terminal of the DC/DC voltage converter comprises the input terminal of the pre-converter, and an output terminal of the DC/DC voltage converter comprises an output terminal of the post-regulator;and wherein the post-regulator is adapted to produce a voltage at the output terminal of the post-regulator that is lower in absolute value than a voltage at the input terminal of the post-regulator.
12
Broadest claimClaim Score 61, broad(NHIP)A DC/DC voltage converter comprising:a pre-converter, the pre-converter comprising a charge pump, the charge pump producing an output voltage equal to a predetermined multiple of an input voltage;a post-regulator comprising a switched inductive circuit;wherein an output terminal of the pre-converter is coupled to an input terminal of the post-regulator, an input terminal of the DC/DC voltage converter comprises an input terminal of the pre-converter, and an output terminal of the DC/DC voltage converter comprises an output terminal of the post-regulator;and wherein the post-regulator is adapted to produce a voltage at the output terminal of the post-regulator that is lower in absolute value than a voltage at the input terminal of the post-regulator.

Independent claims2

329 paragraphs in 6 sections, as filed

This application claims the priority of Provisional Applications Nos. 60/877,952 and 60/877,720, both filed on Dec. 30, 2006, each of which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

This invention pertains to the design, operation and performance of switching power supplies for use in DC/DC conversion and voltage regulation, and to the semiconductor components used in such converters.

BACKGROUND OF THE INVENTION

Voltage regulation is commonly required to prevent variation in the supply voltage powering various microelectronic components such as digital ICs, semiconductor memories, display modules, hard disk drives, RF circuitry, microprocessors, digital signal processors and analog ICs, especially in battery-powered applications such as cell phones, notebook computers and consumer products.

Since the battery or DC input voltage of a product often must be stepped-up to a higher DC voltage, or stepped-down to a lower DC voltage, such converters are referred to as DC-to-DC converters. Step-down converters, commonly referred to as Buck converters, are used whenever a battery's voltage is greater than the desired load voltage. Step-down converters may comprise inductive switching converters, capacitive charge pumps, and linear converters. Conversely, step-up converters, commonly referred to boost converters, are used whenever a battery's voltage is lower than the voltage needed to power its load. Step-up converters may comprise inductive switching converters or capacitive charge pumps.

Another type of converter may operate as either a step-up or a step-down converter, depending on whether the power input to the converter has a voltage above or below its output voltage. Commonly referred to Buck-boost converters, such circuitry is needed whenever a converter's input and output voltages are similar, such that variations in the input voltage preclude the use of a simple boost or Buck converter.

One example an application requiring both step-up and step-down conversion is supplying a regulated 3.3V output from a lithium ion (Lilon) battery. Since a Lilon battery exhibits a terminal voltage which decays from 4.2V when fully charged to below 3V when discharged, the converter must be able to step-down initially and step-up later.

Inductive Switching Converters

Of the above voltage converters, the inductive switching converter can achieve superior performance over the widest range of currents, input voltages and output voltages. The principles of inductive switching converter operation are described in application Ser. No. 11/890,818, titled “High-Efficiency DC/DC Voltage Converter Including Down Inductive Switching Pre-Regulator And Capacitive Switching Post-Converter,” filed contemporaneously herewith and incorporated herein by reference. Two examples of non-isolated inductive switching converters, a synchronous Buck step-down converter and synchronous boost step-up converter, are shown in <figref idrefs="DRAWINGS">FIGS. 1A and 1B</figref>.

Synchronous Buck converter 1 of <figref idrefs="DRAWINGS">FIG. 1A</figref> comprises a power MOSFET 3, an inductor 5, a synchronous rectifier power MOSFET 4, with a rectifier diode 8, and a capacitor 6. Operation of MOSFET 3 is controlled by a pulse-width modulation (PWM) control circuit 2, driving the gate of MOSFET 3. The gate drive may vary in polarity and voltage depending on whether MOSFET 3 is N-channel or P-channel. Synchronous rectifier MOSFET 4, generally an N-channel MOSFET, is driven out of phase with MOSFET 3, but MOSFET 4 is not necessarily on the entire time when MOSFET 3 is off. In general, MOSFET 4 conducts only during times when diode 8 is conducting.

While the control circuit controlling the operation of converter 1 is referred to as PWM control, implying a fixed-frequency variable-pulse-width operation, it may alternatively operate in a variable frequency mode where the clock period is allowed to vary, or alternatively alternating between varying and fixed frequency modes depending on load and input conditions.

The energy input from the power source, battery or power input into DC/DC converter 1 is switched or gated through MOSFET 3. With its positive terminal connected to the battery or input, MOSFET 3 acts like a “high-side” switch controlling the current in inductor 5. Diode 7 is a P-N junction parasitic to MOSFET 3, in parallel to its drain and source, which remains reverse-biased in normal operation. Since diode 7 does not carry current in normal operation, it is illustrated by dotted lines.

By controlling the current in the inductor 5 by controlling the on-time of MOSFET 3, the energy stored in the magnetic field of inductor 5 can be adjusted dynamically to control the voltage on output filter capacitor 6. The output voltage Vout is fed back to the input of PWM control circuit 2, which controls the current IL in inductor 5 through the repeated switching of MOSFET 3. The electrical load connected to the output of converter 1 is not shown.

Driven out of phase with MOSFET 3, synchronous rectifier MOSFET 4 conducts some portion of the time when MOSFET 3 is off. With its positive terminal connected to the inductor, i.e. to the node where the intermediate voltage Vx is present, and its negative terminal connected to the circuit ground, MOSFET 4 acts like a “low-side” switch, shunting the current flowing through diode 8. Diode 8 is a P-N junction parasitic to synchronous rectifier MOSFET 4, in parallel to its drain and source. Diode 8 conducts substantial current only during intervals when both MOSFETs 3 and 4 are off.

Both MOSFETs 3 and 4 are off during every switching transition to prevent shorting of the input power source. The so-called break-before-make (BBM) operation prevents shoot-through conduction by guaranteeing that both MOSFETs 3 and 4 do not conduct simultaneously so as to short or “crow-bar” the input terminal of converter 1 to ground.

During this brief BBM interval, diode 8 must carry the load current IL flowing through inductor 5. Unwanted noise can occur during the transitions associated with BBM operation.

If we define the duty factor D of converter 1 as the percentage of the time that energy flows from the battery or power source into DC/DC converter 1, i.e., the time during which MOSFET 3 is on, then the output-to-input voltage ratio of Buck converter 1 is equal to its duty factor:

This relationship for a Buck or synchronous Buck converter is illustrated by curve 17 in <figref idrefs="DRAWINGS">FIG. 2A</figref> in graph 15. Notice the Buck converter cannot smoothly reach a zero or unity transfer characteristic without exhibiting some discontinuities 19 and 21 at the extremes of D. This phenomenon occurs due to switching delays in the power MOSFETS and the control and gate drive circuitry of converter 1.

As long as the Buck converter's power MOSFET is still switching, tsw is limited to some portion of the clock period T, e.g. 5%<D<95%, essentially due to turn-on and turn-off delay within the MOSFET switch and its control loop. For example at a 95% duty factor and a 3 MHz clock, the off time for the high-side MOSFET 3 is only 5% of the 333 nsec period, or just 16 nsec. This means that MOSFET 3 must turn off and back in only 16 nsec—too rapidly to regulate over a 95% output-to-input conversion ratio. The minimum off-time problem impacts both synchronous and non-synchronous Buck converters. The problem is, however, further exacerbated in a synchronous DC/DC converter since no time remains for the synchronous rectifier MOSFET to turn on and then off again and still exhibit BBM operation.

Referring again to graph 15 in <figref idrefs="DRAWINGS">FIG. 2A</figref>, above some maximum duty factor Dmax, there is not adequate time to maintain switching operation, and converter 1 must jump from Dmax to a 100% duty factor, as shown by discontinuity 21. Above Dmax, converter 1 turns on the high-side MOSFET 3 and leaves it on for the entire period T. The abrupt transition 21 causes a glitch in the output voltage of converter 1. Moreover, at a 100% duty factor, Vout=Vin, as shown by line 16, and all regulation is lost as long as the switching is halted.

Synchronous boost converter 10 shown in <figref idrefs="DRAWINGS">FIG. 1B</figref> includes a low-side power MOSFET 12, a battery connected inductor 13, an output capacitor 15, and a “floating” synchronous rectifier MOSFET 14 with a parallel rectifier diode 16. The gates of the MOSFETs 12 and 14 are driven by break-before-make circuitry (not shown) and controlled by a PWM controller 11 in response to voltage feedback VFB from the output of converter 10, which is present across filter capacitor 15. BBM operation is needed to prevent shorting out filter capacitor 15.

The synchronous rectifier MOSFET 14, which may be an N-channel or a P-channel MOSFET, is considered “floating” in the sense that neith its source nor its drain terminal is permanently connected to any supply rail, i.e. to ground or Vbatt. Diode 16 is a P-N diode intrinsic to synchronous rectifier MOSFET 14, regardless of whether synchronous rectifier MOSFET 14 is a P-channel or an N-channel device. A Schottky diode may be included in parallel with MOSFET 16 but with series inductance may not operate fast enough to divert current from forward-biased intrinsic diode 16. Diode 17 is a P-N junction diode intrinsic to N-channel low-side MOSFET 12 and remains reverse-biased under normal operation. Since diode 17 does not conduct under normal operation, it is shown as dotted lines.

If we again define the duty factor D as the time that energy flows from the battery or power source into DC/DC converter 10, i.e. the time during which low-side MOSFET switch is on and inductor 13 is being magnetized, then the output-to-input voltage ratio of boost converter 10 is equal to the inverse of 1 minus its duty factor, i.e.

This relationship for a boost or synchronous boost converter is illustrated by curve 18 in <figref idrefs="DRAWINGS">FIG. 2A</figref> also in graph 15. Notice that boost converter 10 cannot smoothly reach a unity transfer characteristic without exhibiting some discontinuity at the lower extreme of D. This phenomenon occurs due to switching delays in the power MOSFET 12 and its control and gate drive circuitry.

As long as power MOSFET 12 of boost converter 10 is still switching, tsw is limited to some portion of the clock period T, e.g. 5%<D<95%, essentially due to turn-on and turn-off delay within MOSFET 12 and its control loop. For example at a 5% duty factor and a 3 MHz clock frequency, the off time for MOSFET 12 is only 5% of the 333 nsec period, or just 16 nsec. This means that MOSFET 12 must turn on and back off in only 16 nsec—too rapidly to regulate below a 5% output-to-input conversion ratio. The minimum on time problem impacts both synchronous and non-synchronous boost converters.

Referring again to graph 15 in <figref idrefs="DRAWINGS">FIG. 2A</figref>, below some minimum duty factor Dmin, there is not adequate time to maintain switching operation and converter 10 must jump from Dmin to 0% duty factor, as shown by discontinuity 20. Below Dmin, converter 10 turns on the synchronous rectifier MOSFET 14 and leaves it on for the entire period T. The abrupt transition 20 causes a glitch in the output voltage of boost converter 10. Moreover, at a 100% duty factor, Vout=Vin, as shown by line 16, all regulation is lost as long as the switching is halted.

So in both synchronous Buck converter 1 and synchronous boost converter 10, operating near a unity transfer characteristic, i.e. when Vout≈Vin, shown by line 16, is problematic.

The efficiency η of a voltage converter can be given by

An analysis of inductive switching converter efficiencies is provided in the above-referenced application Ser. No. 11/890,818.

Graph 25 of <figref idrefs="DRAWINGS">FIG. 2B</figref> illustrates examples of typical conversion efficiencies for synchronous Buck and synchronous boost converters as a function of the converter's voltage conversion ratio Vout/Vin. As shown, line 26 illustrates the unity conversion condition, where Vout=Vin. Conversion ratios less than unity, on the left side of line 26, represent step-down conversion. Efficiency curve 27 represents an example of a Buck converter performing step-down voltage conversion. Conversion ratios greater than unity, on the right side of line 26, represent step-up conversion. Efficiency curve 28 represents an example of a boost converter performing step-up voltage conversion.

In general, boost converters exhibit lower efficiencies than Buck converters for comparable load currents, as illustrated by curves 27 and 28, primarily due to the fact that boost converters exhibit higher peak currents than Buck converters. This problem is further accentuated for high Vout/Vin voltage conversion ratios, especially for output voltages approaching ten times the input voltage, as illustrated by the decline of curve 28 with increasing conversion ratios.

Furthermore, in graph 25, efficiency curve 27 for Buck converters is not shown for conversion ratios below 0.1 and above 0.9 and likewise efficiency curve 29 for boost converters is not shown for conversion ratios below 1.1 and above 10, because it requires operation at a duty factor of below 10% or above 90%, an operating condition difficult to achieve, especially at high switching frequencies.

Buck-Boost Switching Converter (Prior Art)

The problem of non-isolated DC/DC switching converter operation near unity transfer is especially difficult in applications when the input voltage may vary above or below the desired output voltage. Examples of this application include the output of noisy AC adapters or in circuitry which must operate as a battery back-up during emergency conditions when a main source of power has failed.

Another scenario where a unity conversion ratio is required occurs when a battery's operating voltage range extends above and below the desired output voltage.

For example, the discharge of a Lilon battery starts at 4.2V at full charge, initially decays rapidly to around 3.6V, then decays slowly from 3.6V to 3.4V, and finally drops quickly to its cutoff at or below 3V. In the event that a DC/DC converter is needed to produce a well-regulated 3.3V output during this entire discharge period, a sub-unity conversion ratio of (3.3V/4.2V), i.e. a ratio of 0.79, is needed at the outset, indicating that a Buck converter is required. At the battery's end-of-life, the conversion ratio exceeds unity, becoming 3.3V/3V, i.e. a conversion ratio of 1.1, and this requires a boost converter to provide the desired 3.3V output voltage. Such an application demanding both step-up and step-down conversion requires a Buck-boost, or up-down converter.

In the case where the user wants to avoid the complexities of up-down conversion, one possible approach is to use only a Buck converter and give up some battery life by cutting the battery off early, e.g. at 3.3V. In practice, however, when considering battery manufacturing variations and converter drop-out and duty factor limitations, too much battery life is sacrificed to rely on a Buck-only converter solution.

If up-down conversion cannot be avoided, one possible solution involves Buck-boost conversion. A Buck-boost converter can easily be derived from combining synchronous Buck and boost converters into a merged circuit. In the circuit diagram of <figref idrefs="DRAWINGS">FIG. 3A</figref>, for example, a Buck-boost converter 35 comprises a synchronous Buck converter, comprising a P-channel or N-channel MOSFET 36, an inductor 38A, an N-channel synchronous rectifier MOSFET 37, an intrinsic rectifier diode 39, and a capacitor 44, is used to power a synchronous boost converter, comprising a low-side N-channel MOSFET 40, an inductor 38B, a synchronous rectifier MOSFET 41, an intrinsic rectifier diode 42, and a filter capacitor 43. Cascade Buck-boost converter 35 first steps down and regulates the input voltage to an intermediate voltage lower than the desired output voltage, and then steps this intermediate voltage up to produce Vout.

Conversely, in <figref idrefs="DRAWINGS">FIG. 3B</figref> a synchronous boost-Buck converter 45 comprises a boost converter, comprising a low-side N-channel MOSFET 46, an inductor 47, an N-channel or P-channel synchronous rectifier MOSFET 48A, an intrinsic diode 49, and a capacitor 54, which is used to power a synchronous Buck converter, comprising a MOSFET 48B, an inductor 52, an N-channel synchronous rectifier MOSFET 50, an intrinsic rectifier diode 51, and a filter capacitor 53, the combined cascade boost-Buck converter collectively driving a load (not shown). In this approach, the input voltage is first stepped-up to an intermediate voltage higher than the desired output voltage, and then is stepped back down to produce Vout.

The overall efficiency of either Buck-boost converter 35 or boost-Buck converter 45 is given by the product of the boost converter's efficiency ηboost multiplied by the Buck converter's efficiency ηBuck, mathematically as ηcascade=ηBuck*ηboost. Even if both converters are 85% efficient, the combined cascade converter reaches only a roughly 70% overall efficiency, significantly lower than the efficiency of a Buck converter or a boost converter operated alone. The overall loss in either a Buck-boost or boost-Buck cascade converter is worse than the loss in either a synchronous Buck converter or a synchronous boost converter, because there are more transistors in series between the input and output terminals, and because all the transistors are switching all the time.

As shown, boost-Buck converter 45 of <figref idrefs="DRAWINGS">FIG. 3B</figref> includes series-connected MOSFETs 48A and 48B with intermediate capacitor 54. Since in steady-state operation, the current in series-connected MOSFETs must be equal, MOSFET 48B is redundant and can be eliminated without impacting circuit operation. Even if this is done, boost-Buck converter 45 requires two inductors 47 and 52, a characteristic highly undesirable from a user's point-of-view.

Similarly, Buck-boost converter 35 of <figref idrefs="DRAWINGS">FIG. 3A</figref> includes inductors 38A and 38B with intermediate capacitor 44. Since in steady state operation the current in inductors 38A and 38B is the same, inductor 38B is redundant and may be eliminated without changing the function of the circuit. In fact, capacitor 44 may also be eliminated without significantly altering the operation of Buck-boost converter 35.

The resulting simplified Buck-boost converter 55, illustrated in <figref idrefs="DRAWINGS">FIG. 3C</figref>, comprises a single-inductor 59; four MOSFETs 57, 56, 60, and 61; diodes 58 and 62 and filter capacitor 63. The PWM control circuitry and break-before-make and gate buffer circuits are not shown. Depending on its terminal conditions, such a converter can operate in three distinct modes, Buck, boost, and Buck-boost.

In <figref idrefs="DRAWINGS">FIG. 3D</figref>, equivalent circuit diagram 65 represents the operation of Buck-boost converter 55 as a Buck converter, where MOSFETs 57 and 56 are switched out-of-phase under PWM control while MOSFET 61 remains turned-on, represented by resistor 67, and MOSFET 60 is turned off, represented by open circuit 66. The overall power loss in Buck-booster converter 55 is greater than in a synchronous Buck converter because it now includes the conduction loss in MOSFET 61, i.e. power lost continuously in resistor 67. As a result of this increased power loss, Buck-boost converter 55 operating in its Buck mode has a lower efficiency than conventional Buck converter 1 shown in <figref idrefs="DRAWINGS">FIG. 1A</figref>.

In <figref idrefs="DRAWINGS">FIG. 3E</figref>, equivalent circuit diagram 70 represents the operation of Buck-boost converter 55 as a boost converter, where MOSFETs 60 and 61 are switched out-of-phase under PWM control while MOSFET 57 remains turned-on, represented by resistor 71, and MOSFET 56 is turned off, represented by open circuit 72. The overall power loss in Buck-boost converter is greater than in a synchronous boost converter because it now includes the conduction loss in MOSFET 57, i.e. power lost continuously in resistor 71. As a result of this increased power loss, Buck-boost converter 55 operating in its boost mode has a lower efficiency than conventional boost converter 10 shown in <figref idrefs="DRAWINGS">FIG. 1B</figref>.

The loss of efficiency using Buck-boost converter 55 is illustrated in <figref idrefs="DRAWINGS">FIG. 4</figref> in the plot of efficiency η for various output-to-input voltage conversion ratios Vout/Vin. For convenience, the efficiency curves 27 and 28 from <figref idrefs="DRAWINGS">FIG. 2B</figref> for conventional Buck and boost converters are repeated as curves 81 and 82, respectively, in <figref idrefs="DRAWINGS">FIG. 4</figref>.

Curve 83 illustrates the efficiency of Buck-boost converter 55 operating in Buck-only mode, shown in equivalent circuit 65. Because of the series resistance associated with on-state MOSFET 61, the efficiency of Buck-boost converter 55 in the Buck only mode is lower than that of the simple Buck converter (curve 81). This loss of efficiency can range from a few percent to over 10%, depending on operating conditions. Curve 85 illustrates the efficiency of Buck-boost converter 55 operating in full Buck-boost mode where all four switches are switching constantly. In this mode Buck-boost converter 55 exhibits even greater losses and poorer efficiency than Buck-boost converter 55 operating in Buck mode (curve 83).

Curve 84 illustrates the efficiency of Buck-boost converter 55 operating in boost-only mode, shown in equivalent circuit 70. Because of the series resistance associated with on-state MOSFET 57, the efficiency of Buck-boost converter 55 in the boost-only mode is lower than that of a simple boost converter (curve 82). This loss of efficiency can range from a few percent to over 10%, depending on operating conditions. Curve 86 illustrates the efficiency of Buck-boost converter 55 operating in full Buck-boost mode, where all four MOSFETs are switching constantly. In this mode, Buck-boost converter 55 exhibits even greater losses and poorer efficiency than Buck-boost converter 55 operating in boost mode (curve 84).

Operating near unity conversion ratios, where the output voltage is slightly above or below its input voltage, i.e. where Vout≈Vin, Buck-boost converter 55 must operate in the Buck-boost mode, where all four MOSFETs are switching constantly. The resulting efficiency (curve 87) can be 10% to 20% lower than the efficiency of conventional Buck and boost converters (curves 81 and 82).

The efficiency penalty for a voltage converter to be able to operate over a wide range of voltage conversion ratios using the prior-art Buck-boost converter is substantial. Moreover, the converter must change its operating mode whenever operating near unity voltage conversion ratios.

Charge Pump Converters

An alternative to the switched-inductor converter is a charge pump, a voltage conversion circuit using only switches and capacitors to perform voltage translation through repeated charge redistribution, i.e. the continuous charging and discharging of a capacitor network driven by a clock or oscillator.

The advantage of a charge pump is that at specific voltage conversion ratios, it can exhibit extremely high conversion efficiencies approaching 100%. The disadvantage is that it can only efficiently generate voltages that are exact integer multiples of the number of flying capacitors used in its converter circuit. Voltages other than select multiples exhibit low efficiencies.

A common charge pump 90 is illustrated in <figref idrefs="DRAWINGS">FIG. 5A</figref> where a single capacitor 93 is employed as a “doubler”, i.e. to double the input voltage. Charge pump 90 comprises four MOSFETs, 92, 91, 94 and 95, configured in a manner similar to an H-bridge except that one terminal, the source of MOSFET 95 is connected to the output terminal and reservoir capacitor 96 rather than to ground.

Operation of charge pump 90 involves repeatedly charging and discharging flying capacitor 93. During the charging phase, diagonal MOSFETs 94 and 91 are closed, charging capacitor 93 to the voltage Vbatt while MOSFETs 92 and 95 remain open. Thereafter, in the charge transfer phase, MOSFETs 94 and 91 are opened, MOSFETs 92 and 95 are closed, and energy is transferred from the flying capacitor 93 to the output reservoir capacitor 96, pumping the output voltage VCP to a value twice the battery voltage or 2·Vbatt

The purpose of the MOSFET switch network is essentially to place the flying capacitor in parallel with the battery during the charging phase and in series, i.e. stacked on top of the battery's positive terminal, during the charge transfer phase, as illustrated by equivalent circuit 100 in <figref idrefs="DRAWINGS">FIG. 5B</figref>. In <figref idrefs="DRAWINGS">FIG. 5B</figref>, a voltage source 101 represents the battery input and a capacitor 102 charged to Vbatt represents flying capacitor 93. By stacking the voltages across voltage source 101 and capacitor 102 atop one another, the output voltage of the charge pump is the sum of the voltages, hence doubling the voltage input. The cycle then repeats with another charging phase.

<figref idrefs="DRAWINGS">FIG. 5C</figref> illustrates a charge pump 110 utilizing two flying capacitors 114 and 115 and a network of seven MOSFETs 111, 112, 113, 116, 117, 118 and 119. The purpose of the MOSFET switching network is to charge capacitors 114 and 115 in series, thereby charging each capacitor to one-half the battery voltage, i.e. Vbatt/2. During the charging of capacitors 114 and 115, MOSFETs 111, 112 and 113 are on and MOSFETs 116, 117, 118 and 119 are off. After the charging phase, the charged capacitors 114 and 115 are connected in parallel, and connected to the positive terminal of the battery. This connection is accomplished by turning on MOSFETs 116, 117, 118 and 119 and turning off MOSFETs 111, 112 and 113. The resulting output voltage, shown in equivalent circuit 121 of <figref idrefs="DRAWINGS">FIG. 5D</figref>, is equal to Vbatt+Vbatt/2, or 1.5Vbatt, as illustrated by battery voltage source 124 and the parallel combination of capacitors 122 and 123 stacked atop one another. Because the output voltage is equal to 1.5 times the input voltage, this charge pump is sometimes referred to as a “fractional” charge pump.

Actually, many different charge pump topologies are possible, but most use only one or two flying capacitors. A single flying capacitor charge pump is capable of efficiently delivering power at an output voltage equal to twice its input voltage, or alternatively, if during the charge transfer phase the capacitor is connected to the negative terminal of the battery an output voltage that is a mirror-image negative voltage of the battery, i.e. −Vbatt. In the latter configuration the charge pump is also known as an inverter. The inverter case is illustrated in equivalent circuit 130 of <figref idrefs="DRAWINGS">FIG. 5E</figref>, where the battery, represented by a voltage source 131, is used to charge a capacitor 132, and then, during the charge transfer phase, the positive terminal of capacitor 132 is connected to ground, i.e. the negative terminal of battery 131. Two-capacitor, fractional charge pumps may also be used to produce an output voltage equal to one-half the input voltage, as shown in equivalent circuit 135 of <figref idrefs="DRAWINGS">FIG. 5F</figref> where each of capacitors 137 and 138 are initially charged to one-half of the voltage Bbatt provided by voltage source 136 are then referenced to the negative battery potential (ground) to provide a positive potential equal to +0.5Vbatt, as shown, or alternatively to provide a negative, inverted potential equal to −0.5Vbatt (not shown).

One problem with charge pump converters is they operate efficiently only at conversion ratios equal to integral multiples of the number of flying capacitors; in other words, they are not true voltage converters. Specifically, if a desired load voltage Vout is below the voltage VCP that the capacitor network produces, the converter cannot adapt. To obtain a voltage-differential between the charge pump's output voltage VCP and the output voltage of the converter Vout requires a resistor or current source to support the voltage mismatch, and the voltage across that lossy element results in lost power and reduced efficiency. An analysis of charge pump efficiencies is described in application Ser. No. 11/890,941, titled “High-Efficiency DC/DC Voltage Converter Including Capacitive Switching Pre-Converter And Up Inductive Switching Post-Regulator,” filed contemporaneously herewith and incorporated herein by reference.

The efficiency of single-mode charge pumps is illustrated in graph 150 of <figref idrefs="DRAWINGS">FIG. 6A</figref> for charge pumps having various multipliers, including a doubler (curve 151), an inverter (curve 152), and fractional charge pumps (curves 153, 154 and 155). Curve 156 represents a direct battery connection, identical to a linear converter's maximum theoretical efficiency, i.e. assuming no quiescent operating current. In each case, as the input to output ratio approaches an integer multiple of ±½Vbatt, the efficiency increases. The charge pump is not capable of delivering an output voltage above that voltage, and to obtain a higher output voltage a charge pump having a different voltage multiplier, i.e. a different operating mode, must be employed.

Each curve shown in graph 150 represents a specific charge pump circuit, e.g. including those shown previously in <figref idrefs="DRAWINGS">FIGS. 5A-5F</figref>. Unless a load operates at an exact half-volt integral multiple of the input voltage, however, the efficiency of the charge pump converter using one or two capacitors will suffer. This behavior is especially problematic for battery powered products where the battery voltage changes markedly as the cell discharges. In the case of Lilon batteries, for example, the voltage can decay more than 1V during discharge, representing a 25% change. Therefore, even if the peak efficiency may be high at one specific operating condition and battery voltage, the overall efficiency of the converter averaged over the battery discharge curve is poor. Weighted average efficiencies can be lower than 60% using a single-mode charge pump.

One way to improve the average efficiency of a charge pump voltage converter is to switch modes between 1X, 1.5X and 2X automatically within one circuit. This feature is particularly useful to supply a fixed voltage over a wide input range. The efficiency of a mode-changing charge pump is illustrated in <figref idrefs="DRAWINGS">FIG. 6B</figref>, where as the battery decays the tri-mode converter circuit switches from 1X-battery-direct mode having an efficiency shown by curve 163, to a 1.5X-fractional-mode with efficiency shown by curve 162, and again to 2X-doubler-mode having an efficiency shown by curve 161. By switching modes in this zigzag pattern, the efficiency of the charge pump converter is improved because the output is not pumped to an excessively high value compared to the load.

Unfortunately, conditions still exist where the efficiency suffers substantially. The mode transitions exhibit dramatic shifts in efficiency (curve 163) at a conversion ratio of one, and again for curve 162 at a 1.5X conversation ratio. The mode transitions may also result in sudden current and voltage discontinuities, or produce instability or noise. To determine what conversion ratio is required, graph 160 also includes curves 166, 165, and 164 relating the required input voltage range (right hand axis) and conversion ratios to produce an output voltage of 3V, 3.5V and 4V, respectively.

Specifically, the charge pump converter in 1.5X mode does not perform well at conditions slightly above a unity conversion ratio, unfortunately manifesting even lower efficiencies than the above-mentioned inductive Buck-boost converter.

Dropout in Prior Art converters

Whenever the input voltage and the output voltage of a voltage converter approach one another within the range of several hundred milli-volts, e.g. Vout=Vin±200 mV, the quality of the converter's regulating ability suffers. Loss of regulation quality may be manifest in several ways, either by a one-time or repeated glitch or discontinuity in output voltage, by increased ripple, or by complete loss of regulation within some narrow voltage band. The phenomenon of degraded regulation whenever Vout approaches Vin is referred to as “dropout”, meaning the converter drops out of regulation.

The Buck converter of <figref idrefs="DRAWINGS">FIG. 1A</figref> and the boost converter of <figref idrefs="DRAWINGS">FIG. 1B</figref> both momentarily lose regulation as their switching duty factor jumps from Dmax or Dmin to 100% and they lose regulation completely while D=100%, since the input is essentially resistively connected to the output during the dropout condition.

While a Buck-boost converter does not exhibit permanent dropout, it can easily suffer a voltage glitch during mode transitions, whenever the converter switches its Buck mode to its Buck-boost mode, or from its Buck-boost mode to its boost mode. Mode transitions occur whenever the converter changes from a circuit having two power devices switching into one where four devices are switching, or vice versa.

To avoid the mode switching transition problem, a Buck-boost converter can be run continuously in Buck-boost mode with all four power devices switching continuously, but as shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, its efficiency is then degraded under all input-output conditions and conversion ratios.

As stated above, a charge pump is incapable of regulating voltage without the use of a series-connected linear converter to provide the regulation function. Unfortunately, it is a well known phenomenon that all linear converters exhibit loss of regulation, i.e. dropout, whenever ΔV across their input and output terminals becomes too small. In essence, dropout occurs in a linear converter because the loop gain of the amplifier performing regulation drops precipitously as its transistor pass element changes from acting as a current source to acting as a variable resistor. If the pass element is a bipolar transistor, the loss of gain occurs at small values of VCE as the device transitions from its active operating region into saturation. In many bipolar linear converters, this dropout condition occurs at more than 400 mV.

In so-called “low dropout” linear converters or “LDOs”, a MOSFET capable of operating as a current source at a lower ΔV is substituted for the bipolar pass element, but the linear converter still drops out at 200 to 300 mV as the power MOSFET pass element transitions from its saturation, i.e. constant current, region into its linear, i.e. resistive, region of operation.

In conclusion, prior-art non-isolated high-efficiency converters exhibit dropout at voltage conversion ratios approaching unity. Mode switching, loss of regulation and dropout can be avoided only by sacrificing efficiency. Isolated converters such as flyback and forward converters are able to operate at high efficiencies near unity conversion without the need switching modes, but their use of physically-large tapped inductors, coupled inductors, and transformers precludes their application in most portable products.

Summary of Prior-Art Down-Up Converters

In conclusion, no existing charge pump converter, Buck-boost switching converter or other inductive switching converter is able to both step-up and step-down DC voltages efficiently, especially for conversion ratios near unity where Vin≈Vout. What is needed is an up-down converter that is efficient over a wide range of input and output voltages, and that does not need to change its operating mode as it operates near a unity voltage conversion ratio, i.e. when Vout≈Vin. Furthermore, the converter should be free from dropout problems, maintaining high-quality regulation even while biased with an output voltage within 200 mV of its input, i.e. within the range Vout=Vin±200 mV.

SUMMARY OF THE INVENTION

A DC/DC voltage converter according to this invention includes a pre-converter and a post-regulator. The pre-converter includes a switched capacitive circuit: and a post-regulator includes a switched inductive circuit. An output terminal of the pre-converter is coupled to an input terminal of the post-regulator. An input terminal of the pre-converter comprises an input terminal of the DC/DC voltage converter, and an output terminal of the post-regulator comprises an output terminal of the DC/DC voltage converter. In many embodiments the pre-converter includes a charge pump and the post-regulator includes a Buck converter.

Within this broad structure, many variations are possible within the scope of the invention. In one group of embodiments, the pre-converter includes a voltage-reducing fractional charge pump and the post-regulator includes a Buck converter. In another group of embodiments, the pre-converter includes a voltage-increasing charge pump and the post-regulator includes a Buck converter. In another group of embodiments, the pre-converter includes a voltage-inverting charge pump and the post-regulator includes a Buck converter.

DC/DC converters according to this invention are capable of operating over a wide range of voltage conversion ratios ranging from step-up to step-down conversion without the need for mode switching. Free from mode switching and dropout problems when Vout≈Vin, the converter does not suffer from noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios. While the converter includes switched inductor operation, it avoids the minimum pulse width problem plaguing conventional switching converters at very high and very low duty factors, including converter dropout, narrow pulses and associated high-current spikes, variable frequency operation, inadequate time to perform break-before-make transitions. In contrast, prior-art non-isolated DC/DC converters suffer from one or more of the aforementioned problems at extreme duty factors, and their use near unity voltage conversion ratios remains problematic.

The method and apparatus of this invention can be used in applications requiring up-down conversion, and avoid the problems of existing Buck-boost and flyback converters. While preferred embodiments of this invention specifically address the implementation of up-down converters, variants include improved down-only converters and DC/DC inverters capable of producing negative, i.e. below ground, supply voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1A</figref> shows a circuit diagram of a conventional synchronous Buck converter.

<figref idrefs="DRAWINGS">FIG. 1B</figref> shows a circuit diagram of a conventional synchronous boost converter

<figref idrefs="DRAWINGS">FIG. 2A</figref> is a graph of voltage conversion ratio versus duty factor for conventional Buck and boost converters.

<figref idrefs="DRAWINGS">FIG. 2B</figref> is a graph of efficiency versus voltage conversion ratio for conventional Buck and boost converters.

<figref idrefs="DRAWINGS">FIG. 3A</figref> is a circuit diagram of a cascaded Buck-boost converter.

<figref idrefs="DRAWINGS">FIG. 3B</figref> is a circuit diagram of a cascaded boost-Buck converter.

<figref idrefs="DRAWINGS">FIG. 3C</figref> is a circuit diagram of a Buck boost converter.

<figref idrefs="DRAWINGS">FIG. 3D</figref> is an equivalent circuit diagram of a Buck-boost converter in Buck-only mode.

<figref idrefs="DRAWINGS">FIG. 3E</figref> is an equivalent circuit diagram of a Buck-boost converter in boost-only mode.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a graph of efficiency versus the voltage conversion ratio for a Buck converter, a boost converter, and Buck-boost converter.

<figref idrefs="DRAWINGS">FIG. 5A</figref> is a circuit diagram of a 2X doubler circuit.

<figref idrefs="DRAWINGS">FIG. 5B</figref> is an equivalent circuit diagram of the doubler circuit during discharge.

<figref idrefs="DRAWINGS">FIG. 5C</figref> is a circuit diagram of a 1.5X fractional circuit.

<figref idrefs="DRAWINGS">FIG. 5D</figref> is an equivalent circuit diagram of the 1.5X circuit during discharge.

<figref idrefs="DRAWINGS">FIG. 5E</figref> is an equivalent circuit diagram of a −X inverter circuit during discharge.

<figref idrefs="DRAWINGS">FIG. 5F</figref> is an equivalent circuit diagram of a 0.5X circuit during discharge.

<figref idrefs="DRAWINGS">FIG. 6A</figref> is a graph of efficiency versus voltage conversion ratio for single-mode charge pumps.

<figref idrefs="DRAWINGS">FIG. 6B</figref> is a graph of efficiency versus voltage conversion ratio for a tri-mode charge pump.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a graph of voltage conversion ratio versus input voltage for various output voltages in a DC/DC converter.

<figref idrefs="DRAWINGS">FIG. 8</figref> is a generalized schematic circuit diagram of a switched CLXD converter according to the invention.

<figref idrefs="DRAWINGS">FIG. 9</figref> is a circuit diagram of a behavioral model of the switched CLXD converter.

<figref idrefs="DRAWINGS">FIG. 10</figref> is a functional circuit diagram of a CLDD converter having a 0.5X pre-converter.

<figref idrefs="DRAWINGS">FIG. 11A</figref> is a functional circuit diagram of a CLUD converter having a 2X pre-converter.

<figref idrefs="DRAWINGS">FIG. 11B</figref> is a functional circuit diagram of a CLUD converter having a 1.5X pre-converter.

<figref idrefs="DRAWINGS">FIG. 12A</figref> is a graph of transfer characteristics of a 2X-type CLUD converter over an input voltage in the range of 2V to 5V.

<figref idrefs="DRAWINGS">FIG. 12B</figref> is a graph of the transfer characteristics of a 2X-type CLUD converter supplied by a 1-cell Lilon battery as a function of time.

<figref idrefs="DRAWINGS">FIG. 12C</figref> is a graph of the transfer characteristics of a 1.5X-type CLUD converter supplied by a 1-cell Lilon battery as a function of time.

<figref idrefs="DRAWINGS">FIG. 12D</figref> is a graph of the transfer characteristics of a 1.5X-type CLUD converter over an input voltage in the range of 2V to 5V.

<figref idrefs="DRAWINGS">FIG. 12E</figref> is a graph of Vout/Vin as a function of duty factor for 2X and 1.5X converters.

<figref idrefs="DRAWINGS">FIG. 13A</figref> is a circuit diagram of a 2X CLUD converter.

<figref idrefs="DRAWINGS">FIG. 13B</figref> is a circuit diagram of a simplified 2X CLUD converter.

<figref idrefs="DRAWINGS">FIG. 13C</figref> is an equivalent circuit diagram of the 2X CLUD converter during the charging and recirculation phase.

<figref idrefs="DRAWINGS">FIG. 13D</figref> is an equivalent circuit diagram of the 2X CLUD converter during the transfer and magnetizing phase.

<figref idrefs="DRAWINGS">FIG. 14A</figref> is a circuit diagram of a 1.5X CLUD converter.

<figref idrefs="DRAWINGS">FIG. 14B</figref> is a circuit diagram of a simplified 1.5X CLUD converter.

<figref idrefs="DRAWINGS">FIG. 14C</figref> is an equivalent circuit diagram of the 1.5X CLUD converter during the charging and recirculation phase.

<figref idrefs="DRAWINGS">FIG. 14D</figref> is an equivalent circuit diagram of the 1.5X CLUD converter during the transfer and magnetizing phase.

<figref idrefs="DRAWINGS">FIG. 15</figref> is a functional circuit diagram of a CLDD converter having a 0.5X pre-converter.

<figref idrefs="DRAWINGS">FIG. 16A</figref> is a graph of the transfer characteristics of a switched 0.5X-type CLDD converter over an input voltage in the range of 2V to 5V.

<figref idrefs="DRAWINGS">FIG. 16B</figref> is a graph of the transfer characteristics of a switched 0.5X-type CLDD converter supplied by a 1-cell Lilon battery as a function of time.

<figref idrefs="DRAWINGS">FIG. 16C</figref> is a graph of Vout/Vin as a function of duty factor for the 0.5X-type CLDD converter.

<figref idrefs="DRAWINGS">FIG. 17A</figref> is a circuit diagram of a 0.5X CLDD converter.

<figref idrefs="DRAWINGS">FIG. 17B</figref> is a circuit diagram of a simplified 0.5X CLDD converter.

<figref idrefs="DRAWINGS">FIG. 17C</figref> is an equivalent circuit diagram of the 0.5X CLDD converter during the charging and recirculation phase.

<figref idrefs="DRAWINGS">FIG. 17D</figref> is an equivalent circuit diagram of the 0.5X CLDD converter during the transfer and magnetizing phase.

<figref idrefs="DRAWINGS">FIG. 18A</figref> is a functional circuit diagram of a CLID converter having a −1X pre-converter.

<figref idrefs="DRAWINGS">FIG. 18B</figref> is a functional circuit diagram of a CLID converter having a −0.5X pre-converter.

<figref idrefs="DRAWINGS">FIG. 19A</figref> is a graph of the transfer characteristics of a switched −1X-type CLID converter over an input voltage in the range of 2V to 5V.

<figref idrefs="DRAWINGS">FIG. 19B</figref> is a graph of the transfer characteristics of a switched −1X-type CLID converter supplied by a 1-cell Lilon battery as a function of time.

<figref idrefs="DRAWINGS">FIG. 19C</figref> is a graph of the transfer characteristics of a switched −0.5X-type CLID converter over an input voltage in the range of 2V to 5V.

<figref idrefs="DRAWINGS">FIG. 19D</figref> is a graph of the transfer characteristics of a switched −0.5X-type CLID converter supplied by a 1-cell Lilon battery as a function of time.

<figref idrefs="DRAWINGS">FIG. 19E</figref> is a graph of Vout/Vin as a function of duty factor for CLID converters having-1X-type and −0.5-type pre-converters.

<figref idrefs="DRAWINGS">FIG. 20A</figref> is a circuit diagram of a −1X CLID converter.

<figref idrefs="DRAWINGS">FIG. 20B</figref> is a circuit diagram of a simplified −1X CLID converter.

<figref idrefs="DRAWINGS">FIG. 20C</figref> is an equivalent circuit diagram of the −1X CLID converter during the charging and recirculation phase.

<figref idrefs="DRAWINGS">FIG. 20D</figref> is an equivalent circuit diagram of the −1X CLID converter during the transfer and magnetizing phase.

<figref idrefs="DRAWINGS">FIG. 21A</figref> is a circuit diagram of a −0.5X CLID converter.

<figref idrefs="DRAWINGS">FIG. 21B</figref> is an equivalent circuit diagram of the −0.5X CLID converter during the charging and recirculation phase.

<figref idrefs="DRAWINGS">FIG. 21C</figref> is an equivalent circuit diagram of the −0.5X CLID converter during the transfer and magnetizing phase.

DESCRIPTION OF THE INVENTION

<figref idrefs="DRAWINGS">FIG. 7</figref> graphically illustrates the requisite voltage conversion ratio Vout/Vin of a DC/DC converter operating at a variety of voltage outputs and for inputs ranging from 1.8V to 6.6V. Curve 181 illustrates that for a 4.5V to 5.5V input range, regulating a 5V output to ±1% accuracy requires operation above and below a unity conversion ratio, meaning an up-down regulating converter is required to hold a tighter tolerance than the ±5% or ±10% accuracy commonly guaranteed by conventional AC/DC wall adapters.

Up-down conversion is also required when using a lithium ion battery to produce a voltage intermediate to its wide voltage range. As examples, curves 182, 183, 184 in <figref idrefs="DRAWINGS">FIG. 7</figref> illustrate outputs at 4V, 3.6V, and 3.3V respectively. Since these load voltages fall within the Lilon battery's normal discharge voltage range of 4.2V to 3V, the converter must regulate in step-down mode, with a voltage conversion ratio below unity at the beginning of the cell's discharge cycle, and in step-up mode, with a conversion ratio above unity later as the cell voltage decays.

Curve 185 illustrates a 3V output which theoretically should require only step-down conversion, but because of the above-mentioned problem of dropout, a Lilon battery supplying a 3V output must cut off above 3.2V, thereby wasting useful battery life. New generation Lilon cells under development may allow operation down to 2.7V, requiring the need to utilize up-down conversion for 2.7 V outputs, as shown by curve 186. At a 2.5V battery condition, dropout issues may also require the use of an up-down converter even to supply a regulated 2.5V output, as shown by curve 187. If, however, up-down conversion results in a loss of efficiency exceeding the extra operating time gained by the extended battery range, then the user lifetime benefit of using a battery capable of lower voltage operation is lost entirely.

Similarly, dropout concerns make it difficult to guarantee a 1.8V regulated output shown by curve 188 from 2-cell-connected nickel-metal-hydride or nickel-cadmium, i.e. NiMH or NiCd, batteries since those their outputs range from 2.4V down to 1.8V. Stopping usage at a 2V battery condition unacceptably wastes more than half the battery's charge life.

Another situation needing an efficient low-dropout up-down converter is the use of power supplies designed to work off two NiMH dry-cells, two alkaline cells, or a single cell Lilon battery. Since the output voltage of 2-series-cell NiMH battery packs ranges from 1.8V to 2.4V, the output voltage of 2-series-cell alkaline batteries ranges from 1.8V up to 3.4V during charging, and the output of a single-cell Lilon battery ranges from 4.2V down to 3V or even 2.7V, then any output between 4.2V and 1.8V needs an up-down converter to maximize efficiency and battery life, as shown by curves 182 through 188.

If we also consider that some systems allow the DC output from the AC/DC wall adapter to be connected without a battery present, the input voltage supplied to a system's DC/DC converter input can be considerably higher than if the battery were present, and may reach as high as 6.5V. When the battery is present and the charger disconnected, the input voltage may be as low as 1.8V. In such cases, every output curve ranging from curve 181 to curve 188, i.e. from 5V down to a 1.8V output, requires an up-down converter.

Today, most electrical loads are supplied by an up-only or down-only converter, requiring the battery to be cut off prematurely to avoid the need for up-down conversion, even at the expense of wasting usable stored charge in the battery. Up-down conversion is typically avoided at all costs except in extreme situations. With the poor efficiency, mode switching, noise glitches, regulation dropout, and poor regulation offered by existing up-down converters, be they DC/DC converters, charge pumps, or linear converters; a widespread requirement up-down conversion and regulation is extremely problematic. Present up-down converters cannot meet the needs of today's efficiency-focused consumer marketplace.

A New DC/DC Converter Topology

This invention provides a new non-isolated DC/DC converter and voltage regulation topology capable of operating over a wide range of voltage conversion ratios ranging from step-up to step-down conversion, without the need for mode switching. Free from mode switching and dropout problems when Vout≈Vin, the converter does not suffer from noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios. While the converter includes switched inductor operation, it avoids the minimum pulse width problem plaguing conventional switching converters at very high and very low duty factors, including converter dropout, narrow pulses and associated high-current spikes, variable frequency operation, inadequate time to perform break-before-make switching, and more. In contrast, prior-art non-isolated DC/DC converters suffer one or more of these problems at extreme duty factors, and their use near unity voltage conversion ratios remains problematic.

The method and apparatus of this invention can be used in applications requiring up-down conversion and avoids the problems of existing Buck-boost and flyback converters. While preferred embodiments of this invention specifically address the implementation of up-down converters, variants include improved down-only regulating converters and DC/DC inverters capable of producing negative, i.e. below ground, supply voltages.

Collectively, the new DC/DC converters described herein comprise three new converter topologies and variants thereof, referred to herein by acronym as <ul><li id="ul0001-0001" num="0000"><ul><li id="ul0002-0001" num="0146">CLUD—switched capacitor-inductor up-down converter</li><li id="ul0002-0002" num="0147">CLDD—switched capacitor-inductor down-down converter</li><li id="ul0002-0003" num="0148">CLID—switched capacitor-inductor inverting-down converter (inverter)</li></ul></li></ul>

Specifically, this invention focuses on switched capacitor-inductor regulating converters comprising a switched-capacitor step-up, step-down, or inverting pre-converter feeding an inductively implemented step-down post-regulator. As a matter of nomenclature, the first C in the acronym represents the capacitive energy storage element in the pre-converter and the L represents the energy storage element, i.e. the coil or inductor, in the converter's second, or post-regulator, stage.

The third character in the converter's name, either: D, U or I, describes whether the pre-converter is stepping the input or battery voltage down or up or inverting the input voltage, respectively, before supplying it to the post regulator. The last character D describes the post-regulator as a step-down converter, meaning the magnitude of the voltage is decreased without changing its polarity. For example, “down” for a positive voltage means providing a smaller positive voltage, while “down” for a negative voltage, the output of an inverting pre-converter, means providing a negative voltage having a smaller absolute value, i.e. one closer to zero.

These topologies, described by the acronyms CLUD, CLDD, and CLID, vary in their utility for differing applications, and as such this new switched capacitor-inductor family of DC/DC converter topologies can be collectively described as CLXD converters, the X referring to a variable U for up, D for down, and I for inverting, respectively.

The above-referenced application Ser. No. 11/890,941 describes other switched inductor-capacitor converters comprising switched capacitor step-down, step-up, or inverting pre-conversion followed by a switched inductive step-up type post-regulator, and is herein incorporated by reference. Collectively these CLXU type regulating converters include the following: <ul><li id="ul0003-0001" num="0000"><ul><li id="ul0004-0001" num="0153">CLDU—switched capacitor-inductor up-down converter</li><li id="ul0004-0002" num="0154">CLUU—switched capacitor-inductor up-up converter</li><li id="ul0004-0003" num="0155">CLIU—switched capacitor-inductor inverting-up converter (inverter)</li><li id="ul0004-0004" num="0156">CLII—switched capacitor-inductor inverting-inverting converter</li></ul></li></ul>

The above-referenced application Ser. No. 11/890,818 and application Ser. No. 11/890,956, titled “High-Efficiency DC/DC Voltage Converter Including Up Inductive Switching Pre-Regulator And Capacitive Switching Post-Converter,” filed contemporaneously herewith and incorporated herein by reference, describe other switched inductor-capacitor converters designated LCXX, where pre-regulation is achieved by a switched inductor method and where post-conversion is accomplished by a switched capacitor stage.

Switched Capacitor-Inductor (CLXD) Converters

<figref idrefs="DRAWINGS">FIG. 8</figref> illustrates a switched CLXD regulating converter 200 comprising a switched-capacitor pre-converter 252 with a conversion ratio n supplying a voltage Vy to a post-regulator 254 comprising a step-down-type switched inductor voltage converter, where the output voltage is further used as feedback to control the operating condition and output of the post-regulator. The output voltage Vy of pre-converter 252 thereby follows the input at an nX multiple for optimum efficiency while the post-regulator dynamically adjusts the output voltage to produce a well-regulated output at a desired voltage Vout.

In converter 200, a charge pump 201 in pre-converter 252 scales the input voltage Vbatt by a factor “n” to produce intermediate voltage Vy. Charge-pump 201, including a capacitor 202 and optionally a capacitor 203 or more, comprises a switched-capacitor network producing a variety of multipliers, including doubling, inverting, fractional, or fractional-inverting. The intermediate node biased at the voltage Vy, the input to the step-down switched inductor post-regulator 254, may also include a filter capacitor 204 and optionally a diode with a grounded anode (not shown).

Within converter 200, switched-inductor post-regulator 254 comprises a PWM controller 212, a break-before-make (BBM) gate buffer 211, a high-side power MOSFET 205, a low-side synchronous rectifier N-channel power MOSFET 206 with an intrinsic PN diode 207, and an inductor 208. High-side MOSFET 205 may be either an N- or a P-channel MOSFET with appropriate adjustments in gate drive voltage waveforms coming from BBM buffer 211. Filter capacitor 209 is connected across the output terminal of converter 200 to insure stability, reduce ripple, and improve transient response. In this embodiment of the invention, the step-up switched-inductor post-regulator 254 is topologically configured as a synchronous Buck converter, although any step-down switched inductor DC/DC converter may be used. For example, MOSFET 206 may be eliminated and diode 207 may be replaced by a Schottky rectifier to implement a conventional Buck converter in lieu of the synchronous Buck converter shown, or a coupled or tapped inductor may be used to implement a flyback or forward converter.

PWM controller 212 controls the on-time of high-side MOSFET 205 by varying a duty factor D in response to feedback voltage VFBin at the input terminal of PWM controller 212, operating at a fixed frequency φ as determined by a ramp generator clock 214. Alternatively, PWM controller 212 may operate at a variable frequency to produce either a fixed or variable on-time for high-side MOSFET 205.

Whenever high-side MOSFET 205 is on, current flows from the output terminal of pre-converter 252 through inductor 208. Inductor 208 is thereby magnetized, storing energy in the amount equal to ½LI2 and resisting any rapid changes in current. At the switching frequency φ, the current in inductor 208 cannot react to the rapid switching of MOSFET 205, so that inductor 208 behaves as a nearly lossless current source, whose average current changes slowly, over many clock cycles in response to the pulse widths, as modulated by PWM controller 212.

Whenever high-side MOSFET 205 is not conducting, inductor 208 drives the voltage Vx below ground, forward biasing diode 207 and allowing current in inductor 208 to flow uninterruptedly, i.e. to recirculate. With MOSFETs 205 and 206 off, the power dissipated in diode 207 is IL·Vf, where Vf is the forward voltage across P-N junction diode 207. Low-side rectifier MOSFET 206 conducts all or some portion of the time when high-side MOSFET 205 is off, shunting diode 207 and redirecting the recirculation current through the channel of low-side MOSFET 206. Since MOSFET 206 only conducts when rectifier diode 207 is conducting, it operates as a “synchronous” rectifier, even if MOSFET 205 conducts occurs only during a portion of the time when diode 207 conducts. During conduction, the voltage drop across the synchronous rectifier MOSFET 206 is given by IL·RDS(on) and its instantaneous power dissipation is IL2·RDS(on).

Break-before make buffer 211 insures that low-side N-channel power MOSFET 206 and high-side power MOSFET 205 never conduct simultaneously to prevent shoot-through conduction, shorting out the load. Shoot-through conduction, the crow barring of the input voltage from overlapping conduction, is an undesirable condition leading to wasted power, loss in efficiency, and potentially resulting in MOSFET device damage. While BBM intervals must be sufficiently long to prevent shoot-through, excessively long BBM intervals are, however, also undesirable since they force diode 207 to carry current for longer times and to dissipate more power.

Except for the BBM period, synchronous rectifier MOSFET 206 ideally should be turned on and conducting whenever high-side MOSFET 205 is off. In some circumstances, however, it may be advantageous to turn off the synchronous rectifier MOSFET 206 prematurely or not to turn it on at all. For example, at very low output currents, unwanted oscillations and reverse current flow may occur if MOSFET 206 is left on for an extended duration. Shutting MOSFET 206 off disables channel conduction, and diode 207, under a reverse bias condition, prevents reverse current conduction, improving the light load efficiency of converter 200.

Alternatively, as described in application Ser. No. 11/890,947, titled “Low-Noise DC/DC Converter With Controlled Diode Conduction,” filed contemporaneously herewith and incorporated herein by reference, synchronous rectifier MOSFET 206 may remain on, but controlled in a manner to limit the magnitude of its drain current when it is not being operated as a fully-on device. Alternating MOSFET 206 between a resistive switch state and a low-current constant-current mode reduces the electrical noise in converter 200.

Examining converter 200 in greater detail, charge pump 201 converts the input voltage Vbatt to an intermediate node voltage Vy=n·Vin using a switched capacitor network with flying capacitor 202 and optionally a second flying capacitor 203. The conversion ratio nX of charge pump 201 may be step-up, step down, or inverting.

In the event that pre-converter 252 is a step-up converter, e.g., a doubler or dual-capacitor fractional version where n=2 or n=1.5, DC-DC converter 200 operates as a CLUD up-down converter, which may step-up or step-down the input voltage. In this configuration, converter 200 can also regulate at unity voltage conversion ratios, i.e. where Vout≈Vin.

Step-down conversion in pre-converter 252, using a fractional charge pump 201 where, for example, n=0.5, results in a CLDD converter. CLDD converters can achieve high step-down conversion ratios while maintaining a duty factor much closer to 50% than simple inductive boost converters.

Inverting pre-conversion may utilize a single capacitor circuit where n=−1 or utilize two capacitors when n=−0.5 to produce a negative voltage. Connecting the output of an inverting pre-converter to the input of a post-regulator comprising a non-inverting inductive Buck converter, results in an output voltage that is smaller, i.e. less negative, than the intermediate voltage Vy. Accordingly, such an inverter is referred to as a CLID converter since the “D” refers to “down” meaning smaller in absolute magnitude, not more negative. A CLID converter can only deliver a negative, i.e. below ground, output voltage. With a step-down post-regulator, a CLID converter cannot produce a positive voltage.

Referring again to <figref idrefs="DRAWINGS">FIG. 8</figref>, the output of converter 200, filtered by reservoir capacitor 209, supplies a load 210 with a regulated voltage Vout. In a preferred embodiment, the output voltage Vout is used to provide a feedback voltage VFB to PWM controller 212, which is converted by level-shifter 213 to the voltage VFBin, the control signal delivered to PWM circuit 212. As shown below, the value of Vy output by the pre-converter 252 is self biasing and allows charge pump 201 to operate at its maximum efficiency point. The negative feedback loop facilitates tight voltage regulation in post converter 254 without significantly affecting the overall efficiency of CLXD converter 200.

In a preferred embodiment, the output voltage of level-shifter 213 is Vout, i.e. the feedback should force the value of Vout to the target value of Vout. In the case of CLUD and CLDD converters, level-shifter 213 may comprise a network of two resistors acting as a voltage divider to match the feedback to the converter's internal voltage reference but need not account for the factor n from the pre-converter. In inverting converters, the feedback must be inverted, i.e. referenced to the converter's ground pin.

Another feature of CLXD converter 200 is the use of oscillator 214 to control the switching of MOSFETs 205 and 206 in post-regulator 254 as well as the MOSFETs (not shown) in pre-converter 252. By synchronizing post-regulator 254 and pre-converter 252 in this way, the size of intermediate filter capacitor 204 can be greatly reduced or, in some cases, eliminated altogether.

Behavioral Model of CLXD Converters

To better understand the operation of CLXD converter 200, behavioral model 250 of <figref idrefs="DRAWINGS">FIG. 9</figref> can be used for control analysis and for estimating efficiency. As shown, charge pump pre-converter 252 is powered from input voltage Vin producing an intermediate voltage Vy which in turn powers switched inductor step down post-regulator 254.

The conversion ratio of pre-converter 252 is given by Vy=n·Vin or expressed as a voltage conversion ratio Vy/Vin for pre-converter 252, the ratio equals

Theoretically, since charge pumps are not voltage converters, the output voltage Vy of pre-converter 252, can be adversely “loaded” by whatever it is driving. Loading means its output is forced to another voltage Vz dissimilar from Vy by an amount ΔV, represented by lossy element 253. Because voltage Vy is not normally supplying current to any load except post-regulator 254, post-regulator 254 cannot force its input Vz to be substantially different than Vy so that ΔV≈0 and Vy≈Vz.

In the CLXD topology, post-regulator 254 operates as a step-down or Buck converter, given by the relation Vout=D·Vz≈D·Vy where D is the duty cycle of the high-side MOSFET 205, ranging between 0% and 100% and with an output similar to curve 18 of <figref idrefs="DRAWINGS">FIG. 2A</figref>. Combining the two equations gives us the important relationship Vout≈D·Vy=n·D·Vbatt

The voltage conversion ratio of the CLXU is therefore given by

From this relation, we can make the important observation for the CLXD converter that the converter's output-to-input ratio is the multiplicative product of its pre-regulator's ratio “n” and the post-regulator's duty-factor dependent voltage factor D. In essence, to properly regulate an output voltage, the duty factor D, the conversion ratio n, or both must be varied dynamically to compensate for changes in input voltage.

While post-regulator 254 of CLXD converter 200 can only step-down its input to a lower voltage, operating in tandem with charge pump pre-converter 252, the combined converter can either step-up, step-down, or even regulate at unity voltage conversion ratios.

Specifically if n>1, the pre-converter steps up, the post converter steps down and the combination forms an up-down CLUD converter. With a single-capacitor voltage doubler charge pump this relation is then given by

<maths id="MATH-US-00006" num="00006"><math overflow="scroll"><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>V</mi><mrow><mi>i</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mi>n</mi></mrow></msub></mfrac><mo>=</mo><mrow><mn>2</mn><mo>·</mo><mi>D</mi></mrow></mrow></math></maths> and with a two-capacitor fractional charge pump this relation is given by

Circuit diagram 300, shown in <figref idrefs="DRAWINGS">FIG. 10</figref>, represents a functional diagram of a CLXD down-down converter comprising a 0.5X step-down charge-pump pre-converter 301 followed by an switched inductor Buck converter as a post regulator.

If n<1, the converter operates only as step-down CLDD converter, but it can achieve high step-down conversion ratios at moderate duty factors. A functional description of a dual-flying capacitor CLDD converter is illustrated in <figref idrefs="DRAWINGS">FIG. 15</figref>. The voltage conversion ratio of the CLDD converter can be described by the relation

If n is negative and the post converter is non-inverting, the resulting CLID converter is inverting and supplies a wide range of negative voltages. Inverting CLID converters are illustrated in <figref idrefs="DRAWINGS">FIGS. 18A and 18B</figref>. For single-capacitor charge-pump implementations such CLIU inverters are described by

Using dual-capacitor fractional inverting charge-pumps, such CLID inverters are described by

In such cases, the boost converter post-regulator decreases the magnitude of the voltage without changing its polarity, i.e. the term “down” refers to making a negative voltage smaller.

CLUD Up-Down Converter Operation

<figref idrefs="DRAWINGS">FIGS. 11A and 11B</figref> are functional diagrams of two types of CLUD up-down converters. In <figref idrefs="DRAWINGS">FIG. 11A</figref>, a converter 270 comprises a 2X step-up charge-pump 271 as a pre-converter with flying a capacitor 272, along with an inductor 277, a high-side MOSFET 274, a low-side N-channel synchronous rectifier MOSFET 275 with an intrinsic P-N diode 276, an optional capacitor 273 and an output filter capacitor 278. Capacitor 273 may range in size, depending on the circuit implementation of charge pump 271, and in some cases can be eliminated.

Similarly, in <figref idrefs="DRAWINGS">FIG. 11B</figref>, a converter 290 comprises a 1.5X step-up charge-pump 291 as pre-converter with flying capacitors 292 and 293, along with an inductor 298, a high-side MOSFET 295, a low-side N-channel synchronous rectifier MOSFET 296 with an intrinsic P-N diode 297, an optional capacitor 294 and an output filter capacitor 299. Capacitor 294 may range in size depending of circuit implementation of charge pump 191 and in some cases can be eliminated.

<figref idrefs="DRAWINGS">FIGS. 12A-12E</figref> illustrate various electrical characteristics of a CLUD converter. Specifically, <figref idrefs="DRAWINGS">FIG. 12A</figref> illustrates the transfer characteristics 310 of a CLDU 3.3V converter over an input voltage range of 2V to 5V, including the operating range of a single-cell lithium ion battery. The notation “1s Lilon” refers to a single series-connected cell comprising lithium ion electrochemistry.

As shown, the unregulated battery or input voltage, shown by curve 311, ranging 2V to 5V, is stepped-up by the 2X capacitive pre-converter to a high intermediate voltage Vy, having a wider range of 4V to 10V, illustrated by curve 312. The slope of curve 312 is therefore double that of curve 311. The intermediate voltage Vy (curve 312) is then stepped down by the inductive Buck post-regulator by a factor D, using a varying duty factor to produce a constant output voltage Vout illustrated by curve 313. Feedback of the output voltage is employed to adjust the duty factor D to maintain a constant output voltage, in this case at 3.3V.

When Vbatt=3.3V, the input and output voltages are equal, and the converter is regulating at a unity conversion ratio. When curve 311 is above curve 313, i.e. to the right of the cross-over point of curves 311 and 313, the converter is providing step-down conversion. When curve 311 is below curve 313, the output voltage is greater than the input voltage, and the converter is acting as a step-up converter. The converter's circuit operation remains the same throughout all conditions shown, even at the cross-over point.

The CLUD converter's operation can also be represented as a function of the time during which the 1s Lilon battery is discharging. As described in graph 320 in <figref idrefs="DRAWINGS">FIG. 11B</figref>, a fully charged 1s Lilon battery exhibits a voltage Vbatt around 4.2V at the onset of discharging, illustrated by curve segment 321, which settles to a voltage of approximately 3.5V before remaining relatively constant for an extended duration, as revealed by curve segment 322. Later, curve 323 illustrates that the battery voltage decays below 3.5V into a range between curves 325 and 326, a condition where a normal 3.3V converter would suffer dropout or mode-switching problems.

As the cell approaches full discharge in curve segment 323, its voltage drops rapidly to 2.7V, below which it must be cut off to avoid over-discharge-induced cell damage. Only specialized Lilon batteries can operate down to 2.7V without growing crystallites that short out the cell.

During the Lilon battery discharge, the output voltage Vy of the 2X switched-capacitor pre-converter tracks discharge characteristic of the battery voltage, as illustrated by curve 324 at a level double the battery input voltage. The inductive Buck post-regulator steps this time-varying intermediate voltage down by a factor D1. The combined effect of the two-stage conversion produces a constant CLUD output voltage Vout having a value in this case of 3.3V, as illustrated by curve 325. Alternatively, at a different time-varying duty factor D2, the intermediate voltage Vy can be stepped down to a different regulated voltage, e.g., 3.0V, as shown by curve 326.

The output voltage of the CLUD converter can be any voltage less than the lowest value of Vy (curve 324), namely 5.4V. Such an output voltage may be greater than, less than or within the range of the battery input voltage. For example, the output voltage 3.3V, represented by curve 325, is inside the Lilon battery's voltage range of 4.2V to 2.7V.

Regardless of the voltage of the Lilon cell, the 2X CLUD converter doubles the battery voltage, using its 2X charge-pump pre-converter, to a varying voltage Vy represented by curve 324. This voltage is then reduced by a duty-factor-dependent Buck converter by a time varying factor D to produce a constant regulated output voltage shown by curves 325 and 326. The converter's condition can be described as shown below in Table 1:

<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="8"><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="35pt" align="left" /><colspec colname="3" colwidth="21pt" align="center" /><colspec colname="4" colwidth="14pt" align="center" /><colspec colname="5" colwidth="21pt" align="center" /><colspec colname="6" colwidth="21pt" align="center" /><colspec colname="7" colwidth="21pt" align="center" /><colspec colname="8" colwidth="21pt" align="center" /><thead><row><entry namest="1" nameend="8" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row><row><entry /><entry /><entry /><entry /><entry /><entry /><entry /><entry>Vout/</entry></row><row><entry>Phase</entry><entry>Up/Down</entry><entry>Vbatt</entry><entry>nX</entry><entry>Vy</entry><entry>D</entry><entry>Vout</entry><entry>Vin</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>321. Full charge</entry><entry>Down</entry><entry>4.2 V</entry><entry>2X</entry><entry>8.4 V</entry><entry>36%</entry><entry>3 V</entry><entry>0.71</entry></row><row><entry>Decay</entry><entry>Down</entry><entry>3.6 V</entry><entry>2X</entry><entry>7.2 V</entry><entry>42%</entry><entry>3 V</entry><entry>0.83</entry></row><row><entry>322. Plateau</entry><entry>Down</entry><entry>3.5 V</entry><entry>2X</entry><entry>7.0 V</entry><entry>43%</entry><entry>3 V</entry><entry>0.86</entry></row><row><entry>Discharge Vbatt ≈</entry><entry>Unity</entry><entry>3.0 V</entry><entry>2X</entry><entry>6.0 V</entry><entry>50%</entry><entry>3 V</entry><entry>1.00</entry></row><row><entry>Vout</entry></row><row><entry>323. Extend</entry><entry>Up</entry><entry>2.7 V</entry><entry>2X</entry><entry>5.4 V</entry><entry>56%</entry><entry>3 V</entry><entry>1.11</entry></row><row><entry>Range</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Using feedback, the duty factor self-adjusts to maintain the proper output voltage and regulation, whereby

In contrast to conventional Buck-boost converters, a CLUD converter does not need to change its operating mode as the battery voltage (curve 323) falls below the output voltage (curve 325), i.e. when Vin=Vout≈3.3V. The CLUD converter therefore remains stable with no dropout and degradation in the quality of regulation.

Using a doubler pre-converter in a LCUD converter like that of converter 270 in <figref idrefs="DRAWINGS">FIG. 1A</figref> to regulate a 1s Lilon battery, the peak voltage of intermediate voltage Vy is over 8V, exceeding the maximum operating voltage of many submicron integrated circuit technologies, especially half micron CMOS. One way to limit the peak voltage is to employ a 1.5X fractional pre-converter similar to charge pump 291 in converter 290 of <figref idrefs="DRAWINGS">FIG. 1B</figref>. As shown in graph 340 of <figref idrefs="DRAWINGS">FIG. 12C</figref>, the peak output voltage of the 1.5X pre-converter is limited to 1.5 times 4.2V, or 6.3V, within the voltage capability of half-micron CMOS technology.

As shown in <figref idrefs="DRAWINGS">FIG. 12C</figref>, the 1s Lilon battery voltage (curve 341) is stepped up by 1.5X to produce a time-varying voltage Vy (curve 342). This voltage is then stepped down by a factor D1 to produce a 3.3V output, shown by curve 343, or alternatively to produce a 3.0V output, shown by curve 344. One common product that uses a single cell Lilon battery and requires a 3.3V regulated supply is the cell phone. Unlike a 3V output, which requires a converter supplied by a 1s Lilon cell to operate mostly in step-down mode, a 3.3V output requires operation closer to unity conversion and exhibits an extended duration in its step-up mode, as shown in Table 2.

<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="8"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="left" /><colspec colname="3" colwidth="21pt" align="center" /><colspec colname="4" colwidth="21pt" align="center" /><colspec colname="5" colwidth="28pt" align="center" /><colspec colname="6" colwidth="21pt" align="center" /><colspec colname="7" colwidth="21pt" align="center" /><colspec colname="8" colwidth="21pt" align="center" /><thead><row><entry namest="1" nameend="8" rowsep="1">TABLE 2</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row><row><entry /><entry /><entry /><entry /><entry /><entry /><entry /><entry>Vout/</entry></row><row><entry>Phase</entry><entry>Up/Down</entry><entry>Vbatt</entry><entry>nX</entry><entry>Vy</entry><entry>D</entry><entry>Vout</entry><entry>Vin</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Full charge</entry><entry>Down</entry><entry>4.2 V</entry><entry>1.5X</entry><entry>6.3 V</entry><entry>52%</entry><entry>3.3 V</entry><entry>0.79</entry></row><row><entry>Decay</entry><entry>Down</entry><entry>3.6 V</entry><entry>1.5X</entry><entry>5.4 V</entry><entry>61%</entry><entry>3.3 V</entry><entry>0.92</entry></row><row><entry>Plateau</entry><entry>Down</entry><entry>3.5 V</entry><entry>1.5X</entry><entry>5.25 V </entry><entry>63%</entry><entry>3.3 V</entry><entry>0.94</entry></row><row><entry>Vbatt ≈ Vout</entry><entry>Unity</entry><entry>3.3 V</entry><entry>1.5X</entry><entry>5.0 V</entry><entry>67%</entry><entry>3.3 V</entry><entry>1.00</entry></row><row><entry>Discharged</entry><entry>Unity</entry><entry>3.0 V</entry><entry>1.5X</entry><entry>4.5 V</entry><entry>73%</entry><entry>3.3 V</entry><entry>1.10</entry></row><row><entry>Extend Range</entry><entry>Up</entry><entry>2.7 V</entry><entry>1.5X</entry><entry>4.1 V</entry><entry>74%</entry><entry>3.3 V</entry><entry>1.22</entry></row><row><entry namest="1" nameend="8" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Despite operating within a range of approximately ±20% of its unity conversion ratio, the 2X CLUD converter exhibits duty factors in the narrow range of 36% to 56%, which enables it to utilize PWM control circuitry that is more easily implemented than converters operating at extreme duty factors, especially at high-switching frequencies. In contrast, the 1.5X CLUD converter exhibits slightly higher duty factors in the range from 52% to 74%, but limits the maximum Vy voltage to 6.3V rather than 8.4V.

Graph 360 in <figref idrefs="DRAWINGS">FIG. 12D</figref> illustrates the voltage transfer characteristics of the 1.5X-type CLUD converter where input voltage ranging from 2V to 5V (curve 361) is stepped up by 1.5X to produce an intermediate voltage Vy (curve 362) and then stepped down by a factor D to produce a constant output voltage (curve 363), in this case 2.7V, but alternatively 3.0V to 3.3V.

Present day converters are not able to operate with high efficiencies over the entire voltage range of a battery. Handset designers today must employ step-down-only Buck converters that cut off at a voltage around 3.5V, thereby forfeiting the battery in the final discharge phase and a portion of voltage-plateau-phase, because the added use-life of these later phases of discharge is balanced by the efficiency loss of a conventional Buck-boost converter. The LCUD converter is equally usable for one and two dry cell applications with inputs of 0.9V up to 2.4V.

As previously derived, the conversion ratio of a nX CLDU converter is given by

<maths id="MATH-US-00012" num="00012"><math overflow="scroll"><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>V</mi><mi>batt</mi></msub></mfrac><mo>=</mo><mrow><mi>n</mi><mo>·</mo><mi>D</mi></mrow></mrow></math></maths> having a corresponding duty factor D given by

In graph 380 of <figref idrefs="DRAWINGS">FIG. 12E</figref>, the duty factor dependence of the voltage conversion ratio for 1.5X and 2X LCUD converters is illustrated by curves 385 and 384 respectively, and compared to the Buck converter's characteristic shown by curve 381.

While the Buck converter (curve 381) operates below a unity voltage conversion ratio (illustrated by dashed line 386) at any and all values of duty factor D, either the 1.5X or the 2X CLUD converter is able to operate above and below the unity conversion condition. The output voltage Vy of the pre-converter (illustrated by curve 382 for a 2X charge pump and by curve 383 for a 1.5X charge pump) illustrates that the operation of the pre-converter operation does not depend on duty factor of the post-regulator.

As shown, a unity conversion ratio occurs in the 2X CLUD converter when the duty factor D=50%. At the same duty factor, the Buck converter exhibits a conversion ratio of 0.5. At high duty factors, where the Buck converter only approaches the unity conversion ratio, the 2X-type CLUD converter is able to provide an output voltage roughly equal to twice the input voltage.

CLUD Converter Implementation

2X-Type CLUD Implementation: <figref idrefs="DRAWINGS">FIG. 13A</figref> illustrates a circuit diagram of a 2X CLDU converter 400. As shown, the switched capacitor pre-converter 400A comprises MOSFETs 401, 402, 403, and 404 with a flying capacitor 405. The MOSFETs are controlled by a break-before-make (BBM) buffer (not shown) to alternatively charge and discharge flying capacitor 405. The intermediate output voltage Vy charges capacitor 405 and powers the input to the inductive post regulator 400B, where MOSFETs 407 and 408, using PWM control, continuously adjust the current flowing in inductor 410 in response to feedback of the output voltage as filtered by a reservoir capacitor 411.

In converter 400, the charge pump pre-converter 400A and the inductive post-regulator 400B share no components and may operate independently. Accordingly MOSFETs 401 through 404 can switch at a frequency different from MOSFETs 407 and 408. In such asynchronous operation, capacitor 406 stores energy output from charge pump pre-converter 400A and supplies it to the input of the Buck post-regulator 400B, and capacitor must have sufficient capacitance to supply all current transients as demanded. While the two clocks controlling pre-converter 400A and post-regulator 400B, respectively, may “free run” and thereby vary in frequency, unsynchronized operation can lead to excessive switching noise in the system.

In a preferred embodiment of a multi-frequency implementation of the CLUD converter 400, pre-converter 400A and post converter 400B switch at different frequencies but are synchronized either by a phase-locked-loop, also known as a PLL, or by using a common clock multiplied-up or divided-down to generate the two dissimilar clock signals. Ideally the clock waveform for the inductive post-regulator 400B comprises a ramp generator to produce a square, triangle, or saw-tooth ramp wave. The gate drive for charge pump MOSFETs 401 through 404 may, however, be a square wave signal generated by feeding the output of the ramp generator into a comparator. Alternatively, one or more of the MOSFETs 401 through 404 in the charge pump pre-converter 400A may be used to limit the inrush current to charge pump pre-converter 400A during the charging or discharging of its flying capacitor 405.

If, in contrast, the charge pump pre-converter 400A and inductive post-regulator 400B are switched in phase and at the same frequency then the size of the intermediate capacitor between the two stages can be greatly diminished or even eliminated. Under such circumstances, since MOSFET 404 in pre-converter 400A and MOSFET 407 in post-regulator 400B are wired in series and switch in unison, they are redundant and one of these MOSFETs may be eliminated.

This simplification for synchronous operation of the charge pump pre-converter and inductive post-regulator is illustrated 2X-type LCUD converter 420 of <figref idrefs="DRAWINGS">FIG. 13B</figref>, where MOSFET 424 serves as both the output transistor for the charge pump pre-converter 420A and as the input device for the inductive post-regulator 420B. This modification reduces series resistance, conduction and switching losses in the LCUD converter and may also save die area. The intervening capacitor is also eliminated since flying capacitor 433 acts as the input filter for post-regulator 420B whenever MOSFET 424 is on and conducting.

As shown, the switched capacitor pre-converter 420A of converter 420 comprises MOSFETs 421, 422, 423, and 424 with a flying capacitor 433. MOSFETs 421 through 424 are controlled by a break-before-make (BBM) buffer 429 to alternatively charge and discharge flying capacitor 433. The current flowing through inductor 427 is dynamically adjusted by the duty factor of high-side MOSFET 424, with a PWM controller 430 responding to changes in the output voltage of converter 420. Feedback signal VFB is adjusted in voltage and polarity by a level shift circuit 432 to control PWM circuit 430.

When high-side MOSFET 424 is conducting, the voltages Vx and Vy′ are both approximately equal to {2Vbatt−IL·RDS}. During this time, inductor 427 is magnetized, i.e. stores energy, while delivering current to the output and simultaneously transferring energy and charging output capacitor 428. When MOSFET 424 is turned off, the voltage Vx flies below ground, forwarding biasing diode 426 and recirculating current.

During some portion of the time while diode 426 is forward-biased, synchronous rectifier MOSFET 425 is turned-on, diverting the current from diode 426. Break-before-make buffer 429 drives the gates of MOSFETs 424 and 425 out of phase, insuring that flying capacitor 433 is not shorted to ground by simultaneous conduction through MOSFETs 424 and 425. Clock pulse generator 431 synchronizes the switching of the MOSFETs in pre-converter 420A and post-regulator 420B, while PWM controller 430 determines the pulse width, i.e. on-time, of all MOSFETs in response to changes in the output voltage and feedback signal VFB.

Notice that in converter 420, the intermediate capacitor connected between the charge pump pre-converter 420A and the inductive post-regulator 420B has been eliminated; there is no equivalent to capacitor 406 of converter 400 in converter 420. Therefore, a steady intermediate voltage Vy does not exist in converter 420. The node voltage Vy′ emulates the behavior of intermediate voltage Vy during the time when MOSFET 424 conducts and inductor 427 is being magnetized. During that portion of the converter's half-cycle, voltage Vy′ has a potential equal to approximately twice the battery input voltage. During the other half-cycle, while flying capacitor 433 is being charged, however, Vy′ is pulled to Vbatt by conducting MOSFET 424 and no longer behaves as a semi-constant voltage source or power supply. So Vy′ acts as a “virtual” constant voltage source whenever it is powering the post-regulator 420B, hence the prime notation “′”.

In an alternative embodiment, synchronous rectifier MOSFET 425 may be eliminated and recirculation current carried entirely by diode 426, which preferably should comprise a Schottky metal-semiconductor diode rather than a P-N junction diode. Schottky diodes are preferred because they exhibit lower forward voltage drops than P-N junction diodes. In yet another embodiment, a Schottky diode can be placed in parallel with MOSFET 425 and intrinsic P-N diode 426.

The operation of CLUD converter 420 is illustrated in <figref idrefs="DRAWINGS">FIGS. 13C and 13D</figref>. In circuit 440 of <figref idrefs="DRAWINGS">FIG. 13C</figref>, flying capacitor 433 is charged through conducting MOSFETs 423 and 422, while MOSFETs 421 and 424 remain off. Flying capacitor 433 is then charged to the full battery input voltage, i.e. to Vbatt.

During this cycle synchronous rectifier MOSFET 425 is conducting inductor recirculation current IL, thereby moving energy from inductor 427 to output capacitor 428 and a load (not shown). This phase of operation can be referred to as the “charging and recirculation phase”, i.e. the charging of the flying capacitor and the maintaining of the output voltage through inductor recirculation. During the charging and recirculation phase, MOSFET 424 is turned off and output capacitor COut supplies the necessary load current Iout to the electrical load. Specifically, during this phase the energy in inductor 427 is used to replenish output capacitor 428 as it is being discharged by the load. Current recirculation includes MOSFET 425, diode 426 and filter capacitor 428. The voltage across capacitor 428 begins to sag during this cycle and is replenished during the subsequent transfer phase shown in <figref idrefs="DRAWINGS">FIG. 13D</figref>.

<figref idrefs="DRAWINGS">FIG. 13D</figref> represents the transfer phase, during which energy is transferred from flying capacitor 433 in pre-converter 420A to inductor 427 in post-regulator 420B. This transfer is achieved by turning off MOSFETs 422, 423, and 425, and turning on MOSFETs 421 and 424, thereby connecting flying capacitor 433 in series with inductor 427 and magnetizing, i.e. storing energy (I2L) in inductor 427. Simultaneous to magnetizing the inductor, the current charges capacitor 428 to a voltage D·Vy, i.e., the voltage on the flying capacitor (2·Vbatt) times the duty factor D of MOSFET 424.

The two phases alternate to keep inductor 427 magnetized and flying capacitor 433 and output capacitor 428 charged. The entire system is efficient because once the voltage builds up on flying capacitor 433 and output capacitor 428 during start-up, steady state operation must only replenish enough charge to compensate for the small shifts in voltage resulting from voltage sagging across capacitors 433 and 428 while they are discharging.

1.5X-Type CLUD Implementation: In another embodiment of this invention, <figref idrefs="DRAWINGS">FIG. 14A</figref> illustrates a circuit diagram of a 1.5X-type CLUD converter 460. Using a fractional charge pump rather than a doubler, the switched capacitor pre-converter 460A comprises two flying capacitors 468 and 469 driven by seven MOSFETs 461, 462, 463, 464, 465, 466, and 467. The MOSFETs are controlled by a break-before-make (BBM) buffer (not shown) to alternatively charge and discharge flying capacitors 468 and 469. The intermediate output voltage Vy charges capacitor 475 and powers the inductive post regulator 460B, where MOSFETs 470 and 471, using PWM control, continuously adjust the current flowing in inductor 473 in response to feedback of the output voltage as filtered by reservoir capacitor 474.

In converter 460, the charge pump pre-converter 460A and the inductive post-regulator 460B share no components and may operate independently. Accordingly MOSFETs 470 through 471 can switch at a frequency different than MOSFETs 461 through 467. In such asynchronous operation, capacitor 475 stores energy output from pre-converter 460A and supplies it to the input of the Buck post-regulator 460B. Capacitor 475 and must have sufficient capacitance to supply all currents transients as demanded. While the two clocks controlling pre-converter 460A and post-regulator 460B, respectively, may “free run” and thereby vary in frequency, unsynchronized operation can lead to excessive switching noise in the system.

In a preferred embodiment of a multi-frequency implementation of 1.5X CLUD converter 460, pre-converter 460A and post converter 460B switch at different frequencies but are synchronized either by a phase-locked-loop, also known as a PLL, or by using a common clock multiplied-up or divided-down to generate the two dissimilar clock signals. Ideally, the clock waveform for the inductive post-regulator 460B comprises a ramp generator to produce a square, triangle, or saw-tooth ramp wave. The gate drive for the MOSFETs in pre-converter 460A may, however, be a square wave signal generated by feeding the output of the ramp generator into a comparator. Alternatively, one or more of the MOSFETs in charge pump pre-converter 460A may be used to limit the inrush current to the charge pump during the charging or discharging of flying capacitors 468 and 469.

If, in contrast, charge pump pre-converter 460A and inductive post regulator 460B are switched in phase and at the same frequency, the size of the intermediate capacitor 475 between the two stages can be greatly diminished or even eliminated. Under such circumstances, since each of MOSFETs 466 and 467 in the charge pump pre-converter 460A is connected in series with MOSFET 470 in post-regulator 460B, and MOSFETs 466, 467 and 470 are switching on and off together at the same frequency, MOSFET 467 may be eliminated.

The resulting 1.5X-type LCUD converter 480 is illustrated in <figref idrefs="DRAWINGS">FIG. 14B</figref>, where MOSFETs 486 and 487 serve both as output transistors for charge pump pre-converter 480A and as input devices for inductive post-regulator 480B. This modification reduces series resistance, conduction and switching losses in LCUD converter 480 and also saves die area. The intervening capacitor is also eliminated since flying capacitors 488 and 489 act in parallel as an input filter for post-regulator 480B whenever MOSFETs 486 and 487 are on and conducting.

As shown, the fractional switched capacitor pre-converter 480A of simplified converter 480 comprises seven MOSFETs 481, 482, 483, 484, 485, 486 and 487 with flying capacitors 488 and 489. The MOSFETs are controlled by a break-before-make (BBM) buffer 492 to alternatively charge and discharge flying capacitors 488 and 489. The current flowing through inductor 490 is dynamically adjusted by the duty factor of MOSFETs 486 and 487, with a PWM controller 493 responding to changes in the output voltage of converter 480. The feedback signal VFB is adjusted in voltage by level shift circuit 494 to control PWM circuit 493.

When high-side MOSFETs 486 and 487 are conducting, the voltage Vx is biased at Vy′ approximately equal to {2Vbatt−IL·½RDS} during which time inductor 490 is magnetized, i.e. stores energy while delivering current to the output and simultaneously transferring energy and charging output capacitor 491. When MOSFETs 486 and 487 are turned off, the voltage Vx flies below ground, forwarding-biasing diode 489 and recirculating current. The synchronized conduction of MOSFETs 486 and 487 not only performs the function of controlling the output current of 1.5X charge pump pre-converter 480A, but performs the function of the input MOSFETs for the inductive Buck post converter 480B, thereby eliminating the need for one high-current low-resistance MOSFET, saving die area and improving efficiency.

Some portion of the time while diode 489 is forward biased, synchronous rectifier MOSFET 488 is turned on, diverting current from diode 489. Break-before-make buffer 492 drives MOSFETs 488 out of phase with MOSFETs 486 and 487, insuring that flying capacitors 488 and 489 are not shorted to ground by simultaneous conduction of MOSFETs 486, 487, and 488. Clock pulse generator 495 synchronizes the switching of boost post-regulator 480B and charge pump pre-converter 480A, while PWM controller 493 determines the pulse width, i.e. on-time, of all MOSFETs in response to changes in the output voltage and feedback signal VFB.

Notice that in converter 480 the intermediate capacitor connected between charge pump pre-converter 480A and inductive post-regulator 480B has been eliminated, i.e., there in no equivalent to capacitor 475 of converter 460 in simplified converter 480. Therefore, a steady intermediate voltage Vy does not exist in converter 480. The node voltages Vy′ emulate the behavior of intermediate voltage Vy during the time when MOSFETs 486 and 487 conduct and inductor 490 is being magnetized. During that portion of the half-cycle of converter 480, voltage Vy′ has a potential equal to approximately 1.5 times the battery input voltage. During the other half-cycle, each of series-connected capacitors 488 and 489 is charged to a voltage of Vbatt/2 through conducting MOSFETs 481, 482 and 483 and no longer behaves as a semi-constant voltage source or power supply. So Vy′ acts as a “virtual” constant voltage source whenever it is powering post-regulator 480B, hence the prime notation “′”.

In an alternative embodiment, synchronous rectifier MOSFET 488 may be eliminated and recirculation current may be carried entirely by diode 489, which preferably should comprise a Schottky metal-semiconductor diode rather than a P-N junction. Schottky diodes are preferred because they exhibit lower forward voltage drops than junction diodes. In yet another embodiment, a Schottky diode is placed in parallel with MOSFET 488 and intrinsic P-N diode 489.

The operation of the fractional CLUD converter 480 is illustrated in <figref idrefs="DRAWINGS">FIGS. 14C and 14D</figref>. In equivalent circuit diagram 510 of <figref idrefs="DRAWINGS">FIG. 14C</figref>, capacitors 488 and 489 are charged through conducting MOSFETs 481, 482 and 483 while MOSFETs 484, 485, 486 and 487 remain off. Series-connected flying capacitors 488 and 489 are then each charged to the half the battery input voltage, i.e., to Vbatt/2.

During this phase, synchronous rectifier MOSFET 488 is conducting a recirculation current IL, thereby moving energy from inductor 490 to output capacitor 491 and a load (not shown). This phase can be referred to as the “charging and recirculation phase”, i.e. the charging of the flying capacitors and the maintaining of the output voltage through current recirculation through inductor 490. During this phase, MOSFETs 486 and 487 are turned off and output capacitor COut supplies the necessary load current Iout to the electrical load. Specifically, during this phase the energy in inductor 490 is used to replenish output capacitor 491 as it is being discharged by the load. Current recirculation includes MOSFET 488, diode 489 and output capacitor 491. The voltage across capacitor 491 begins to sag during this phase and is replenished during the subsequent transfer phase, shown in <figref idrefs="DRAWINGS">FIG. 14D</figref>.

<figref idrefs="DRAWINGS">FIG. 14D</figref> illustrates the transfer phase, where energy is transferred from flying capacitors 488 and 489 in pre-converter 480A to inductor 488 in post-regulator 480B. This energy transfer is achieved by shutting off MOSFETs 481, 482, and 483, and by turning on MOSFETs 484, 485, 486 and 487, thereby connecting flying capacitors 488 and 489 in parallel, stacked atop the voltage Vbatt and in series with inductor 490. This connection simultaneously magnetizes inductor 490, i.e. storing energy I2L, and transfers charge from flying capacitors 488 and 489 to output capacitor 491 at a voltage D·Vy, i.e., the voltage on the flying capacitors 488 and 489 (1.5·Vbatt) times the duty factor D of MOSFETs 486 and 487.

The two phases alternate to keep inductor 490 magnetized and flying capacitors 488 and 489 and output capacitor 491 charged. The entire system is efficient because once the voltage builds up on flying capacitors 488 and 489 and output capacitor 491 during start-up, steady state operation must only replenish enough charge to compensate for the small shifts in voltage resulting from voltage sagging across capacitors 488, 489 and 491 while they are discharging.

CLXD Converter Efficiency

One unexpected aspect of a CLXD converter, and in fact any CLXX class converter, is the relative independence of its overall efficiency η on input and load conditions. This can better be understood by referring to <figref idrefs="DRAWINGS">FIG. 9</figref> where charge-pump pre-converter 252 produces an intermediate voltage Vy that provides the input voltage to inductive post-regulator 254.

The lossy element 253 is included in the behavioral model to illustrate that because charge-pump pre-converter 252 cannot actually regulate voltage, any voltage mismatch ΔV between the intermediate voltage Vy and the desired intermediate voltage Vz needed to power post-regulator 254 will result in a further loss of efficiency. In LC-class converters like those described in the above-referenced application Ser. Nos. 11/890,818 and 11/890,956, closed loop feedback around the entire loop from the output terminal of the converter to the input terminal of the PWM controller is beneficial to counter any “loading” effects on the charge pump. But in CL-class converters like converter 250, the output of charge pump pre-converter 252 is internal to the converter, and unless the input to post converter 254 is used to supply an external load, then Vz will naturally operate at the voltage Vy, the optimum efficiency condition.

Specifically, in CLXX-type converters such as converter 250, charge pump pre-converter 252 operates in an open-loop manner to produce an output voltage Vy that is some fixed multiple “n” of the input voltage. For example, using one or two flying capacitors, the multiplier will be an integral multiple of 0.5V. As long as Vz can be maintained near the voltage n·Vin, i.e. where Vy≈Vz, the efficiency of charge pump pre-converter 252 will remain high. Any deviation ΔV from this optimum condition will result in a loss of efficiency in charge pump pre-converter 252, where the mismatch is given by ΔV=Vz−Vy resulting in a loss that has the same mathematical form ΔV/Vin as the losses in a linear converter, even though lossy element 253 is not really regulating voltage. Specifically, the loss of efficiency may be defined as Ploss2=Iy·ΔV=Iy|(Vy−Vz)|

The efficiency of element 253, is then given by

<maths id="MATH-US-00014" num="00014"><math overflow="scroll"><mrow><msub><mi>η</mi><mn>2</mn></msub><mo>=</mo><mrow><mfrac><msub><mi>P</mi><mi>z</mi></msub><msub><mi>P</mi><mi>y</mi></msub></mfrac><mo>=</mo><mrow><mfrac><mrow><msub><mi>P</mi><mi>y</mi></msub><mo>-</mo><msub><mi>P</mi><mrow><mi>loss</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow></msub></mrow><msub><mi>P</mi><mi>y</mi></msub></mfrac><mo>=</mo><mrow><mfrac><mrow><mrow><msub><mi>I</mi><mi>y</mi></msub><mo>·</mo><msub><mi>V</mi><mi>y</mi></msub></mrow><mo>-</mo><mrow><msub><mi>I</mi><mi>y</mi></msub><mo>⁡</mo><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>y</mi></msub><mo>-</mo><msub><mi>V</mi><mi>z</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow><mrow><msub><mi>I</mi><mi>y</mi></msub><mo>·</mo><msub><mi>V</mi><mi>y</mi></msub></mrow></mfrac><mo>=</mo><mfrac><msub><mi>V</mi><mi>z</mi></msub><msub><mi>V</mi><mi>y</mi></msub></mfrac></mrow></mrow></mrow></mrow></math></maths> and where Vz≦Vy, i.e. the maximum theoretical efficiency of the second element is 100%. From the converter transfer function Vy=n·Vin then

In reality, however, the maximum efficiency of charge pump pre-converter 252 is not 100%. Charge pump pre-converter 252 typically has a maximum efficiency in the range of 96% when delivering power to a load operating at a voltage Vz. Assuming that this efficiency remains relatively constant, the conversion efficiency of the first two stages is given by

When n=1, the charge pump is not actually stepping up voltage and the efficiency equation defaults to that of linear converter.

Referring again to converter 250 in <figref idrefs="DRAWINGS">FIG. 9</figref>, the overall efficiency of the CLXD converter shown can be estimated as the product of the aforementioned charge pump efficiency η1·η2 and the efficiency of the switched inductor post converter η3.

For post-regulator 254, its input power is given by Pz=Iz·Vz while Pout=Iout·Vout. The efficiency η3 of post-regulator 254 can then be expressed as

Typical values range from 94% to 89% depending on operating conditions, power MOSFET resistance and operating currents. Since the efficiency η3 of post-regulator 254 depends on the voltage conversion ratio, and since the conversion ratio depends on duty factor D, then it follows logically that the switching converter's efficiency depends on duty factor, i.e. η3=f(D).

The overall efficiency of LCXX converter 250, then, is given by the product of the efficiency of charge-pump pre-converter 252 and the efficiency of inductive post-regulator 254.

Since feedback within post-regulator 254 maintains the targeted output voltage Vout by adjusting its duty factor for a wide range of intermediate voltages Vz then, unloaded, Vz=Vy=n·Vin and the above equation simplifies to η=ηCP·η3=η1·η3 where η3 is a function of the duty factor D. Using a step-down, Buck converter topology for the post-regulator 254, the voltage transfer function of CLXD converter 250 is given by Vout=D·Vy=[n·D] Vin.

Switched CLXX-type and CLXD-type converters of this invention can produce a well regulated output voltage with efficiencies that are relatively insensitive to the Vout/Vin voltage conversion ratio. In the event that the charge-pump pre-converter is a step-up fractional charge pump, e.g. where n=1.5 or 2, the resulting CLUD converter is able to operate in either step-up or step-down modes without exhibiting any mode changes, narrow pulse, or dropout effects near unity voltage conversion ratios, i.e. when Vout≈Vin. A CLUD converter is able to operate over a range of output to input voltage ratios far beyond those attainable by a Buck converter, boost converter or charge pump. Assuming a practical limitation to duty factors in the range between 10% and 90%, Table 3 compares the usable range of voltage conversion ratios of the CLUD converter to those of a charge pump doubler, Buck converter, and boost converter.

<tables id="TABLE-US-00003" num="00003"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="56pt" align="left" /><colspec colname="2" colwidth="42pt" align="left" /><colspec colname="3" colwidth="56pt" align="left" /><colspec colname="4" colwidth="63pt" align="left" /><thead><row><entry namest="1" nameend="4" rowsep="1">TABLE 3</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry>Converter</entry><entry>Range of</entry><entry>Range of</entry><entry>Unity Ratio</entry></row><row><entry>Topology</entry><entry>Vout/Vin</entry><entry>Efficiency</entry><entry>Efficiency</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>2X Charge Pump</entry><entry> 0.1 to 2.0</entry><entry>Above 1.8</entry><entry>Poor, η < 50%</entry></row><row><entry>Boost Converter</entry><entry> 1.1 to 15</entry><entry>Good up to ~8-10</entry><entry>Dropout below 1.1</entry></row><row><entry>Buck Converter</entry><entry> 0.1 to 0.9</entry><entry>Good over range</entry><entry>Dropout above 0.9</entry></row><row><entry>2X CLUD</entry><entry> 0.2 to ~1.8</entry><entry>Good over range</entry><entry>Good, η > 92%</entry></row><row><entry>1.5X CLUD</entry><entry>0.15 to ~1.5</entry><entry>Good over range</entry><entry>Good, η > 92%</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Despite its high efficiency characteristic, a Buck converter operating between a 10% and a 90% duty factor is only capable of step-down conversion ratios, i.e. for Vout={0.1Vin to 0.9Vin} as shown by curve 471. Similarly, a boost converter operating between a 10% and a 90% duty factor is only capable of step-up conversion ratios, i.e. where Vout={1.1Vin to 8Vin}. Furthermore 2X charge pump efficiency (curve 473) is high only for conversion ratios exceeding 1.8.

In contrast, the efficiency of a CLUD is high over a wide range of voltage conversion ratios, i.e. where Vout={0.15Vin to 1.8Vin}. This result is unexpected considering the CLUD converter combines elements of the charge pump and the boost converter, yet regulates over a much wider range of operating conditions than either of them.

Switched Capacitor-Inductor Down-Down (CLDD) Converters

The CLXD converter topology is also useful for step-down voltage regulation. By utilizing a step-down charge-pump as a pre-converter, step-down voltage conversion is performed in two stages, or as a CLDD converter. Examining the implementation of the CL type down-down converters in greater detail, <figref idrefs="DRAWINGS">FIG. 15</figref> illustrates the functional block representation of a switched 0.5X-type LCDD regulating converter 550. Converter 550 comprises a pre-converter 550A which includes a fractional charge pump 551 with flying capacitors 553 and 554 and a filter capacitor 552, where the output of charge pump 551 supplies an intermediate voltage Vy. Intermediate voltage Vy in turn powers a step-down switched-inductor post-regulator 550B comprising an inductor 558, a MOSFET 555, a low-side N-channel synchronous rectifier MOSFET 556 with an intrinsic rectifier diode 557 and an output capacitor 559. Since Vy=0.5·Vbatt and Vout=D·Vy, then the voltage conversion ratio of 0.5X-type CLDD converter 550 is given by

An example of the voltage transfer characteristic of 0.5X CLDD converter 550 is shown on graph 570 of <figref idrefs="DRAWINGS">FIG. 16A</figref> for an input ranging from 2V to 5V. As shown, the Vbatt input (curve 571) is stepped down by a factor of 2 to produce a Vy intermediate voltage (curve 572) that changes in proportion to the battery input. This voltage is then further reduced by a varying factor of D in the step-down type post-regulator 550B to produce a constant output voltage 573, in this case 0.9V. The step-down conversion ratio of 0.5X CLDD converter 550 is substantial even at moderate duty factor ratios. For example at a 50% duty factor the step-down voltage conversion is a factor of 4X, i.e. Vout=25% of Vbatt.

Another example of CLDD conversion is illustrated in graph 590 of <figref idrefs="DRAWINGS">FIG. 16B</figref> where the discharge of a 1s Lilon battery is stepped down and regulated to 0.9V. The Lilon battery fully charged starts with a 4.2V condition (curve 591) that decays over time to a plateau voltage (curve 592) of approximately 3.5V and then eventually reached its discharged condition of 2.7V in region of curve 593. The CLDD converter's fractional pre-converter produces a time varying voltage Vy equal to one-half of Vbatt, shown by Vy curve 594 ranging from 2.1V to 1.4V. Vy is then further stepped down to 0.9V by an a varying amount D by the step-down post-regulator to produce a constant 0.9V output (curve 595).

For a given step down ratio, the duty factor D of the CLDD converter is lower than a Buck or CLUD converter, making it ideally suited for operating at low output-to-input voltage conversion ratios. This feature is illustrated in graph 620 in <figref idrefs="DRAWINGS">FIG. 16C</figref> showing the voltage conversion ratio at various duty factors. The graph compares the voltage conversion characteristic of a 0.5X-type CLDD converter (curve 623) to that of a conventional Buck converter (curve 623).

Neither the Buck converter nor 0.5X-type CLDD converter operates above a unity conversion ratio, meaning both converters are limited to step-down operation. At low duty factors, the conversion ratio of both the Buck converter and CLDD converter asymptotically approaches zero. At a 50% duty factor, the Buck converter has an output-to-input voltage ratio of one-half, while the 0.5X-type CLDD converter exhibits an input-to-output voltage ratio of one-quarter. From the relationship

<maths id="MATH-US-00020" num="00020"><math overflow="scroll"><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>V</mi><mi>batt</mi></msub></mfrac><mo>=</mo><mrow><mrow><mi>n</mi><mo>·</mo><mi>D</mi></mrow><mo>=</mo><mrow><mn>0.5</mn><mo>·</mo><mi>D</mi></mrow></mrow></mrow></math></maths> having a corresponding duty factor D given by

<maths id="MATH-US-00021" num="00021"><math overflow="scroll"><mrow><mi>D</mi><mo>=</mo><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>V</mi><mi>y</mi></msub></mfrac><mo>=</mo><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><mrow><mi>n</mi><mo>·</mo><msub><mi>V</mi><mi>batt</mi></msub></mrow></mfrac><mo>=</mo><mrow><mn>2</mn><mo>⁢</mo><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>B</mi><mi>batt</mi></msub></mfrac></mrow></mrow></mrow></mrow></math></maths> describing D as function of the product of the voltage conversion ratio and the pre-converter factor nX, it is clear that smaller values of “n” increase the minimum duty factor for any given conversion ratio, making it easier to implement converters with high step-down conversion ratios. For example, at a 50% duty factor, a 0.5X CLDD converter can step down its input voltage by a factor of 4, a value double that of a Buck converter. The relationship between duty factor and conversion ratio for the 0.5X-type CLDD converter is illustrated by curve 623 in graph 620 of <figref idrefs="DRAWINGS">FIG. 16C</figref> and contrasted with the conversion ratio of a conventional Buck converter (curve 621) and a 0.5X charge pump (curve 622).

<tables id="TABLE-US-00004" num="00004"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="56pt" align="left" /><colspec colname="3" colwidth="56pt" align="left" /><colspec colname="4" colwidth="56pt" align="left" /><colspec colname="5" colwidth="56pt" align="left" /><thead><row><entry namest="1" nameend="5" rowsep="1">TABLE 4</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row><row><entry>Condition</entry><entry>2X CLUD</entry><entry>1.5X CLUD</entry><entry>Buck</entry><entry>0.5X CLDD</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>D = 90%</entry><entry>Vout/Vin = 1.8</entry><entry>Vout/Vin = 1.35</entry><entry>Vout/Vin = 0.9</entry><entry>Vout/Vin = 0.45</entry></row><row><entry>D = 50%</entry><entry>Vout/Vin = 1</entry><entry>Vout/Vin = 0.75</entry><entry>Vout/Vin = 0.5</entry><entry>Vout/Vin = 0.25</entry></row><row><entry>D = 10%</entry><entry>Vout/Vin = 0.2</entry><entry>Vout/Vin = 0.15</entry><entry>Vout/Vin = 0.1</entry><entry>Vout/Vin = 0.05</entry></row><row><entry>lim D → 0%</entry><entry>Vout/Vin = 0</entry><entry>Vout/Vin = 0</entry><entry>Vout/Vin = 0</entry><entry>Vout/Vin = 0</entry></row><row><entry>1 s Lilon→0.9 V</entry><entry>11% < D < 17%</entry><entry>14% < D < 22%</entry><entry>21% < D < 33%</entry><entry>43% < D < 67%</entry></row><row><entry>5 V ± 10%→1.2 V</entry><entry>11% < D < 13%</entry><entry>15% < D < 18%</entry><entry>22% < D < 27%</entry><entry>44% < D < 53%</entry></row><row><entry>3 s Lilon→3.3 V</entry><entry>13% < D < 20%</entry><entry>18% < D < 27%</entry><entry>26% < D < 41%</entry><entry>52% < D < 82%</entry></row><row><entry>1 s Lilon→1.2 V</entry><entry>14% < D < 22%</entry><entry>19% < D < 30%</entry><entry>29% < D < 44%</entry><entry>57% < D < 88%</entry></row><row><entry>2 s Lilon→1.2 V</entry><entry>7%* < D < 11%</entry><entry>10% < D < 15%</entry><entry>14% < D < 22%</entry><entry>29% < D < 44%</entry></row><row><entry>12 V ± 10%→1.2 V</entry><entry>5%* < D < 6%*</entry><entry>6%* < D < 7%*</entry><entry>9%* < D < 11%</entry><entry>18% < D < 22%</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Table 4 illustrates the duty factor range of some common step-down conversion applications with input voltages ranging from those supplied by 1s Lilon to 3s Lilon batteries, along with 5V and 12V supplies regulated at ±10%. Those conditions marked with an asterisk (*) may require limiting the converter's operating frequency in order to meet the full range in required duty factors. The CLDD converter accommodated all the applications without requiring duty factors under ten percent.

0.5X-Type CLDD Implementation: <figref idrefs="DRAWINGS">FIG. 17A</figref> illustrates a circuit diagram of a 0.5X-type CLDD converter 660. Using a ground-referenced fractional charge pump, the switched capacitor pre-converter 660A comprises two flying capacitors 666 and 667 driven by five MOSFETs 661, 662, 663, 664, and 665. The MOSFETs are controlled by break-before-make (BBM) buffer (not shown) to alternatively charge and discharge flying capacitors 666 and 667. The output voltage Vy charges capacitor 675 and powers the input to the inductive post-regulator 660B, where MOSFETs 668 and 669 using PWM control, continuously adjust the current flowing in inductor 671 in response to feedback of the output voltage as filtered by reservoir capacitor 672.

In converter 660, the charge pump pre-converter 660A and the inductive post-regulator 660B share no components and may operate independently. Accordingly, MOSFETs 668 through 669 can switch at a frequency different than MOSFETs 661 through 665. In such asynchronous operation, capacitor 675 must store energy output from charge pump pre-converter 660A and supply it to the input of post-regulator 660B and must comprise sufficient capacitance to supply all current transients as demanded. While the two clock pulse generators controlling pre-converter 660A and post-regulator 660B, respectively, may “free run” and thereby vary in frequency, unsynchronized operation can lead to excessive switching noise in the system.

In a preferred embodiment of a multi-frequency implementation of 0.5X CLDD converter 660, pre-converter 660A and post-regulator 660B switch at different frequencies but are synchronized either by a phase-locked-loop, also known as a PLL, or by using a common clock generator, multiplied-up or divided-down to generate the two dissimilar clock signals. Ideally the clock waveform for inductive post-regulator 660B comprises a ramp generator rather to produce a square, triangle, or saw-tooth ramp wave. The gate drive for charge pump MOSFETs 661, 662, 663, 664 and 665 may however comprise square wave signals generated by feeding the output of the ramp generator into a comparator. Alternatively, one or more of the MOSFETs 661, 662, 663, 664 and 665 in the charge pump pre-converter 660A may be used to limit the inrush current to the charge pump during the charging or discharging of its flying capacitors.

If, in contrast, charge pump pre-converter 660A and inductive post-regulator 660B are switched in phase and at the same frequency, the size of an intermediate capacitor between the two stages can be greatly diminished or even eliminated. Under such circumstances, since each of MOSFETs 664 and 665 in the charge pump pre-converter 660A is wired in series with MOSFET 668 in post-regulator 660B, whenever MOSFETs 664, 665 and 668 are switching on and off together at the same frequency, MOSFET 668 is redundant and may be eliminated.

The resulting 0.5X-type LCDD converter 700 is illustrated in <figref idrefs="DRAWINGS">FIG. 17B</figref>, where MOSFETs 704 and 705 serve both as output transistors for the charge pump pre-converter 700A and as input devices for the inductive post-regulator 700B. This modification reduces series resistance, conduction and switching losses in the LCDD converter and also saves die area. The intervening capacitor 675 is also eliminated, since flying capacitors 706 and 707 act in parallel as an input filter for post-regulator 700B whenever MOSFETs 704 and 705 are on and conducting.

As shown, the fractional switched capacitor pre-converter 700A of converter 700 comprises five MOSFETs 701, 702, 703, 704, and 705 with flying capacitors 706 and 707. The MOSFETs are controlled by break-before-make (BBM) buffer 713 to alternatively charge and discharge flying capacitors 706 and 707. The current flowing through inductor 710 is dynamically adjusted by the duty factor of MOSFETs 704 and 705, with a PWM controller 712 responding to changes in the output voltage of converter 700. Feedback signal VFB is adjusted in voltage by a level shift circuit 714 to control PWM controller 712.

When high-side MOSFETs 704 and 705 are conducting, the voltage Vx is biased at Vy′ approximately equal to {0.5Vbatt−IL·½RDS}, during which time inductor 710 is magnetized, i.e. stores energy while delivering current to the output terminal and simultaneously transferring energy and charging output capacitor 711. When MOSFETs 704 and 705 are turned off, the voltage Vx flies below ground, forwarding biasing diode 709 and recirculating current. The synchronized conduction of MOSFETs 704 and 705 not only performs the function of controlling the output current of 0.5X charge pump pre-converter 700A, but also performs the function of the input MOSFETs for the inductive post converter 700B, thereby eliminating the need for one high current low-resistance MOSFET, saving die area and improving efficiency.

Some portion of the time while diode 709 is forward-biased, synchronous rectifier MOSFET 708 is turned on, diverting the current from diode 709. Break-before-make buffer 713 drives the gate of MOSFETs 708 out of phase with MOSFETs 704 and 705, insuring that flying capacitors 706 and 707 are not shorted to ground by simultaneous conduction of MOSFETs 704, 705, and 708. A clock generator 715 synchronizes the switching of pre-converter 700A to the switching of post-regulator 700B, while PWM controller 712 controls the pulse width, i.e. on-time, of all MOSFETs in response to changes in the output voltage and feedback signal VFB.

Notice that in converter 700, the intermediate capacitor connected between charge pump pre-converter 700A and inductive post-regulator 700B has been eliminated, i.e., there in no equivalent to capacitor 675 of converter 660 in converter 700. Therefore, a steady intermediate voltage Vy does not exist in converter 700. The node voltage Vy′ emulates the behavior of intermediate voltage Vy during the time when MOSFETs 704 and 705 conduct and inductor 710 is being magnetized. During that portion of the half-cycle of converter 700, the voltage Vy′ is approximately equal to one-half the battery input voltage. During the other half-cycle, when flying capacitors 706 and 707 are charged in series, each capacitor is charged to a voltage of Vbatt/2 through conducting MOSFETs 701, 702 and 703 and no longer behaves as a semi-constant voltage source or power supply. So Vy′ acts as a “virtual” constant voltage source whenever it is powering post-regulator 700B, hence the prime notation “′”.

In an alternative embodiment, synchronous rectifier MOSFET 708 may be eliminated and recirculation current carried entirely by diode 709, which preferably should comprise a Schottky metal-semiconductor diode, not a P-N junction diode. Schottky diodes are preferred because they exhibit lower forward voltage drops than junction diodes. In yet another embodiment, a Schottky diode can be placed in parallel with MOSFET 708 and intrinsic P-N diode 709.

The operation of fractional CLDD converter 700 is illustrated in <figref idrefs="DRAWINGS">FIGS. 17C and 17D</figref>. In equivalent circuit diagram 720 of <figref idrefs="DRAWINGS">FIG. 17C</figref>, capacitors 706 and 707 are charged through conducting MOSFETs 701 and 702 while MOSFETs 703, 704, and 705 remain off. Series-connected flying capacitors 706 and 707 are each charged to the half the battery input voltage, i.e. to Vbatt/2.

During this phase, synchronous rectifier MOSFET 708 is conducting recirculation current IL through inductor 710, thereby moving energy from inductor 710 to output capacitor 711 and to load 721. The phase can be referred to as the “charging and recirculation phase”, i.e. the charging of the flying capacitors and the maintaining of the output voltage through inductor recirculation. During this phase, MOSFETs 704 and 705 are turned off and output capacitor Cout 711 supplies the necessary load current Iout to the electrical load 721. Specifically, during this phase the energy in inductor 710 is used to replenish output capacitor 711 as it is being discharged by load 721. A recirculation current flows through MOSFET 708, diode 709 and filter capacitor 711. The voltage across capacitor 711 begins to sag during this cycle and is replenished during the subsequent transfer phase shown in <figref idrefs="DRAWINGS">FIG. 17D</figref>.

<figref idrefs="DRAWINGS">FIG. 17D</figref> represents the transfer phase, when energy is transferred from flying capacitors 706 and 707 in pre-converter 700A to inductor 710 in post-regulator 700B. This transfer is achieved by shutting off charge circuit MOSFETs 701, 702, and 709, and by turning on MOSFETs 703, 704, and 705, thereby connecting flying capacitors 706 and 707 in parallel referenced to ground, and in series with inductor 710. This connection simultaneously magnetizes inductor 710, storing energy I2L, and transfers charge from flying capacitors 706 and 707 to reservoir capacitor 711 at a voltage D·Vy, i.e., the voltage on the flying capacitors (0.5·Vbatt) times the duty factor D of MOSFETs 704 and 705.

The two phases alternate to keep inductor 710 magnetized and flying capacitors 706 and 707 and output capacitor 711 charged. The entire system is efficient because once the voltage builds up on flying capacitors 706 and 707 and filter capacitor 711 during start-up, steady state operation must only replenish enough charge to compensate for the small shifts in voltage resulting from voltage sagging across capacitors 706, 707 and 711 as they discharge.

Switched Capacitor-Inductor (CLID) Regulating Inverters

The generic CLXD converter topology of <figref idrefs="DRAWINGS">FIG. 9</figref> is also useful for producing regulated voltages below ground. By utilizing an inverting charge-pump as a pre-converter followed by an inductive down converter, inverting voltage conversion is performed in two stages, referred to herein as a CLID converter. The switched-inductor post converter as described comprises a down converter, meaning the absolute magnitude of the voltage is decreased.

Examining the implementation of the CLID-type inverters in greater detail, <figref idrefs="DRAWINGS">FIGS. 18A and 18B</figref> illustrate the functional block diagrams of two different switched CLID inverting converters, comprising a −1X type pre-converter in <figref idrefs="DRAWINGS">FIG. 18A</figref> and a fractional −0.5X type pre-converter in <figref idrefs="DRAWINGS">FIG. 18B</figref>. In both <figref idrefs="DRAWINGS">FIG. 18A</figref> and <figref idrefs="DRAWINGS">FIG. 18B</figref>, the post converter comprises a non inverting Buck converter, a circuit that decreases the absolute magnitude of the negative output voltage, i.e. a smaller, less negative voltage. Such circuit topologies are referred to herein as CLID inverters.

In <figref idrefs="DRAWINGS">FIG. 18A</figref>, a −1X type CLID inverting converter 760 comprises a pre-converter 760A and a post-regulator 760B. Pre-converter 760A comprises a doubler charge pump 761 with a flying capacitor 762 and a filter capacitor 763, where the output of charge pump 761 supplies a negative, i.e. below ground, intermediate voltage Vy. The intermediate voltage Vy in turn powers a non-inverting step-down switched-inductor post-regulator 760B, comprising an inductor 766, a MOSFET 764, a synchronous rectifier MOSFET 765 with an intrinsic rectifier diode 767 and an output capacitor 768. MOSFET 765 includes a P-N diode 767 which remains reverse-biased since Vx≦0. In some cases, depending on the magnitude of the capacitance C1 of filter capacitor 763, a P-N diode is included in parallel with capacitor 763 to clamp the positive voltage range of Vy. Since Vy=−1·Vbatt and Vout=D·Vy, then the voltage conversion ratio of −1X-type CLID converter 760 is given by

The ability of −1X CLID inverting converter 760 to create and regulate a −0.9V or −1.8V output from a wide range of input voltages is illustrated in graph 800 of <figref idrefs="DRAWINGS">FIG. 19A</figref>, with inputs as shown ranging from 2V up to 5V, a range including 1s Lilon discharge condition. As shown, the battery or input voltage (curve 801) is inverted to produce intermediate voltage Vy shown by curve 802. Using a non-inverting Buck type post-regulator operating at a duty factor D1, a regulated −0.9V output (curve 803) is produced, or at a different duty factor D2, a −1.2V output (not shown) may be produced.

An example of CLID conversion is illustrated in graph 820 of <figref idrefs="DRAWINGS">FIG. 19B</figref> where the discharge of a 1s Lilon battery is inverted and regulated to −1.8V. The Lilon battery fully charged starts with a 4.2V condition (curve 821) that decays over time to a plateau voltage (curve 822) of approximately 3.5V and then eventually reaches its discharged condition of 2.7V (curve 823). The single-capacitor pre-converter 760A of −1X-type CLID converter 760 produces a time varying negative voltage −Vy, shown by curve 824, ranging from −4.2V to −2.7V. The intermediate voltage −Vy is then stepped down in magnitude to −1.8V by an a varying amount D, using a step-down post-regulator to produce a constant −1.8V output (curve 825).

In some cases, a −1X pre-converter in a −1X CLID inverting converter produces an undesirably large negative intermediate voltage Vy at high input voltage conditions, forcing the post-regulator to operate at low duty factors. One way to avoid this problem is to employ a −0.5X-type fractional charge pump inverting pre-converter instead of a −1X type pre-converter.

−0.5X-type CLID Inverting converter: In <figref idrefs="DRAWINGS">FIG. 18B</figref>, a −0.5X type CLID inverting converter 780 comprises a pre-converter 780A and a post-regulator 780B. Pre-converter 780A comprises a fractional charge pump 781 with flying capacitors 782 and 783 and a filter capacitor 784, where the output of charge pump 781 supplies a negative, i.e. below ground, intermediate voltage Vy. Intermediate voltage Vy in turn powers a non-inverting step-down switched-inductor post converter 780B comprising an inductor 788, a MOSFET 785, a synchronous rectifier MOSFET 786 with an intrinsic rectifier diode 787 with an output capacitor 789. MOSFET 786 includes a P-N diode 787 which remains reverse biased since Vx≦0. In some cases, depending on the magnitude of the capacitance C1 of filter capacitor 784, a diode parallel to capacitor 784 is included to clamp the positive voltage range of Vy. Since Vy=−0.5Vbatt and Vout=D·Vy, then the voltage conversion ratio of −0.5X-type CLID converter 780 is given by

The ability of −0.5X CLIU inverting converter 780 to create and regulate a −0.9V output from a wide range of input voltages is illustrated in graph 840 of <figref idrefs="DRAWINGS">FIG. 19C</figref>, with inputs as shown ranging from 2V up to 5V, a range including a 1s Lilon discharge condition. As shown, battery or input voltage (curve 841) is inverted and halved to produce intermediate voltage Vy, shown by curve 843, ranging from 1V to 2.5V. Using step-down post-regulator 780B operating at a duty factor D1, a regulated −0.9V output (curve 844) is produced, or at a different duty factor (not shown), a −1.8V output may be produced from a 1s Lilon battery.

An example of −0.5X CLID conversion is illustrated in graph 860 of <figref idrefs="DRAWINGS">FIG. 19D</figref>, where the discharge of a 1s Lilon battery is inverted and regulated to −0.9V. The Lilon battery fully charged starts with a 4.2V condition (curve 861) that decays over time to a plateau voltage (curve 862) of approximately 3.5V and then eventually reached its discharged condition of 2.7V (curve 863). The single-capacitor pre-converter 780A of −0.5X-type CLID converter 780 produces a time varying negative voltage −Vy, shown by curve 865, ranging from −2.1V to −1.35V. The intermediate voltage Vy is then stepped down in absolute magnitude to −0.9V by a varying amount D, using non-inverting step-down post-regulator 780B to produce a constant −0.9V output (curve 866).

The duty factor for CLID inverting converters can be derived by rearranging the formula for the CLXD converter to yield

<maths id="MATH-US-00024" num="00024"><math overflow="scroll"><mrow><mi>D</mi><mo>=</mo><mrow><mfrac><msub><mi>V</mi><mi>out</mi></msub><mrow><mi>n</mi><mo>·</mo><msub><mi>V</mi><mi>batt</mi></msub></mrow></mfrac><mo>=</mo><mrow><mo>-</mo><mfrac><msub><mi>V</mi><mi>out</mi></msub><msub><mi>V</mi><mi>batt</mi></msub></mfrac></mrow></mrow></mrow></math></maths> in the case of the single capacitor inverter and by

Since n<0 and Vout/Vbatt<0, both numbers are negative and the duty factor equation mathematically behaves the same as a non-inverting CLID converter. This principle is illustrated in graph 880 of <figref idrefs="DRAWINGS">FIG. 19E</figref>, where curve 881 represents the voltage conversion ratio of a Buck converter as a function of duty factor. The conversion ratio of a −1X-type CLID inverting converter (curve 882) is the negative mirror image of the conversion ratio of a Buck converter (curve 881) and the conversion ratio of a −0.5X CLID inverting converter (curve 883) is one-half that value, or a negative mirror image of the conversion ratio of a +0.5X CLDD converter, described previously.

Table 5 contrasts the D=50% preferred conversion ratio for −1X CLID and −0.5X CLID converters and illustrates the duty factor range needed to output several negative output voltages from a Lilon battery.

<tables id="TABLE-US-00005" num="00005"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="63pt" align="left" /><colspec colname="3" colwidth="70pt" align="left" /><colspec colname="4" colwidth="63pt" align="left" /><thead><row><entry namest="1" nameend="4" rowsep="1">TABLE 5</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry>Condition</entry><entry>−0.5X CLID</entry><entry>−1X CLID</entry><entry>Buck (Positive)</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>D = 50%</entry><entry>Vout/Vin = −0.25</entry><entry>Vout/Vin = −0.5</entry><entry>Vout/Vin = 0.5</entry></row><row><entry>Lilon → −3.0 V</entry><entry>N/A</entry><entry>71% < D < 100%*</entry><entry>71% < D < 100%*</entry></row><row><entry>Lilon → −2.7 V</entry><entry>N/A</entry><entry>64% < D < 90%</entry><entry>64% < D < 90%</entry></row><row><entry>Lilon → −1.8 V</entry><entry>N/A</entry><entry>43% < D < 60%</entry><entry>43% < D < 60%</entry></row><row><entry>Lilon → −0.9 V</entry><entry>42% < D < 60%</entry><entry>21% < D < 30%</entry><entry>21% < D < 30%</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Those conditions marked with an asterisk (*) may require limiting the converter's operating frequency in order to meet the full range in required duty factors. Those marked with N/A require both step-up and step-down inversion.

CLID Converter Implementation: A circuit diagram of a CLID converter 900 using a −1X-type pre-converter is shown in <figref idrefs="DRAWINGS">FIG. 20A</figref>. As shown, a charge pump inverting pre-converter 900A comprises MOSFETs 901, 902, 903, and 904 and a flying capacitor 905, providing intermediate negative output voltage −Vy, and an optional filter capacitor 906. A diode across capacitor 906 may be included to limit the Vy positive voltage swing and may be omitted depending on the capacitance value C1 of capacitor 906. Intermediate voltage Vy is connected to an inductor 911 of Buck-type post-regulator 600B with a ground-connected MOSFET 909, a floating synchronous rectifier MOSFET 907 with an intrinsic P-N diode 908 and an output capacitor 912 driving a load (not shown). Since Vx≦0, the output of −1X-type CLID converter 900 is given by the equation Vout=−D·Vbatt

Since MOSFETs 904 and 907 are connected in series, synchronous operation of charge pump pre-converter 900A and inductive post-regulator 900B at the same frequency and in phase means that one of these two MOSFETs is redundant and can be eliminated, along with capacitor 906. This simplified version of the CLID converter is illustrated as converter 930 of <figref idrefs="DRAWINGS">FIG. 20B</figref>.

As shown, a charge pump inverting pre-converter 930A comprises MOSFETs 931, 932, and 933 with a flying capacitor 936, which provides an intermediate negative output voltage Vy′. Intermediate voltage Vy′ is connected to an inductor 939 of a Buck-type post-regulator 930B having a ground-connected MOSFET 935, a synchronous rectifier MOSFET 934 with an intrinsic P-N diode 937 and an output capacitor 940 driving a load (not shown).

Post-regulator 930B is controlled by PWM a controller 945, driving MOSFET 935 in response to the feedback signal VFB from the output, terminal of converter 930, level shifted to the appropriate value VFBin by a level shift circuit 946. Level shift circuit 946 is needed to convert the output voltage Vout which is negative, i.e. below circuit ground, to a voltage within the range of the PWM control circuit 945. One convenient method to implement level shift circuit 946 involves current mirrors. The implementation of a feedback circuit is described in the above-referenced application Ser. No. 11/890,818.

As shown, a clock and ramp generator 947 is used to switch PWM controller 945 at a frequency φ and is used to drive the MOSFETs 931, 932 and 933 in pre-converter 930A at a frequency m·φ, where in the simplified case m=1 and the charge pump pre-converter 930A and switched inductor post-regulator 930B are clocked at the same frequency and synchronized to the same clock. A break-before-make (BBM) circuit 938 provides the gate drive and necessary level shifting VG1 to VG3 to MOSFETs 931, 932 and 933, respectively. A BBM circuit 949 drives MOSFET 935 and synchronous rectifier MOSFET 934 in response to PWM controller 945, preventing significant shoot-through conduction, i.e. simultaneous conduction in MOSFETs 935 and 934 to prevent damage and improve the efficiency of converter 930.

As shown in the equivalent circuit diagrams of <figref idrefs="DRAWINGS">FIGS. 20C and 20D</figref>, the operation of −1X-type CLID converter 930 occurs in two alternating phases. In the charging and recirculating phase, shown in <figref idrefs="DRAWINGS">FIG. 20C</figref>, flying capacitor 936 is charged through MOSFETs 931 and 932 to substantially the full battery voltage Vbatt, while the current IL in inductor 939 re-circulates through diode 938, the on-state synchronous rectifier MOSFET 935, output capacitor 940, and to load 961. MOSFETs 933 and 934 remain off in this phase of operation. The on-time of synchronous rectifier MOSFET 935 may be less than the entire period during which diode 938 is conducting and may rely on more control signals than simply the gate drive of MOSFET 934 to determine when it should commence and cease conduction.

In the second phase, shown in <figref idrefs="DRAWINGS">FIG. 20D</figref>, conducting MOSFETs 931, 932, and 935 are turned off and MOSFETs 933 and 934 are turned on to connect flying capacitor 936 to inductor 939 thereby magnetizing the inductor. During this cycle output capacitor 940 supplies load 961. After a prescribed time, determined by PWM controller 945, converter 930 reverts to the first phase, alternating according to the duty factor provided by PWM controller 945.

In another embodiment, synchronous rectifier MOSFET is never turned off fully but only reduced to low current operation, in the range of a few microamperes to reduce noise as described in the above-referenced application Ser. No. 11/890,947.

Fractional CLIU Converter Implementation: A CLID converter 1000 using a −0.5X-type pre-converter 1000A is shown in <figref idrefs="DRAWINGS">FIG. 21A</figref>. Fractional charge pump pre-converter 1000A comprises MOSFETs 1001 through 1007 with flying capacitors 1016 and 1017. As converter 1000 is a simplified circuit, intermediate voltage Vy is not a constant voltage. Instead, during the conduction of MOSFETs 1006 and 1007, the voltage Vy acts like a virtual voltage source connected to inductor 1010 of non-inverting Buck-type post-regulator 1000B. Post-regulator 1000B includes MOSFETs 1006 and 1007, a synchronous rectifier MOSFET 1008 with an intrinsic P-N diode 1009, and an output capacitor 1011 driving a load (not shown). The output voltage of −0.5X-type LCID converter is given by the equation Vout=n·D·Vbatt=−0.5·D·Vbatt

Post-regulator 1000B is controlled by a PWM controller 1012 driving MOSFETs 1006 and 1007 in response to the feedback signal VFB from the output terminal of converter 1000, level shifted to the appropriate value VFBin by level shift circuit 1014. Level shift circuit 1014 is needed to convert the output voltage Vout which is negative, i.e. below ground, to a positive signal within the range of the PWM controllwe 1012. One convenient method to implement level shift circuit 1014 involves current mirrors. The implementation of a feedback circuit is described in the above-referenced application Ser. No. 11/890,818.

As shown, a clock and ramp generator 1015 is used to switch PWM controller 1012 at a frequency φ and is used to drive MOSFETs 1001 through 1007 in charge pump pre-converter 1000A at a frequency m·φ, which may be higher or lower than the switching frequency of post-regulator 1000B. In the embodiment shown in <figref idrefs="DRAWINGS">FIG. 21A</figref>, m=1 and charge pump pre-converter 1000A and switched inductor post-regulator 1000B are clocked at the same frequency and synchronized to the same clock. A break-before-make (BBM) circuit 1013 provides the gate drive and necessary level shifting VG1 to VG7 to MOSFETs 1001 through 1007. BBM circuit 1013 drives MOSFETs 1006 and 1007 and synchronous rectifier MOSFET 1008 in response to PWM controller 1012, preventing significant shoot-through conduction, i.e. simultaneous conduction in MOSFETs 1009, 1006 and 1007, to prevent damage and improve the efficiency of converter 1000.

As shown in the equivalent circuit diagrams of <figref idrefs="DRAWINGS">FIGS. 21B and 21C</figref>, the operation of −0.5X fractional type CLID inverting converter 1000 occurs in two alternating phases. In the charging and recirculating phase, shown in <figref idrefs="DRAWINGS">FIG. 21B</figref>, flying capacitors 1016 and 1017 are charged through MOSFETs 1001, 1002, and 1003 to substantially one-half the battery voltage, i.e. Vbatt/2, while the current IL in inductor 1010 re-circulates through diode 1009, the on-state synchronous rectifier MOSFET 1008, output capacitor 1011, and to the load 1021. The recirculation path is completed by capacitor 1011. MOSFETs 1004, 1005, 1006, and 1007 remain off in this phase of operation. The on-time of synchronous rectifier MOSFET 1008 may be less than the entire period during which diode 1009 is conducting and may rely on more control signals than simply the gate drive of MOSFETs 1006 and 1007 to determine when it should commence and cease conduction.

In the second phase, MOSFETs 1001, 1002, 1003 and 1008 are turned off and MOSFETs 1004, 1005, 1006, 1077 and 1063 are turned on to connect flying capacitors 1016 and 1017 to inductor 1010, thereby magnetizing inductor 1010. After a prescribed time determined by the PWM controller 1012, converter 1000 reverts to the first phase, alternating according to the duty factor provided by PWM controller 1012.

In another embodiment, synchronous rectifier MOSFET 1008 is never turned off fully but only reduced to low current operation, in the range of a few microamperes to reduce noise as described in the above-referenced application Ser. No. 11/890,947.

While specific embodiments according to the invention are described above, these embodiments are intended to be illustrative and not limiting. Many additional and alternative embodiments within the broad scope of this invention will be apparent to persons of skill in the art.

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US2008157733A1	United States of America	A1	2008-07-03
US2008158915A1	United States of America	A1	2008-07-03
WO2008082578A1	World Intellectual Property Organization (WIPO)	A1	2008-07-10
WO2008082581A1	World Intellectual Property Organization (WIPO)	A1	2008-07-10
WO2008082582A1	World Intellectual Property Organization (WIPO)	A1	2008-07-10
WO2008082585A1	World Intellectual Property Organization (WIPO)	A1	2008-07-10
TW200843307A	Taiwan Province of China	A	2008-11-01
TW200843308A	Taiwan Province of China	A	2008-11-01
TW200843309A	Taiwan Province of China	A	2008-11-01
TW200843310A	Taiwan Province of China	A	2008-11-01
US2009059630A1	United States of America	A1	2009-03-05
US2009102439A1	United States of America	A1	2009-04-23
KR20090106405A	Republic of Korea	A	2009-10-08
KR20090107519A	Republic of Korea	A	2009-10-13
WO2010014232A2	World Intellectual Property Organization (WIPO)	A2	2010-02-04
CN101647181A	China	A	2010-02-10
CN101647182A	China	A	2010-02-10
TW201014136A	Taiwan Province of China	A	2010-04-01
WO2010014232A3	World Intellectual Property Organization (WIPO)	A3	2010-04-22
WO2010014232A3	World Intellectual Property Organization (WIPO)	A3	2010-04-22
JP2010515419A	Japan	A	2010-05-06
US7777459B2This record	United States of America	B2	2010-08-17
US7782027B2	United States of America	B2	2010-08-24
US7786712B2	United States of America	B2	2010-08-31
US7812579B2	United States of America	B2	2010-10-12
KR20110033949A	Republic of Korea	A	2011-04-01
EP2313963A2	European Patent Office (EPO)	A2	2011-04-27
US7977927B2	United States of America	B2	2011-07-12
CN102171918A	China	A	2011-08-31
JP2011530269A	Japan	A	2011-12-15
TWI357710B	Taiwan Province of China	B	2012-02-01
TWI357711B	Taiwan Province of China	B	2012-02-01
TWI357712B	Taiwan Province of China	B	2012-02-01
TWI357713B	Taiwan Province of China	B	2012-02-01
CN101647181B	China	B	2012-08-29
CN101647182B	China	B	2013-01-30
TWI403082B	Taiwan Province of China	B	2013-07-21
KR20130109261A	Republic of Korea	A	2013-10-07
KR20130111645A	Republic of Korea	A	2013-10-10
KR101335764B1	Republic of Korea	B1	2013-12-02
KR101340204B1	Republic of Korea	B1	2013-12-10
JP5401546B2	Japan	B2	2014-01-29
KR20140079873A	Republic of Korea	A	2014-06-27
KR101436774B1	Republic of Korea	B1	2014-09-03
KR20150006486A	Republic of Korea	A	2015-01-16
KR101497723B1	Republic of Korea	B1	2015-03-02
KR101504884B1	Republic of Korea	B1	2015-03-20
CN102171918B	China	B	2015-04-01
JP5757685B2	Japan	B2	2015-07-29
EP2313963A4	European Patent Office (EPO)	A4	2018-01-31
EP2313963B1	European Patent Office (EPO)	B1	2019-10-02

72 transactions on the USPTO file

Allowed after 1 non-final rejection, 1 final rejection and 1 RCE.

Non-final rejections: 1
Final rejections: 1
RCEs: 1
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2022-02-17	Payment of Maintenance Fee, 12th Year, Large EntityM1553	M1553
2020-03-27	Email NotificationEML_NTR	EML_NTR
2020-03-27	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2020-03-26	Correspondence Address ChangeC.AD	C.AD
2018-02-19	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2010-08-17	Recordation of Patent Grant MailedPGM/	PGM/
2010-08-17	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2010-07-28	Issue Notification MailedAllowedWPIR	WPIR
2010-07-19	Dispatch to FDCD1935	D1935
2010-07-19	Application Is Considered Ready for IssuePILS	PILS
2010-07-06	Issue Fee Payment VerifiedN084	N084
2010-07-06	Issue Fee Payment ReceivedIFEE	IFEE
2010-04-15	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2010-04-14	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2010-04-14	Case Docketed to Examiner in GAUDOCK	DOCK
2010-03-29	Paralegal or electronic terminal disclaimer approvedP574	P574
2010-03-13	Date Forwarded to ExaminerFWDX	FWDX
2010-03-13	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2010-03-01	Information Disclosure Statement consideredIDSC	IDSC
2010-03-01	Terminal Disclaimer FiledDIST	DIST
2010-03-01	Reference capture on IDSRCAP	RCAP
2010-03-01	Information Disclosure Statement (IDS) FiledM844	M844
2010-03-01	Request for Continued Examination (RCE)RCEX	RCEX
2010-03-01	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2010-03-01	Workflow - Request for RCE - BeginBRCE	BRCE
2009-12-30	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2009-12-29	Final RejectionFinal rejectionCTFR	CTFR
2009-10-21	Reference capture on IDSRCAP	RCAP
2009-10-21	Information Disclosure Statement (IDS) FiledM844	M844
2009-10-21	Information Disclosure Statement consideredIDSC	IDSC
2009-10-21	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2009-10-20	Date Forwarded to ExaminerFWDX	FWDX
2009-09-03	Information Disclosure Statement consideredIDSC	IDSC
2009-09-03	Reference capture on IDSRCAP	RCAP
2009-09-03	Information Disclosure Statement (IDS) FiledM844	M844
2009-09-03	Response after Non-Final ActionA...	A...
2009-09-03	Request for Extension of Time - GrantedXT/G	XT/G
2009-09-03	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2009-05-21	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2009-05-20	Non-Final RejectionNon-final rejectionCTNF	CTNF
2009-05-07	Case Docketed to Examiner in GAUDOCK	DOCK
2009-03-05	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2009-03-04	Reference capture on IDSRCAP	RCAP
2009-03-04	Information Disclosure Statement (IDS) FiledM844	M844
2009-03-04	Information Disclosure Statement consideredIDSC	IDSC
2009-03-04	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2009-01-20	Case Docketed to Examiner in GAUDOCK	DOCK
2008-12-03	Application Dispatched from OIPEOIPE	OIPE
2008-11-21	Sent to Classification ContractorPGPC	PGPC
2008-11-21	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2008-11-21	Mail Pre-Exam NoticeMPEN	MPEN
2008-11-10	Mail-Petition Decision - GrantedMPTGR	MPTGR
2008-11-10	Petition Decision - GrantedPTGR	PTGR
2008-07-30	Mail Non-Compliant Preliminary AmendmentMNPRL	MNPRL
2008-07-30	Non-Compliant Preliminary AmendmentNPRL	NPRL
2008-06-12	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2008-06-12	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2008-06-12	Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW	CORRDRW
2008-06-12	Petition EnteredPET.	PET.
2008-06-12	Preliminary AmendmentA.PE	A.PE
2008-05-14	Information Disclosure Statement consideredIDSC	IDSC
2008-05-14	Reference capture on IDSRCAP	RCAP
2008-05-14	Information Disclosure Statement (IDS) FiledM844	M844
2008-05-14	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2008-05-02	Withdraw Pre-Exam AbandonAbandonedWPABN	WPABN
2007-11-26	Preliminary AmendmentA.PE	A.PE
2007-10-23	Abandonment -- During Preexam ProcessingAbandonedABNX	ABNX
2007-08-22	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2007-08-15	Cleared by OIPE CSRL194	L194
2007-08-15	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2007-08-09	Initial Exam Team nnIEXX	IEXX
2007-08-08	Claim Preliminary AmendmentCLAIM	CLAIM

6 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2025-05-08	AssignmentAS	AS
2022-02-17	Maintenance fee paymentMAFP	MAFP
2018-02-19	Maintenance fee paymentMAFP	MAFP
2014-02-17	Fee paymentFPAY	FPAY
2010-07-28	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2008-07-25	AssignmentAS	AS

High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator

Summary by NHIP

Claim Score by NHIP

Abstract

Term

FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION

SUMMARY OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

DESCRIPTION OF THE INVENTION

Priority claims10

Members52

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Transactions

Over the term

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Titles

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Abstract

Term

CROSS-REFERENCE TO RELATED APPLICATIONS

FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION

SUMMARY OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

DESCRIPTION OF THE INVENTION

Priority claims10

Members52

Over time

Transactions

Over the term

Events

Numbers

Titles

Patent term adjustment

Classification