US7772048B2

Forming semiconductor fins using a sacrificial fin

Summary by NHIP

Sacrificial fin semiconductor method

The method forms semiconductor fins by trimming a first fin, epitaxially growing second and third fins under overhanging capping layers, and selectively etching the original fin. Distinctive elements include isotropic trimming, oxide growth on sidewalls, and selective etching between silicon germanium first fins and silicon second and third fins.

Claim Score by NHIP

Read claim 6, the broadest

Abstract

A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.

US7772048B2, drawing sheet 1 — Sheet 1 of 12

Term

1.4 yearsleft in the term

Expires 14 February 2028, including 356 days of term adjustment.

13 claims: 3 independent, 10 dependent

1
A method for forming a semiconductor device comprising:forming a first fin structure having a first semiconductor fin and a capping layer overlying the first semiconductor fin, wherein the first semiconductor fin has a first sidewall and a second sidewall aligned with sides of the capping layer;trimming the first semiconductor fin resulting in the capping layer having a first overhang extending past first sidewall and the second overhand extending past the second sidewall;epitaxially growing a second semiconductor fin on the first sidewall under the first overhang and a third semiconductor fin on the second sidewall under the second overhang;removing the capping layer to expose first semiconductor fin;and removing the first semiconductor fin by performing an etch that is selective between the first semiconductor fin and the second and third semiconductor fins.
6
Broadest claimClaim Score 59, broad(NHIP)A method for forming a semiconductor device comprising:forming a capping structure over a semiconductor layer;removing portions of the semiconductor layer not protected by the capping structure to form a first semiconductor fin from the semiconductor layer, wherein the first semiconductor fin has a first sidewall and a second sidewall;trimming the first semiconductor fin resulting in the capping layer having a first overhang extending past first sidewall and the second overhand extending past the second sidewall;epitaxially growing a second semiconductor fin on the first sidewall under the first overhang and a third semiconductor fin on the second sidewall under the second overhang;removing the capping structure to expose the first semiconductor fin;and removing the first semiconductor fin by performing an etch that is selective between the first semiconductor fin and the second and third semiconductor fins.
11
A method for forming a FinFET transistor comprising:forming a first semiconductor material over a semiconductor seed layer to form a sacrificial layer;forming a capping structure over the sacrificial layer to define exposed sacrificial layer regions and unexposed sacrificial layer regions, wherein the unexposed sacrificial layer regions are below the capping structure;removing sacrificial layer material and underlying seed layer material from the exposed sacrificial layer regions to define a first semiconductor fin having a first sidewall and a second sidewall;removing material from the first semiconductor fin resulting in having the first and second sidewalls recessed relative to a periphery of the capping structure whereby the capping structure has a first overhang extending past the first sidewall and a second overhang extending past the second sidewall;epitaxially growing a layer of semiconductor material along the first and second sidewalls of the sacrificial structure, thereby substantially defining a second semiconductor fin on the first sidewall and a third semiconductor fin on the second sidewall;removing the capping structure to expose the first semiconductor fin;removing the first semiconductor fin to leave the second and third semiconductor fins;forming a gate dielectric layer over the second and third semiconductor fins;forming a gate electrode layer over the gate dielectric layer;and removing portions of the gate electrode layer to form a gate electrode structure that extends over the second and third semiconductor fins.

Independent claims3

53 paragraphs in 4 sections, as filed

0001This application is related to U.S. patent application Ser. No. 11/678322, titled “Semiconductor Fin Integration Using a Sacrificial Fin,” filed on even date herewith, filed by the inventors hereof, and assigned to the assignee hereof,

BACKGROUND

00021. Field

0003This disclosure relates generally to forming semiconductor fins for use in making semiconductor devices, and more specifically, to forming the semiconductor fins using a sacrificial fin.

00042. Related Art

0005The use of semiconductor fins in making semiconductor devices provides advantages over planar semiconductor devices. Transistors having a fin for the channel can be made to have lower leakage and higher drive because the gate, being on two sides of the channel, has more control of the channel. One of the desires generally relevant to semiconductor devices, including those using semiconductor fins, is to increase the density; to increase the number of devices in a given area. In the case of semiconductor fins, the minimum fins spacing is lithographically limited. Transistors using fins, however, are not expected to fit all of the requirements of an integrated circuit design. Thus, one issue is integrating the fins with planar transistors while improving density.

0006Thus, there is a need to improve the density of semiconductor devices using fins while also having desirable electrical characteristics, and a further desire is to efficiently integrate semiconductor fins with planar transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

0007The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

0008<figref idref="DRAWINGS">FIG. 1</figref> is a cross section of a semiconductor device at a stage in processing according to an embodiment of the invention;

0009<figref idref="DRAWINGS">FIG. 2</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref> at a subsequent stage in processing;

0010<figref idref="DRAWINGS">FIG. 3</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 2</figref> at a subsequent stage in processing;

0011<figref idref="DRAWINGS">FIG. 4</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 3</figref> at a subsequent stage in processing;

0012<figref idref="DRAWINGS">FIG. 5</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 4</figref> at a subsequent stage in processing;

0013<figref idref="DRAWINGS">FIG. 6</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 5</figref> at a subsequent stage in processing;

0014<figref idref="DRAWINGS">FIG. 7</figref> is a cross section of a semiconductor device at a stage in processing according to another embodiment of the invention;

0015<figref idref="DRAWINGS">FIG. 8</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 7</figref> at a subsequent stage in processing;

0016<figref idref="DRAWINGS">FIG. 9</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 8</figref> at a subsequent stage in processing;

0017<figref idref="DRAWINGS">FIG. 10</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 9</figref> at a subsequent stage in processing;

0018<figref idref="DRAWINGS">FIG. 11</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 10</figref> at a subsequent stage in processing;

0019<figref idref="DRAWINGS">FIG. 12</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 11</figref> at a subsequent stage in processing;

0020<figref idref="DRAWINGS">FIG. 13</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 12</figref> at a subsequent stage in processing;

0021<figref idref="DRAWINGS">FIG. 14</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 13</figref> at a subsequent stage in processing;

0022<figref idref="DRAWINGS">FIG. 15</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 14</figref> at a subsequent stage in processing;

0023<figref idref="DRAWINGS">FIG. 16</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 15</figref> at a subsequent stage in processing;

0024<figref idref="DRAWINGS">FIG. 17</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 16</figref> at a subsequent stage in processing;

0025<figref idref="DRAWINGS">FIG. 18</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 17</figref> at a subsequent stage in processing;

0026<figref idref="DRAWINGS">FIG. 19</figref> is a cross section of a semiconductor device at stage in processing for an alternative to a obtaining a semiconductor device similar to that of <figref idref="DRAWINGS">FIG. 10</figref>; and

0027<figref idref="DRAWINGS">FIG. 20</figref> is a cross section of the semiconductor device of <figref idref="DRAWINGS">FIG. 19</figref> at a subsequent stage in processing.

DETAILED DESCRIPTION

0028In one aspect, a sacrificial fin is formed of silicon germanium (SiGe) with an overlying nitride layer. The SiGe fin is trimmed to result in the silicon nitride (nitride) layer having an overhang extending past the sides of the SiGe fin. Epitaxial silicon is grown on the sides of the SiGe fin. During the growth, the nitride overhang functions to contain the silicon growth which has the affect of reducing or eliminating the occurrence of facets in the silicon growth. The reduction or elimination of facets provides for more control of the silicon width. The SiGe fin is removed leaving two silicon fins that are then used in transistor formation. This is better understood by reference to the drawings in the following description.

0029Shown in <figref idref="DRAWINGS">FIG. 1</figref> is semiconductor device 10 comprising a substrate 12, an insulating layer 14, a silicon germanium (SiGe) fin 16 over insulating layer 14, and a capping layer 18 over SiGe fin 16. Substrate 12 and insulating layer 14 and SiGe fin 16 may be formed from a semiconductor-on-insulator (SOI) substrate in which the overlying semiconductor layer is SiGe. Substrate 12 can be considered a handle wafer portion because it provides structural support. In this case SiGe fin 16 may be about 100 nanometers (nm) in height. Capping layer 18 and SiGe fin 16 arise from forming a SiGe layer over insulating layer 14 and another layer, preferably nitride in this example, over the SiGe layer. The nitride layer is patterned and the SiGe is then patterned as well. The width of SiGe fin 16 is preferably the smallest that can be achieved by the lithography that is available but could be another width. SiGe fin 16 is the length that is desired for the fin transistor to be formed in silicon using SiGe fin 16. At the end of this length, not shown but conventional for fins, is a source/drain region that is also elevated at the same height as SiGe fin 16. This source/drain is also covered with the nitride.

0030Shown in <figref idref="DRAWINGS">FIG. 2</figref> is semiconductor device 10 after trimming SiGe fin 16 which results in an overhang 20 where nitride layer 18 extends past the sides of trimmed SiGe fin 16. Preferably the overhang is about a fourth of the width of SiGe fin 16 of <figref idref="DRAWINGS">FIG. 1</figref>. Thus for an overhang on both sides of SiGe fin 16, trimming reduces the width in half to achieve the 25% overhang of overhang 20. Trimming is a well known process for silicon gates. Trimming processes, such as those used for trimming polysilicon gates, may be used with the corresponding adjustment in chemistry to account for the trimming being of SiGe instead of silicon. One such method is to oxidize along the sides and remove the resulting oxide. Another is to apply an isotropic etch.

0031Shown in <figref idref="DRAWINGS">FIG. 3</figref> is semiconductor device 10 after epitaxially growing a silicon fin 22 on one sidewall of SiGe fin 16 and a silicon fin 24 on the other side of SiGe fin 16. Silicon fins 22 and 24 have a width a little less than the amount of the overhang of overhang 20. Thus, silicon fins 22 and 24 are less than 25% of the width of SiGe fin 16. Thus about 20% of the width of SiGe fin 16 is achievable. The result is that for every sacrificial SiGe fin, there are two silicon fins. The width of sacrificial SiGe fin 16 is of a width to achieve the desired width and spacing of silicon fins 22 and 24. The spacing of the SiGe fins is preferably the minimum spacing. Thus if the SiGe fins are at the minimum spacing or repeat distance, also commonly called minimum pitch, the density is doubled from what the minimum pitch would normally provide by having two silicon fins per sacrificial SiGe fin.

0032Shown in <figref idref="DRAWINGS">FIG. 4</figref> is semiconductor device 10 after removing capping layer 18 shown in <figref idref="DRAWINGS">FIG. 3</figref>. The portions of capping layer 18 over the SiGe source/drain regions, which are not shown in the FIGS. are not removed at this step. This has the affect of exposing SiGe fin 16.

0033Shown in <figref idref="DRAWINGS">FIG. 5</figref> is semiconductor device 10 after removing SiGe fin 16. This leaves silicon fins 22 and 24 standing alone. There are etch chemistries that are selective between SiGe and silicon. One such chemistry is thermal gaseous HCl. Other selective etches include plasma fluorine chemistries or peroxide wet etches. Capping layer 18 over the SiGe source/drain regions may be removed after removing SiGe fin 16.

0034Shown in <figref idref="DRAWINGS">FIG. 6</figref> is semiconductor device 10 after forming a gate dielectric 26 on silicon fin 22, a gate dielectric 28 on semiconductor fin 24, and a polysilicon layer 30 on silicon fins 22 and 24. Gate dielectric 26 and gate dielectric 28 in this example are thermal oxides which may be grown in a typical fashion for gate dielectrics. An alternative would be to provide a high k gate dielectric such as hafnium oxide. In such case the gate dielectric would be deposited and would then be on the surface of insulating layer 14. Polysilicon layer 30 would be patterned and used as a gate. The view in <figref idref="DRAWINGS">FIG. 6</figref> is unchanged by patterning polysilicon layer 30.

0035Thus it is seen that fins can be made using a sacrificial SiGe fin to grow sublithographic silicon fins. With the trimming of the SiGe fin, there is left an overhang of an overlying capping layer. The overhang of the overlying capping layer constrains the epitaxial silicon growth to occur in one direction only so that facets do not occur or at least are significantly reduced. Thus fins 22 and 24 have thicknesses that are substantially uniform and have a well controlled width.

0036Shown in <figref idref="DRAWINGS">FIG. 7</figref> is a semiconductor device 50 comprising a substrate 52 (handle wafer portion), an insulating layer 54 over substrate 52, and a silicon layer 56 over the insulating layer. This is similar to a conventional SOI wafer except that silicon layer 56 is preferably thinner than the semiconductor layer on a conventional SOI wafer. For example, silicon layer 56 is preferably about 20 nm or even less. This can be achieved in a conventional SOI substrate by oxidizing the semiconductor surface of a conventional SOI substrate and then removing the oxide. The thickness can be quite thin because its purpose is as a seed layer. It may be thicker than the minimum but because it will be part of the channel, it should still be sufficiently thin to allow sufficient channel control, especially to avoid excessive off-state leakage.

0037Shown in <figref idref="DRAWINGS">FIG. 8</figref> is semiconductor device 50 after growing a SiGe layer 58 on silicon layer 56. The height of SiGe layer 58 is the desired height of the fins that will be subsequently formed, which is about 100 nm but could be another height. This structure of semiconductor device 50 shown in <figref idref="DRAWINGS">FIG. 8</figref> may also be directly available commercially from a vendor who may make it by this or another process such as layer transfer.

0038Shown in <figref idref="DRAWINGS">FIG. 9</figref> is semiconductor device 50 after forming a capping layer 60, preferably of oxide, over SiGe layer 58 and then removing a portion of SiGe layer 58 and capping layer 60. The removed portion is from a region 62 for forming planar transistors and the remaining portion of SiGe layer 58 is in a region 64 for forming fin transistors (finFETs). Silicon layer 56 is exposed in region 62.

0039Shown in <figref idref="DRAWINGS">FIG. 10</figref> is semiconductor device 50 after selectively growing epitaxial silicon on silicon layer 56 to form an epitaxial layer 66 that will function as the body for planar transistors and then removing capping layer 60. Dotted line 68 shows the previous surface of silicon layer 56. Line 68 is dotted because the demarcation of silicon layer 56 would unlikely to be discernible after performing the epitaxial growth to form epitaxial layer 66.

0040Shown in <figref idref="DRAWINGS">FIG. 11</figref> is semiconductor device 50 after forming isolation regions 70 and 72 in epitaxial layer 66 and forming a capping layer 74, preferably of nitride, over epitaxial layer 66, isolation regions 70 and 72, and SiGe layer 58. Capping layer 74 is preferably about 20-50 nm in thickness.

0041Shown in <figref idref="DRAWINGS">FIG. 12</figref> is semiconductor device 50 after performing a patterned etch through capping layer 74, SiGe layer 58, and silicon layer 56. This leaves a fin of SiGe similar to that of <figref idref="DRAWINGS">FIG. 1</figref> and the dimensions may be the same. A difference is that SiGe layer 58 is over a silicon layer, silicon layer 56, whereas SiGe fin 16 is directly on an insulating layer. In this cross section of <figref idref="DRAWINGS">FIG. 12</figref>, only the fin portion of SiGe layer 58 is shown, but source/drain portions at the ends of the fin are present and covered by nitride layer 74.

0042Shown in <figref idref="DRAWINGS">FIG. 13</figref> is semiconductor device 50 after trimming SiGe layer 58 and silicon layer 56. The trimming is the same as for the trimming shown in <figref idref="DRAWINGS">FIG. 2</figref> except that both SiGe and silicon are being trimmed so if an isotropic etch is used, it preferably is not selective, or at least not significantly so, between silicon and SiGe. Capping layer 74 thus overhangs past the sides of trimmed SiGe layer and silicon layer 56 by an overhang 76. The trimming is symmetrical so capping layer 74 overhangs on both sides. The trim also etches the side of epitaxial layer 66.

0043Shown in <figref idref="DRAWINGS">FIG. 14</figref> is semiconductor device 50 after silicon fins 78 and 80 are selectively epitaxially grown on the sides of SiGe layer 58 and silicon layer 56, and silicon fill 82 is simultaneously grown on the side of epitaxial layer 66. These silicon fins 78 and 80 are formed the same as described for silicon fins 22 and 24 of <figref idref="DRAWINGS">FIG. 3</figref> except for the growth from silicon layer 56. Thus, silicon fins 78 and 80 are formed at about 20% of the width of the SiGe layer 58 of <figref idref="DRAWINGS">FIG. 12</figref>. As described relative to <figref idref="DRAWINGS">FIG. 3</figref>, the result is that for every sacrificial SiGe fin, there are two silicon fins. The width of 58 sacrificial SiGe layer is of a width to achieve the desired width and spacing for silicon fins 78 and 80. The spacing of the SiGe fins is preferably the minimum spacing. Thus if the SiGe fins are at the minimum spacing, also commonly called minimum pitch, the density is doubled from what the minimum pitch would normally provide by having two silicon fins per sacrificial SiGe fin. The lines between silicon layer 56 and silicon fins 78 and 80 are unlikely to be visible due to they are the same material and silicon fins 78 and 80 are epitaxially grown.

0044Shown in <figref idref="DRAWINGS">FIG. 15</figref> is semiconductor device 50 after removing capping layer 74 over the fin portion of SiGe layer 58, which is in region 64. The portions of capping layer 74 over region 62 and over the source/drain regions (not shown) are not removed at this time.

0045Shown in <figref idref="DRAWINGS">FIG. 16</figref> is semiconductor device 50 after removing the fin portion of SiGe layer 58. The source/drain regions are not removed because they are still capped by capping layer 74. The resulting structure has fins 78 and 80 with silicon layer 56 between them. The removing of SiGe is selective to silicon. An etch chemistry that is effective for this purpose is thermal gaseous HCl. Other selective etches include plasma fluorine chemistries or peroxide wet etches. Capping layer 74 over region 62 and over the source/drains is removed after the SiGe fin portion is removed.

0046Shown in <figref idref="DRAWINGS">FIG. 17</figref> is semiconductor device 50 after forming a gate dielectric 84 on epitaxial layer 66, a gate dielectric layer 85 on the side of silicon fill 82, a gate dielectric layer 86 on silicon fins 78 and 80 and silicon layer 56, and a polysilicon layer 88 after forming gate dielectrics 84 and 86. As shown gate dielectrics 84 and 86 are preferably thermally grown oxide. An alternative would be to use another type of gate dielectric such as a high k dielectric such as hafnium oxide. In such case the gate dielectric would be deposited over all of the surfaces shown in <figref idref="DRAWINGS">FIG. 17</figref> before the formation of polysilicon layer 88. Polysilicon layer 88 could be replaced by another gate electrode material other than polysilicon or in addition to polysilicon.

0047Shown in <figref idref="DRAWINGS">FIG. 18</figref> is semiconductor device 50 after patterning polysilicon layer 88 and forming a transistor 96 in region 62 and a transistor 98 in region 64. Transistor 96 is a planar transistor having a portion of polysilicon layer 88 as the gate, source/drains 92 and 94 in epitaxial layer 66, and sidewall spacer 90 around the gate.

0048Thus it is seen that there is an integration on the same substrate of an integrated circuit of a planar transistor and a finFET. This shows that this integration may be achieved while using the overhang to achieve the reduced faceting while achieving sublithographic pitch by having two silicon fins per sacrificial fin with the sacrificial fins being at the minimum pitch. Also the height of the planar transistor above insulating layer 54 is substantially the same as the height of the finFET. This is beneficial for subsequent processing.

0049Shown in <figref idref="DRAWINGS">FIG. 19</figref> is a semiconductor device 100 comprising a substrate 102, an insulating layer 104, a silicon layer 106 that has been patterned, and a capping layer 108. Silicon layer 106 has a region 110 for planar transistors and a region 112 for forming finFETs. Silicon layer 106 has a height in region 110 that is about the same as the desired fin height and a height that is sufficient to function as a seed for SiGe epitaxial growth in region 112. This reduced height for silicon layer 106 in region 112 is achieved by a timed etch.

0050Shown in <figref idref="DRAWINGS">FIG. 20</figref> is semiconductor device 100 after epitaxially growing a SiGe layer 114 over silicon layer 106 in region 112 while capping layer 108 is present and then removing capping layer 108. This achieves the structure of <figref idref="DRAWINGS">FIG. 10</figref>. The process continues as described for <figref idref="DRAWINGS">FIGS. 11-18</figref>. This shows there are multiple techniques available to achieve the structure of <figref idref="DRAWINGS">FIG. 10</figref>.

0051Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different materials may be used than those described. For example, the sacrificial fin may be a different material than SiGe and the fins to be left remaining may be a different material than silicon. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

0052Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.

0053Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

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Members2

Family members, oldest first
Document	Office	Kind
US2008206934A1	United States of America	A1	2008-08-28
US7772048B2This record	United States of America	B2	2010-08-10

53 transactions on the USPTO file

Allowed after 1 non-final rejection.

Non-final rejections: 1
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2021-12-14	Payment of Maintenance Fee, 12th Year, Large EntityM1553	M1553
2017-12-12	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2010-08-10	Recordation of Patent Grant MailedPGM/	PGM/
2010-08-10	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2010-07-22	Email NotificationEML_NTR	EML_NTR
2010-07-21	Issue Notification MailedAllowedWPIR	WPIR
2010-07-12	Dispatch to FDCD1935	D1935
2010-07-09	Application Is Considered Ready for IssuePILS	PILS
2010-07-02	Response to Reasons for AllowanceREAS	REAS
2010-07-02	Issue Fee Payment VerifiedN084	N084
2010-07-02	Issue Fee Payment ReceivedIFEE	IFEE
2010-04-07	Electronic ReviewELC_RVW	ELC_RVW
2010-04-07	Email NotificationEML_NTF	EML_NTF
2010-04-07	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2010-04-01	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2010-01-12	Date Forwarded to ExaminerFWDX	FWDX
2010-01-08	Response after Ex Parte Quayle ActionA.QU	A.QU
2009-11-16	Electronic ReviewELC_RVW	ELC_RVW
2009-11-16	Email NotificationEML_NTF	EML_NTF
2009-11-16	Mail Ex Parte Quayle Action (PTOL - 326)MCTEQ	MCTEQ
2009-11-09	Quayle actionCTEQ	CTEQ
2009-08-18	Date Forwarded to ExaminerFWDX	FWDX
2009-06-19	Response after Non-Final ActionA...	A...
2009-04-06	Electronic ReviewELC_RVW	ELC_RVW
2009-04-06	Email NotificationEML_NTF	EML_NTF
2009-04-06	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2009-03-12	Non-Final RejectionNon-final rejectionCTNF	CTNF
2009-01-11	Date Forwarded to ExaminerFWDX	FWDX
2008-12-15	Response to Election / Restriction FiledELC.	ELC.
2008-11-14	Electronic ReviewELC_RVW	ELC_RVW
2008-11-14	Email NotificationEML_NTF	EML_NTF
2008-11-14	Mail Restriction RequirementMCTRS	MCTRS
2008-11-10	Restriction/Election RequirementCTRS	CTRS
2008-10-22	Date Forwarded to ExaminerFWDX	FWDX
2008-10-20	Response to Election / Restriction FiledELC.	ELC.
2008-09-30	Electronic ReviewELC_RVW	ELC_RVW
2008-09-30	Email NotificationEML_NTF	EML_NTF
2008-09-30	Mail Restriction RequirementMCTRS	MCTRS
2008-09-25	Restriction/Election RequirementCTRS	CTRS
2008-08-29	Email NotificationEML_NTR	EML_NTR
2008-08-29	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2008-08-20	Case Docketed to Examiner in GAUDOCK	DOCK
2007-06-12	Case Docketed to Examiner in GAUDOCK	DOCK
2007-05-12	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2007-04-17	Application Dispatched from OIPEOIPE	OIPE
2007-03-08	Sent to Classification ContractorPGPC	PGPC
2007-03-08	Application Is Now CompleteCOMP	COMP
2007-02-26	Cleared by OIPE CSRL194	L194
2007-02-23	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2007-02-23	Reference capture on IDSRCAP	RCAP
2007-02-23	Electronic Information Disclosure StatementEIDS.	EIDS.
2007-02-23	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2007-02-23	Initial Exam Team nnIEXX	IEXX

37 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2021-12-14	Maintenance fee paymentMAFP	MAFP
2020-02-17	AssignmentAS	AS
2020-02-17	AssignmentAS	AS
2020-01-17	AssignmentAS	AS
2020-01-17	AssignmentAS	AS
2019-12-10	AssignmentAS	AS
2019-12-10	AssignmentAS	AS
2019-09-10	AssignmentAS	AS
2019-02-20	AssignmentAS	AS
2019-02-20	AssignmentAS	AS
2017-12-12	Maintenance fee paymentMAFP	MAFP
2017-09-21	AssignmentAS	AS
2017-02-01	AssignmentAS	AS
2016-11-08	AssignmentAS	AS
2016-11-07	AssignmentAS	AS
2016-09-21	AssignmentAS	AS
2016-09-21	AssignmentAS	AS
2016-06-16	AssignmentAS	AS
2016-01-13	AssignmentAS	AS
2016-01-12	AssignmentAS	AS
2015-12-21	AssignmentAS	AS
2015-12-21	AssignmentAS	AS
2015-12-21	AssignmentAS	AS
2014-02-10	Fee paymentFPAY	FPAY
2013-11-06	AssignmentAS	AS
2013-11-06	AssignmentAS	AS
2013-06-18	AssignmentAS	AS
2013-06-18	AssignmentAS	AS
2010-07-21	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2010-05-13	AssignmentAS	AS
2010-05-13	AssignmentAS	AS
2010-03-15	AssignmentAS	AS
2010-03-15	AssignmentAS	AS
2007-09-19	AssignmentAS	AS
2007-09-19	AssignmentAS	AS
2007-02-23	AssignmentAS	AS
2007-02-23	AssignmentAS	AS

Forming semiconductor fins using a sacrificial fin

Summary by NHIP

Claim Score by NHIP

Abstract