Nitride-based semiconductor device and method for fabricating the same

TECHNICAL FIELD

0001The present invention relates to a nitride-based semiconductor device such as a semiconductor laser that can be used in the fields of optical information processing and displays and also relates to a method for fabricating such a device.

BACKGROUND ART

0002A violet semiconductor laser, made of Group III-V nitride semiconductors (Al_xGa_yIn_1-x-yN (where 0≦x≦1 and 0≦y≦1) such as gallium nitride (GaN), is a key device for realizing ultrahigh density recording by optical disk drives, and is about to be actually used in consumer electronics products. The output of a violet semiconductor laser must be increased not just to enable high-speed writing on an optical disk but also to develop new fields of technology including application to laser displays. A conventional violet semiconductor laser is disclosed in Non-Patent Document No. 1, for example.

0003Recently, a GaN wafer has been regarded as a strong candidate for a wafer for fabricating a nitride-based semiconductor device thereon. This is because a GaN wafer is superior in the degree of crystal lattice matching and heat dissipation ability to a sapphire wafer that has been used in the pertinent art. Another advantage is that the GaN wafer has electrical conductivity, whereas the sapphire wafer is an insulator. That is to say, a structure in which current also flows across a GaN substrate can be adopted by arranging an additional electrode on the back surface of the GaN substrate, too. If an electrode is arranged on the back surface of a GaN substrate with electrical conductivity, then the size (i.e., the chip area) of each semiconductor device can be reduced, thus increasing the number of chips that can be made out of a single wafer. As a result, the manufacturing cost can be reduced.

0004A GaN wafer may be made in the following manner, for example. First, a GaN single-layer film is grown on a sapphire wafer by an MOVPE process. Thereafter, a thick GaN film is grown on the GaN single-layer film by a hydride VPE (HVPE) process, for example. And then the sapphire wafer is removed.

0005A GaN wafer obtained in this manner has dislocations (including edge dislocations, spiral dislocations and mixed dislocations) at a density of about 5×10⁷cm⁻². If the dislocation density is that high, it is difficult to make highly reliable semiconductor lasers. In addition, the uppermost surface of a GaN wafer made by an HVPE or any other process may have pits, hillocks and so on, and therefore, may sometimes have an unevenness of about 0.1 mm. Such unevenness on the principal surface of a GaN wafer will pose a big obstacle to a photolithographic process, for example, thus decreasing the production yield of devices.

0006To iron out such unevenness on the principal surface of a wafer, the principal surface of a wafer needs to be polished and planarized. Since GaN is highly resistant to chemicals, it is difficult to planarize the GaN wafer by chemical polishing, and therefore, mechanical polishing is usually adopted. In that case, however, the surface of the GaN wafer often gets scratched and damages are often left in the vicinity of the surfaces of crystals.

0007Besides, machining strains (residual strains) are often left on the surface of the wafer and have an in-plane distribution in many cases. When observed using an atomic force microscope (AFM), the scratched had a depth of several tens of μm and the root mean square (RMS), calculated on an area of 50 μm square, was 1.6 nm. If GaN crystals were grown as they are on the principal surface of such a GaN wafer, then the surfaces of crystals would be seriously affected by those scratches.

0008To make the density of dislocations in the nitride-based semiconductor layer that has been grown on a GaN wafer lower than that of the GaN wafer, an epitaxial lateral overgrowth (ELO) has been adopted. Hereinafter, the epitaxial lateral overgrowth will be described with reference to <figref idref="DRAWINGS">FIGS. 12(</figref><i>a</i>) through <b>12</b>(<i>d</i>).

0009First, as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>a</i>), a GaN wafer <b>1001</b> is provided and a mask layer <b>1003</b> of SiO₂is formed thereon. The mask layer <b>1003</b> has striped openings that selectively expose regions of the principal surface of the wafer that will function as a seed for crystal growth.

0010Next, as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>b</i>), an epitaxial lateral overgrowth process is carried out as an MOVPE process, thereby growing an n-GaN layer <b>1002</b> from the respective openings of the mask layer <b>1003</b>. In this process step, conditions for growing GaN crystals less easily on the mask layer <b>1003</b> are adopted. However, polycrystalline GaN sometimes precipitates on the mask layer <b>1003</b>, too. The GaN wafer <b>1001</b> often has n-type conductivity. Thus, by supplying not only a source gas of gallium nitride but also monosilane (SiH₄) and disilane (Si₂H₆) onto the GaN wafer, a GaN layer <b>1002</b> having n-type conductivity is formed.

0011If the n-GaN layer <b>1002</b> continues to be grown as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>c</i>), then adjacent portions of the n-GaN layer <b>1002</b> will soon be combined with each other, thus forming a single continuous layer as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>d</i>).

0012The n-GaN layer <b>1002</b> formed by such a process has regions where the density of dislocations is reduced to 7×10⁵cm⁻²or less. If the device structure is fabricated over such regions with a reduced density of dislocations, then the reliability can be increased. However, if polycrystalline GaN precipitates on the mask layer <b>1003</b> as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>b</i>), then crystallinity deteriorated regions <b>1004</b> will be produced as shown in <figref idref="DRAWINGS">FIG. 12(</figref><i>c</i>).

0013To further reduce the density of dislocations, Patent Document No. 1 discloses a semiconductor device in which a mask layer is formed in striped recesses and an air gap is provided over the mask layer. <figref idref="DRAWINGS">FIG. 13</figref> illustrates a structure including an n-GaN wafer <b>101</b> in which recesses are covered with a mask layer <b>103</b> and an n-GaN layer <b>103</b> that has grown from striped ridges. The n-GaN layer <b>103</b> includes low-dislocation regions <b>104</b> with a relatively low density of dislocations and high-dislocation regions <b>105</b> with a relatively high density of dislocations. A ridge stripe <b>106</b>, defining a current injection region, for example, is arranged on a low-dislocation region <b>104</b> on the n-GaN layer <b>102</b>. <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0014">Non-Patent Document No. 1: Japanese Journal of Applied Physics (Jpn. J. Appl. Phys.), Vol. 39. p. L647, 2000</li><li id="ul0002-0002" num="0015">Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 2002-9004</li></ul></li></ul>

DISCLOSURE OF INVENTION

Problems to be Solved by the Invention

0016The semiconductor laser disclosed in Patent Document No. 1 can minimize the deterioration of crystallinity due to the polycrystalline GaN that has precipitated on the mask layer. However, the present inventors discovered that if a structure including an electrode on the back surface of a GaN substrate was adopted, the desired laser oscillation could not be realized easily as in the situation where the structure formed by the method shown in <figref idref="DRAWINGS">FIG. 12</figref> was adopted unless the voltage applied between the electrodes was increased.

0017In order to overcome the problems described above, a primary object of the present invention is to provide a highly reliable nitride-based semiconductor device at a good yield.

Means for Solving the Problems

0018A nitride-based semiconductor device according to the present invention includes a substrate structure with electrical conductivity and a semiconductor multilayer structure that is supported on the substrate structure. The principal surface of the substrate structure has at least one vertical growth region, which functions as a seed crystal for growing a nitride-based semiconductor vertically, and a plurality of lateral growth regions for allowing the nitride-based semiconductor that has grown on the vertical growth region to grow laterally. The sum ΣX of the respective sizes of the vertical growth regions as measured in a first direction, which is parallel to the principal surface of the substrate structure, and the sum ΣY of the respective sizes of the lateral growth regions as measured in the first direction satisfy the inequality ΣX/ΣY>1.0.

0019In one preferred embodiment, the substrate structure is made of Al_x1Ga_y1In_x1N crystals (where x1+y1+z1=1, x1≧0, y1≧0 and z1≧0), and the semiconductor multilayer structure includes an Al_x2Ga_y2In_z2N crystal layer (where x2+y2+z2=1, x2≧0, y2≧0 and z2≧0) that has grown from the vertical growth region on the principal surface of the substrate structure.

0020In another preferred embodiment, the substrate structure includes: a substrate body made of Al_x1Ga_y1In_z1N crystals (where x1+y1+z1=1, x1>=0, y1≧0 and z1>0); and an Al₃Ga_y3In_z3N crystal layer (where x3+y3+z3=1, x3≧0, y3≧0 and z3>0), which has been formed on the upper surface of the substrate body and of which the surface functions as the principal surface of the substrate structure. And the semiconductor multilayer structure includes an Al_x2Ga_y2In_z2N crystal layer (where x2+y2+z2=1, x2≧0, y2≧0 and z2≧0) that has grown from the vertical growth region on the principal surface of the substrate structure.

0021In still another preferred embodiment, the vertical and lateral growth regions on the principal surface of the substrate structure extend in stripes perpendicularly to the first direction.

0022In this particular preferred embodiment, the vertical growth region on the principal surface of the substrate structure is defined by a striped ridge portion that is present on the principal surface of the substrate structure.

0023Alternatively or additionally, the nitride-based semiconductor device further includes a mask layer that covers the principal surface of the substrate structure. The mask layer includes at least one striped opening, which is aligned with the vertical growth regions, and masking portions, which are aligned with the lateral growth regions.

0024In a specific preferred embodiment, the area of the opening of the mask layer is greater than the overall area of the masking portions of the mask layer.

0025In still another preferred embodiment, the semiconductor multilayer structure includes an active layer, of which the bandgap is smaller than that of the Al_x2Ga_y2In_z2N crystal layer. The device further includes a current confining structure for injecting carriers into a part of the active layer.

0026In this particular preferred embodiment, the current confining structure is located right over the lateral growth regions on the principal surface of the substrate structure.

0027In yet another preferred embodiment, the Al_x3Ga_y3In_z3N layer has a structure in which at least one of the mole fractions x3, y3 and z3 of its constituents changes in the thickness direction thereof.

0028In a specific preferred embodiment, the Al_x3Ga_y3In_z3N includes at least two layers.

0029A method for fabricating a nitride-based semiconductor device according to the present invention includes the steps of: (A) providing a substrate structure, which has, on its principal surface, a plurality of vertical growth regions functioning as a seed crystal for growing a nitride-based semiconductor vertically and a plurality of lateral growth regions for allowing the nitride-based semiconductor that has grown on the vertical growth regions to grow laterally, the substrate structure satisfying the inequality X/Y>1.0, where X is the size of each said vertical growth region as measured in a first direction, which is parallel to the principal surface of the substrate structure, and Y is the size of each said lateral growth region as measured in the first direction; and (B) growing a nitride-based semiconductor layer on the principal surface of the substrate structure.

0030In one preferred embodiment, the step (A) includes the step of providing a wafer made of Al_x1Ga_y1In_z1N crystals (where x1+y1+z1=1, x1>=0, y1≧0 and z1≧0) as the substrate structure, and the step (B) includes the step of growing an Al_x2Ga_y2In_z2N crystal layer (where x2+y2+z2=1, x2≧0, y2≧0 and z2≧0), functioning as the nitride-based semiconductor layer, from the vertical growth regions on the principal surface of the substrate structure.

0031In another preferred embodiment, the step (A) includes the steps of: (a1) providing a wafer made of Al_x1Ga_y1In_z1N crystals (where x1+y1+z1=1, x1≧0, y1≧0 and z1≧0) as a substrate body; and (a2) growing an Al_x3Ga_y3In_z3N crystal layer (where x3+y3+z3=1, x3≧0, y3≧0 and z3≧0), of which the surface functions as the principal surface of the substrate structure, on the upper surface of the substrate body. The step (B) includes growing an Al_x2Ga_y2In_z2N crystal layer (where x2+y2+z2=1, x2≧0, y2≧0 and z2≧0), functioning as the nitride-based semiconductor layer, from the vertical growth regions on the principal surface of the substrate structure.

0032In still another preferred embodiment, the vertical and lateral growth regions on the principal surface of the substrate structure extend in stripes perpendicularly to the first direction.

0033In this particular preferred embodiment, the vertical growth regions on the principal surface of the substrate structure are defined by striped ridge portions that are present on the principal surface of the substrate structure.

0034In a specific preferred embodiment, the step (A) includes the steps of: covering the principal surface of the substrate structure with a resist mask that has a pattern defining the vertical growth regions; and selectively etching away exposed portions of the principal surface of the substrate structure that are not covered with the resist mask.

0035Alternatively or additionally, the device further includes a mask layer that covers the principal surface of the substrate structure. The mask layer includes striped openings, which are aligned with the vertical growth regions, and masking portions, which are aligned with the lateral growth regions.

0036In this particular preferred embodiment, the overall area of the openings of the mask layer is greater than that of the masking portions of the mask layer.

0037In yet another preferred embodiment, the method further includes the step (C) of forming a semiconductor multilayer structure including the nitride-based semiconductor layer and other semiconductor layers that have been stacked on the nitride-based semiconductor layer. The step (C) includes the steps of (c1) forming an active layer, of which the bandgap is smaller than that of the Al_x2Ga_y2In_z2N crystal layer, and (c2) forming a current confining structure for injecting carriers into a part of the active layer.

0038In this particular preferred embodiment, the step (c2) includes the step of arranging the current confining structure right over the lateral growth regions on the principal surface of the substrate structure.

0039In yet another preferred embodiment, the step (a2) includes the step of changing at least one of the mole fractions x3, y3 and z3 of the constituents of the Al_x3Ga_y3In_z3N layer in the thickness direction thereof.

0040In a specific preferred embodiment, the Al_x3Ga_y3In_z3N layer includes at least two layers.

0041In yet another preferred embodiment, the step (a2) includes the step of changing growth temperatures while the Al_x3Ga_y3In_z3N layer is growing.

0042In yet another preferred embodiment, at least one of X and Y changes from one position to another on the principal surface of the substrate structure as a wafer.

Effects of the Invention

0043According to the present invention, electrical resistance to a current flowing across the principal surface of a substrate can be reduced, thus increasing the reliability and production yield of a nitride-based semiconductor device to be fabricated by an epitaxial lateral overgrowth process.

BRIEF DESCRIPTION OF DRAWINGS

0044<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view illustrating a first preferred embodiment of a nitride-based semiconductor device according to the present invention.

0045<figref idref="DRAWINGS">FIGS. 2(</figref><i>a</i>) and <b>2</b>(<i>b</i>) are respectively a plan view illustrating the n-GaN substrate <b>101</b> of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref> and a cross-sectional view as viewed on the plane B-B′.

0046<figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) through <b>3</b>(<i>d</i>) are cross-sectional views illustrating respective process steps for growing the n-GaN layer <b>102</b> shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0047<figref idref="DRAWINGS">FIG. 4(</figref><i>a</i>) is a graph showing a correlation between the width X of seed portions and the voltage, and <figref idref="DRAWINGS">FIGS. 4(</figref><i>b</i>) and <b>4</b>(<i>c</i>) are graphs each showing a correlation between ΣX/ΣY and the voltage.

0048<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view illustrating a modified example of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0049<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view illustrating a second preferred embodiment of a nitride-based semiconductor device according to the present invention.

0050<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view illustrating a modified example of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 6</figref>.

0051<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view illustrating a third preferred embodiment of a nitride-based semiconductor device according to the present invention.

0052<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view illustrating a modified example of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0053<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view illustrating another modified example of the semiconductor device shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0054<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view illustrating a fourth preferred embodiment of a nitride-based semiconductor device according to the present invention.

0055<figref idref="DRAWINGS">FIGS. 12(</figref><i>a</i>) through <b>12</b>(<i>d</i>) are cross-sectional views illustrating conventional epitaxial lateral overgrowth process steps.

0056<figref idref="DRAWINGS">FIG. 13</figref> is a cross-sectional view illustrating a main portion of a conventional semiconductor laser formed by an epitaxial lateral overgrowth process to have air gaps.

DESCRIPTION OF REFERENCE NUMERALS

0000<ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0057"><b>101</b> n-GaN substrate</li><li id="ul0003-0002" num="0058"><b>102</b> n-GaN layer</li><li id="ul0003-0003" num="0059"><b>103</b> SiN_x</li><li id="ul0003-0004" num="0060"><b>104</b> low-dislocation region</li><li id="ul0003-0005" num="0061"><b>105</b> high-dislocation region</li><li id="ul0003-0006" num="0062"><b>106</b> position of ridge stripe</li><li id="ul0003-0007" num="0063"><b>107</b> polycrystalline GaN</li><li id="ul0003-0008" num="0064"><b>201</b> n-AlGaN/GaN superlattice contact layer</li><li id="ul0003-0009" num="0065"><b>202</b> n-AlGaN/GaN superlattice cladding layer</li><li id="ul0003-0010" num="0066"><b>203</b> n-GaN optical guide layer</li><li id="ul0003-0011" num="0067"><b>204</b> MQW active layer</li><li id="ul0003-0012" num="0068"><b>205</b> p-GaN optical guide layer</li><li id="ul0003-0013" num="0069"><b>206</b> p-AlGaN/GaN superlattice cladding layer</li><li id="ul0003-0014" num="0070"><b>207</b> p-GaN contact layer</li><li id="ul0003-0015" num="0071"><b>208</b> p-electrode</li><li id="ul0003-0016" num="0072"><b>209</b> insulating film (SiO₂)</li><li id="ul0003-0017" num="0073"><b>210</b> n-electrode</li><li id="ul0003-0018" num="0074"><b>211</b> void (combined portion)</li><li id="ul0003-0019" num="0075"><b>601</b> n-AlGaN/GaN superlattice contact layer</li><li id="ul0003-0020" num="0076"><b>602</b> n-AlGaN/GaN superlattice cladding layer</li><li id="ul0003-0021" num="0077"><b>603</b> n-GaN optical guide layer</li><li id="ul0003-0022" num="0078"><b>604</b> MQW active layer</li><li id="ul0003-0023" num="0079"><b>605</b> p-GaN optical guide layer</li><li id="ul0003-0024" num="0080"><b>606</b> p-AlGaN/GaN superlattice cladding layer</li><li id="ul0003-0025" num="0081"><b>607</b> p-GaN contact layer</li><li id="ul0003-0026" num="0082"><b>608</b> p-electrode</li><li id="ul0003-0027" num="0083"><b>609</b> insulating film (SiO₂)</li><li id="ul0003-0028" num="0084"><b>610</b> n-electrode</li><li id="ul0003-0029" num="0085"><b>801</b> (AlIn)GaN layer</li><li id="ul0003-0030" num="0086"><b>1001</b> n-GaN substrate structure</li><li id="ul0003-0031" num="0087"><b>1002</b> n-GaN layer</li><li id="ul0003-0032" num="0088"><b>1003</b> SiO₂</li><li id="ul0003-0033" num="0089"><b>1004</b> crystallinity deteriorated region</li><li id="ul0003-0034" num="0090"><b>1007</b> polycrystalline GaN</li><li id="ul0003-0035" num="0091"><b>1101</b> low-temperature (AlIn)GaN layer</li><li id="ul0003-0036" num="0092"><b>1102</b> high-temperature (AlIn)GaN layer</li><li id="ul0003-0037" num="0093"><b>1201</b> (AlIn)GaN layer with low carrier density</li><li id="ul0003-0038" num="0094"><b>1202</b> (AlIn)GaN layer with high carrier density</li><li id="ul0003-0039" num="0095"><b>1203</b> n-GaN layer (low-carrier-density layer)</li><li id="ul0003-0040" num="0096"><b>1204</b> n-GaN layer (high-carrier-density layer)</li></ul>

BEST MODE FOR CARRYING OUT THE INVENTION

0097Hereinafter, preferred embodiments of a nitride-based semiconductor device according to the present invention will be described with reference to the accompanying drawings.

0098In the preferred embodiments to be described below, a nitride-based semiconductor is supposed to be grown by an MOVPE process. However, crystal growing processes that can be used in the present invention include not only MOVPE but also hydride vapor phase epitaxy (H-VPE) process, molecular beam epitaxy (MBE) process and other known methods for growing a nitride-based semiconductor.

Embodiment 1

0099First, referring to <figref idref="DRAWINGS">FIG. 1</figref>, illustrated schematically is a cross section of a nitride-based semiconductor device according to a first specific preferred embodiment of the present invention.

0100The semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref> includes a GaN substrate <b>101</b> including multiple striped ridges on the principal surface thereof and an n-GaN layer <b>102</b> that has grown on the GaN substrate <b>101</b>. In an actual semiconductor device, a number of nitride-based semiconductor layers are usually stacked one upon the other on the n-GaN layer <b>102</b>. However, if the n-GaN layer <b>102</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> is used as a channel layer for transistors, a gate insulating film, an interconnect structure and so on are formed on the n-GaN layer <b>102</b>.

0101The configuration of the GaN substrate <b>101</b> will be described in further detail with reference to <figref idref="DRAWINGS">FIG. 2</figref>. Specifically, <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>) is a top view illustrating the principal surface of the GaN substrate <b>101</b> of a nitride-based semiconductor device and <figref idref="DRAWINGS">FIG. 2(</figref><i>b</i>) is a cross-sectional view thereof as viewed on the plane B-B′. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the respective upper surfaces of the ridge portions that have been formed on the principal surface of the GaN substrate <b>101</b> are “vertical growth regions” functioning as a seed crystal for growing a nitride-based semiconductor vertically. On the other hand, the recesses are “lateral growth regions” that allow the nitride-based semiconductor, which has grown from the respective upper surfaces of the ridge portions (i.e., the vertical growth regions), to grow laterally. In this preferred embodiment, the vertical growth regions and the lateral growth regions are arranged alternately and periodically parallel to the principal surface of the substrate as pointed by the arrow A (i.e., in the first direction) in <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>). The ends <b>101</b><i>a </i>and <b>101</b><i>b </i>of the GaN substrate <b>101</b> are faces that are exposed by cutting or cleaving a GaN wafer. Even if those “vertical growth regions” and “lateral growth regions” of the same size are arranged periodically on a single GaN wafer, the size of the “vertical growth region” or “lateral growth region” located at the end <b>101</b><i>a </i>or <b>101</b><i>b </i>of the GaN substrate <b>101</b> is usually smaller than that of the other “vertical growth regions” or “lateral growth regions” that are not located at the ends <b>101</b><i>a </i>and <b>10</b><i>b </i>of the GaN substrate <b>101</b> when the GaN wafer is divided into multiple chip substrates.

0102Suppose the size of each of those vertical growth regions as measured in the direction pointed by arrow A (i.e., in the first direction) is X and the size of each of those lateral growth regions as measured in the first direction is Y. Also, the sum of the respective sizes of the vertical growth regions included in a single semiconductor device is represented by Σx and the sum of the respective sizes of the lateral growth regions included in a single semiconductor device is represented by Σy. In that case, the principal surface of the n-GaN substrate <b>101</b> has been patterned in this preferred embodiment so as to satisfy the inequality ΣX/ΣY>1.0. In this preferred embodiment, the vertical growth regions and the lateral growth regions extend in stripes perpendicularly to the first direction (i.e., in a second direction). That is why the size measured in the direction pointed by the arrow A (i.e., in the first direction) will sometimes be referred to herein as the “width”.

0103The raised and recessed structure on the principal surface of the n-GaN substrate <b>101</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> can be formed by known photolithography and etching techniques. In this preferred embodiment, first, an n-GaN wafer <b>101</b> with a substantially flat surface is provided and the principal surface of the n-GaN wafer <b>101</b> is covered with a resist layer. Next, the resist layer is subjected to an exposure process using a photomask with a striped pattern, and then developed, thereby defining a resist mask (not shown) that has striped openings. Thereafter, exposed portions of the principal surface of the n-GaN wafer <b>101</b>, which are not covered with the resist mask, are selectively etched away, thereby forming the recesses shown in <figref idref="DRAWINGS">FIG. 2</figref> on the principal surface of the n-GaN wafer <b>101</b>. After that, the resist mask is removed.

0104In this preferred embodiment, the principal surface of the n-GaN substrate <b>101</b> is a (0001) plane. Also, in this preferred embodiment, the pattern of the resist mask is defined such that the width Y of the recesses (i.e., the size measured in the first direction) becomes approximately equal to 10 μm and that the width of the ridges (i.e., the size measured in the first direction) becomes approximately equal to 7 μm.

0105After the resist mask has been stripped, an SiN_xlayer is deposited over the entire surface of the wafer by a plasma CVD process. Thereafter, a resist is deposited for planarization purposes on the wafer <b>101</b> covered with the SiN_xlayer. Subsequently, the resist and SiN_xlayer are etched back until the top of the n-GaN wafer <b>101</b> (i.e., the upper surface of the ridge portions) is exposed, thereby forming a mask layer <b>103</b> of the SiN_xlayer only in the recesses. After that, the remaining resist is removed with an organic solvent, for example.

0106According to this method, only the recesses on the principal surface of the substrate can be selectively covered with the mask layer <b>103</b>, and the upper surface of the exposed ridge portions functions as a seed for crystal growth. This mask layer <b>103</b> will function as a selective growth mask in the process step of selectively growing a nitride-based semiconductor laterally as will be described later. That is why the mask layer <b>103</b> is preferably made of a material that does not allow the nitride-based semiconductor to grow easily on its surface.

0107Next, the n-GaN wafer <b>101</b> having the structure shown in <figref idref="DRAWINGS">FIG. 2</figref> is loaded into the growth chamber of an MOVPE system to grow an n-type GaN layer <b>102</b> on the upper surface of the ridge portions (i.e., from seed portions) at 1,050° C. by an MOVPE process. In this preferred embodiment, SiH₄is used as an n-type dopant. The GaN layer <b>102</b> grows not only vertically on the ridge portions (i.e., perpendicularly to the principal surface of the substrate) but also parallel to the principal surface of the wafer (i.e., laterally). In this manner, the GaN layer <b>102</b> expands toward, and reaches over, the recesses where the mask layer <b>103</b> is embedded.

0108As a result of this selective growth, the GaN crystals that have grown from the upper surface of each ridge portion is combined with the GaN crystals that have grown from the upper surface of its adjacent ridge portion, thereby forming a single n-GaN layer <b>102</b> eventually.

0109As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the n-GaN substrate <b>101</b>, of which the principal surface is already covered with the n-GaN layer <b>102</b>, has a plurality of air gaps between the recesses on the principal surface of the substrate and the n-GaN layer <b>102</b>. Those air gaps are arranged in stripes in the direction in which the striped ridge portions extend.

0110As described above, the respective GaN crystals that have grown from those ridge portions are combined with each other substantially at the center of the air gaps. It should be noted that the growth rates of the n-GaN crystals in the a-axis direction (in the lateral direction) and in the c-axis direction (in the vertical direction) are controllable by adjusting the concentration of a dopant to be introduced into the GaN crystals.

0111As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the n-GaN layer <b>102</b> includes low-dislocation regions <b>104</b> having a relatively low density of dislocations and high-dislocation regions <b>105</b> having a relatively high density of dislocations. The high-dislocation regions <b>105</b> are located on the ridge portions on the principal surface of the substrate, while the low-dislocation regions <b>104</b> are located over the air gaps. In some of the air gaps, polycrystalline GaN <b>107</b> may have grown on the mask layer <b>103</b>. When the selective growth process is carried out to form the n-GaN layer <b>102</b>, conditions to limit the growth of nitride semiconductor crystals on the mask layer <b>103</b> are adopted but the polycrystalline GaN <b>107</b> may still be produced partially. If the growth rate of the polycrystalline GaN <b>107</b> is low or if the recesses on the principal surface of the substrate are sufficiently deep, then the formation of the n-GaN layer <b>102</b> is not interfered with by the polycrystalline GaN <b>107</b>.

0112In the example illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, a ridge stripe <b>106</b> is arranged on a low-dislocation region <b>104</b> of the n-GaN layer <b>102</b>. The ridge stripe <b>106</b> has as low a density of dislocations as the underlying low-dislocation region <b>104</b> and is a semiconductor region with excellent crystallinity. Therefore, the ridge stripe <b>106</b> is used as the active region of a semiconductor device, which needs to have a particularly high degree of crystallinity.

0113Hereinafter, it will be described in further detail with reference to <figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) through <b>3</b>(<i>d</i>) how the n-GaN layer <b>102</b> grows. In <figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) through <b>3</b>(<i>d</i>), only a portion of a wafer, which will eventually be used in the semiconductor device shown in <figref idref="DRAWINGS">FIG. 1</figref>, is illustrated.

0114First, as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>), an n-GaN wafer <b>101</b>, of which the principal surface has recesses and in which the bottom and side surface of the recesses are covered with a mask layer <b>103</b>, is provided and loaded into the chamber of an MOVPE system. The n-GaN wafer <b>101</b> shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>) corresponds to the n-GaN substrate <b>101</b> shown in <figref idref="DRAWINGS">FIG. 2(</figref><i>a</i>).

0115Thereafter, the principal surface of the n-GaN wafer <b>101</b> is subjected to a heat treatment process at a temperature of about 500° C. to about 1,100° C. (i.e., thermal cleaning). This heat treatment process may be carried out at 750° C. for at least one minute, preferably five minutes or more. During this heat treatment process, a gas including nitrogen (N) atoms such as N₂, NH₃or hydrazine gas is preferably supplied into the chamber.

0116After the heat treatment process, an n-GaN layer <b>102</b> is selectively grown on the ridge portions at a temperature of about 1,050° C. by an MOVPE process. <figref idref="DRAWINGS">FIG. 3(</figref><i>b</i>) shows the n-GaN layer <b>102</b> growing. At this point in time, the n-GaN crystals that have grown on the respective ridge portions still have a striped shape and have not been combined together to form a single layer. Subsequently, if the n-GaN crystals are further grown as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>c</i>), then a single continuous n-GaN layer <b>102</b> can soon be formed as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>d</i>).

0117In this manner, if n-GaN crystals <b>102</b> are grown on the n-GaN wafer <b>101</b>, including ridge portions or recesses as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>), by an MOVPE process, then GaN will not grow epitaxially on the regions that are covered with the mask layer <b>103</b> but will be selectively grown epitaxially on the ridge portions (seed portions) of the n-GaN wafer <b>101</b>, which are exposed through the openings of the mask layer <b>13</b>. Each of the crystallographic planes functioning as the seed portions is a (0001) plane just like the principal surface of the wafer and may be formed in a striped shape with a width of about 7 μm.

0118When the n-GaN crystals are selectively grown laterally in this manner, the polycrystalline GaN <b>107</b> is sometimes crystallized on the mask layer <b>103</b> in the recesses as shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>b</i>). Particularly if droplets of Ga or GaN have been deposited on the mask layer <b>103</b> in the recesses as a result of the heat treatment process (i.e., thermal cleaning) to be carried out before the crystals are formed, then the polycrystalline Ga <b>107</b> can grow easily on the mask layer <b>103</b> from those droplets. However, the polycrystalline GaN <b>107</b> that has grown on the mask layer <b>103</b> has a smaller height than the ridge portions, and therefore, does not affect the crystallinity of the n-GaN crystals <b>102</b> that has grown laterally from the upper surface of the ridge portions. From this viewpoint, the recesses preferably have a depth of at least 500 nm.

0119A currently available n-GaN wafer <b>101</b> has a density of dislocations of about 5×10⁶cm⁻². However, in a laterally grown portion of the n-GaN layer <b>102</b>, the density of dislocations can be lower than that of the wafer by at least one order of magnitude. As a result, the reliability of the resultant semiconductor device can be increased significantly. In addition, by performing the process steps shown in <figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) through <b>3</b>(<i>d</i>), the unwanted effects that would be caused by the scratches on the principal surface of the n-GaN wafer <b>101</b> can be reduced, too. The principal surface of the n-GaN wafer <b>101</b> usually has a lot of scratches (with a depth of approximately several tens of nm) that have been made here and there as a result of a polishing process. That is why if GaN crystals were grown on the principal surface of the n-GaN wafer <b>101</b> as it is, then the resultant GaN crystal layer would have a noticeably waving surface due to the influence of those scratches. However, if those striped recesses (to be the air gaps) are made on the GaN wafer <b>101</b> as is done in this preferred embodiment, then GaN crystals grown on those recesses will not be affected by the scratches. Although the ridge portions are easily affected by the unevenness on the principal surface of the wafer, the laterally grown portions are hardly affected by that unevenness. Due to these effects, the method shown in <figref idref="DRAWINGS">FIGS. 3(</figref><i>a</i>) through <b>3</b>(<i>d</i>) can increase the degree of planarity of the surface of the GaN crystals greatly.

0120As described above, according to this preferred embodiment, ΣX/ΣY is preferably set to be at least greater than 1.0, more preferably greater than 2.0, and even more preferably greater than 3. The effects achieved by this setting will be described.

0121First, referring to <figref idref="DRAWINGS">FIGS. 4(</figref><i>a</i>) through <b>4</b>(<i>c</i>), shown are a curve representing a correlation between the width X of the seed portion and the voltage and curves representing correlations between ΣX/ΣY and the voltage. The differences between the curves shown in <figref idref="DRAWINGS">FIGS. 4(</figref><i>b</i>) and <b>4</b>(<i>c</i>) lie in the scale and the range of the axis of abscissas.

0122As can be seen from <figref idref="DRAWINGS">FIG. 4</figref>, if the width X of each of the crystal growth seed portions (i.e., the vertical growth regions) is increased and the width Y of each of the recesses (i.e., the lateral growth regions) is decreased on the principal surface of the n-GaN substrate <b>101</b>, then the voltage to be applied to produce the same amount of current can be reduced. This is because as ΣX/ΣY is increased, the overall area of the regions where the current can flow vertically increases on the principal surface of the substrate. The larger the area of a current flowing region, the lower the resistance. As a result, the voltage to be applied to produce the same amount of current between the electrodes can be reduced.

0123Suppose the operating current of a semiconductor laser is defined at 100 mA, for example. In that case, to reduce the increase in voltage due to the resistance of the principal surface of the substrate to 0.01 V or less, the seed portion may have a width of 6 μm or more. And if this voltage increase is equal to or smaller than 0.01 V, the decrease in the reliability of the semiconductor laser can be avoided. It should be noted that each of the lateral growth portions of the n-GaN layer <b>102</b> preferably has a width (which will be referred to herein as a “wing width”) of at least 6 μm. Accordingly, if the lateral growth portion should have a horizontally symmetrical shape, the recess preferably has a width Y of about 12 μm. However, if the asymmetrical lateral growth process is carried out as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the width of one of the two lateral growth portions can be expanded effectively. As a result, the width of the recess can be reduced without reducing the wing width.

0124It should be noted that to reduce the electrical resistance, the number of air gaps (i.e., recesses) between the n-GaN substrate <b>101</b> and the n-GaN layer <b>102</b> is preferably as small as possible. That is why the air gaps are preferably created only right under the regions where the density of dislocations needs to be decreased (i.e., current confining structure). If one air gap is provided for a single semiconductor laser in this manner, then Σx/ΣY will have a large value that is greater than 1.0 but equal to or smaller than 30. The present inventors discovered and confirmed via experiments that Σx/ΣY is preferably at least equal to 2 and more preferably 3 or more. If a single lateral growth region is defined in a single substrate for one semiconductor device and is sandwiched between two vertical growth regions on the right- and left-hand sides thereof, then Σx/ΣY can be set to be at least equal to 6 (e.g., 9 or more). This is beneficial because the greater Σx/ΣY, the lower the applied voltage can be as can be seen from <figref idref="DRAWINGS">FIG. 4(</figref><i>c</i>).

0125On the surface of a GaN wafer, there are a number of scratches as described above. Thus, it was commonly believed in the art that the size X of the vertical growth regions be minimized. It was also believed that as crystal regions that have grown on the vertical growth regions have a relatively low degree of crystallinity, the greater their size X, the more badly the crystal regions grown on the lateral growth regions are affected. However, the present inventors discovered and confirmed via experiments that even if the size X of the vertical growth regions was increased, the degree of crystallinity of the crystal regions grown on the lateral growth regions did not deteriorate. This is probably because since the GaN wafer <b>101</b>, of which the material is homogeneous with that of the n-GaN layer <b>102</b>, is used, almost no stress (or strain) should be caused between them. That is to say, even if the lateral growth is produced to decrease the density of dislocations locally, the number of dislocations that have been produced in the vertical growth regions and then reached the low-dislocation portions of the lateral growth regions can be reduced significantly. Among other things, since the density of dislocations in the GaN wafer <b>101</b> for use in this preferred embodiment has been reduced to 10⁷cm⁻²or less, the number of dislocations reaching the low-dislocation portions can be reduced even more significantly. Consequently, the air gaps may be arranged only under the regions where the current confining structure will be formed.

0126In this manner, the number of unnecessary air gaps is preferably minimized either by eliminating the air gaps entirely from where there is no need to provide the current confining structure or by reducing the areas of the air gaps, if any. By removing those unnecessary air gaps, the degree of close constant between the wafer and the semiconductor multilayer structure can be increased significantly. As a result, when the wafer is cleaved by drawing scribe lines, the number of collapsing air gaps can be reduced and the scribe lines can be drawn uniformly even inside the substrate structure. Consequently, the semiconductor multilayer structure will come off the wafer much less often during the processing steps of polishing and mounting, the wafer can be cleaved more satisfactorily, and the yield can be increased.

0127In this preferred embodiment and other preferred embodiments to be described later, an n-GaN substrate is used. However, the substrate structure for supporting the semiconductor multilayer structure does not have to be the n-GaN substrate but may also be a structure made of Al_x1Ga_y1In_z1N crystals (where x1+y1+z1=1, x1≧0, y1≧0 and z1≧0). Likewise, the nitride semiconductor layer to be selectively grown laterally on the substrate structure does not have to be the n-GaN layer but may also be an Al_x2Ga_y2In_z2N crystal layer (where x2+y2+z2=1, x2≧0, y2≧0 and z2≧0).

0128In the preferred embodiment described above, the mask layer <b>103</b> covers both the bottom and side surface of each recess. Alternatively, only the bottom of each recess may be covered with the mask layer <b>103</b>. Also, the mask layer <b>103</b> does not have to be made of SiN_xbut may also be made of another dielectric material or amorphous insulator. Even by using a mask layer made of SiO₂, SiON, Al₂O₃, AlON, TiO₂, ZrO₂or Nb₂O₅, to name a few, the selective lateral growth is also realized.

0129It should be noted that even if the bottom of the recess is not covered with the mask layer, the growth of a nitride semiconductor on the bottom of the recess can sometimes be controlled. That is why the bottom of the recess should be, but does not always have to be, covered with the mask layer. Furthermore, the present invention is also effectively applicable to even a situation where a substrate having the conventional structure that has already been described with reference to <figref idref="DRAWINGS">FIG. 12</figref> is used. That is to say, even when the substrate shown in <figref idref="DRAWINGS">FIG. 12</figref> is used, the resistance to be produced when current flows across the principal surface of the substrate can also be reduced by setting ΣX/ΣY preferably greater than 1.0, more preferably greater than 2.0, and even more preferably greater than 3.

0130The same statement will apply to all of the other preferred embodiments to be described later.

Embodiment 2

0131Hereinafter, a second preferred embodiment of a nitride-based semiconductor device according to the present invention will be described with reference to <figref idref="DRAWINGS">FIG. 6</figref>, which schematically illustrates a cross-sectional structure of a nitride semiconductor laser according to this preferred embodiment.

0132The semiconductor laser illustrated in <figref idref="DRAWINGS">FIG. 6</figref> includes an n-GaN substrate <b>101</b> with a striped recess on its principal surface and a semiconductor multilayer structure that has been grown on the GaN substrate <b>101</b>. The lowermost layer of the semiconductor multilayer structure is an n-GaN layer <b>102</b> that has been grown on the n-GaN substrate <b>101</b>. The n-GaN substrate <b>101</b> and the n-GaN layer <b>102</b> of this preferred embodiment are made by the same method as the counterparts of the first preferred embodiment described above.

0133The semiconductor multilayer structure is formed by stacking an n-AlGaN/GaN superlattice contact layer <b>201</b>, an n-AlGaN/GaN superlattice cladding layer <b>202</b>, an n-GaN optical guide layer <b>203</b>, a multiple-quantum well (MQW) active layer <b>204</b>, a p-GaN optical guide layer <b>205</b>, a p-AlGaN/GaN cladding layer <b>206</b> and a p-GaN contact layer <b>207</b> in this order on the n-GaN layer <b>102</b>. These nitride-based semiconductor layers can be grown effectively by an MOVPE process.

0134The p-GaN contact layer <b>207</b> and the p-AlGaN/GaN cladding layer <b>206</b> have been patterned so as to define a ridge stripe, which may have a width (a strip width) of about 2 μm. The top of the semiconductor multilayer structure is covered with an insulating film <b>209</b>, which has a striped opening over the ridge stripe. Through the opening of the insulating film <b>209</b>, a portion of the upper surface of the p-GaN contact layer <b>207</b> is electrically in contact with a p-electrode <b>208</b>. An n-electrode <b>210</b> is arranged on the back surface of the n-GaN substrate <b>101</b>.

0135The shape and location of the ridge stripe (more exactly, the shape and location of the opening of the insulating film <b>209</b>) define the current (or carrier) injection region of the active layer <b>204</b>. In this preferred embodiment, the opening of the insulating film <b>209</b> is arranged right over the low-dislocation region of the n-GaN layer <b>102</b>. Therefore, if a predetermined voltage is applied between the p- and n-electrodes <b>208</b> and <b>210</b>, the carriers, injected from the electrodes <b>208</b> and <b>210</b>, will flow selectively through a portion of the MQW active layer <b>204</b> that is located right over the recess (i.e., air gap) of the substrate. That portion of the semiconductor multilayer structure, located right over the recess (air gap) on the principal surface of the substrate, has a lower density of dislocations and other defects than the other portions. Also, the ridge stripe is preferably arranged right over the air gap but not just over the void <b>211</b> at the combined portion of the n-GaN layer <b>102</b>. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, there is a dislocation extending straight upward from this void <b>211</b>.

0136In the semiconductor laser of this preferred embodiment, when a voltage is applied between the n- and p-electrodes <b>210</b> and <b>208</b>, holes are injected from the p-electrode <b>208</b> toward the MQW active layer <b>204</b> and electrons are injected from the n-electrode <b>210</b> toward the MQW active layer <b>204</b>. As a result, a gain is produced in the MQW active layer <b>204</b> and laser oscillation is produced in a wavelength range in the vicinity of 400 nm. In this preferred embodiment, a single recess is arranged under the current confining structure and ΣX/ΣY is defined within the range of 1.0 to 30. More specifically, the sum of the sizes X<b>1</b> and X<b>2</b> shown in <figref idref="DRAWINGS">FIG. 6</figref> is set equal to about 120 μm to about 400 μm and the size Y is set equal to about 20 μm to about 40 μm. Consequently, ΣX/ΣY=(X<b>1</b>+X<b>2</b>)/Y falls within the range of 6 to 10. Thus, in this preferred embodiment, the injected current flows vertically at a significantly reduced resistance compared to the conventional one. As a result, the voltage to be applied between the electrodes can be reduced.

0137In this preferred embodiment, the density of dislocations in the semiconductors right over the air gap is also lower than that of dislocations in the GaN substrate <b>101</b> by at least one order of magnitude and the influence of scratches on the principal surface of the GaN substrate <b>101</b> can also be reduced significantly.

0138The nitride-based semiconductor device of the preferred embodiment described above is a semiconductor laser with a current confining structure such as a ridge stripe. However, the present invention is in no way limited to that specific preferred embodiment. Alternatively, the present invention may also be applied to a light-emitting diode (LED) that needs no current confining structure. Even in an LED, by reducing the size of the air gap (recess), the electrical resistance can also be reduced overall when current is made to flow across the principal surface of its substrate.

0139In the semiconductor laser of this preferred embodiment, the p- and n-electrodes <b>208</b> and <b>210</b> are arranged on the opposite sides of the substrate <b>101</b> as shown in <figref idref="DRAWINGS">FIG. 6</figref>. Alternatively, the p- and n-electrodes <b>208</b> and <b>210</b> may be arranged on the same side (i.e., on the principal surface) of the substrate <b>101</b>. According to the conventional ELO process, a thick film needs to be formed to reduce the electrical resistance with respect to current flowing parallel to the principal surface of the substrate. However, according to the present invention, the area of the air gap portion can be reduced and therefore the electrical resistance with respect to the laterally flowing current can also be reduced overall. As a result, the long crystal growth process, which had to be carried out to form the thick film, can be shortened, thus increasing the throughput of the manufacturing process. It should be noted that even when arranged on the back surface of the substrate <b>101</b>, the n-electrode does not have to cover the back surface entirely but may cover the back surface only partially as shown in <figref idref="DRAWINGS">FIG. 7</figref>.

0140There is a void at the combined portion <b>211</b> of the n-GaN layer <b>102</b> that has grown laterally and dislocations are easily produced in the vicinity of the combined portion <b>211</b>. Even in the n-GaN layer <b>102</b>, leakage current is easily generated at and around the combined portion <b>211</b>. That is why to reduce the threshold current of the semiconductor laser and increase the long-term reliability thereof, a structure that prevents current from flowing through the combined portion <b>211</b> is preferably adopted. In the example illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the n-electrode <b>210</b> and the current confining structure such as a ridge stripe are arranged on the same side with respect to the combined portion <b>211</b>. By adopting such an arrangement, it is possible to prevent the current path from crossing the dislocations that are present around the combined portion <b>211</b>.

Embodiment 3

0141Hereinafter, a third preferred embodiment of a nitride-based semiconductor device according to the present invention will be described with reference to <figref idref="DRAWINGS">FIG. 8</figref>.

0142The arrangement of this preferred embodiment is different from that shown in <figref idref="DRAWINGS">FIG. 1</figref> in that a GaN layer <b>801</b> (with a thickness of 1 μm) is further provided on the surface of the n-GaN substrate <b>101</b> according to this preferred embodiment. Specifically, after the GaN layer <b>801</b> has been grown on the principal surface of the n-GaN wafer <b>101</b>, a striped ridge is formed on the principal surface of the wafer by the method that has already been described for the first preferred embodiment.

0143In this preferred embodiment, the ridge portion (corresponding to a raised portion of the resist) has a width X of about 20 μm and the recess has a width Y of about 5 μm. The bottom and side surface of the recess are covered with a mask layer <b>103</b> of SiO₂that has been deposited by ECR sputtering process or thermal CVD process.

0144The n-GaN layer <b>102</b> is also selectively grown laterally by the same method as that already described for the first preferred embodiment. In this preferred embodiment, ΣX/ΣY is defined approximately equal to eight.

0145Hereinafter, it will be described how the GaN layer <b>801</b> on the n-GaN wafer <b>101</b> works.

0146As described above, the principal surface of the n-GaN wafer <b>101</b> has scratches, damage and so on that were made during the polishing process. However, the principal surface of the GaN wafer has not only such surface damages that were caused by the polishing process but also variations in crystallographic orientations that were caused while the GaN wafer itself was made. For that reason, if a GaN layer were epitaxially grown directly on such a GaN wafer, the resultant GaN layer might have a decreased degree of surface planarity or morphology. To avoid those unwanted effects caused by the state of the principal surface of the wafer, a buffer layer such as the GaN layer <b>801</b> is preferably inserted between the GaN wafer <b>101</b> and the n-GaN layer <b>102</b>.

0147By inserting such a buffer layer, the degree of unevenness on the uppermost surface of the substrate structure can be reduced and the degree of planarity of its crystal faces can be increased. In addition, the unwanted effects that could be caused by the variations in crystallographic orientations on the principal surface of the GaN wafer can also be reduced.

0148The GaN layer <b>801</b> may have a multilayer structure. <figref idref="DRAWINGS">FIG. 9</figref> illustrates a structure in which a low-temperature GaN layer <b>1101</b> has been grown at a temperature of about 500° C. to about 600° C. on the n-GaN wafer <b>101</b> and then a high-temperature GaN layer <b>1102</b> has been grown thereon at a temperature of about 1,000° C. to about 1,100° C. By growing the low-temperature GaN layer <b>1101</b>, the effects that could be caused by the defects in the n-GaN wafer <b>101</b> can be minimized. In addition, the degree of crystallinity can be increased by the high-temperature GaN layer <b>1102</b>. As a result, the density of defects in the n-GaN layer <b>102</b> that has grown on the high-temperature GaN layer <b>1102</b> can be further reduced.

0149<figref idref="DRAWINGS">FIG. 10</figref> illustrates a structure in which a GaN layer having non-uniform dopant concentrations or carrier densities in the thickness direction has been formed on the GaN wafer <b>101</b>. Specifically, on the GaN wafer <b>101</b>, stacked are an (AlIn)GaN layer <b>1201</b> having a relatively low carrier density of about 5×10¹⁷cm⁻³and an (AlIn)GaN layer <b>1202</b> having a relatively high carrier density of about 1×10¹⁷cm⁻³. As used herein, the “(AlIn)GaN layer” refers to a GaN layer and a nitride-based semiconductor layer in which at least a portion of Ga in the GaN layer has been replaced with Al or In.

0150In this preferred embodiment, only the (AlIn)GaN layer <b>1202</b> having the relatively high carrier density has the recesses. Alternatively, the bottom of the recesses may reach the (AlIn)GaN layer <b>1201</b> having the relatively low carrier density.

0151The n-GaN layer <b>102</b> may be grown by the same method as that already described for the first preferred embodiment.

0152If the (AlIn)GaN layer <b>1201</b> having the relatively high carrier density were grown directly on the principal surface of the GaN wafer <b>101</b>, then dislocations would be produced in GaN crystals having the high carrier density and its degree of crystallinity would decrease. For that reason, during the initial stage of growth of (AlIn)GaN crystals on the principal surface of the GaN wafer <b>101</b>, the crystals are preferably grown under such conditions as to make the carrier density as low as possible.

0153In the example illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the GaN layer <b>1201</b> having the relatively low carrier density is formed on the GaN wafer <b>101</b> first. However, since the ridge portion with the narrow stripe width has a high carrier density, the electrical resistance has also been reduced sufficiently.

0154The exposed surface of the (AlIn)GaN layer <b>1202</b> having the relatively high carrier density functions as the seed portions, from which the n-GaN layer <b>102</b> grows not only vertically but also laterally as well. The n-GaN layer <b>102</b> does not have to have a uniform carrier density but may have a distribution, too. For example, a GaN layer <b>1203</b> having a relatively low carrier density of 5×10¹⁷cm⁻³or less may be formed during an initial stage of the growth process and then a GaN layer <b>1204</b> having a relatively high carrier density of about 5×10¹⁷cm⁻³may be stacked thereon.

0155The (AlIn)GaN layer <b>1202</b> having the relatively high carrier density preferably has a thickness of 50 nm to 500 nm, while the GaN layer <b>1203</b> having the relatively low carrier density preferably has a thickness of 50 nm to 1,000 nm.

0156The buffer layer to be inserted between the n-GaN layer <b>102</b> and the GaN substrate <b>101</b> does not have to be a GaN layer but may also be made of a material represented by Al_x3Ga_y3In_z3N (where x3+y3+z3=1, x3≧0, y3≧0 and z3≧0).

0157A substrate with such a buffer layer and a substrate with no buffer layer will be collectively referred to herein as “substrate structures”. That is to say, the “substrate structure” may refer to only a substrate body made of Al_x1Ga_y1In_z1N crystals (where x1+y1+z1=1, x1≧0, y1≧0 and z1≧0) or a structure including an Al_x3Ga_y3In_z3N crystal layer (where x3+y3+z3=1, x3≧0, y3≧0 and z3≧0) on the upper surface of such a substrate body. If the Al_x3Ga_y3In_z3N crystal layer (where x3+y3+z3=1, x3>0, y3≧0 and z3≧0) has been formed on the uppermost surface of such a substrate body, then a particular region on the surface of this crystal layer will function as a “vertical growth region”.

Embodiment 4

0158Hereinafter, a fourth preferred embodiment of a nitride-based semiconductor device according to the present invention will be described with reference to <figref idref="DRAWINGS">FIG. 11</figref>.

0159In the example illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, each of multiple recesses on the principal surface of the GaN wafer <b>101</b> has a width of about 5 μm but the widths of the ridge portions (raised portions) change from one position to another. That is to say, the widths of the ridge portions are relatively small near the outer periphery of the wafer but gradually increase toward the center of the wafer. In the other respects, the arrangement shown in <figref idref="DRAWINGS">FIG. 11</figref> is the same as that of the first preferred embodiment that has already been described with reference to <figref idref="DRAWINGS">FIG. 1</figref>.

0160By adopting such an arrangement, not only can the density of dislocations in the GaN wafer <b>101</b> be reduced by at least one order of magnitude but also can be the warp of the wafer due to a difference in lattice constant between the wafer and the semiconductor multilayer structure be reduced as well.

0161In general, if an n-GaN wafer <b>101</b> is heated to a crystal growing temperature of 1,000° C. to 1,100° C. and then cooled to room temperature, the wafer will usually be warped due to a difference in lattice constant between the wafer and the semiconductor multilayer structure. The warp direction of the wafer changes depending on whether the lattice constant of the semiconductor multilayer structure is smaller than that of the GaN wafer <b>101</b> or greater than it.

0162If the lattice constant of the semiconductor multilayer structure is greater than that of the GaN wafer <b>101</b>, the ridge portions preferably have variable widths that decrease toward the outer periphery of the wafer. This is because the stress on the periphery of the wafer can be reduced by doing so. On the other hand, if the lattice constant of the semiconductor multilayer structure is smaller than that of the GaN wafer <b>101</b>, the ridge portions preferably have variable widths that increase toward the outer periphery of the wafer. In that case, X/Y may be set approximately equal to 0.5 at the center of the wafer and approximately equal to 2.0 on the periphery of the wafer, respectively.

0163Alternatively, similar effects are achievable even by making the widths of the ridge portions (i.e., raised portions) constant irrespective of the position and changing the widths of the recesses from one position on the wafer to another. However, if the widths of the recesses were increased excessively, then the crystal growing process needed to combine the n-GaN layer <b>102</b> might be too long to finish. That is why the widths are preferably adjusted within an appropriate range. In that case, X/Y may be set approximately equal to 0.5 at the center of the wafer and approximately equal to 1.0 on the periphery of the wafer, respectively.

INDUSTRIAL APPLICABILITY

0164A nitride-based semiconductor device according to the present invention can be used effectively as a light source for an optical recorder, an optical display (laser display) device and so on that need a highly reliable GaN based semiconductor laser. The present invention is also effectively applicable for use in laser cutting, medical treatments, and so on. Furthermore, if the present invention is applied to another nitride-based semiconductor device including an active region such as a channel region, then the channel can have a much smaller number of defects. As a result, a high-reliability device is realized.