Systems and methods for synchronizing wireless communication systems

BACKGROUND

p-0002The present invention relates to wireless communication systems, and in particular, to systems and methods for synchronizing wireless communication systems.

p-0003Wireless communication systems are electronic systems that allow information to be transferred between two systems using electromagnetic waves propagating through space or air. <figref idrefs="DRAWINGS">FIG. 1A</figref> illustrates a typical wireless communication system. Wireless communication system <b>100</b> includes two wireless communication devices <b>101</b> and <b>102</b>. In a typical wireless communication system, digital information is received in a first wireless device <b>101</b> and transmitted to the other wireless device <b>102</b>. Similarly, digital information may be received in wireless device <b>102</b> and transmitted to wireless device <b>101</b>. The transmitted digital information may then be used by other electronic devices coupled to wireless devices <b>101</b> or <b>102</b>. Wireless device <b>101</b> may include a digital processing component <b>110</b>, an analog processing component <b>120</b>, and an antenna <b>121</b>. During transmission, digital information may be received by the digital processing component <b>110</b> (e.g., from an electronic device such as a computer system). During reception, information may be received from analog processing component <b>120</b> as a digital data stream from an analog-to-digital converter, for example. Digital processing component <b>110</b> may perform a variety of functions for transmitting and receiving data including, for example, Fourier Transforms, Inverse Fourier Transforms, coding or decoding (e.g., for error correction), and a variety of other processing steps that occur on received and transmitted digital signals. During transmission, digital signals are transferred to an analog processing component <b>120</b>. Analog processing component <b>120</b> may include analog-to-digital and digital-to-analog conversion, filtering, gain control, and frequency up coversion and down conversion, for example, to translate the digital information into an analog waveform that may be transmitted on antenna <b>121</b>. The analog waveform is received by the other antenna <b>131</b> and processed by analog processing component <b>130</b>. The received waveform may be amplified, down converted, filtered, and converted back into the digital domain. Digital processing component <b>140</b> in the receiving system may receive streams of digital information to be processed and provided as an output of the wireless system.

p-0004One problem associated with wireless communication systems involves synchronizing the transmitting and receiving systems so information may be accurately transmitted and received. For example, the data formats of the transmitted information may include precise timing characteristics. Additionally, processing the digital streams of data that flow from the analog processing component (the “analog front end”) may require that the digital processing component configure the analog front-end in particular ways at very precise periods of time. For example, <figref idrefs="DRAWINGS">FIG. 1B</figref> illustrates one wireless transmission scheme know as frequency hopping. In a frequency hopping wireless system, transmitted data may be modulated at different frequencies at different times. For example, data may be transmitted on a frequency channel <b>101</b> by modulating the analog signals at a frequency of f<b>1</b>. At other times, data may be transmitted on frequency channels <b>102</b> and <b>103</b> by modulating the analog signals at frequencies of f<b>2</b> or f<b>3</b>. In a frequency hopping system, data transmission may move from one frequency to the next at certain points in time. In order to receive the transmitted data, the receiving system must accurately track the changes in frequency of the transmitting system. Thus, the receiving system must be synchronized in time with the transmitting system so that, for example, when the transmitting system changes from one frequency to another, the receiving system changes frequencies at the same time. Moreover, the receiving system must have some method of determining the frequencies that the transmitting system is hopping between. Other timing requirements may be associated with the digital formats of the transmitted data (e.g., packet formats) and the modulation techniques used. Synchronization of the transmitting and receiving systems becomes particularly important as data rates increase.

p-0005<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a wireless communication system protocol. The example data transmission format shown in <figref idrefs="DRAWINGS">FIG. 2</figref> illustrates some of the problems solved by embodiments of the present invention. The data transmitted from a wireless system may be used to perform a variety of functions. The structure of a data packet may include a preamble <b>201</b> used for synchronization, a second preamble <b>202</b> used for channel estimation and calibration, and then a payload carrying data. The synchronization preamble may comprise multiple blocks of data as shown at <b>220</b>. In one example system, the synchronization preamble may include 24 blocks. Each block may also be referred to as a “symbol.” The symbols are transmitted sequentially by the transmitting system and received by the receiver. The transmitting system may send each symbol using a different frequency. For example, the first symbol, S<b>1</b>, may be transmitted on frequency f<b>1</b>, the second symbol, S<b>2</b>, may be transmitted on frequency f<b>2</b>, and the third symbol, S<b>3</b>, may be transmitted on frequency f<b>3</b>. The fourth symbol, S<b>4</b>, may be transmitted on frequency f<b>1</b> again. This is an example of a frequency hopping pattern wherein the frequency hopping sequence is [f<b>1</b>, f<b>2</b>, f<b>3</b>]. Wireless systems may use a variety of other hopping sequences (i.e., hopping patterns).

p-0006The time domain illustration of a symbol is illustrated at <b>230</b>. The start of the symbol is at t<b>1</b>. A time t<b>3</b>, symbol <b>230</b>A ends and symbol <b>230</b>B begins. Thus, times t<b>1</b> and t<b>3</b> represent the time domain boundaries of the symbol. Some protocols may include a division of the symbol into two components. The first component includes a data transmission component from time t<b>1</b> to t<b>2</b>, and the second component of the symbol from t<b>2</b> to t<b>3</b> may be zero. If a total of 165 samples of a received symbol are obtained, 128 samples may include data and 37 samples may be zero, for example. For synchronization, the symbols may be a pseudo-random number sequence (e.g., “PN sequences” or “PN codes”). The data represented by the samples may be an orthogonal frequency division multiplexed (“OFDM”) signal, for example, as shown at <b>240</b>. The baseband OFDM signal illustrated may include 128 subcarriers spread out between −264 MHz to +264 MHz. Of the 128 subcarriers, 112 may be spaced symmetrically about zero frequency, with 56 subcarriers such as f_S1, f_S2, though f_SN, both above and below zero frequency. Each subcarrier may contain 2-bits of data, for example. Data may be encoded in the OFDM signal <b>240</b> and transmitted as a symbol during the period from t<b>1</b> to t<b>2</b>. For a 264 MHz bandwidth OFDM symbol, the system may be sampled at 528 MHz. Accordingly, the symbol period (from t<b>1</b> to t<b>3</b>) may be about 312.5 nanoseconds (“ns”). Therefore, a wireless system receiving symbols may be required to switch from one carrier frequency f<b>1</b> to another carrier frequency f<b>2</b> synchronously with the transmitting system, for example, with a precision of about 1 clock cycle, or about 2 ns). In particular, the receiving wireless system may have to reconfigure analog component to receive different signals at different frequencies at different times. The timing of analog reconfiguration should be such that the analog receiver circuits are able to process incoming data. Accordingly, changes to analog circuits must be timed precisely with changes in the transmitted signals. More generally, the timing of analog and digital processing steps may require close alignment in time with timing characteristics of received data.

p-0007Thus, there is a need for improved synchronization in wireless systems. The present invention solves these and other problems by providing systems and methods for synchronizing wireless communication systems.

SUMMARY

p-0008Embodiments of the present invention include systems and methods for synchronizing wireless communication systems. In one embodiment the present invention includes a wireless communication system comprising an analog receiver for receiving a plurality of symbols on a plurality of frequency channels, each symbol lasting a first time period, a reference frequency generator for generating a periodic reference signal having a period equal to the first time period of each symbol, and a channel controller coupled to the reference frequency generator, the channel controller generating a command to the analog receiver to change from one frequency channel to another frequency channel a predetermined amount of time after the reference frequency signal enters a predetermined state.

p-0009In one embodiment, the present invention further comprises a delay coupled to the reference frequency generator, wherein the delay triggers the channel controller to generate said command a predetermined amount of time after the reference frequency signal enters said predetermined state.

p-0010In one embodiment, the reference frequency generator is a counter, and wherein said command is generated a predetermined amount of time after said counter reaches a predetermined value.

p-0011In one embodiment, the present invention further comprises a plurality of correlators, wherein each correlator receives a digital representation of said symbols and correlates each symbol with a plurality of reference values, and in accordance therewith, generates correlation results, and wherein the correlation results control the commands generated by the channel controller.

p-0012In one embodiment, the correlation results for each symbol are compared to a threshold.

p-0013In one embodiment, the correlation results for each symbol include a plurality of correlation results, and wherein at least one of said plurality of correlation results is stored and associated with a state of said reference frequency signal.

p-0014In one embodiment, the correlation results are compared against a first threshold for a first time period and the correlation results are compared against a second threshold for a second time period.

p-0015In one embodiment, the present invention further comprises a memory for storing a time each symbol is detected.

p-0016In one embodiment, the present invention further comprises a memory for storing a plurality of values indicating the number of times a corresponding plurality of symbols are detected at a particular time.

p-0017In another embodiment, the present invention includes a method of receiving information in a wireless communication system comprising receiving a plurality of symbols on a plurality of frequency channels, each symbol lasting a first time period, generating a reference frequency having a period equal to the first time period of the symbol, and generating a channel control signal to change from a first channel to a second channel at a predetermined point in time of the reference frequency period.

p-0018In one embodiment, the present invention further comprises detecting a first symbol in said plurality of symbols and starting the reference frequency in response to detecting the first symbol.

p-0019In one embodiment, generating the reference frequency comprises operating a counter that cycles through a plurality of values during each reference frequency period, and wherein the predetermined point in time of the reference frequency period corresponds to one of said plurality of values.

p-0020In one embodiment, the present invention further comprises storing a delay value.

p-0021In one embodiment, the present invention further comprises detecting said predetermined point in time of the reference frequency period and generating said channel control signals a predetermined amount of time after said detection.

p-0022In another embodiment, the present invention includes a baseband processor comprising a symbol processor that detects symbols received by said baseband processor, a reference frequency generator that generates a periodic reference signal having a period equal to a symbol period, control logic coupled to the reference frequency generator, wherein the control logic receives the reference frequency signal and generates an output when the reference frequency signal is in a predetermined state, and a channel controller coupled to the output of the control logic, the channel controller generating frequency synthesizer control signals in response to the control logic output signal a predetermined amount of time after receiving said output from said control logic.

p-0023In one embodiment, the reference frequency generator is a counter and the predetermined state is a predetermine value of said counter.

p-0024In one embodiment, the reference frequency generator is a first counter and the control logic includes a second counter for generating said control logic output signal after counting for said predetermined amount of time.

p-0025In one embodiment, said symbol processor includes a plurality of cross-correlators, and wherein the channel controller generates first frequency control signals corresponding to a first frequency pattern if a first of said plurality of cross-correlators indicates that a symbol has been received, and the channel controller generates second frequency control signals corresponding to a second frequency pattern if a second of said plurality of cross-correlators indicates that a symbol has been received.

p-0026In one embodiment, the reference frequency generator is a counter, and wherein said symbol processor includes a plurality of cross-correlators that generate a plurality of correlation results for each symbol, and wherein each correlation result corresponds in time to a plurality of values of said counter, and wherein a representative value of said counter is stored for each of a plurality of received symbols and used to produce a final value for generating said control logic output.

p-0027In another embodiment, the present invention includes a method of receiving information in a wireless communication system comprising receiving a digital signal at a first data rate, filtering the digital signal, decimating the digital signal to a second data rate, correlating the digital signal with a plurality of reference values, and programming a synthesizer with one of a plurality of frequency patterns corresponding to the reference value resulting in the largest correlation result.

p-0028In one embodiment, the present invention further comprises comparing the correlation results against a first threshold during a first time period and comparing the correlation results against a second threshold during a second time period.

p-0029In one embodiment, the present invention further comprises comparing the correlation results against a first threshold, and in accordance therewith, detecting an increase in a first correlation result, and generating a hopping command a predetermined amount of time after detecting said increase in said correlation result.

p-0030In one embodiment, the digital signal includes a plurality of symbols having a first period, the method further comprising operating a counter having a period equal to the first period.

p-0031The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0032<figref idrefs="DRAWINGS">FIG. 1A</figref> illustrates a wireless communication system.

p-0033<figref idrefs="DRAWINGS">FIG. 1B</figref> illustrates frequency hopping in a wireless communication system.

p-0034<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a wireless communication system protocol.

p-0035<figref idrefs="DRAWINGS">FIG. 3</figref> illustrates a receive path for a wireless communication system according to one embodiment of the present invention.

p-0036<figref idrefs="DRAWINGS">FIGS. 4A-D</figref> illustrate a baseband processor for use in a wireless communication system according to one embodiment of the present invention.

p-0037<figref idrefs="DRAWINGS">FIGS. 5A-B</figref> illustrate a baseband processor for use in a wireless communication system according to another embodiment of the present invention.

p-0038<figref idrefs="DRAWINGS">FIG. 6</figref> illustrates pattern selection and synchronization techniques according to one embodiment of the present invention.

p-0039<figref idrefs="DRAWINGS">FIG. 7</figref> illustrates a reference symbol that may be used in one embodiment of the present invention.

p-0040<figref idrefs="DRAWINGS">FIG. 8</figref> illustrates a pattern selection and synchronization based on cluster analysis according to one embodiment of the present invention.

p-0041<figref idrefs="DRAWINGS">FIG. 9</figref> illustrates a baseband processor according to one embodiment of the present invention.

p-0042<figref idrefs="DRAWINGS">FIG. 10</figref> is an illustrative example of a cross-correlator according to one embodiment of the present invention.

p-0043<figref idrefs="DRAWINGS">FIG. 11</figref> is an illustrative example of a pattern selector according to one embodiment of the present invention.

p-0044<figref idrefs="DRAWINGS">FIG. 12A</figref> is an illustrative example of the methods implemented by a timing processor according to one embodiment of the present invention.

p-0045<figref idrefs="DRAWINGS">FIG. 12B</figref> illustrates the output of a cross-correlation during reception of one example symbol.

p-0046<figref idrefs="DRAWINGS">FIG. 13A</figref> illustrates an example method of processing correlation results according to one embodiment of the present invention.

p-0047<figref idrefs="DRAWINGS">FIG. 13B</figref> illustrates an example histogram of timer values according to one embodiment of the present invention.

p-0048<figref idrefs="DRAWINGS">FIGS. 14A-B</figref> illustrate threshold generation according to one embodiment of the present invention.

DETAILED DESCRIPTION

p-0049Described herein are techniques for systems and methods for synchronizing wireless communication systems. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

p-0050<figref idrefs="DRAWINGS">FIG. 3</figref> illustrates a receive path for a wireless communication system according to one embodiment of the present invention. Wireless communication system <b>300</b> includes an antenna <b>310</b>, amplifier <b>311</b>, down converter <b>312</b>, frequency synthesizer <b>330</b>, filter <b>314</b>, variable gain amplifier (“VGA”) circuit <b>315</b>, analog-to-digital converter (“A/D”) <b>316</b>, and baseband processor <b>320</b>. Antenna <b>310</b> receives wireless signals and couples the received signals to the input of amplifier <b>311</b>. Amplifier <b>311</b> may be a low noise amplifier (“LNA”) for amplifying very low voltages representing the received signals. The received signals may be modulated at different carrier frequencies at different times as described above. In this example, the signals are down converted using down converter <b>312</b>. Down converter <b>312</b> may be a mixer circuit having inputs coupled to the output of LNA <b>311</b> and second inputs coupled to a frequency synthesizer <b>330</b>. Frequency synthesizer <b>330</b> may be a programmable frequency synthesizer for generating different frequencies in response to control signals received from baseband processor <b>320</b>. Baseband processor <b>320</b> may change the control signals to reprogram synthesizer and thereby change the down conversion frequencies for down converting received RF signals at different times. The down converted signal at the output of down converter <b>312</b> is referred to as a “baseband signal.” The output of down converter <b>312</b> is coupled through a filter <b>314</b> to the input of an VGA <b>315</b> for amplifying the baseband signal. The output of VGA <b>315</b> is coupled to the input of A/D <b>316</b> and sampled. The output of A/D <b>316</b> is a digital data stream, which is coupled to the input of baseband processor <b>320</b> for digital signal processing. The sample rate of the A/D <b>316</b> may be 1.056 giga-samples per second (“Gsps”), for example. The digital representations of the received symbols may be processed by symbol processor <b>321</b>, which may be included as part of baseband processor <b>320</b>, for example. Symbol processor <b>321</b> may detect incoming symbols and synchronize changes in the frequency synthesizer to be coincident with the symbol boundaries at the mixer.

p-0051For example, in a frequency hopping systems, frequency synthesizer <b>312</b> may be required to change between down converter frequencies at the time boundary between adjacent symbols. Embodiments of the present invention may be used to program the frequency synthesizer to change the down conversion frequency at the time boundary of each symbol. To achieve this, it is desirable to change the synthesizer frequency provided at the input of down converter <b>312</b> at the moment a symbol ends and the next symbol begins (the symbol boundary). As a symbol is received, there is a processing delay td<b>1</b> (e.g., analog and/or digital) from the output of the mixer to symbol processor <b>321</b>. The delay td<b>1</b> represents the time for the end of a full symbol to propagate through the analog and digital circuit to be detected by symbol processor <b>321</b>. A delay td<b>2</b> represents the amount of time from detection of a symbol to a change in frequency of mixer <b>312</b>. For example, when symbol is detected in symbol processor <b>321</b>, there may be a delay between the point in time of detection and the time it takes for baseband processor to reprogram frequency synthesizer <b>330</b> and for the new output frequency to arrive at the down convertor <b>312</b>. There may also be a settling time for down converter <b>312</b>. As illustrated below, symbol processor <b>321</b> may detect a symbol before the entire symbol has been received. For example, symbol processor <b>321</b> may detect a first portion of the symbol, and cause control signals to reprogram frequency synthesizer <b>330</b> to change frequency. However, after symbol processor <b>321</b> detects a symbol, it may delay issuing changes to frequency synthesizer <b>330</b> so that down converter <b>312</b> changes the down conversion frequency at precisely the boundary between the symbol being received and the next symbol. Accordingly, baseband processor <b>320</b> may include a delay <b>322</b> for delaying the issuance of frequency control signals (sometimes referred to as “channel control signals,” “frequency hopping signals,” “hopping signals,” or “hop control signals”). In some applications, the delay may be approximately equal to the total symbol period less the portion of the symbol period used for detecting the symbol, less the propagation delays from the output of down converter <b>312</b> to symbol detection, and less the propagation delay from detection to changing the frequency of the down converter.

p-0052In some applications, symbol detection may not result in an exact point in time or a precise cycle of a baseband system clock. Symbol detection results may non-idealities leading to multiple detection results, such as clusters of peaks described below, for example. Accordingly, embodiments of the present invention may include an offset value (an offset of a counter period, for example) for determining the point in time to start the delay. A timebase counter may be used to establish a timebase for the receiving system. The offset value may be determined by analyzing symbol detection results, such as cross-correlation results described below. The offset value may be related to the state of the timebase counter, so that when the timebase counter enters a particular state, the system triggers a change in the control signals to the frequency synthesizer, which may include starting delay <b>322</b>.

p-0053<figref idrefs="DRAWINGS">FIGS. 4A-D</figref> illustrate a baseband processor for use in a wireless communication system according to one embodiment of the present invention. <figref idrefs="DRAWINGS">FIG. 4A</figref> illustrates a baseband processor <b>400</b> including a symbol processor <b>402</b>, reference frequency generator <b>403</b>, and channel control <b>404</b>. Symbol processor <b>402</b> receives digital data from an A/D <b>401</b> over N bit lines. The digital data may include symbols, which are detected by symbol processor <b>402</b>. Reference frequency generator <b>403</b> generates periodic reference signal that may be used as a timebase for synchronizing received symbols with functions carried out on the wireless receiver. In one embodiment, reference frequency generator <b>403</b> generates a periodic signal having a period equal to the symbol period. <figref idrefs="DRAWINGS">FIG. 4B</figref> illustrates the timing of symbols and the reference frequency generator <b>403</b>. Symbols are received sequentially as shown at <b>410</b>. The modulation frequencies for the symbols may be different according to the particular frequency hopping pattern used by the transmitting wireless system. The symbols are first down converted (using a mixer circuit) and then sampled by A/D <b>401</b>. The symbol periods, Tsym, are illustrated at <b>420</b>. The arrows <b>490</b> represent the boundaries between adjacent symbols (symbol boundaries). The period of a signal from the reference frequency generator <b>403</b> (the reference frequency signal period) is illustrated at <b>430</b> and <b>440</b>. <figref idrefs="DRAWINGS">FIG. 4B</figref> illustrates that the reference frequency period may not be coincident with the symbol boundaries. As mentioned above, it may be desirable to generate channel control signals at a point in time just before the symbol boundary so that the frequency synthesizer can be reprogrammed to a new frequency to down convert the next incoming symbol. Thus, a delay of t<b>1</b> at <b>430</b> is introduced so that the channel control signals are reprogrammed at the proper time. Reference frequency generator <b>403</b> may be started by detecting a symbol, for example, and the start of a delay may be triggered either by detection of a symbol or detection of a particular state of the reference frequency generator. As illustrated at <b>440</b>, symbol detection may include an uncertainty error, “δ”. Thus, the system may first operate in an initialization phase to account for the uncertainty. Accordingly, in one embodiment, the delay may be triggered by symbol detection during a first period of time (e.g., an initialization phase) and the delay may be triggered by a predetermined state of the reference frequency signal during a second period of time (e.g., a post-initialization or normal operation phase). The state of the reference frequency signal for triggering the delay may be calculated by analyzing the detected symbols. A specific example of symbol detection and analysis is provided below.

p-0054<figref idrefs="DRAWINGS">FIGS. 4C and 4D</figref> illustrate an example of a baseband processor for use in a wireless communication system according to one embodiment of the present invention. In this example, the reference frequency generator is implemented using a counter <b>403</b>A. Counter <b>403</b>A may have a count period equal to the symbol period Tsym shown in <figref idrefs="DRAWINGS">FIG. 4D</figref> at <b>410</b>. Counter <b>403</b>A may start counting when a symbol is detected. The counter receives a system clock (not shown) and may count for a time Tsym and then restart. As shown at <b>420</b> in <figref idrefs="DRAWINGS">FIG. 4D</figref>, the reference frequency period of counter <b>403</b>A is equal to the symbol period Tsym, but the boundaries may not be coincident. As illustrated in <figref idrefs="DRAWINGS">FIG. 4</figref> at <b>420</b>, counter <b>403</b>A reaches a count value of N=N<b>1</b> at the same period as the symbols are received. Counter <b>403</b>A may increment at the same rate as the sample period of the symbols, for example. Accordingly, each value of counter <b>403</b>A may correspond to a particular digital sample of a symbol. Thus, by triggering a delay when counter <b>403</b>A reaches a particular state (e.g., a predetermine or specified counter value), the control signals may be transmitted at a time very close to the symbol boundary, and the frequency synthesizer may be reprogrammed to down convert incoming symbols received on other frequencies. Counter <b>403</b>A may be a modulo-N counter, for example. In one embodiment, counter <b>403</b>A may be a modulo <b>165</b> counter.

p-0055<figref idrefs="DRAWINGS">FIGS. 5A-B</figref> is an example of a baseband processor for use in a wireless communication system according to another embodiment of the present invention. This example illustrates a symbol <b>550</b> that starts at time “t<b>1</b>”, ends at time “t<b>5</b>”, and includes 165 samples. The sample rate may be 528 Msps, for example. The first 128 samples of the symbol carry data, which may be encoded using quadrature amplitude modulation (“QAM”) techniques, for example. The following 37 samples of the symbol may be set to zero. Symbol <b>550</b> may be received at an analog front end, digitized for processing on N digital bit lines (e.g., 5 bits), and coupled to the input of symbol processor <b>502</b> included as part of baseband processor <b>500</b>. Symbol processor <b>502</b> may detect incoming symbols by analyzing the data stored in the first portion of the symbol (e.g., the first 128 samples of the symbol). A time delay, d<b>1</b>, may exist between the time a symbol is down converted and the time the symbol is detected. Thus, the end of a symbol at the output of the down converter may occur at time t<b>2</b>, and detection may occur at time t<b>3</b>. Delay, d<b>1</b>, may include a 2-3 sample delay (about 4-5 ns) due to analog filters and variable gain amplifiers in the analog front end and a 9-10 sample delay (about 19 ns) due to a digital decimation filter shown below, for example. As illustrated in <figref idrefs="DRAWINGS">FIG. 5B</figref>, baseband processor <b>500</b> may include a reference frequency generator implemented as a counter <b>504</b> for setting a timebase (“a timebase counter”), a delay <b>506</b> for delaying issuance of channel control signals, and a channel controller <b>508</b> for generating channel control signals to change the frequency of a frequency synthesizer (not shown). Because the channel control signals may be used for reprogramming the frequency synthesizer to down convert different carrier frequencies used in a frequency hopping system, these signals are sometimes referred to as hop control signal and hopping commands. The system may also include a delay, d<b>2</b>, between issuance of the channel control signals and settling of the analog channel to receive a new down conversion frequency. Delay, d<b>2</b>, may include a delay from the time the hopping commands are dispatched to the time the commands actually reach the frequency synthesizer (about 2-3 ns), synthesizer settling time (less than 5 samples or 9.5 ns), and the settling time of the analog channel including the mixer and analog filter transient response (about 4 samples or 8 ns). Thus, the system may include a delay <b>506</b>, which may be programmable, introduced between the time the symbol is detected and the time the hopping commands are dispatched. In one embodiment, counter <b>504</b> has a count period equal to the symbol period, and the delay is triggered every time the counter reaches a particular value N=N<b>1</b>. As illustrated in <figref idrefs="DRAWINGS">FIG. 5A</figref>, the time when counter <b>504</b> has a value of N=N<b>1</b> is the time to issue a signal to start delay <b>506</b>. When delay <b>506</b> ends, the new values of channel control signals may be sent to the synthesizer, and accordingly, the analog front end will be ready to receive the next symbol and down convert the symbol from a new down conversion frequency at t<b>5</b>. By changing the frequency of the synthesizer at the last possible moment before reception of a new symbol, the system is able to capture the maximum amount of information in the wireless channel available for each modulation frequency, and thereby reduce distortion and SNR.

p-0056<figref idrefs="DRAWINGS">FIG. 6</figref> illustrates pattern selection and synchronization techniques according to one embodiment of the present invention. A baseband processor according to embodiments of the present invention may include one or more cross-correlators <b>601</b>A-C for detecting received symbols. In one embodiment, the sequence of frequencies (i.e., hopping patterns) used by the transmitting system may be determined in the baseband by analyzing the received data against a plurality of reference symbols <b>602</b>A-C. If data received in a symbol correlates or otherwise matches one of the reference symbols, such a result may indicate the hopping pattern that is being used by the transmitting system. For example, in one application, the transmitting system may transmit symbols including a pseudo-random number sequence (e.g., “PN sequences” or “PN codes”) in each symbol for the first <b>24</b> symbols. Such example reference symbols are illustrated by symbols <b>700</b> in <figref idrefs="DRAWINGS">FIG. 7</figref>. The first PN sequence may be transmitted using a hopping pattern of {f<b>1</b>, f<b>2</b>, f<b>3</b>, f<b>1</b>, f<b>2</b>, f<b>3</b>, etc . . . }, for example. Examples of hopping patterns are shown below. Different PN sequences may indicate different hopping patterns. Accordingly, different PN sequences may be used as the different reference symbols so that if one of the correlators <b>601</b>A-C indicates a match, the system is able to identify the hopping pattern as the pattern corresponding to the PN sequence that produced the match. More generally, reference symbols <b>602</b> may be used to detect the hopping pattern by associating each reference symbol with a particular hopping pattern (e.g., by using the output of particular cross-correlators to determine hopping pattern selection).

p-0057In this example, a channel controller <b>610</b> includes a hopping pattern state machine <b>611</b>. The correlator <b>601</b>A-C that generates a match (a value indicating a correlation between a received symbol and the reference symbol) is selected at <b>603</b> and coupled to the input of hopping pattern state machine <b>611</b> to program the particular hopping pattern. Detection of a symbol by correlators <b>601</b>A-C may also trigger the start of a modulo-N counter <b>604</b>. Counter <b>604</b> has a period equal to the period of the received symbols. Counter <b>604</b> is compared to an offset value (N<b>1</b>) stored at <b>605</b> by comparator <b>606</b>. Offset value N<b>1</b> may be set during initialization, for example. When the value of counter <b>604</b> matches the offset value, a delay <b>608</b> is triggered. Delay <b>608</b> may be programmable using delay register <b>607</b>, for example. At the end of a programmed time period, delay <b>608</b> triggers channel controller <b>610</b> and hop commands are dispatched.

p-0058<figref idrefs="DRAWINGS">FIG. 8</figref> illustrates a pattern selection and synchronization based on cluster analysis according to one embodiment of the present invention. In one embodiment, cross-correlators may not generate a single result on a particular sample of the symbol period. Rather, cross-correlators may generate a cluster of results that may be analyzed to generate an offset value. For example, in one embodiment, synchronization may include generating cross-correlations for each reference symbol at <b>801</b>. At <b>802</b>, the cross-correlation results may be compared to a threshold value at <b>802</b>. If a cross-correlation result is greater than a threshold, a first “peak” may be detected from a potential plurality of correlation results for a symbol (i.e., a cluster) at <b>803</b>. At <b>804</b>, the correlation results and time the result occurred may be stored. At <b>805</b>, a hopping pattern may be selected based on the particular correlator generating a “peak.” At <b>806</b>, a baseband reference frequency may be started (e.g., a timebase counter). At <b>807</b>, another cross-correlation peak in the cluster may be detected. At <b>808</b>, the next detected peak is compared with the previously stored peak. If the next peak is greater than the stored peak (e.g., or greater than the stored peak by a specified amount), then the new correlation results and time may be saved at <b>810</b>. If the next peak is less than the stored peak, the process may discard the information for the new peak. If there are more peaks at <b>811</b>, then peak detection and comparison (at <b>807</b>-<b>810</b>) are repeated. Subsequent analysis of clusters of correlation results for other symbols received by the system may be analyzed at <b>812</b>. A detailed example of the steps described above is provided below.

p-0059<figref idrefs="DRAWINGS">FIG. 9</figref> illustrates a baseband processor according to one embodiment of the present invention. Baseband processing <b>900</b> includes a filter <b>901</b>, decimator <b>902</b>, block memory <b>903</b>, threshold generator <b>904</b>, cross correlator (“Xcorr”) <b>905</b>, pattern selector <b>906</b>, timing processor <b>907</b>, counter <b>908</b>, delay <b>909</b>, and channel control <b>910</b>. Digital data streams are received from analog-to-digital converters (“ADC”) in the analog front end (not shown). The digital data may correspond to a plurality of symbols, and may be received at approximately 1.056 Giga-samples per second (“Gsps”), for example. In one embodiment, the digital data may be received separately as in-phase (“I”) and quadrature (“Q”) digital signals.

p-0060Digital data may be received at the input of filter <b>901</b>. Filter <b>901</b> may be used to eliminate signal content such as noise or unwanted signal components (sometimes referred to as “blockers”). For example, the output of an ADC may have a bandwidth from −528 MHz to +528 MHz, but the bandwidth of the signal of interest (i.e., the “target signal”) may only be from −264 MHz to +264 MHz. The output of filter <b>901</b> is coupled to the input of decimator <b>902</b>. Decimator <b>902</b> reduces the sample rate of the signal by decimating the signal. For example, in one embodiment, a signal with a sample frequency of 1.056 Gsps is decimated down to a 528 Mega-sample per second (“Msps”) signal by removing every other sample. Decimation of the signal may cause folding of frequencies into the band of the target signal. Filter <b>901</b> reduces the effects of folding of blockers and noise into the frequency range of the signal of interest, thereby improving the signal-to-noise ratio (“SNR”) and reducing distortion caused by unwanted signal content.

p-0061The output of decimator <b>901</b> is coupled to Xcorr <b>905</b>. As mentioned above, during initialization Xcorr <b>905</b> performs cross-correlations on incoming data signals with a plurality of reference sequences and generates output signals for use in hop pattern detection, selection, and synchronization. In one embodiment, Xcorr <b>905</b> performs a cross-correlation of the input with a plurality of references and generates an output for each reference. The references may correspond to one of a plurality of hopping patterns, for example Xcorr <b>905</b> may include multiple cross-correlators, for example. An example cross-correlator that may be used is in embodiments of the present invention is disclosed in commonly-owned concurrently filed U.S. patent application Ser. No. 11/706,709 entitled Cross-Correlator Circuits and Methods, naming Alireza Mehrnia and Alireza Tarighat-Mehrabani as inventors, the disclosure of which is hereby incorporated herein by reference. An input of pattern selector <b>906</b> is coupled to the output of Xcorr <b>905</b>. An input of pattern selector <b>906</b> is also coupled to the output of threshold generator <b>904</b>.

p-0062Threshold generator <b>904</b> may receive the incoming digital data from the ADCs and generate a threshold for use in pattern selector <b>906</b> for determining if an output signal from Xcorr <b>905</b> indicates a match between a received symbol and a reference sequence. Threshold generator <b>904</b> may perform statistical calculations on the data such as root-mean-square and average calculations, for example. As described in more detail below, threshold generator <b>904</b> may operate in different modes at different times to generate different thresholds at different points in time during digital data processing. In one embodiment, threshold generator <b>904</b> may generate a high threshold and a low threshold (i.e., a first threshold that is greater than a second threshold). For example, threshold generator <b>904</b> may determine the RMS of incoming data and generate a threshold using a first gain during a first time period. At second time period, threshold generator <b>904</b> may generate a threshold using another gain. In one example embodiment, threshold generator <b>904</b> may initially calculate the RMS of a first plurality of symbols (e.g., the first 9 symbols) received at a first gain (e.g., Av=12), and then change to a second gain (e.g., Av=10) for the next plurality of symbols (e.g., the remaining symbols). The threshold may be an 11 bit unsigned integer, for example.

p-0063Pattern selector <b>906</b> receives the threshold from threshold generator <b>904</b> and the correlation results from Xcorr <b>905</b>. Pattern selector <b>906</b> may apply the correlation results against the threshold to detect peaks in the signals received from Xcorr <b>905</b>. For example, peak in one of the cross-correlations may be compared against the threshold. If the peak is greater than the threshold, then cross-correlation results are used for further processing. In one example embodiment described below, pattern selector <b>906</b> may provide both I and Q components of a cross-correlation result, a magnitude of the I and Q signals, and an indicator specifying which hopping pattern the results correspond to.

p-0064Timing processor <b>907</b> is coupled to the output of pattern selector <b>906</b>. Timing processor <b>907</b> programs a time base for the system using cross-correlation results. The time base may be implemented using a counter <b>908</b>, for example. In one embodiment, timing processor <b>907</b> determines an offset for the counter to synchronize received digital data (e.g., symbols) with the counter. The output of counter <b>908</b> may be coupled through delay <b>909</b> to triggering changes in the analog components through channel control <b>910</b> so that the receiving system can track frequency changes in the transmitting system.

p-0065<figref idrefs="DRAWINGS">FIG. 10</figref> is an example cross-correlator according to one embodiment of the present invention. Cross-correlator <b>1000</b> receives digital data on signal lines <b>1001</b>. The digital data may include both I and Q components of a signal, may be represented as 6-bit digital values, and may be received at a data rate of 528 MSPS. Cross-correlator (“Xcorr”) <b>1000</b> may include a plurality of cross-correlation stages <b>1010</b>, <b>1020</b>, and <b>1030</b> that each receives the input data stream (e.g., I/Q data). Data is received by each cross-correlation stage, and a cross-correlation with different reference values is carried out. The reference values may represent different hopping patterns, for example, and may be PN sequences. Each cross-correlation stage may include a different PN sequence. If received data is cross-correlated against different PN sequences, the stage generating a cross-correlation result above a threshold may be considered to be a match of the incoming data with the PN sequence. Thus, if a particular stage generates a cross-correlation result above a threshold, the hopping pattern may be ascertained.

p-0066Cross-correlation stage <b>1010</b> includes two cross-correlation circuit blocks <b>1011</b> and <b>1012</b> for processing I and Q components of a signal received as digital data. An example of the circuit is shown for block <b>1011</b>. Digital data is received in a storage element <b>1013</b>, which may be a shift register that receives incoming data by successively shifting in received data values. Each digital data value may be represented as 6 bits in the shift register, and the register may store 128 values, for example. Each digital value in storage elements <b>1013</b>A, <b>1013</b>B, <b>1013</b>C through <b>1013</b>N may be multiplied by corresponding reference values. For example, the digital value in storage element <b>1013</b>A may be multiplied by a first reference value of a first PN sequence using multiplier <b>1015</b>A, and the digital value in storage element <b>1013</b>B may be multiplied by a second reference value of the PN sequence using multiplier <b>1015</b>B. Similarly, the received digital values in storage element <b>1013</b> are multiplied against each of the stored reference values using other multipliers. The digital outputs of the multipliers are coupled to summing circuit <b>1016</b> and added. The output of summing circuit <b>1016</b> is coupled to a first input of magnitude calculator <b>1017</b>. The other input of magnitude calculator is coupled to the output the second cross-correlation block <b>1012</b>, which includes the substantially the same circuits at block <b>1011</b>. Magnitude calculator <b>1017</b> may square each Ixcorr and Qxcorr input, sum the results, and calculate the square root of the sum, for example, to generate a magnitude value.

p-0067Synchronization of a wireless system may include using the cross-correlation results to determine timing requirements of the receiving system. For example, as shown in <b>1010</b>A, if an incoming digital data stream correlates with the stored reference value <b>1014</b>, the output of cross-correlation stage <b>1010</b> will go up in value. If the same received data is cross-correlated with other reference values in stages (e.g., cross-correlation stages <b>1020</b> and <b>1030</b>), the outputs may not increase if the incoming data does not correlate with the stored reference values as shown at <b>1020</b>A and <b>1030</b>A. Ideally, incoming data will match one of the reference values (e.g., PN sequences) when a full symbol is received in storage elements <b>1013</b> and cross-correlated against the stored reference values. Accordingly, the period of time when the output of the cross-correlation stage increases also represents the period of time when a full symbol has been loaded into the cross-correlator storage element <b>1013</b>. The time when the full symbol has been loaded into the storage element <b>1013</b> also represents the time when the receiving wireless system has information about the boundaries between the received symbols. Therefore, cross-correlator stage outputs may be used in timing circuits for the receiving system so that the received system can process information without violating symbol boundaries.

p-0068<figref idrefs="DRAWINGS">FIG. 11</figref> is an example pattern selector <b>1100</b> according to one embodiment of the present invention. In this example, magnitude calculators are shown as part of the pattern selector to illustrate the operation of the system. Magnitude calculators <b>1101</b>-<b>1105</b> each include inputs coupled to receive Ixcorr and Qxcorr correlation results of the summing circuits from the cross-correlators. The outputs of the magnitude calculators <b>1101</b>-<b>1105</b> may be 12-bit unsigned digital values, for example, corresponding to the correlation of the input signal with a different PN sequence. The output of each magnitude calculator <b>1101</b>-<b>1105</b> is coupled to inputs of comparators <b>1111</b>-<b>1115</b>. Comparators <b>1111</b>-<b>1115</b> also have inputs coupled to receive a threshold on lines <b>1150</b>. The threshold may also be a 12-bit unsigned digital value, for example. In this example, comparators <b>1111</b>-<b>1115</b> perform a digital subtraction operation. Accordingly the inputs of the comparators coupled to the magnitude calculators are labeled with a minus sign, “−”, and the inputs of the comparators coupled to receive the threshold value are labeled with a plus sign, “+”. The output of the comparators <b>1111</b>-<b>1115</b> may be the sign bit of the result, for example. Thus, if the magnitude of any of the cross-correlation results is greater than the threshold, the sign bit will transition from zero to one (i.e., in this example a positive output will result in a ‘0’ sign bit and a negative output will result in a ‘1’ sign bit). Accordingly, comparators <b>1111</b>-<b>1115</b> may be used to determine the hopping pattern of the incoming signal. The following table illustrates hopping patterns that may be selected in an exampe system based on the correlation results with different PN sequences:

p-0069<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="56pt" align="center" /><colspec colname="2" colwidth="161pt" align="left" /><thead><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row><row><entry>PN Sequence</entry><entry>Hopping Pattern Frequencies (1 = f1, 2 = f2, 3 = f3)</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>1</entry><entry>{1, 2, 3, 1, 2, 3, 1, 2, 3, . . . }</entry></row><row><entry>2</entry><entry>{1, 3, 2, 1, 3, 2, 1, 3, 2, . . . }</entry></row><row><entry>3</entry><entry>{1, 1, 2, 2, 3, 3, 1, 1, 2, 2, . . . }</entry></row><row><entry>4</entry><entry>{1, 1, 3, 3, 2, 2, 1, 1, 3, 3, . . . }</entry></row><row><entry>5</entry><entry>{1, 2, 1, 2, 1, 2, 1, 2 . . . }</entry></row><row><entry>6</entry><entry>{1, 3, 1, 3, 1, 3, 1, 3. . . }</entry></row><row><entry>7</entry><entry>{1, 1, 1, 1, . . . }</entry></row><row><entry>8</entry><entry>{2, 2, 2, 2, . . . }</entry></row><row><entry>7</entry><entry>{3, 3, 3, 3, . . . }</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

p-0070Therefore, in this example outputs of digital comparators are used to indicate which PN sequence has a correlation result above the threshold, and thereby signal the detection of a particular hopping pattern. The outputs of comparators <b>1111</b>-<b>1115</b> may also be used to store the relevant cross-correlation results. For example, the outputs of comparators <b>1111</b>-<b>1115</b> are coupled to the input of a selection circuit <b>1120</b>, such as a multiplexer, so that if the output of a comparator is high, the correlation results (e.g., Ixcorr, Qxcorr, and the magnitude calculation of Ixcorr and Qxcorr) may be loaded into a storage element such as register <b>1121</b>. Accordingly, the output of pattern selector <b>1100</b> may include a signal (e.g., on a particular line) indicating which hopping pattern has been selected and cross-correlation results.

p-0071<figref idrefs="DRAWINGS">FIG. 12A</figref> is an illustrative example of the methods implemented by a timing processor <b>1200</b> according to one embodiment of the present invention. The timing processor in this example may also be referred to as a peak position processor because cross-correlation peaks from the cross-correlator are processed to set the timing of the system to be synchronous with received symbols. In this example, processor <b>1200</b> receives a plurality of signal lines <b>1201</b>. A positive signal on one of the signal lines <b>1201</b> represents the detected reception of a symbol, and may further correspond to the detection of a particular PN sequence. Because the signal lines <b>1201</b> may indicate a particular hopping pattern, these signal lines may be referred to as “pattern indicator” lines. Signal lines <b>1201</b> are coupled to the inputs of an OR gate <b>1207</b>. The output of OR gate <b>1207</b> is coupled to a counter <b>1210</b> for generating a reference frequency. In this example, counter <b>1210</b> is an 8 bit modulo-165 free running counter triggered by a system clock (not shown). Thus, once triggered by the detection of a received symbol, counter <b>1210</b> will count up to (or down from) 165, generate an output on line <b>1208</b>, and then start a new count. Accordingly, for a symbol having total of 165 samples, the symbol period is equal to the period of the counter if the sample rate is the same as the clock frequency driving the counter, for example. Thus, counter <b>1210</b> may be referred to as a time base counter because it establishes a time base having the same period as the period of received symbols. However, the boundaries of the received symbols and the counter may not be coincident.

p-0072Hopping control logic <b>1211</b> includes a counter <b>1213</b> for implementing a delay. In this example counter <b>1213</b> is a down counter, which may be triggered when counter <b>1210</b> has a value of zero (e.g., during initialization) or under other conditions described below (e.g., normal mode). It is to be understood that an up or down counter could be used for counter <b>1213</b>. When a first peak is detected (e.g., by a transition from ‘0’ to ‘1’ on one of signal lines <b>1201</b>), control logic and reset controller <b>1250</b> may trigger down counter <b>1213</b> at the same time counter <b>1210</b> is started. Down counter <b>1213</b> may be programmed to a predetermined delay stored in register <b>1212</b>. The delay represents the amount of time after a peak has been detected that the system should wait before issuing a hop command. A hopping state machine <b>1214</b> is used to issue hop commands that cause a frequency synthesizer (not shown) to change from one frequency to another and thereby change the down conversion frequency for receiving incoming modulated symbols. Hopping state machine <b>1214</b> is coupled to receive the pattern indicator lines <b>1201</b>. Pattern indicator lines <b>1201</b> program hopping state machine to implement different hopping patterns (e.g., if pattern #1 indicator line is ‘1’ and the other indicator lines are ‘0’, then hopping state machine may implement a {1, 2, 3, 1, 2, 3, . . . } hopping pattern). When down counter <b>1213</b> reaches the end of the count (equal to the programmed delay), it issues a signal to hopping state machine <b>1214</b>, which in turn generates channel control signals that cause a programmable frequency synthesizer to change from a first frequency in the hopping pattern to a second frequency in the hopping pattern. For example, the output of hopping state machine <b>1214</b> may be a 4-bit signal for programming a frequency synthesizer to generate 12 frequencies.

p-0073As mentioned above, the cross-correlator may generate correlation results for each received symbol having more than one magnitude value above a threshold. These clusters of peaks may be analyzed by processor <b>1200</b> to determine a time for issuing hop commands to a frequency synthesizer. For each received symbol, the correlation results generated are analyzed, and one result is selected and stored in memory. Each correlation result will be received by processor <b>1200</b> at some moment in time, which can be recorded as the value of time base counter <b>1210</b> at the moment a particular correlation result is detected. The time of the selected correlation result may also be stored in a memory. This process may be repeated for a plurality of symbols and corresponding clusters. After a plurality of clusters have been received, and selected correlation results and associated time values stored in memory, the clusters can be used to determine an offset value for triggering delay counter <b>1213</b>. For example, in one embodiment, the plurality of time values are used to generate a histogram that represents the number of times a selected result, out of a cluster of correlation results, was received at particular point in time of the time base counter <b>1210</b>. For example, analysis of clusters may result in the selected result occurring three times when counter <b>1210</b> has a value of 12 (i.e., for three different clusters). Similarly, no correlation results may have been selected when counter <b>1210</b> had a value of 13 or 14, 2 correlation results may have been selected when counter <b>1210</b> had a value of 15, 5 correlation results may have been selected when counter <b>1210</b> had a value of 16, and 1 correlation result may have been selected when counter <b>1210</b> had a value of 17. The system may select, for example, an offset value of 16 and compare this offset value against the value in time base counter <b>1210</b> to systematically start the down counter <b>1213</b> as symbols are received at later points in time.

p-0074In this example, processor <b>1200</b> receives the Qxcorr, Ixcorr, and magnitude calculation of the detected correlation result (See <figref idrefs="DRAWINGS">FIG. 10</figref>) on signal lines <b>1202</b>, <b>1203</b>, and <b>1205</b>, respectively. The threshold value is received on lines <b>1204</b>. The first set of correlation results received by processor <b>1200</b> is stored in a cluster memory bank <b>1224</b>. For example, the magnitude result may be stored in a first memory location A, the Ixcorr result may be stored in a second memory location B, the Qxcorr result may be stored in a third memory location C, and the value of the time base counter <b>1210</b> on the clock cycle when the results are received (e.g., zero for the first set of results) may be stored in a fourth memory location D. These correlation results shall be referred to hereafter as “peaks” because they represent correlation results having corresponding magnitudes above a threshold value.

p-0075The first detected peak is stored in memory <b>1224</b>. However, for any given symbol, subsequent peaks may be detected at the output of the cross-correlator. <figref idrefs="DRAWINGS">FIG. 12B</figref> illustrates the output of a cross-correlation during reception of one example symbol. As illustrated in <figref idrefs="DRAWINGS">FIG. 12B</figref>, there may be a plurality of peaks A-H (i.e., a cluster of peaks or “cluster”) above the threshold value for each symbol. In one embodiment, an offset value for triggering a hopping operation may be determined by analyzing the received peaks above the threshold for a received symbol, and selecting one of the symbols corresponding peaks as a representative peak for the cluster. This process may be repeated for a plurality of symbols, and an analysis of the results may be used to generate a final offset value to be used to trigger hopping operations.

p-0076In this example, processor <b>1200</b> includes two comparators <b>1221</b> and <b>1222</b>. Comparator <b>1221</b> includes an input coupled to receive a threshold value and a magnitude value. Comparator <b>1222</b> includes an input coupled to receive a magnitude value. The second input to comparator <b>1222</b> is coupled to the output of a digital multiplier <b>1225</b>. The input of multiplier <b>1225</b> is coupled to the magnitude value for the previously received peak stored in memory <b>1224</b>. Thus, if a subsequently received peak for a symbol is above a threshold and the magnitude of the subsequently received peak is greater in value than the previously stored peak multiplied by some factor, then both the outputs of comparators <b>1221</b> and <b>1222</b> will be ‘1’, and correlation results for the subsequent peak will be stored in memory <b>1224</b>—overwriting the correlation results for the previously stored peak. Comparators <b>1221</b> and. <b>1222</b> may implement digital subtraction as described above, for example, and generate a sign bit, which is received by an AND gate <b>1223</b> to active a write enable.

p-0077Thus, one example algorithm for analyzing correlation results of received symbols to generate an offset value is illustrated by <figref idrefs="DRAWINGS">FIGS. 12A and 12B</figref>. For example, if a symbol generates the cluster of results illustrated in <figref idrefs="DRAWINGS">FIG. 12B</figref>, the correlation results for peak A will be stored in memory <b>1224</b>. The “timer value” of counter <b>1210</b> stored for this result is ‘0’. When counter <b>1210</b> is ‘1’, the results are below the threshold and therefore ignored. When counter <b>1210</b> is ‘2’, a second peak (peak B) above the threshold is detected. Peak A and peak B are compared. If peak B is larger than peak A by a factor (e.g., 1.25), then the results for peak B are stored in memory <b>1224</b>, overwriting the peak A's results. In this case, the timer value stored in memory for peak B is ‘2’. Peaks C and D are similarly processed, but the results for these peaks are not stored because the peaks are not larger than peak B by a predetermined factor. However, the results for peak E are greater than peak B by a factor (e.g., 1.25). Thus, the results for peak E are stored in memory. The stored timer value for peak E is ‘10’.

p-0078As subsequent symbols are received, the memory address may be incremented to new locations. Accordingly, subsequent correlation results for a subsequent symbol may not overwrite the final result for a previous symbol. Thus, as each symbol is received, the cross correlation results are analyzed, and the results for one of the peaks are selected and stored as the representative peak for the cluster. In one embodiment, 15 symbols may be received to generate 15 clusters, which are analyzed to generate 15 representative peaks with corresponding correlation results and timer values. Some of the representative peaks may have different timer values, but some may have the same timer value. At the end of each cluster, the timer value may be used to increment memory locations in position memory bank <b>1227</b> to create a histogram of the results. The histogram represents the number of times a representative peak in each cluster (corresponding to different received symbols).occurred at a particular value of the time base counter <b>1210</b>.

p-0079Control logic and reset controller <b>1250</b> is coupled to the pattern indicator lines <b>1250</b> for triggering down counter <b>1213</b> each time a representative peak in a cluster of peaks is written into memory <b>1224</b>. For example, a first peak in a cluster may trigger controller <b>1250</b>, and thereby also trigger down counter <b>1213</b>. If a subsequent peak in the cluster is determined to be the representative peak, then down counter <b>1213</b> may be restarted at the time the selected peak is received. The delay from down counter <b>1213</b> to a hopping command will thus be from the representative peak in the cluster. Accordingly, control and reset controller <b>1250</b> includes an input coupled to pattern indicator lines <b>1201</b> and another input coupled to the output of AND gate <b>1223</b>. As mentioned above, AND gate <b>1223</b> generates an output when a peak is selected for storage in memory <b>1224</b>. Thus, if control and reset logic <b>1250</b> detects a peak on lines <b>1201</b> and the detected peak is selected for storage in memory <b>1224</b> as a representative peak of the cluster, then controller <b>1250</b> signals hopping control logic <b>1211</b> to restart down counter <b>1213</b>.

p-0080<figref idrefs="DRAWINGS">FIG. 13A</figref> illustrates an example method of processing correlation results according to one embodiment of the present invention. At <b>1301</b>, cluster peak results are determined and stored. For example, correlation results may be compared to a threshold to determine if the results are peaks, and the received peaks may be compared to previous peaks to determine if they should be stored. The time value for the peak may also be stored. The time value may be the value of a time base counter at the time the peak was received. At <b>1302</b>, a memory cell value corresponding to the time value of the peak result may be incremented by one. <figref idrefs="DRAWINGS">FIG. 13B</figref> illustrates an example histogram of timer values according to one embodiment of the present invention. This figure illustrates that a memory may be used to represent points in time. The memory location with address ‘−32’ may represent a point in time earlier than the memory cell with address ‘+31’, for example. The center address of the memory (address 0) may represent the point in time where the time base counter is zero. Thus, if three stored representative peaks in three different clusters had corresponding timer values of zero, then the value of memory location 0 may be may be incremented three times to a final value of 3. Similarly, stored representative peaks that occurred at times before the time base counter had a value of zero would have addresses in the range of −32 to −1, and stored representative peaks that occurred at times after the time base counter had a value of zero would have addresses in the range of +1 to +31, for example. Accordingly, the values in each memory cell in <figref idrefs="DRAWINGS">FIG. 13B</figref> represent the number of times a representative peak occurred at a particular value of the time base counter.

p-0081Referring again to <figref idrefs="DRAWINGS">FIG. 13A</figref>, if additional clusters to be analyzed are received, the process may store more cluster peak results and continue incrementing memory cell values to record the time value of the free running counter associated with each peak. When there are no further clusters to be analyzed at <b>1310</b>, the timing of the system is set based on the values stored in the memory cells. A variety of algorithms could be used to determine an offset based on the values stored in memory. For example, an algorithm could use the counter value corresponding to earliest peak detected, the value with the most representative peaks, or other algorithms that consider the distribution of representative peaks over time represented in position memory <b>1227</b> or the particular correlation results stored in cluster memory <b>1224</b>, or combinations of both.

p-0082Referring again to <figref idrefs="DRAWINGS">FIG. 12A</figref>, cluster memory <b>1224</b> is addressed by cluster memory address controller <b>1252</b>, which stores a cluster index (or symbol index) so that results from clusters for different symbols are stored in different memory locations and do not over-write the previous results for a previous symbol's corresponding cluster. Cluster address controller <b>1252</b> is controlled by cluster window controller <b>1251</b>.

p-0083Cluster window controller <b>1251</b> controls the time period during each cycle of timebase counter <b>1210</b> when incoming peaks are analyzed. Peaks at the cross-correlator output may be analyzed starting with the first received peak for each symbol, and continuing for a time period. The time period during which detected peaks are analyzed by processor <b>1200</b> may be referred to as the “cluster window.” For example, when timebase counter <b>1210</b> reaches zero, or when a peak is received on indicator lines <b>1201</b>, whichever occurs first, another count may be initiated by cluster window controller <b>1251</b> (e.g., for 20 cycles of the system clock—“20 samples”) during which a plurality of incoming peaks (i.e., peak clusters) are analyzed. At the end of the time period, the final selected peak is stored in memory <b>1224</b> and used to increment one of the memory cells in position memory <b>1227</b>. Additionally, cluster window controller <b>1251</b> may increment cluster address controller to the next memory location in memory <b>1224</b> for storing information about subsequent peak clusters generated by subsequently received symbols.

p-0084Address mapping logic <b>1226</b> includes an input coupled to receive the final timer values for each cluster in cluster memory <b>1224</b> and another input coupled to time base counter <b>1210</b>. At the end of each cycle of counter <b>1210</b>, information for one representative peak out of a cluster of detected peaks will be stored in cluster memory <b>1224</b>. The timer value, which represents the value of time base counter <b>1210</b> at the moment the stored peak was detected, is used to select a memory location in position memory <b>1227</b> to increment. In this example, the stored timer value is used as an address input to address mapping logic <b>1226</b>. Address mapping logic <b>1226</b> specifies the address in position memory <b>1227</b> to be incremented by incrementor <b>1229</b>. Address mapping logic <b>1226</b> will use a new stored timer value once every counter period (e.g., 165 samples). Counter <b>1210</b> may configure address mapping logic <b>1226</b> every cycle, for example.

p-0085Block decision boundary <b>1228</b> may store an offset value representing the point in time when the system should hop between synchronizer frequencies. Block decision boundary <b>1228</b> may include logic responsive to cluster address controller <b>1252</b>. When a cluster index value in address controller <b>1252</b> reaches a final address signaling that the last cluster to be analyzed has been received (e.g., 15 symbols and corresponding clusters have been received), the block boundary logic <b>1228</b> may implement an algorithm for determining which position in position memory <b>1227</b> is to be used as the final block boundary offset value. Hopping control logic <b>1211</b> may receive as inputs the stored offset value in block decision boundary <b>1228</b> and the changing values of time base counter <b>1210</b>. After the block decision boundary offset value has been determined (e.g., based on the information in memory <b>1227</b> as described above), down counter <b>1213</b> may be initiated on each cycle of counter <b>1210</b> when the value of counter <b>1210</b> corresponds to the offset value stored in block decision boundary <b>1228</b>. In one embodiment, block decision boundary <b>1228</b> stores a sequence of bits that will match a particular sequence of bits in counter <b>1210</b> representing the point in time in each cycle of counter <b>1210</b> when the system should start down counter <b>1213</b>. Hopping control logic <b>1211</b> receives the changing values of timebase counter <b>1210</b> and the offset value from block decision boundary <b>1228</b>, and performs a comparison of the two values. In this example, down counter <b>1213</b> will be started when the value of counter <b>1210</b> matches the offset value in block decision boundary <b>1228</b>.

p-0086In the example shown in <figref idrefs="DRAWINGS">FIG. 12A</figref>, when the final cluster has been analyzed and the appropriate offset value has been stored in the block boundary <b>1228</b>, the remaining hopping commands become systematically triggered when the free running timebase counter <b>1210</b> hits the value specified by block boundary <b>1228</b>. For instance, cluster address controller <b>1252</b> includes an output coupled to hopping control logic <b>1211</b> for signaling the end of processing. When the cluster index in address controller <b>1252</b> increments to a particular value representing the last cluster to be analyzed, the cluster index may also be used by logic <b>1211</b> to start using the final offset value in block boundary <b>1228</b>, rather than signals from controller <b>1250</b>, for starting down counter <b>1213</b> for controlling system hopping.

p-0087<figref idrefs="DRAWINGS">FIGS. 14A-B</figref> illustrates threshold generation according to one embodiment of the present invention. In one embodiment, thresholds may be generated based on the incoming symbols. For example, an analog signal containing symbols may be digitized in an analog-to-digital converter to generate a digital data stream. The digital data stream may represent each symbol as 165 samples at a frequency of 1.056 GHz, for example. Embodiments of the present invention may generate thresholds based on characteristics of the received digital data. For example, the system may determine characteristics of the received signal such as RMS to generate a threshold level. In one example embodiment, statistical calculations are performed on the received digital data to generate the threshold. As illustrated in <figref idrefs="DRAWINGS">FIG. 14</figref>, the system may include a statistical calculator <b>1401</b> for performing statistical analysis on incoming data. For example, the system may perform a root-mean-square operation on incoming data.

p-0088In one embodiment, the system may use different thresholds at different times. For example, the output of statistical calculator may be amplified by multipliers <b>1402</b> or <b>1403</b>. The system may count the number of symbols received, may use a first gain <b>1402</b> for a first number of received symbols to generate a first threshold, and use a second gain for a second number of received symbols to generate a second threshold. The system may include a selection circuit <b>1404</b> (e.g., a multiplexer) that receives the two thresholds and selects one of the thresholds based on the number of symbols received. The number of symbols received may be stored as a digital index value, for example (“symbol number”).

p-0089As illustrated in the example of <figref idrefs="DRAWINGS">FIG. 14B</figref>, I and Q digital data streams may be received at the input of an RMS calculator <b>1411</b>. The output RMS result may be amplified by a gain of 12 (“×12”) for the first nine (9) symbols for generating a first threshold value. The RMS result may be amplified by a gain of 10 (“×10”) on receiving the tenth symbol and subsequent symbols for generating a second threshold value. Selection of threshold values may be made by selector <b>1414</b>, for example.

p-0090The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. The features and functions described above may be embodied in various forms, such as semiconductor circuits implemented using application specific integrated circuits or programmable logic, or as software such Verilog, VHDL, or other run time logic (RTL) encoding formats. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims.