US7693003B2

Semiconductor package

Summary by NHIP

Multi-Chip Package Routing

The semiconductor package connects multiple chips by selectively enabling specific input/output pads based on decoded coding information. The number of decoding pads per chip scales logarithmically with the total chip count, following the formula log 2 n for n chips.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A semiconductor package facilitates package connection due to different locations of input/output pads in each interlayer die depending on coding information in a multi-chip package. The semiconductor package includes many chips. Each of the chips includes: input/output pads configured to input and output data having a given bandwidth; a decoding pad configured to receive coding information; and a code control unit configured to decode the coding information and to enable an input/output pad positioned at a specific location among the input/output pads according to the decoding result.

US7693003B2, drawing sheet 1 — Sheet 1 of 12

Term

1.5 yearsleft in the term

Expires 2 April 2028, including 281 days of term adjustment.

13 claims: 1 independent, 12 dependent

1
Broadest claimClaim Score 65, broad(NHIP)A semiconductor package including a plurality of chips, wherein each of the chips include:input/output pads configured to input and output data at a given bandwidth;a decoding pad configured to receive coding information;and a code control unit configured to decode the coding information to obtain a decoding result, and to enable an input/output pad positioned at a specific location among the input/output pads according to the decoding result, wherein a location of an enabled input/output pad of one chip is different from a location of an enabled input/output pad of another chip.

59 paragraphs in 5 sections, as filed

0001The present application claims the benefit of priority of Korean patent application number 10-2007-12123, filed on Feb. 6, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND

0002The present invention generally relates to a semiconductor package, and more specifically, to a technology of differentiating locations of input/output pads in an interlayer die depending on coding information in a multi-chip package to facilitate package connection.

0003Due to high performance of electronic devices, various techniques for providing semiconductor modules of high capacity have been developed. In order to enhance the capacity of semiconductor modules, high integration of devices, stack-structured packaging methods, and methods for reducing the package size so as to mount more packages on a printing circuit board have been provided. As a result, various kinds of packages, such as Thin Small Outline Package (TSOP), Fine Pitch Ball Grid Array (FBGA), and Multi Chip Package (MCP), have been developed.

0004Also, due to speed-up and scale-down of the multimedia system, the component parts thereof become smaller. For example, semiconductor integrated circuits (IC) become smaller through reduction of memory chips, and several chips are mounted in one package to increase board packing efficiency.

0005MCP refers to a package including several chips each having a different function in that package. Each chip of the MCP is attached to one substrate, and connected electrically with each other to perform a function. The multi-chip packaged semiconductor device can include a plurality of semiconductor devices in one package, thereby reducing the size of the system.

SUMMARY

0006Various embodiments consistent with the present invention are directed to enabling input/output pads positioned at different locations in each die depending on coding information in the same bandwidth in a stack or multi-chip package to facilitate package connection.

0007A semiconductor package includes a plurality of chips. Each of the plurality of chips includes input/output pads configured to input and output data having a given bandwidth, a decoding pad configured to receive coding information, and a code control unit configured to decode the coding information and to enable an input/output pad positioned at a specific location among the input/output pads according to the decoding result.

BRIEF DESCRIPTION OF THE DRAWINGS

0008<figref idref="DRAWINGS">FIGS. 1</figref>a through 1c are diagrams illustrating the connection structure of input/output pads in a conventional semiconductor package.

0009<figref idref="DRAWINGS">FIGS. 2</figref>a through 2c are diagrams illustrating the connection structure of input/output pads in a semiconductor package (×4) according to an embodiment consistent with the present invention.

0010<figref idref="DRAWINGS">FIGS. 3</figref>a through 3c are diagrams illustrating the connection structure of input/output pads in a semiconductor package (×8) according to an embodiment consistent with the present invention.

0011<figref idref="DRAWINGS">FIGS. 4</figref>a through 4c are diagrams illustrating the connection structure of input/output pads in a semiconductor package (×16) according to an embodiment consistent with the present invention.

0012<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating a code control unit in a semiconductor package (×4) according to an embodiment consistent with the present invention.

0013<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a code control unit in a semiconductor package (×8) according to an embodiment consistent with the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

0014The present invention will be described in detail with reference to the accompanying drawings.

0015<figref idref="DRAWINGS">FIGS. 1</figref>a through 1c illustrate a connection structure of input/output pads in a conventional semiconductor package.

0016<figref idref="DRAWINGS">FIG. 1</figref>a shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×4. A semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>a has a double layered chip (2 and 4) structure. Each of chips 2 and 4 includes an input/output pad 10 for inputting and outputting data. Input/output pad 10 is electrically connected to a bond finger 6 outside of chips 2 and 4 through a metal wire (not shown).

0017<figref idref="DRAWINGS">FIG. 1</figref>b shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×8. A semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>b has a double layered chip (2 and 4) structure. Each of chips 2 and 4 includes an input/output pad 10 for inputting and outputting data.

0018<figref idref="DRAWINGS">FIG. 1</figref>c shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×16. A semiconductor device of <figref idref="DRAWINGS">FIG. 1</figref>c has a double layered chip (2 and 4) structure. Each of chips 2 and 4 includes an input/output pad 10 for inputting and outputting data.

0019In a conventional multi-chip package, input/output pads 10 positioned at the same locations A, B, and C of first chip 2 and second chip 4 are enabled at the same time, so that the input/output operation of data is performed. For example, in first chip 2 and second chip 4, the data bandwidth of which is ×4, input/output pads 10 positioned at the same location A are enabled so as to input and output data DQ12˜DQ15. As a result, when the bandwidth of data is determined in the stack or multi-chip package, it is not easy to interconnect input/output pad 10 to bond finger 6.

0020<figref idref="DRAWINGS">FIGS. 2</figref>a through 2c illustrate the connection structure of input/output pads in a semiconductor package (×4) according to an embodiment consistent with the present invention.

0021<figref idref="DRAWINGS">FIG. 2</figref>a shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×4. A semiconductor device of <figref idref="DRAWINGS">FIG. 2</figref>a has a double layered chip 20 structure. Each of chips 20 includes an input/output pad 22 for inputting and outputting data. Input/output pad 22 is electrically connected to a bond finger 24 through a metal wire (not shown).

0022<figref idref="DRAWINGS">FIG. 2</figref>b shows a multi-chip package having a four-layered chip structure, the data bandwidth of which is ×4. A semiconductor device of <figref idref="DRAWINGS">FIG. 2</figref>b has a four-layered chip 20 structure. Each of chips 20 includes an input/output pad 22 for inputting and outputting data.

0023<figref idref="DRAWINGS">FIG. 2</figref>c shows a multi-chip package having an n-layered chip structure, the data bandwidth of which is ×4. A semiconductor device of <figref idref="DRAWINGS">FIG. 2</figref>c has an n-layered chip 20 structure. Each of chips 20 includes an input/output pad 22 for inputting and outputting data.

0024Each chip 20 includes a code control unit 26 for enabling input/output pads 22 positioned at different locations in each die depending on coding information. Each chip 20 includes decoding pads 1a˜na, 1m˜nm for providing coding information to code control unit 26.

0025<figref idref="DRAWINGS">FIGS. 3</figref>a through 3c are diagrams illustrating the connection structure of input/output pads in a semiconductor package (×8) according to an embodiment consistent with the present invention.

0026<figref idref="DRAWINGS">FIG. 3</figref>a shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×8. A semiconductor device of <figref idref="DRAWINGS">FIG. 3</figref>a has a double layered chip 30 structure. Each of chips 30 includes an input/output pad 32 for inputting and outputting data. Input/output pad 32 is electrically connected to a bond finger 34 through a metal wire (not shown).

0027<figref idref="DRAWINGS">FIG. 3</figref>b shows a multi-chip package having a four-layered chip structure, the data bandwidth of which is ×8. A semiconductor device of <figref idref="DRAWINGS">FIG. 3</figref>b has a four-layered chip 30 structure. Each of chips 30 includes an input/output pad 32 for inputting and outputting data.

0028<figref idref="DRAWINGS">FIG. 3</figref>c shows a multi-chip package having an n-layered chip structure, the data bandwidth of which is ×8. A semiconductor device of <figref idref="DRAWINGS">FIG. 3</figref>c has an n-layered chip 30 structure. Each of chips 30 includes an input/output pad 32 for inputting and outputting data.

0029Each chip 30 includes a code control unit 36 for enabling input/output pads 32 positioned at different locations in each die depending on coding information. Each chip 30 includes decoding pads 1a˜na, 1m˜nm for providing coding information to code control unit 36.

0030<figref idref="DRAWINGS">FIGS. 4</figref>a through 4c illustrates the connection structure of input/output pads in a semiconductor package (×16) according to an embodiment consistent with the present invention.

0031<figref idref="DRAWINGS">FIG. 4</figref>a shows a multi-chip package having a two-layered chip structure, the data bandwidth of which is ×16. A semiconductor device of <figref idref="DRAWINGS">FIG. 4</figref>a has a double layered chip 40 structure. Each of chips 40 includes an input/output pad 42 for inputting and outputting data. Input/output pad 42 is electrically connected to a bond finger 44 through a metal wire (not shown).

0032<figref idref="DRAWINGS">FIG. 4</figref>b shows a multi-chip package having a four-layered chip structure, the data bandwidth of which is ×16. A semiconductor device of <figref idref="DRAWINGS">FIG. 4</figref>b has a four-layered chip 40 structure. Each of chips 40 includes an input/output pad 42 for inputting and outputting data.

0033<figref idref="DRAWINGS">FIG. 4</figref>c shows a multi-chip package having an n-layered chip structure, the data bandwidth of which is ×16. A semiconductor device of <figref idref="DRAWINGS">FIG. 4</figref>c has an n-layered chip 40 structure. Each of chips 40 includes an input/output pad 42 for inputting and outputting data.

0034Each chip 40 includes a code control unit 46 for enabling input/output pads 42 positioned at different locations in each die depending on coding information. Each chip 40 includes decoding pads 1a˜na, 1m˜nm for providing coding information to code control unit 46.

0035In this embodiment, a multi-chip package, where a plurality of chips are stacked, includes decoding pads 1a˜na, 1b˜nb, . . . , 1m˜nm for decoding code in each die when input/output pads 22, 32, 42 are connected. As a result, input/output pads 22, 32, 42 positioned at different locations in each die are enabled depending on decoding information of the decoding pads 1a˜na, 1b˜nb, . . . , 1m˜nm in the multi-chip package having the same data bandwidth to facilitate package interconnection.

0036<figref idref="DRAWINGS">FIG. 5</figref> illustrates code control unit 26 in the semiconductor package (×4) according to an embodiment consistent with the present invention.

0037Code control unit 26 includes a decoder 27, input/output control units 28A˜28D, and input/output driving units 29A˜29D. Decoder 27 decodes input signals from the decoding pads (1a and 1b). Input/output control units 28A˜28D are selectively activated in response to a decoding signal applied from decoder 27 so as to input and output signals of global input/output lines GIO selectively.

0038In other words, one of input/output control units 28A˜28D, which is selected in response to an output signal from decoder 27, inputs and outputs data of global input/output line GIO into input/output pad 22. Input/output driving units 29A˜29D selectively drive data DQ0˜DQ15 in response to control signals of input/output control units 28A˜28D, so as to input and output the data through input/output pad 22.

0039When the number of chips is two, the number of decoding pads 1a in one chip is one. When the number of chips is four, the number of decoding pads 1a, 1b in one chip is two. When the number of chips is n, the number of decoding pads 1a˜1m in one chip is log2n, where n is a natural number.

0040For example, when two chips of data bandwidth ×4 is deposited as shown in <figref idref="DRAWINGS">FIG. 2</figref>a, output signals of decoding pads 1a and 2a are used as code information. That is, when decoding pad 1a positioned in the lower chip is ‘high,’ decoding pad 2a positioned in the upper chip becomes ‘low.’

0041In the lower chip, input/output pad 22 located at (D) is enabled to input/output data DQ8˜DQ11. In the upper chip, input/output pad 22 located at (E) is enabled to input/output data DQ12˜DQ15. As a result, input/output pads 22 located at different regions (D) and (E) are enabled to facilitate interconnection between input/output pad 22 and bond finger 24.

0042When four chips of data bandwidth ×4 are disposed as shown in <figref idref="DRAWINGS">FIG. 2</figref>b, two decoding pads (1a, 1b) (2a, 2b) (3a, 3b) (4a, 4c) in each chip 20 utilize output signals of code control unit 26 as code information.

0043When decoding pads (1a, 1b) are ‘low’ in the first chip, data are outputted through corresponding input/output pad 22. When decoding pad 2a is ‘high’ and decoding pad 2b is ‘low’ in the second chip, data is inputted and outputted through the corresponding input/output pad 22. When decoding pad 3a is ‘low’ and decoding pad 3b is ‘high’ in the third chip, data is inputted and outputted through the corresponding input/output pad 22. When decoding pads (4a, 4b) are ‘high’ in the fourth chip, data is inputted and outputted through the corresponding input/output pad 22.

0044When decoding pads (1a, 1b) are ‘low’, input/output control unit 28A and input/output driving unit 29A are activated in the first chip located at the bottom of chips 20 of the multi-chip package. As a result, data DQ0˜DQ3 applied from global input/output line GIO are inputted and outputted through the corresponding input/output pad 22. Reset input/output control units 28B˜28D of the first chip are disabled so that data DQ4˜DQ15 are not inputted and outputted.

0045When decoding pad 2a is ‘high’ and decoding pad 2b is ‘low,’ input/output control unit 28B and input/output driving unit 29B are activated in the second chip of chips 20 of the multi-chip package. As a result, data DQ4˜DQ7 applied from global input/output line GIO are inputted and outputted through the corresponding input/output pad 22. Reset input/output control units 28A, 28C, 28D of the second chip are disabled so that data DQ0˜DQ3, DQ8˜DQ15 are not inputted and outputted.

0046When decoding pad 3a is ‘low’ the decoding pad 3b is ‘high,’ input/output control unit 28C and input/output driving unit 29C are activated in the third chip of chips 20 of the multi-chip package. As a result, data DQ8˜DQ11 applied from global input/output line GIO are inputted and outputted through the corresponding input/output pad 22. Reset input/output control units 28A, 28B, 28D of the third chip are disabled so that data DQ0˜DQ7, DQ12˜DQ15 are not inputted and outputted.

0047When decoding pads (4a, 4b) are ‘high,’ input/output control unit 28D and input/output driving unit 29D are activated in the fourth chip of chips 20 of the multi-chip package. As a result, data DQ12˜DQ15 applied from global input/output line GIO are inputted and outputted through the corresponding input/output pad 22. Reset input/output control units 28A˜28C of the fourth chip are disabled so that data DQ0˜DQ11 are not inputted and outputted.

0048Although decoder 27, input/output control units 28A˜28D, and input/output driving units 29A˜29D are not shown in <figref idref="DRAWINGS">FIG. 5</figref>, decoder 27, input/output control units 28A˜28D, and input/output driving units 29A˜29D can be easily appreciated by a person having ordinary skill in the art.

0049<figref idref="DRAWINGS">FIG. 6</figref> illustrates code control unit 36 in a semiconductor package (×8) according to an embodiment consistent with the present invention.

0050Code control unit 36 includes a decoder 37, input/output control units 38A˜38D, and input/output driving units 39A˜39D. Decoder 37 decodes input signals from decoding pads (1a, 1b). Input/output control units 38A˜38D are selectively activated in response to a decoding signal applied from decoder 37, so as to input and output signals of global input/output lines GIO selectively. In other words, one of input/output control units 38A˜38D, which is selected in response to an output signal from decoder 37, inputs and outputs data of global input/output line GIO into input/output pad 32. Input/output driving units 39A˜39D selectively drive data DQ0˜DQ31 in response to control signals of input/output control units 38A˜38D, so as to input and output data through input/output pad 32.

0051When decoding pads (1a, 1b) are ‘low,’ input/output control unit 38A and input/output driving unit 39A are activated in the first chip located at the bottom of chips 30 of the multi-chip package. As a result, data DQ0˜DQ7 applied from global input/output line GIO are inputted and outputted through corresponding input/output pad 32. Reset input/output control units 38B˜38D of the first chip are disabled so that data DQ8˜DQ31 are not inputted and outputted.

0052When decoding pad 2a is ‘high’ and decoding pad 2b is ‘low,’ input/output control unit 38B and input/output driving unit 39B are activated in the second chip of chips 30 of the multi-chip package. As a result, data DQ8˜DQ15 applied from global input/output line GIO are inputted and outputted through corresponding input/output pad 32. Reset input/output control units 38A, 38C, 38D of the second chip are disabled so that data DQ0˜DQ7, DQ16˜DQ31 are not inputted and outputted.

0053When decoding pad 3a is ‘low’ and decoding pad 3b is ‘high,’ input/output control unit 38C and input/output driving unit 39C are activated in the third chip of chips 30 of the multi-chip package. As a result, data DQ16˜DQ23 applied from global input/output line GIO are inputted and outputted through the corresponding input/output pad 32. Reset input/output control units 38A, 38B, 38D of the third chip are disabled so that data DQ0˜DQ15, DQ24˜DQ31 are not inputted and outputted.

0054When decoding pads (4a, 4b) are ‘high,’ input/output control unit 38D and input/output driving unit 39D are activated in the fourth chip of chips 30 of the multi-chip package. As a result, data DQ24˜DQ31 applied from global input/output line GIO are inputted and outputted through corresponding input/output pad 32. Reset input/output control units 38A˜38C of the fourth chip are disabled so that data DQ0˜DQ23 are not inputted and outputted.

0055Although decoder 37, input/output control units 38A˜38D, and input/output driving units 39A˜39D are not shown in <figref idref="DRAWINGS">FIG. 6</figref>, decoder 37, input/output control units 38A˜38D, and input/output driving units 39A˜39D can be easily appreciated by a person having ordinary skill in the art.

0056In this embodiment, code control units 26 and 36 may be applied to the semiconductor package having a four-layered structure chip, the data bandwidth of which is ×4 and ×8. However, when the data bandwidth is ×4, ×8, ×16, etc., the present invention can be easily designed. When the chip of the semiconductor package is two-layered, four-layered, etc., the code control unit can be designed.

0057Although one embodiment consistent with the present invention is applied to a stack or multi-chip package, it is appreciated that there are other embodiments, which are applicable to a DRAM+DRAM structure, DRAM+NAND flash structure, and System In Packaged (SIP) such as DRAM+controller.

0058As described above, according to an embodiment consistent with the present invention, input/output pads positioned at different locations in each die are selected in a stack or multi-chip package including two or more chips so as to facilitate package connection. Due to the optimization of the interconnection line, the loading of the input/output pads can be minimized.

0059The foregoing description of various embodiments of the invention has been presented for purposes of illustrating and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. Thus, the embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

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Document	Relation	Office	Cited during
US9966961B1	Cited by	United States of America	Applicant
US9653132B2	Cited by	United States of America	Applicant
KR100597787B1	Cites	Republic of Korea	Applicant
JP2005317830A	Cites	Japan	Applicant
US5066831A	Cites	United States of America	Search report
US5254482A	Cites	United States of America	Search report
US5272664A	Cites	United States of America	Search report
US5751015A	Cites	United States of America	Search report
US5768584A	Cites	United States of America	Applicant
US5987623A	Cites	United States of America	Search report
US6184713B1	Cites	United States of America	Search report
US6356958B1	Cites	United States of America	Search report
US6555398B1	Cites	United States of America	Search report
US6705877B1	Cites	United States of America	Search report
US6882171B2	Cites	United States of America	Search report
US7061263B1	Cites	United States of America	Search report
US7114659B2	Cites	United States of America	Search report
US7285980B2	Cites	United States of America	Search report
JP2005317830A	Cites	Japan	Third party observation
KR100597787B1	Cites	Republic of Korea	Third party observation

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1020070012123	Republic of Korea	–	2007-02-06
20070012123	Republic of Korea	A	2007-02-06

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Document	Office	Kind
KR100819660B1	Republic of Korea	B1	2008-04-07
US2008186798A1	United States of America	A1	2008-08-07
JP2008193041A	Japan	A	2008-08-21
US7693003B2This record	United States of America	B2	2010-04-06
JP5174379B2	Japan	B2	2013-04-03

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Semiconductor package

Summary by NHIP

Claim Score by NHIP

Abstract