Test apparatus, test method, analyzing apparatus and computer readable medium

CROSS REFERENCE TO RELATED APPLICATION

0001This is a continuation application of PCT/JP2006/316638 filed on Aug. 24, 2006 which claims priority from a Japanese Patent Application No. 2005-268728 filed on Sep. 15, 2005, the contents of which are incorporated herein by reference.

BACKGROUND

00021. Technical Field

0003The present invention relates to a test apparatus, a test method, a calculating apparatus and a computer-readable medium. More particularly, the present invention relates to a test apparatus, a test method, a calculating apparatus and a computer-readable medium which calculate a remedy solution for a defective storage cell in a memory under test.

00042. Related Art

0005<figref idref="DRAWINGS">FIG. 5</figref> illustrates the configuration of a conventional test apparatus <b>100</b> which calculates a remedy solution for replacing a defective storage cell in a semiconductor memory with a backup cell (for example, see Non-patent Document 1).

0006The test apparatus <b>100</b> includes therein a plurality of test signal feeding sections <b>120</b>, a plurality of defect detecting sections <b>130</b>, a plurality of fail memories <b>140</b>, and a plurality of calculating sections <b>150</b>. Each of the test signal feeding sections <b>120</b> feeds a test signal to a corresponding one of a plurality of memories under tests <b>110</b>. Each of the defect detecting sections <b>130</b> detects information identifying a defective storage cell in a corresponding one of the memories under test <b>110</b> (fail information) with reference to the data read from the corresponding memory under test <b>110</b> in response to the test signal, and writes the detected fail information into a corresponding one of the fail memories <b>140</b>. The fail information written on each of the fail memories <b>140</b> is transferred to a corresponding one of the calculating sections <b>150</b> on completion of the test on a corresponding one of the memories under test <b>110</b>. Each of the calculating sections <b>150</b> obtains a remedy solution for a corresponding one of the memories under test <b>110</b> with reference to the fail information transferred thereto. Here, the calculating sections <b>150</b> perform the processing to obtain the remedy solutions while the test signal feeding sections <b>120</b> and the defect detecting sections <b>130</b> perform tests.

0007Non-patent Document 1: Jin-Fu Li and 6 other members, “A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy”, INTERNATIONAL TEST CONFERENCE, INTERNATIONAL TEST CONFERENCE 2003 PROCEEDINGS, Sep. 30, 2003, p. 393-402

0008<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart illustrating the processing timings seen when the conventional test apparatus <b>100</b> tests a group of memories under test <b>110</b> during one test session.

0009The test apparatus <b>100</b> requires a different duration to calculate a remedy solution for each of the memories under test <b>110</b>. Therefore, even if each calculating section <b>150</b> concurrently starts the calculation for a corresponding one of the memories under test <b>110</b>, each calculating section <b>150</b> finishes the calculation at a different timing. Furthermore, since the remedy solution calculations are NP-complete, it is not known in advance how long the test apparatus <b>100</b> will require in order to complete the calculations. For these reasons, one or more of the calculating sections <b>150</b> may not complete the calculations by the time the test signal feeding sections <b>120</b> and the defect detecting sections <b>130</b> finish the tests which are performed in parallel.

0010Here, until the calculating sections <b>150</b> complete the current calculations, the pieces of fail information written in the fail memories <b>140</b> are not transferred to the calculating sections <b>150</b>. Therefore, the defect detecting sections <b>130</b> can not start the tests on the next group of memories under test <b>110</b> until the calculating sections <b>150</b> finish the current calculations. Here, consider a case where the test apparatus <b>100</b> tests a group of memories under test <b>110</b> during each test session. In this case, if the test apparatus <b>100</b> takes a relatively long time to calculate a remedy solution for any one of the memories under test <b>110</b> in the tested group, the test apparatus <b>100</b> can start testing none of the memories under test <b>110</b> included in the next group until completing the relatively lengthy calculation. This means a longer waiting time X from the end of the current tests to the start of the next tests. As a result, the test apparatus <b>100</b> suffers from a lowered throughput.

SUMMARY

0011Therefore, it is an object of an aspect of the innovations herein to provide a test apparatus, a test method, a calculating apparatus and a computer-readable medium, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.

0012According to a first aspect related to the innovations herein, one exemplary test apparatus may include a test apparatus for testing a plurality of memories under test. The test apparatus includes a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding sections feeds a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test, a plurality of defect detecting sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of defect detecting sections detects a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value, a plurality of first calculating sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of first calculating sections calculates a remedy solution for a corresponding one of the plurality of memories under test and the remedy solution remedies the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test, and a second calculating section that takes over, from one or more of the plurality of first calculating sections which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, in response to a start of calculations by the plurality of first calculating sections for remedy solutions for a different group of memories under test, and performs the taken over remedy solution calculations.

0013According to a second aspect related to the innovations herein, one exemplary test method may include a test method for testing a plurality of memories under test. The test method includes a plurality of test signal feeding steps that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding steps feeds a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test, a plurality of defect detecting steps that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of defect detecting steps detects a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value, a plurality of first calculating steps that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of first calculating steps calculates a remedy solution for a corresponding one of the plurality of memories under test and the remedy solution remedies the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test, and a second calculating step of taking over, from one or more of the plurality of first calculating steps in which the remedy solution calculations have not been finished, the unfinished remedy solution calculations, in response to a start of calculations in the plurality of first calculating steps for remedy solutions for a different group of memories under test, and performing the taken over remedy solution calculations.

0014According to a third aspect related to the innovations herein, one exemplary computer-readable medium, including thereon a program for use with a test apparatus, may include a program for use with a test apparatus that tests a plurality of memories under test when executed. When the program is executed, the computer-readable medium causes the test apparatus to function as a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding sections feeds a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test, a plurality of defect detecting sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of defect detecting sections detects a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value, a plurality of first calculating sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of first calculating sections calculates a remedy solution for a corresponding one of the plurality of memories under test and the remedy solution remedies the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test, and a second calculating section that takes over, from one or more of the plurality of first calculating sections which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, in response to a start of calculations by the plurality of first calculating sections for remedy solutions for a different group of memories under test, and performs the taken over remedy solution calculations.

0015According to a fourth aspect related to the innovations herein, one exemplary calculating apparatus may include a calculating apparatus for a test apparatus that tests a plurality of memories under test. Here, the test apparatus includes a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding sections feeds a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test, a plurality of defect detecting sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of defect detecting sections detects a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value, and a plurality of first calculating sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of first calculating sections calculates a remedy solution for a corresponding one of the plurality of memories under test and the remedy solution remedies the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test. Here, the calculating apparatus takes over, from one or more of the plurality of first calculating sections which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, in response to a start of calculations by the plurality of first calculating sections for remedy solutions for a different group of memories under test, and performs the taken over remedy solution calculations.

0016According to a fifth aspect related to the innovations herein, one exemplary computer-readable medium, including thereon a program for use with a calculating apparatus, may include a program for use with a calculating apparatus for a test apparatus that tests a plurality of memories under test when executed. Here, the test apparatus includes a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding sections feeds a test signal designed to test a corresponding one of the plurality of memories under test to the corresponding memory under test, a plurality of defect detecting sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of defect detecting sections detects a defect in a corresponding one of the plurality of memories under test when data read from the corresponding memory under test in response to the test signal is different from an expected value, and a plurality of first calculating sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of first calculating sections calculates a remedy solution for a corresponding one of the plurality of memories under test and the remedy solution remedies the defect in the corresponding memory under test by replacing a defective storage cell in the corresponding memory under test with a backup cell of the corresponding memory under test. When the program is executed, the computer-readable medium causes the calculating apparatus to take over, from one or more of the plurality of first calculating sections which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, in response to a start of calculations by the plurality of first calculating sections for remedy solutions for a different group of memories under test, and perform the taken over remedy solution calculations.

0017The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0018<figref idref="DRAWINGS">FIG. 1</figref> illustrates the configuration of a test apparatus <b>20</b> relating to an embodiment of the present invention.

0019<figref idref="DRAWINGS">FIG. 2</figref> is a timing chart illustrating the processing timings at the individual constituents of the test apparatus <b>20</b>.

0020<figref idref="DRAWINGS">FIG. 3</figref> is a timing chart illustrating the processing timings of the respective constituents of the test apparatus <b>20</b> when first calculating sections <b>28</b> continue their calculations even after the end of the tests performed in parallel, adaptively to the long time period required by a second calculating section <b>30</b> to complete taken-over calculations.

0021<figref idref="DRAWINGS">FIG. 4</figref> illustrates the processing time period required by each first calculating section <b>28</b> and the order in which the second calculating section <b>30</b> performs calculations.

0022<figref idref="DRAWINGS">FIG. 5</figref> illustrates the configuration of a conventional test apparatus <b>100</b>.

0023<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart illustrating the processing timings seen when the conventional test apparatus <b>100</b> tests a group of memories under test during each test session.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

0024Hereinafter, an embodiment of the present invention will be described. The embodiment does not limit the invention according to the claims, and all the combinations of the features described in the embodiment are not necessarily essential to means provided by aspects of the invention.

0025<figref idref="DRAWINGS">FIG. 1</figref> illustrates the configuration of a test apparatus <b>20</b> relating to an embodiment of the present invention. The test apparatus <b>20</b> concurrently tests a plurality of memories under test <b>10</b>-<b>1</b> to <b>10</b>-n (n is a natural number equal to or higher than two, and the memories under test <b>10</b>-<b>1</b> to <b>10</b>-n are hereinafter collectively referred to as the memories under test <b>10</b>). With reference to the test results, the test apparatus <b>20</b> efficiently calculates, for each of the memories under test <b>10</b>, a remedy solution to replace a defective storage cell in the memory under test <b>10</b> with a backup cell. Referring to the test apparatus <b>20</b>, the memories under test <b>10</b> may be individual devices, or individual blocks obtained by partitioning the storage region of a semiconductor memory chip.

0026The test apparatus <b>20</b> includes therein a plurality of test signal feeding sections <b>22</b>-<b>1</b> to <b>22</b>-n, a plurality of defect detecting sections <b>24</b>-<b>1</b> to <b>24</b>-n, a plurality of fail memories <b>26</b>-<b>1</b> to <b>26</b>-n, a plurality of first calculating sections <b>28</b>-<b>1</b> to <b>28</b>-n, and a second calculating section <b>30</b>.

0027The test signal feeding sections <b>22</b>-<b>1</b> to <b>22</b>-n (hereinafter, collectively referred to as the test signal feeding sections <b>22</b>) are provided in a one-to-one correspondence with the memories under test <b>10</b>. Each test signal feeding section <b>22</b> feeds a test signal to test a corresponding one of the memories under test <b>10</b>, to the corresponding memory under test <b>10</b>.

0028The defect detecting sections <b>24</b>-<b>1</b> to <b>24</b>-n (hereinafter, collectively referred to as the defect detecting sections <b>24</b>) are provided in a one-to-one correspondence with the memories under test <b>10</b>. Each defect detecting section <b>24</b> detects a defect in a corresponding one of the memories under test <b>10</b> when the data read from the corresponding memory under test <b>10</b> in response to the test signal is different from an expected value. Specifically speaking, each defect detecting section <b>24</b> detects a defective storage cell from among the large number of storage cells of the corresponding memory under test <b>10</b>. Each defect detecting section <b>24</b> writes information identifying the detected defective storage cell (fail information) into a corresponding one of the fail memories <b>26</b>-<b>1</b> to <b>26</b>-n.

0029The fail memories <b>26</b>-<b>1</b> to <b>26</b>-n (hereinafter, collectively referred to as the fail memories <b>26</b>) are provided in a one-to-one correspondence with the memories under test <b>10</b>. Each fail memory <b>26</b> stores thereon the fail information for a corresponding one of the memories under test <b>10</b> which is written by a corresponding one of the defect detecting sections <b>24</b>. The fail information written into each fail memory <b>26</b> is transferred to a corresponding one of the first calculating sections <b>28</b>-<b>1</b> to <b>28</b>-n after the test of the corresponding memory under test <b>10</b> is completed. For example, the fail information is transferred in such a manner that the data stored on each fail memory <b>26</b> is read by a corresponding one of the first calculating sections <b>28</b>-<b>1</b> to <b>28</b>-n.

0030The first calculating sections <b>28</b>-<b>1</b> to <b>28</b>-n (hereinafter, collectively referred to as the first calculating sections <b>28</b>) are provided in a one-to-one correspondence with the memories under test <b>10</b>. Each first calculating section <b>28</b> receives the fail information stored on a corresponding one of the fail memories <b>26</b>. With reference to the fail information transferred thereto, each first calculating section <b>28</b> calculates a remedy solution designed to remedy the defect of a corresponding one of the memories under test <b>10</b> by replacing the defective storage cell in the corresponding memory under test <b>10</b> with one of the backup cells of the corresponding memory under test <b>10</b>.

0031In response to the start of the remedy solution calculations by the first calculating sections <b>28</b> for a next group of memories under test <b>10</b>, the second calculating section <b>30</b> takes over, from one or more of the first calculating sections <b>28</b> which have not finished calculating the remedy solutions, the unfinished remedy solution calculations, and calculates the remedy solutions in place of the one or more of the first calculating sections <b>28</b>.

0032The above-described test apparatus <b>20</b> sets within the memories under test <b>10</b> the remedy solutions calculated by the first calculating sections <b>28</b> and the second calculating section <b>30</b>, to feed each of the calculated remedy solutions back to a corresponding one of the memories under test <b>10</b>. With the calculated remedy solutions being set within the memories under test <b>10</b>, when the defective storage cells in the memories under test <b>10</b> are accessed for data writing or reading, the memories under test <b>10</b> can change the access destinations from the defective storage cells to the backup cells.

0033<figref idref="DRAWINGS">FIG. 2</figref> is a timing chart illustrating the processing timings of the individual constituents of the test apparatus <b>20</b>.

0034The test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> test a plurality of memories under test <b>10</b> during each test session (for example, test a group of n memories under test <b>10</b> during each test session) for detecting defective storage cells. Specifically speaking, to begin with, the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> test an initial group of memories under test <b>10</b> (for example, a first group of memories under test <b>10</b>) (a first period). While testing the initial group (for example, the first group) of memories under test <b>10</b>, the defect detecting sections <b>24</b> write the obtained pieces of fail information (for example, the pieces of fail information for the first group) sequentially into the fail memories <b>26</b>. On completion of the tests, the pieces of fail information for the first group which have been written into the fail memories <b>26</b> are transferred to the first calculating sections <b>28</b>. For example, on completion of the tests on the first group of memories under test <b>10</b>, the pieces of fail information associated with the first group of memories under test <b>10</b> are transferred to the first calculating sections <b>28</b> (at the start of a second period). When the pieces of fail information have been completely transferred, the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> start testing the next group of memories under test <b>10</b> (for example, the second group of memories under test <b>10</b>) (the second period). In the above-described manner, the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> repeatedly perform the fail information transfer operation and the test operation.

0035When receiving the pieces of fail information transferred from the fail memories <b>26</b>, the first calculating sections <b>28</b> calculate the remedy solutions for the memories under test <b>10</b>. For example, when receiving from the fail memories <b>26</b> the pieces of fail information associated with the first group of memories under test <b>10</b> which are tested during the first period, the first calculating sections <b>28</b> calculate the remedy solutions for the memories under test <b>10</b> included in the first group (the second period).

0036Note that the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> operate independently from the first calculating sections <b>28</b>. While the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> perform the processing associated with a given group of memories under test <b>10</b>, the first calculating sections <b>28</b> perform the processing associated with a different group of the memories under test <b>10</b>. Take as an example the second period. The first calculating sections <b>28</b> calculate the remedy solutions for a group of memories under test <b>10</b> which have already been tested by the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> (for example, the first group of memories under test <b>10</b> which are tested immediately before the second group of memories under test <b>10</b>), while the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> test a different group of memories under test <b>10</b> (for example, the second group of memories under test <b>10</b>).

0037Here, one or more of the first calculating sections <b>28</b> may not complete their calculations by the time the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> complete the tests which are performed in parallel (for example, see the second memory under test <b>10</b> in the first group shown in the section of the second period). If such occurs, in response to the end of the tests by the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b> on a group of memories under test <b>10</b> (for example, the second group of memories under test <b>10</b>), the second calculating section <b>30</b> takes over the unfinished remedy solution calculations from the first calculating sections <b>28</b> which have not finished calculating the remedy solutions. For example, the second calculating section <b>30</b> takes over the unfinished remedy solution calculations at the end of the tests performed by the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b>, or when a predetermined time has elapsed after the end of the tests. When more than one of the first calculating sections <b>28</b> have not finished calculating the remedy solutions, the second calculating section <b>30</b> may take over more than one remedy solution calculation (for example, see a third period).

0038Once the second calculating section <b>30</b> takes over the one or more unfinished remedy solution calculations, the first calculating sections <b>28</b> terminate any ongoing calculations. In response to the end of the tests on a group (for example, the second group) of memories under test <b>10</b> by the test signal feeding sections <b>22</b> and the defect detecting sections <b>24</b>, the first calculating sections <b>28</b> start calculating the remedy solutions for that group (for example, the second group) of memories under test <b>10</b>.

0039As described in the above, in the test apparatus <b>20</b>, when the first calculating sections <b>28</b> do not finish the calculations within a predetermined time period, the second calculating section <b>30</b> takes over the unfinished calculations. Which is to say, in the test apparatus <b>20</b>, the first calculating sections <b>28</b> perform the remedy solution calculations at regular intervals for a large part of the memories under test <b>10</b> for which the remedy solutions can be easily calculated because of, for example, a small number of defective storage cells, and the second calculating section <b>30</b> separately and independently performs the remedy solution calculations on a small part of the memories under test <b>10</b> for which the remedy solutions can not be easily calculated. As a result, the test apparatus <b>20</b> can improve the yield ratio of the memories under test <b>10</b> and can also increase the system throughput.

0040In the test apparatus <b>20</b>, it is not necessary to provide second calculating sections <b>30</b> in a one-to-one correspondence with the memories under test <b>10</b>. The number of the second calculating sections <b>30</b> can be thus set smaller than the number of the memories under test <b>10</b>. Therefore, the second calculating section <b>30</b> may be realized by using, for example, an information processing apparatus that is more expensive but has a higher computing capability than the first calculating sections <b>28</b>, so that the system as a whole can achieve the enhanced processing capability.

0041Alternatively, the second calculating section <b>30</b> can be realized by using an information processing apparatus connected to the first calculating sections <b>28</b> via a network.

0042As a further alternative example, the second calculating section <b>30</b> can be realized by installing a program onto a computer. The program to be installed in the computer is provided by a user by way of a storage medium or via a network.

0043The program to be installed in the computer and to cause the computer to function as the second calculating section <b>30</b> has a module that, in response to the start of the remedy solution calculations by the first calculating sections <b>28</b> for a group of memories under test <b>10</b>, takes over the unfinished remedy solution calculations from one or more of the first calculating sections <b>28</b> which have not finished calculating the remedy solutions for a previous group of memories under test <b>10</b> and calculates the remedy solutions. The program or module instructs the processor or the like in the computer, so as to cause the computer to function as the second calculating section <b>30</b>.

0044The above-described program or module may be stored on an external storage medium. The storage medium is, for example, an optical storage medium such as DVD and CD, a magnet-optical storage medium such as MD, a tape medium, a semiconductor memory such as an IC card and the like, in addition to a flexible disk and a CD-ROM. The storage medium may be a storage device such as a hard disk or RAM which is provided in a server system connected to a dedicated communication network or the Internet, and the program may be provided to the computer via the network.

0045When the second calculating section <b>30</b> takes over the remedy solution calculations from the first calculating sections <b>28</b>, one or more of the first calculating sections <b>28</b> which have not finished calculating the remedy solutions transmit the corresponding pieces of fail information to the second calculating section <b>30</b>, and the second calculating section <b>30</b> starts calculating the remedy solutions with reference to the pieces of fail information received from the first calculating sections <b>28</b>. When required to transmit the corresponding pieces of fail information, the first calculating sections <b>28</b> may be in the middle of the calculations for the calculations. In this case, the first calculating sections <b>28</b> may also transmit, to the second calculating section <b>30</b>, the resulting data obtained by the calculations that have been done. The second calculating section <b>30</b> may use the resulting data to calculate the remedy solutions. This can reduce the quantity of the calculations that have to be done by the second calculating section <b>30</b> in the test apparatus <b>20</b>.

0046On condition that the second calculating section <b>30</b> has no unfinished calculations which have been taken over from the first calculating section <b>28</b>, the second calculating section <b>30</b> may perform part of the calculation assigned to at least one of the first calculating sections <b>28</b>, while the first calculating sections <b>28</b> perform the calculations. In other words, when not performing any calculations, the second calculating section <b>30</b> may help the first calculating sections <b>28</b> to perform the calculations. In this manner, the test apparatus <b>20</b> can make efficient use of the computation resource provided by the second calculating section <b>30</b>.

0047In a case where the second calculating section <b>30</b> takes over the unfinished remedy solution calculations from the first calculating sections <b>28</b> which have not finished calculating the remedy solutions in response to the end of the tests on a given group (for example, the second group) of memories under test <b>10</b>, the second calculating section <b>30</b> performs the taken-over calculations during the test period of testing the next group (for example, the third group) of memories under test <b>10</b> (for example, the third period). Here, if the second calculating section <b>30</b> has not finished the remedy solution calculations taken over from the first calculating sections <b>28</b>, for example, by a predetermined time, the second calculating section <b>30</b> may terminate the unfinished calculations and judge that the corresponding memories under test <b>10</b> can not be remedied. For example, if the second calculating section <b>30</b> is still performing the taken-over remedy solution calculations at the end of the tests which are conducted concurrently with the taken-over remedy solution calculations (or when a predetermined time period has elapsed after the end of the tests), the second calculating section <b>30</b> terminates the unfinished calculations.

0048The test apparatus <b>20</b> can terminate the calculations by the second calculating section <b>30</b> when the calculations by the second calculating section <b>30</b> are lengthy, thereby improving the processing efficiency.

0049<figref idref="DRAWINGS">FIG. 3</figref> is a timing chart illustrating the processing timings of the respective constituents of the test apparatus <b>20</b> when the first calculating sections <b>28</b> continue their calculations even after the end of the tests performed in parallel, adaptively to the long time period required by the second calculating section <b>30</b> to complete the taken-over calculations.

0050In a case where the second calculating section <b>30</b> takes over the unfinished remedy solution calculations from the first calculating sections <b>28</b> which have not finished calculating the remedy solutions in response to the end of the tests on a certain group (for example, the second group) of memories under test <b>10</b>, the second calculating section <b>30</b> performs the taken-over calculations during the test period of testing the next group (for example, the third group) of memories under test <b>10</b> (for example, the third period). During this test period (for example, the third period), the first calculating sections <b>28</b> calculate the remedy solutions for the tested certain group (for example, the second group) of memories under test <b>10</b>.

0051A case is assumed where the test apparatus <b>20</b> has completed the tests on a given group (for example, the third group) of memories under test <b>10</b> but the second calculating section <b>30</b> has not completed calculating the remedy solutions for a different group (for example, the first group) of memories under test <b>10</b>. In such a case, the first calculating sections <b>28</b> may continue, even after the end of the tests on the given group (for example, the third group) of memories under test <b>10</b>, calculating the remedy solutions for a further different group (for example, the second group) of memories under test <b>10</b> until the second calculating section <b>30</b> completes calculating the remedy solutions.

0052In the test apparatus <b>20</b>, the first calculating sections <b>28</b> continue performing the calculations after the end of the tests until the second calculating section <b>30</b> completes the calculations as stated above. This configuration can prevent the second calculating section <b>30</b> from being heavily loaded with the calculations, thereby preventing an increase in the waiting time. As a result, the test apparatus <b>20</b> can efficiently perform the tests.

0053<figref idref="DRAWINGS">FIG. 4</figref> illustrates the processing time period required by each first calculating section <b>28</b> and the order in which the second calculating section <b>30</b> performs the calculations.

0054At such a timing that the first calculating sections <b>28</b> can start calculating the remedy solutions for a new group of memories under test <b>10</b>, the second calculating section <b>30</b> may take over the unfinished remedy solution calculations from the first calculating sections <b>28</b> which have not finished calculating the remedy solutions, on condition that the number of first calculating sections <b>28</b> which have not finished calculating the remedy solutions is lower than or equal to a predetermined threshold value. For example, the second calculating section <b>30</b> may take over the unfinished remedy solution calculations, on condition that the second calculating section <b>30</b> has no unfinished calculations thereon and the number of first calculating sections <b>28</b> which have not finished calculating the remedy solutions is lower than or equal to such a number that the second calculating section <b>30</b> can complete the taken-over calculations within the test period of testing one group of memories under test <b>10</b>.

0055In the above-described manner, the test apparatus <b>20</b> determines the timing at which the second calculating section <b>30</b> takes over the unfinished remedy solution calculations. With such a configuration, the second calculating section <b>30</b> can take over the unfinished remedy solution calculations as soon as possible within the processing capability of the second calculating section <b>30</b>. As a result, the test apparatus <b>20</b> can improve the processing speed as a whole.

0056When taking over the remedy solution calculations for two or more memories under test <b>10</b> from two or more first calculating sections <b>28</b>, the second calculating section <b>30</b> may perform the remedy solution calculations in the ascending order of the numbers of the defective storage cells in the memories under test <b>10</b>.

0057By determining the order of performing the calculations in the above manner, the test apparatus <b>20</b> can calculate the remedy solutions for the memories under test <b>10</b> in such an order that the easier the calculations are expected to be, the earlier the calculations are performed. Therefore, the test apparatus <b>20</b> can reduce the number of memories under test <b>10</b> which are judged not to be able to be remedied since it is difficult to calculate the remedy solutions.

0058While the embodiment of the present invention has been described, the technical scope of the invention is not limited to the above described embodiment. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention.