Flat panel display

CLAIM OF PRIORITY

0001This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from the two applications both of which are entitled FLAT PANEL DISPLAY DEVICE and earlier filed in the Korean Intellectual Property Office on the 28 of May 2005 and the 23 of June 2005 and there, duly assigned Ser. Nos. 10- 2005-0045298 and 10-2005-0054369, respectively.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a flat panel display, and more particularly, to a flat panel display that prevents the voltage drop of a driving power and minimizes a reduction of characteristics of electronic devices included in a circuit region where various circuit devices are mounted.

00042. Description of the Related Art

0005A lot of research into manufacturing super slim and flexible flat panel displays, such as Organic Light Emitting Displays (OLEDs) or Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) in connection with driving characteristics thereof has been conducted.

0006An Active Matrix (AM) flat panel display includes a pixel circuit in each pixel, and the pixel circuit controls and drives a light emitting device of the pixel according to a signal supplied from a scan line or a data line.

0007The driving power supplied to each pixel circuit is supplied to pixels by lines. The voltage of the power supplied to each of the pixels is not uniform due to a voltage drop in Vdd lines. As a result, non-uniform brightness can occur resulting in the degradation of the image quality.

0008Also, in the case of the AM OLED, at least one capacitor is included in each of the pixels, and a voltage drop can occur in the capacitor due to the multiple pixels. This problem is increased when the screen is large and when there are more capacitors.

0009To address this problem, a technique of forming an additional power supply layer has been developed by the present inventor.

0010U.S. Published Patent Application No. 2003/0111954A relates to an organic electroluminescent display having a top emitting structure in which an additional power supply layer supplies power to a substrate. However, in this case, the operation of electronic devices of a scan driver, a data driver, or particularly a Complementary Metal Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) can be interrupted by the power supply layer.

SUMMARY OF THE INVENTION

0011The present invention provides a flat panel display that prevents a voltage drop of a driving power and improves the characteristics of electronic devices in a circuit region where various circuit devices are mounted and electronic devices included in a pixel region.

0012According to an aspect of the present invention, a flat panel display is provided including: a substrate; an insulating film arranged on the substrate; a pixel region including at least one light emitting diode, the pixel region being arranged on the insulating film and adapted to display an image; a circuit region arranged on the insulating film and including electronic devices adapted to control signals supplied to the pixel region; and a conductive film interposed between the substrate and the insulating film in a region corresponding to the pixel region and electrically connected to one electrode of the at least one light emitting diode.

0013According to another aspect of the present invention, a flat panel display is provided including: a substrate including a conductive pattern unit of a conductive material; an insulating film arranged on the substrate; a pixel region including a light emitting diode, the pixel region arranged on the insulating film and adapted to display an image; and a circuit region arranged on the insulating film and including electronic devices adapted to control signals supplied to the pixel region; the conductive pattern unit includes a first pattern unit arranged in a region corresponding to the pixel region and a second pattern unit arranged in a region corresponding to the circuit region.

0014According to another aspect of the present invention, a flat panel display is provided including: a substrate including first and second pattern units of a conductive material; an insulating film arranged on the substrate; a light emitting diode arranged on the insulating film; a Thin Film Transistor (TFT) arranged on the insulating film and electrically connected to the light emitting diode; and at least one electronic device arranged on the insulating film to correspond to an outer side of the first pattern unit and electrically connected to the TFT; the first pattern unit is electrically connected to the TFT and the second pattern unit is arranged in a region corresponding to the electronic device.

0015According to another aspect of the present invention, flat panel display is provided including: a substrate including first and second pattern units of a conductive material; an insulating film arranged on the substrate; a light emitting diode arranged on the insulating film; a capacitor unit having at least two capacitors connected in parallel to each other, the capacitor unit arranged on the insulating film and electrically connected to the light emitting diode; and at least one electronic device arranged on the insulating film corresponding to an outer side of the first pattern unit and electrically connected to the capacitor unit; the first pattern unit is an electrode of the capacitor unit and wherein the second pattern unit is arranged in a region corresponding to the at least one electronic device.

BRIEF DESCRIPTION OF THE DRAWINGS

0016A more complete appreciation of the present invention and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

0017<figref idref="DRAWINGS">FIG. 1</figref> is a plan view of an Active Matrix (AM) Organic Light Emitting Display (OLED) of a flat panel display according to an embodiment of the present invention;

0018<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram of a pixel region of the AM OLED of <figref idref="DRAWINGS">FIG. 1</figref> according to an embodiment of the present invention;

0019<figref idref="DRAWINGS">FIG. 3</figref> is a detailed schematic circuit diagram of a pixel circuit of one unit pixel in the pixel region of <figref idref="DRAWINGS">FIG. 2</figref> according to an embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a substrate taken along a line I-I of <figref idref="DRAWINGS">FIG. 1</figref> according to an embodiment of the present invention;

0021<figref idref="DRAWINGS">FIG. 5</figref> is a plan view of a layout of a pixel structure to realize the circuit of <figref idref="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention;

0022<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view taken along a line II-II of <figref idref="DRAWINGS">FIG. 5</figref>;

0023<figref idref="DRAWINGS">FIG. 7</figref> is a plan view of a layout of a pixel structure to realize the circuit of <figref idref="DRAWINGS">FIG. 3</figref> according to another embodiment of the present invention;

0024<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view taken along a line III-III of <figref idref="DRAWINGS">FIG. 7</figref>;

0025<figref idref="DRAWINGS">FIG. 9</figref> is a plan view of a layout of a pixel structure to realize the circuit of <figref idref="DRAWINGS">FIG. 3</figref> according to another embodiment of the present invention;

0026<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view taken along a line IV-IV of <figref idref="DRAWINGS">FIG. 9</figref>;

0027<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of a Complementary Metal Oxide Semiconductor (CMOS) device in a circuit region of <figref idref="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention;

0028<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view of another substrate with respect to the cross-sectional view taken along line I-I of <figref idref="DRAWINGS">FIG. 1</figref> according to another embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 13</figref> is a plan view of patterns units of <figref idref="DRAWINGS">FIG. 12</figref> according to an embodiment of the present invention; and

0030<figref idref="DRAWINGS">FIG. 14</figref> is a cross-sectional view of a CMOS device in a circuit region of <figref idref="DRAWINGS">FIG. 3</figref> according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0031The present invention is described more fully below with reference to the accompanying drawings in which exemplary embodiments of the present invention are shown.

0032<figref idref="DRAWINGS">FIG. 1</figref> is a plan view of an Active Matrix (AM) Organic Light Emitting Display (OLED) of a flat panel display according to an embodiment of the present invention. Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the OLED includes a pixel region P and a circuit region C located on edges of the pixel region P.

0033The pixel region P includes a plurality of pixels, and each pixel includes an organic light emitting device such as an organic Light Emitting Diode (LED). In a full color OLED, red R, green G, and blue B color pixels are arranged in various patterns, such as a line shape, a mosaic shape, or a lattice shape, and the OLED can be a mono color flat panel display.

0034The circuit region C includes electronic devices that control the organic LEDs located in pixels of the pixel region P, and circuits in the circuit region C control image signals inputted to the pixel region P and supply power to the electronic devices.

0035The pixel region P and the circuit region C of <figref idref="DRAWINGS">FIG. 1</figref> can be realized in a schematic circuit diagram.

0036<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram of one unit pixel in the pixel region P and electronic devices E<b>1</b>, E<b>2</b>, and E<b>3</b> in the circuit region C connected to the pixel region according to an embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 3</figref> is a detailed circuit diagram of a pixel circuit SC in the pixel region P according to an embodiment of the present invention.

0037Referring to <figref idref="DRAWINGS">FIG. 2</figref>, the pixel includes a power line Vdd which is a source of driving power of an organic LED, a data line, and a scan line.

0038The pixel circuit SC in each pixel is electrically connected to the data line, scan line, <b>8</b> and the Vdd power line Vdd and controls the emission of light of the organic LED.

0039The circuit region C can include the first electronic device E<b>1</b> electrically connected to the scan line, the second electronic device E<b>2</b> electrically connected to the data line, and the third electronic device E<b>3</b> electrically connected to the Vdd power line Vdd. The first electronic device E<b>1</b> can be a scan driver, the second electronic device E<b>2</b> can be a data driver, and the third electronic device E<b>3</b> can be a Vdd power source. The electronic devices E<b>1</b>, E<b>2</b>, and E<b>3</b> can be realized by printing on a substrate like the pixel circuit SC or mounting an additional device on the substrate, or can be connected to the pixel circuit SC through a connection medium such as a cable, or a flexible printed circuit board.

0040Also, the circuit region C can further include various electronic devices for displaying an image in the pixel region P by controlling the emission of light of an organic LED, and include terminal pads connected to external circuits.

0041In <figref idref="DRAWINGS">FIG. 3</figref>, the pixel circuit SC includes two Thin Film Transistors (TFTs) M<b>1</b> and M<b>2</b> and one capacitor Cst, and the circuit region C includes a Complementary Metal Oxide Semiconductor (CMOS) device CM connected to a scan line.

0042Referring to <figref idref="DRAWINGS">FIG. 3</figref>, the pixel circuit SC of the AM OLED according to the current embodiment of the present invention includes at least two TFTs, i.e., a switching TFT M<b>2</b> and a driving TFT M<b>1</b>, a capacitor Cst, and an organic LED.

0043The switching TFT M<b>2</b> is turned on or off by a scan signal supplied to a scan line to transmit a data signal supplied to a data line to the storage capacitor Cst and the driving TFT M<b>1</b>. The switching TFT M<b>2</b> according to the current embodiment of the present invention is not limited thereto, but rather can include a switching circuit having a plurality of TFTs and capacitors or can further include a circuit that compensates for a Vth of the driving TFT M<b>1</b> or a circuit that compensates for a voltage drop of the power line Vdd.

0044The driving TFT M<b>1</b> determines the amount of current inputted to the organic LED according to a data signal transmitted through the switching TFT M<b>2</b>.

0045The capacitor unit Cst stores the data signal transmitted through the switching TFT M<b>2</b> for one frame time. As depicted in <figref idref="DRAWINGS">FIG. 3</figref>, the capacitor unit Cst according to this embodiment of the present invention can include two capacitors, i.e., a first capacitor C<b>1</b> and a second capacitor C<b>2</b>.

0046In the circuit diagram of <figref idref="DRAWINGS">FIG. 3</figref>, the driving TFT M<b>1</b> and the switching TFT M<b>2</b> are depicted as P-type Metal Oxide Semiconductor (PMOS) TFTs, but the present invention is not limited thereto. At least one of the driving TFT M<b>1</b> and the switching TFT M<b>2</b> can be an N-type Metal Oxide Semiconductor (NMOS) TFT. Also, the number of TFTs and capacitors are not limited to the current embodiment, but can be varied as necessary.

0047The CMOS device CM illustrated in <figref idref="DRAWINGS">FIG. 3</figref> has a coupled structure of a P type TFT T<b>1</b> and an N type TFT T<b>2</b>. The scan driver does not necessarily include only the CMOS device CM, but can form a driver circuit in connection with various kinds of TFTs and circuit devices.

0048In the present invention, the pixel region P and the circuit region C can be realized on a substrate depicted in <figref idref="DRAWINGS">FIG. 4</figref>. <figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a substrate <b>100</b> taken along a line I-I of <figref idref="DRAWINGS">FIG. 1</figref>.

0049Referring to <figref idref="DRAWINGS">FIG. 4</figref>, a first pattern unit <b>101</b><i>a </i>is formed on the substrate <b>100</b>, and an insulating film <b>102</b> is formed to cover the first pattern unit <b>101</b><i>a. </i>

0050The substrate <b>100</b> can be an insulating substrate formed of glass or plastic. The substrate <b>100</b> is not limited thereto, and can also be a conductive metal substrate. In this case, the entire substrate <b>100</b> is electrically connected to the first pattern unit <b>101</b><i>a</i>, and an effect of the present invention, which will be described later, can be obtained by forming the thickness of the insulating film <b>102</b> on an upper part of the first pattern unit <b>101</b><i>a </i>differently from the thickness of the insulating film <b>102</b> on an upper part of the substrate <b>100</b>. Hereinafter, however, the substrate <b>100</b> is an insulating substrate, and when the substrate <b>100</b> refers to a conductive substrate, additional comments will be added.

0051The first pattern unit <b>101</b><i>a </i>can be formed of any conductive material. For example, a metal such as Al, Mo, Ag, Mg, W, Fe, Cr, Ni, Mn, etc. can be used to form the first pattern unit <b>101</b><i>a. </i>

0052As depicted in <figref idref="DRAWINGS">FIG. 4</figref>, the first pattern unit <b>101</b><i>a </i>is located in a region corresponding to the pixel region P, and is arranged not to be located in a region corresponding to the circuit region C.

0053The insulating film <b>102</b> can be a single structure or a multi-layer structure of an organic insulating film, an inorganic insulating film, or an organic-inorganic hybrid film. The organic insulating film can be formed of a polymer, for example, a versatile polymeric material such as PMMA or PS, a polymer derivative having a phenol group, acrylic polymer, imide group polymer, arylether group polymer, amide group polymer, fluorine group polymer, p-xylyrene group polymer, vinyl alcohol group polymer, and a blend of these materials. The inorganic insulating film can be formed of SiO₂, SiNx, SiON, Al₂O₃, TiO₂, Ta₂O₅, HfO₂, ZrO₂, BST, PZT, etc. As depicted in <figref idref="DRAWINGS">FIG. 4</figref>, the insulating film <b>102</b> can have a planarized surface.

0054<figref idref="DRAWINGS">FIG. 5</figref> is a plan view of a layout of a pixel structure that can realize the circuit of <figref idref="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view taken along a line II-II of <figref idref="DRAWINGS">FIG. 5</figref>.

0055Referring to <figref idref="DRAWINGS">FIG. 5</figref>, each pixel is arranged crossing a scan line <b>151</b>, a data line <b>152</b>, and a Vdd power line <b>153</b>.

0056As described above, each pixel includes a switching TFT M<b>2</b>, a capacitor unit Cst, a driving TFT M<b>1</b>, and an organic LED having a pixel electrode <b>161</b>.

0057In the current embodiment of the present invention, a second electrode <b>132</b> of the capacitor unit Cst is electrically connected to the first pattern unit <b>101</b><i>a </i>via a first through hole <b>140</b>. Accordingly, a voltage drop of the capacitor unit Cst is prevented, and at the same time, a voltage drop of the Vdd power line <b>153</b> is prevented.

0058The structure of the pixel circuit according to the current embodiment of the present invention is described in detail as follows with reference to <figref idref="DRAWINGS">FIG. 6</figref>. <figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view of the driving TFT M<b>1</b>, the optical LED, and the capacitor unit Cst of the circuit diagram of <figref idref="DRAWINGS">FIG. 3</figref>.

0059In <figref idref="DRAWINGS">FIG. 6</figref>, only the driving TFT M<b>1</b> is depicted. However, when a switching device S<b>1</b> includes a TFT, the TFT can be formed when the driving TFT M<b>1</b> is formed. Therefore, hereinafter, the driving TFT M<b>1</b> will be mainly described.

0060As described above, the first pattern unit <b>101</b><i>a </i>is formed on the substrate <b>100</b>, and the insulating film <b>102</b> covering the first pattern unit <b>101</b><i>a </i>is formed. A TFT, a capacitor unit Cst, etc., are formed on the insulating film <b>102</b>.

0061A semiconductor layer <b>111</b> of the TFT is formed on the insulating film <b>102</b>. The semiconductor layer <b>111</b> can be formed of an inorganic semiconductor or an organic semiconductor.

0062The inorganic semiconductor can include CdS, GaS, ZnS, CdSe, CaSe, ZnSe, CdTe, SiC, or Si. After amorphous silicon is formed on the insulating film <b>102</b>, the amorphous silicon is transformed into polysilicon through a crystalline process, and then the semiconductor layer <b>111</b> is formed by patterning the polysilicon. The amorphous silicon can be crystallized using various crystallization methods including Solid Phase Crystallization (SPC), laser crystallization, Sequential Lateral Solidification (SLS), or metal Induced lateral crystallization.

0063The organic semiconductor material includes pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, oligoacen of naphthalene and its derivatives, alpha-5-thiophene oligothiophene and its derivatives, phthalocianin that does not include a metal and its derivatives, phyromeliticdianhydride and its derivatives, phyromelitic diimid and its derivatives, conjugated polymer that includes thiophene and its derivatives, and a polymer that includes fluorine and its derivatives.

0064The semiconductor layer <b>111</b> can be divided into a source region <b>111</b><i>b </i>and a drain region <b>111</b><i>c </i>on both sides of a channel region <b>111</b><i>a</i>. The source and drain regions <b>111</b><i>b </i>and <b>111</b><i>c </i>can be reversed according to the TFT-type.

0065After the semiconductor layer <b>111</b> is formed, a gate insulating film <b>103</b> covering the semiconductor layer <b>111</b> is formed, and a gate electrode <b>112</b> is formed on a region of the gate insulating film <b>103</b> corresponding to the channel region <b>111</b><i>a</i>. When the gate electrode <b>112</b> is formed, a first electrode <b>131</b> of the capacitor unit Cst is formed. The gate electrode <b>112</b> and the first electrode <b>131</b> of the capacitor unit Cst can be formed of a material that includes a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or a compound of these metals, or a transparent conductive material such as ITO, IZO, ZnO, or In₂O₃. Also, the gate electrode <b>112</b> and the first electrode <b>131</b> can be formed of a conductive organic material or a conductive paste that includes conductive particles of a metal such as Ag, Mg, or Cu, and can be formed in a single layer structure or a multiple layer structure.

0066An inter-insulating film <b>104</b> is then formed to cover the gate electrode <b>112</b> and the first electrode <b>131</b>.

0067Contact holes <b>141</b> and <b>142</b> passing through the inter-insulating film <b>104</b> and the gate insulating film <b>103</b> are then formed, and source and drain electrodes <b>113</b> and <b>114</b> are formed on the inter-insulating film <b>104</b>. The source and drain electrodes <b>113</b> and <b>114</b> respectively contact the source and drain regions <b>111</b><i>b </i>and <b>111</b><i>c </i>of the semiconductor layer <b>111</b> via the contact holes <b>141</b> and <b>142</b>.

0068The source and drain electrodes <b>113</b> and <b>114</b> can also be formed of a material that includes a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or a compound of these metals, or a transparent conductive material such as ITO, IZO, ZnO, or In₂O₃. Also, the source and drain electrodes <b>113</b> and <b>114</b> can be formed of a conductive organic material or a conductive paste that includes conductive particles of a metal such as Ag, Mg, or Cu, and can be formed in a single layer structure or a multiple layer structure.

0069A second electrode <b>132</b> of the capacitor unit Cst is formed on the inter-insulating film <b>104</b> at the same time as the source and drain electrodes <b>113</b> and <b>114</b>. The first through hole <b>140</b> is formed in the inter-insulating film <b>104</b>, the gate insulating film <b>103</b>, and the insulating film <b>102</b> so that the second electrode <b>132</b> of the capacitor unit Cst formed on the inter-insulating film <b>104</b> can connect the first pattern unit <b>101</b><i>a. </i>

0070The structure of the TFT, as depicted in <figref idref="DRAWINGS">FIG. 6</figref>, according to the current embodiment of the present invention is not limited thereto, and can have various TFT structures such as a bottom gate structure.

0071After the TFT and the capacitor unit Cst are formed, a planarizing film <b>105</b> covering the TFT and the capacitor unit Cst is formed. A via hole <b>164</b> is formed in the planarizing film <b>105</b>, and a pixel electrode <b>161</b> of an OLED is formed on the planarizing film <b>105</b>. As a result, the pixel electrode <b>161</b> is connected to the drain electrode <b>114</b> of the driving TFT M<b>1</b>.

0072An opening <b>107</b> for exposing a predetermined portion of the pixel electrode <b>161</b> is formed in the pixel defining film <b>106</b> after a pixel defining film <b>106</b> covering the planarizing film <b>105</b> and the pixel electrode <b>161</b> has been formed.

0073The gate insulating film <b>103</b>, the inter-insulating film <b>104</b>, the planarizing film <b>105</b>, and the pixel defining film <b>106</b> can also be an organic insulating film, an inorganic insulating film, or an organic-inorganic hybrid film, and can be formed to a single layer structure or a multiple layer structure. The organic insulating film can be formed of a polymer, for example, a versatile polymeric material such as PMMA or PS, a polymer derivative having a phenol group, acrylic polymer, imide group polymer, arylether group polymer, amide group polymer, fluorine group polymer, p-xylyrene group polymer, vinyl alcohol group polymer, and a blend of these materials. The inorganic insulating film can be formed of SiO₂, SiNx, SiON, Al₂O₃, TiO₂, Ta₂O₅, HfO₂, ZrO₂, BST, PZT, etc.

0074An organic light emitting layer <b>162</b> and a facing electrode <b>163</b> are sequentially formed on the pixel electrode <b>161</b> exposed through the opening <b>107</b> in the pixel defining film <b>106</b>.

0075The pixel electrode <b>161</b> can function as an anode electrode, and the facing electrode <b>163</b> can function as a cathode electrode. The pixel electrode <b>161</b> can be patterned to a size corresponding to each of the pixels, and the facing electrode <b>163</b> can be formed to cover all of the pixels.

0076The organic LED can be a top emission type since the first pattern unit <b>101</b><i>a </i>is formed on the substrate <b>100</b>. In this case, the pixel electrode <b>161</b> can be used as a reflection electrode. When the pixel electrode <b>161</b> is used as the reflection electrode, the pixel electrode <b>161</b> can be formed of ITO, IZO, ZnO or In₂O₃on a reflection film after the reflection film is formed using Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound of these metals. The facing electrode <b>163</b> can be a transparent electrode. When the facing electrode <b>163</b> is used as the transparent electrode, the facing electrode <b>163</b> can be formed such that after depositing a thin film formed of a metal having a low work function, such as Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, or a compound of these metals facing the organic light emitting layer <b>162</b>, an auxiliary electrode layer or a bus electrode line formed of a material for forming the transparent electrode, such as ITO, IZO, ZnO or In2O 3, can be formed on the material layer. When the second electrode layer <b>34</b> is used as the reflection electrode, the second electrode layer <b>34</b> is formed by depositing Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, or a compound of these metals.

0077Materials for forming the pixel electrode <b>161</b> and the facing electrode <b>163</b> are not limited thereto, and can be conductive organic materials or conductive pastes.

0078The organic light emitting layer <b>162</b> can be a low molecular weight organic layer or a polymer organic layer. When the organic light emitting layer <b>162</b> is a low molecular weight organic film, the organic light emitting layer <b>162</b> may be a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an EMission Layer (EML), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL) or a combination of these layers and can be composed of copper phthalocyanine (CuPc), N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), or tris-8-hydroxyquinoline aluminum (Alq3). The low molecular weight organic film can be formed using an evaporation method.

0079When the organic light emitting layer <b>162</b> is a polymer organic film, the organic light emitting layer <b>162</b> can be an HTL and an EML. The HTL can be formed of poly-(2,4)-ethylene-dihydroxy thiophene (PEDOT) and the EML can be formed of Poly-Phenylenevinylene (PPV), Soluble PPV's, Cyano-PPV, or Polyfluorene and can be formed using a screen printing process or an inkjet printing process.

0080An upper part of the organic LED is sealed from external air after being formed.

0081According to an embodiment of the present invention, a first capacitor C<b>1</b> includes the first pattern unit <b>101</b><i>a</i>, the insulating film <b>102</b>, the gate insulating film <b>103</b>, and the first electrode <b>131</b>, and a second capacitor C<b>2</b> includes the first electrode <b>131</b>, the inter-insulating film <b>104</b>, and the second electrode <b>132</b>. The second electrode <b>132</b> is connected to the first pattern unit <b>101</b><i>a </i>so that the first capacitor C<b>1</b> and the second capacitor C<b>2</b> can be connected in parallel with each other. Also, as depicted in <figref idref="DRAWINGS">FIG. 5</figref>, the source electrode <b>113</b> is connected to the second electrode <b>132</b> of the capacitor unit Cst so that the driving TFT M<b>1</b> and the capacitor unit Cst can be electrically connected to each other. Also, the Vdd power line <b>153</b> formed when the source and drain electrodes <b>113</b> and <b>114</b> are formed, is connected to the source electrode <b>113</b> and the first pattern unit <b>101</b><i>a</i>, and realizes the same circuit as depicted in <figref idref="DRAWINGS">FIG. 3</figref>.

0082In this way, the first pattern unit <b>101</b><i>a </i>according to an embodiment of the present invention is used as an electrode of the capacitor unit Cst, thereby preventing a voltage drop of the capacitor unit Cst, and the first pattern unit <b>101</b><i>a </i>can also prevent the voltage drop of the Vdd power line <b>153</b> since the first pattern unit <b>101</b><i>a </i>is electrically connected to the Vdd power line <b>153</b>.

0083As described above, the capacitor structure according to the present invention can be applied to various structures.

0084<figref idref="DRAWINGS">FIG. 7</figref> is a plan view of a pixel of an OLED according to another embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view taken along a line III-III of <figref idref="DRAWINGS">FIG. 7</figref>.

0085The basic structure of the pixel of an OLED depicted in <figref idref="DRAWINGS">FIGS. 7 and 8</figref> is substantially the same as that of <figref idref="DRAWINGS">FIGS. 5 and 6</figref>. Thus, a detailed description thereof has been omitted, but the main differences will be described.

0086Referring to <figref idref="DRAWINGS">FIG. 7</figref>, the OLED according to the current embodiment of the present invention does not include an additional Vdd power line, and as depicted in <figref idref="DRAWINGS">FIG. 8</figref>, a first pattern unit <b>101</b><i>a </i>functions as the Vdd power line. That is, a driving power which is supplied to an existing Vdd line is also supplied to the first pattern unit <b>101</b><i>a</i>. Accordingly, only a scan line <b>151</b> and a data line <b>152</b> pass through each pixel, thereby enabling a compact structure. Also, the risk of electrical disconnection between the Vdd line and an adjacent pixel can be removed.

0087A second electrode <b>132</b> of a capacitor unit Cst is connected to the drain electrode of a switching TFT M<b>2</b> as one body, and is connected to a gate electrode <b>112</b> of a driving TFT M<b>1</b> via a contact hole <b>143</b> (see <figref idref="DRAWINGS">FIG. 7</figref>). As depicted in <figref idref="DRAWINGS">FIGS. 7 and 8</figref>, a first electrode <b>131</b> of the capacitor unit Cst is electrically connected to the first pattern unit <b>101</b><i>a</i>, to which the Vdd power is supplied, via a first through hole <b>140</b>.

0088Also, a source electrode <b>113</b> of the driving TFT M<b>1</b> is connected to the first pattern unit <b>101</b><i>a </i>via a second through hole <b>144</b>. Other structures in <figref idref="DRAWINGS">FIGS. 7 and 8</figref> are the same as those in <figref idref="DRAWINGS">FIGS. 5 and 6</figref>.

0089In the current embodiment of the present invention, the voltage drop of the capacitor unit Cst can be prevented since the first electrode <b>131</b> of the capacitor unit Cst, formed at the same time as the gate electrode <b>112</b>, is electrically connected to the first pattern unit <b>101</b><i>a</i>, and also, the voltage drop of the Vdd power line can be prevented since the Vdd line that supplies a Vdd power does not pass the pixels.

0090<figref idref="DRAWINGS">FIG. 9</figref> is a plan view of a pixel of an OLED according to another embodiment of the present invention, and <figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view taken along a line IV-IV of <figref idref="DRAWINGS">FIG. 9</figref>.

0091The pixel of an OLED in <figref idref="DRAWINGS">FIGS. 9 and 10</figref> does not include an additional Vdd line like the pixel of an OLED of <figref idref="DRAWINGS">FIGS. 7 and 8</figref>, and a first pattern unit <b>101</b><i>a </i>functions as the Vdd line.

0092Also, the drain electrode of a switching TFT M<b>2</b> is connected to a first electrode <b>131</b> of a capacitor unit Cst, and the first electrode <b>131</b> of the capacitor unit Cst is formed in one body with a gate electrode <b>112</b> of a driving TFT M<b>1</b>.

0093As depicted in <figref idref="DRAWINGS">FIGS. 9 and 10</figref>, a second electrode <b>132</b> of the capacitor unit Cst is electrically connected to the first pattern unit <b>101</b><i>a</i>, to which the Vdd power is supplied, via a first through hole <b>140</b>. Also, the second electrode <b>132</b> and a source electrode <b>113</b> of the driving TFT M<b>1</b> are formed in one body.

0094Other structures of <figref idref="DRAWINGS">FIGS. 9 and 10</figref> are the same as those of <figref idref="DRAWINGS">FIGS. 7 and 8</figref>, and thus, detailed descriptions thereof have been omitted.

0095According to the current embodiment of the present invention, the voltage drop of the capacitor unit Cst can be prevented since the second electrode <b>132</b> of the capacitor unit Cst, formed at the same time as the source and drain electrodes <b>113</b> and <b>114</b>, is electrically connected to the first pattern unit <b>101</b><i>a</i>, and also, the voltage drop of the Vdd power line can be prevented since the Vdd line that supplies a Vdd power does not pass the pixels.

0096<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of a CMOS device CM in the circuit region C of <figref idref="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention. Referring to <figref idref="DRAWINGS">FIG. 11</figref>, the CMOS device CM located in the circuit region C is formed in a region where the first pattern unit <b>101</b><i>a </i>is not formed.

0097That is, as depicted in <figref idref="DRAWINGS">FIG. 11</figref>, an insulating film <b>102</b> is formed on a substrate <b>100</b>, and a P type TFT T<b>1</b> and an N type TFT T<b>2</b> are formed on the insulating film <b>102</b>. Each of the P type TFT T<b>1</b> and the N type TFT T<b>2</b> can be formed at the same time as the driving TFT M<b>1</b>.

0098The P type TFT T<b>1</b> includes a semiconductor active layer <b>211</b> having source and drain regions <b>211</b><i>b </i>and a channel region <b>211</b><i>a</i>, a gate electrode <b>212</b> insulated from the semiconductor active layer <b>211</b>, and source and drain electrodes <b>213</b> contacting the source and drain regions <b>211</b><i>b </i>of the semiconductor active layer <b>211</b>.

0099The N type TFT T<b>2</b> includes a semiconductor active layer <b>221</b> having source and drain regions <b>221</b><i>b </i>and a channel region <b>221</b><i>a</i>, a gate electrode <b>222</b> insulated from the semiconductor active layer <b>221</b>, and source and drain electrodes <b>223</b> contacting the source and drain regions <b>221</b><i>b </i>of the semiconductor active layer <b>221</b>. LDD regions <b>221</b><i>c </i>are located between the source and drain regions <b>221</b><i>b </i>and the channel region <b>221</b><i>a. </i>

0100The CMOS devices CM can perform without interruption with a conductive film that supplies a Vdd power since the CMOS devices do not have the conductive film thereunder.

0101When the substrate <b>100</b> is a conductive substrate, the effect of the conductive substrate can be minimized when a Vdd power is supplied to the substrate <b>100</b> by forming the insulating film <b>102</b> thicker than the pixel region P.

0102The pixel region P and the circuit region C according to the present invention can be realized as depicted in <figref idref="DRAWINGS">FIG. 12</figref>. <figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional view of another substrate with respect to the cross-sectional view taken along line I-I of <figref idref="DRAWINGS">FIG. 1</figref> according to another embodiment of the present invention.

0103Referring to <figref idref="DRAWINGS">FIG. 12</figref>, a second pattern unit <b>101</b><i>b </i>is formed besides the first pattern unit <b>101</b><i>a</i>, and an insulating film <b>102</b> covering the first pattern unit <b>101</b><i>a </i>and the second pattern unit <b>101</b><i>b </i>is formed on the substrate <b>100</b>.

0104The second pattern unit <b>101</b><i>b </i>can be formed of any conductive material like the first pattern unit <b>101</b><i>a</i>, for example, a metal such as Al, Mo, Ag, Mg, W, Fe, Cr, Ni, Mn, etc.

0105As depicted in <figref idref="DRAWINGS">FIG. 12</figref>, the second pattern unit <b>101</b><i>b </i>located in a region corresponding to the circuit region C. <figref idref="DRAWINGS">FIG. 13</figref> is a plan view of pattern units of <figref idref="DRAWINGS">FIG. 12</figref> according to an embodiment of the present invention. As depicted in <figref idref="DRAWINGS">FIG. 13</figref>, the second pattern unit <b>101</b><i>b </i>can be patterned corresponding to electronic devices in the circuit region C. Like the example of the present invention, when a CMOS device is located in the circuit region C, a third pattern unit <b>101</b><i>c </i>and a fourth pattern unit <b>101</b><i>d </i>can be formed corresponding to active layers of a P type TFT T<b>1</b> and an N type TFT T<b>2</b> of the CMOS device.

0106<figref idref="DRAWINGS">FIG. 14</figref> is a cross-sectional view of a CMOS device CM in the circuit region C of <figref idref="DRAWINGS">FIG. 3</figref> according to another embodiment of the present invention. Referring to <figref idref="DRAWINGS">FIG. 14</figref>, the CMOS device CM located in the circuit region C is formed on the second pattern unit <b>101</b><i>b. </i>

0107That is, as depicted in <figref idref="DRAWINGS">FIG. 14</figref>, the third pattern unit <b>101</b><i>c </i>and the fourth pattern unit <b>101</b><i>d </i>are respectively formed on a substrate <b>100</b>, and after an insulating film <b>102</b> covering the third pattern unit <b>101</b><i>c </i>and the fourth pattern unit <b>101</b><i>d </i>is formed, a P type TFT T<b>1</b> and an N type TFT T<b>2</b> are formed on the insulating film <b>102</b>. The P type TFT T<b>1</b> and the N type TFT T<b>2</b> can be formed together with a driving TFT M<b>1</b>.

0108The P type TFT T<b>1</b> includes a semiconductor active layer <b>211</b> having source and drain regions <b>211</b><i>b </i>and a channel region <b>211</b><i>a</i>, a gate electrode <b>212</b> insulated from the semiconductor active layer <b>211</b>, and source and drain electrodes <b>213</b> contacted the source and drain regions <b>211</b><i>b </i>of the semiconductor active layer <b>211</b>.

0109The N type TFT T<b>2</b> includes a semiconductor active layer <b>221</b> having source and drain regions <b>221</b><i>b </i>and a channel region <b>221</b><i>a</i>, a gate electrode <b>222</b> insulated from the semiconductor active layer <b>221</b>, and source and drain electrodes <b>223</b> contacted the source and drain regions <b>221</b><i>b </i>of the semiconductor active layer <b>221</b>. LDD regions <b>221</b><i>c </i>are located between the source and drain regions <b>221</b><i>b </i>and the channel region <b>221</b><i>a. </i>

0110In the CMOS device CM, a positive voltage is supplied to the third pattern unit <b>101</b><i>c </i>located under the P type TFT T<b>1</b>, and a negative voltage is supplied to the fourth pattern unit <b>101</b><i>d </i>located under the N type TFT T<b>2</b> so that the third pattern unit <b>101</b><i>c </i>and the fourth pattern unit <b>101</b><i>d </i>respectively act as back gates. Although not depicted, the third pattern unit <b>101</b><i>c </i>is connected to the Vdd power line so that a positive Vdd voltage is supplied thereto, and the fourth pattern unit <b>101</b><i>d </i>is electrically connected to a cathode power source, which is another driving power source of an OLED, so that a negative voltage is supplied thereto.

0111In the circuit region C, the second pattern unit <b>101</b><i>b </i>is not limited thereto, but can be formed in various ways according to electronic devices located in the circuit region C. For example, when a PMOS TFT or an NMOS TFT exists in the circuit region C besides the CMOS device, an additional conductive pattern matching the TFT is formed, and a corresponding positive or negative voltage is supplied to the conductive pattern so that the conductive pattern can perform as a back gate.

0112In the present invention, the characteristics of electronic devices in the circuit region C can further be improved by forming conductive patterns performing as back gates in the circuit region C.

0113The flat panel display according to the present invention can provide the following advantages.

0114The voltage drop of a Vdd line caused by resistance of the Vdd line can be prevented, and at the same time, electronic devices in a circuit region can be prevented from reducing characteristics caused by a conductive film to which a Vdd power is supplied in the circuit region.

0115The voltage drop of a capacitor can be prevented since an electrode of a capacitor unit acts as a conductive film.

0116In the circuit region, the characteristics of the electronic devices can further be improved by forming conductive patterns corresponding to the electronic devices and corresponding voltages are supplied to the conductive patterns so that the conductive patterns can perform as back gates.

0117While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various modifications in form and detail can be made therein without departing from the spirit and scope of the present invention as defined by the following claims.