Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver

This application claims the benefit of the Korean Patent Application No. 10-2005-0094074, filed on Oct. 6, 2005, which is hereby incorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital telecommunications system, and more particularly, to a digital television (DTV) transmitter/receiver and a method of coding data in the DTV transmitter/receiver. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for modulating a digital television signal to a vestigial side band (VSB) mode and transmitting and receiving the VSB modulated digital television signal.

2. Discussion of the Related Art

Since the second half of 1998, the United States of America has adopted an advanced television systems committee (ATSC) 8T-VSB transmission method as the 1995 standard for broadcasting. Presently, the Republic of Korea is also providing broadcast programs by adopting the ATSC 8T-VSB transmission method as the standard for broadcasting. Accordingly, experimental broadcasting began in May 1995, and a test-broadcasting system began on Aug. 31, 2000.

<figref idrefs="DRAWINGS">FIG. 1</figref> illustrates a conventional ATSC 8T-VSB transmitting system. A data randomizer randomizes MPEG video/audio data that are inputted. A Reed-Solomon encoder Reed-Solomon encodes data so as to add a 20-byte parity code. A data interleaver interleaves the data. A trellis encoder converts the data from bytes to symbols and, then, trellis-encodes the converted data. A multiplexer (MUX) multiplexes a symbol column and synchronization signals, and a pilot inserter adds a pilot signal to the symbol column. A VSB modulator converts the symbol column to an 8VSB signal of an intermediate frequency bandwidth. And, a RF converter converts the VSB-converted signal to an RF bandwidth signal and transmits the RF bandwidth-converted signal to an antenna.

The 8T-VSB transmission mode, which is adopted as the standard for digital broadcasting in North America and the Republic of Korea, is a system that has been developed for the transmission of MPEG video/audio data. However, presently, the technology for processing digital signals is being developed at a vast rate, and, as a larger number of the population uses the Internet, digital electric appliances, computers, and the Internet are being integrated. Therefore, in order to meet with the various requirements of the users, a system that can add video/audio data through a digital television channel so as to transmit diverse additional information needs to be developed.

Some users may assume that additional data broadcasting would be applied by using a PC card or a portable device having a simple in-door antenna attached thereto. However, when used indoors, the intensity of the signals may decrease due to a blockage caused by the walls or disturbance caused by approaching or proximate mobile objects. Accordingly, the quality of the received digital signals may be deteriorated due to a ghost effect and noise caused by reflected waves. However, unlike the general video/audio data, when transmitting the additional data, the data that is to be transmitted should have a low error ratio. More specifically, in case of the video/audio data, errors that are not perceived or acknowledged through the eyes or ears of the user can be ignored, since they do not cause any or much trouble. Conversely, in case of the additional data (e.g., program execution file, stock information, etc.), an error even in a single bit may cause a serious problem. Therefore, a system highly resistant to ghost effects and noise is required to be developed.

The additional data are generally transmitted by a time-division method through the same channel as the MPEG video/audio data. However, with the advent of digital broadcasting, ATSC VSB digital television receivers that receive only MPEG video/audio data are already supplied to the market. Therefore, the additional data that are transmitted through the same channel as the MPEG video/audio data should not influence the conventional ATSC VSB receivers that are provided in the market. In other words, this may be defined as ATSC VSB compatibility, and the additional data broadcast system should be compatible with the ATSC VSB system. Herein, the additional data may also be referred to as enhanced data or E-VSB data. Furthermore, in a poor channel environment, the receiving quality of the conventional ATSC VSB receiving system may be deteriorated. More specifically, resistance to changes in channels and noise is more highly required when using portable and/or mobile receivers.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a digital television (DTV) transmitter and a method of coding data in the DTV transmitter that substantially obviate one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a digital television system that is suitable for transmitting additional data and that is highly resistant to noise.

Another object of the present invention is to provide a digital television system that can enhance a decoding performance of an additional data symbol.

A further object of the present invention is to provide a digital television (DTV) transmitter and a method of coding data in the DTV transmitter that can insert known data in a specific area of the additional data and transmitting the data to a transmitter/receiver, thereby enhancing the reception performance of the digital television system.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a digital television (DTV) transmitter for coding enhanced data for transmission includes a data formatter for generating an enhanced data packet including the enhanced data and a known data sequence, a data randomizer for randomizing the enhanced data packet, a Reed-Solomon (RS) encoder for RS-coding the randomized data packet by adding first parity data, a data interleaver for interleaving the RS-coded data packet, and a trellis encoding unit for trellis-encoding the interleaved data packet, wherein the trellis encoding unit may include a trellis-coded modulation (TCM) encoder for generating a first output bit by trellis-encoding a first input bit and generating a second output bit by bypassing the first input bit, and a pre-coder for generating a third output bit by pre-coding a second input bit, wherein memories included in the TCM encoder and the pre-coder are initialized when the known data sequence is inputted to the trellis encoding unit.

The trellis encoding unit may further include an initialization controller for generating initialization data bits required to initialize the memories of the TCM encoder and the pre-coder, and a multiplexer for replacing a portion of the known data sequence with the initialization data bits, wherein an output of the multiplexer is inputted to the TCM encoder and the pre-coder. And, the DTV transmitter may further include a backward-compatibility processor which generates second parity data based on the RS-coded data packet in which the portion of the known data sequence is replaced with the initialization data bits to reflect the replacement made by the multiplexer. Herein, the multiplexer further may replace the first parity data included in the interleaved data packet with the second parity data.

In another aspect of the present invention, a method of coding enhanced data for transmission in a digital television (DTV) transmitter includes generating an enhanced data packet including the enhanced data and a known data sequence, randomizing the enhanced data packet, Reed-Solomon (RS)-coding the randomized data packet by adding first parity data, interleaving the RS-coded data packet, and trellis-encoding the interleaved data packet using a trellis encoding unit which includes a trellis-coded modulation (TCM) encoder and a pre-coder, wherein trellis-encoding the interleaved data packet may include generating a first output bit by trellis-encoding a first input bit and generating a second output bit by bypassing the first input bit in the TCM encoder, generating a third output bit by pre-coding a second input bit in the pre-coder, and initializing memories included in the TCM encoder and the pre-coder when the known data sequence is inputted to the trellis encoding unit.

Herein, initializing memories included in the TCM and the pre-coder may include generating initialization data bits required to initialize the memories of the TCM encoder and the pre-coder, replacing a portion of the known data sequence with the initialization data bits, and inputting the known data sequence including the initialization data bits to the TCM encoder and the pre-coder. The trellis-encoding the interleaved data packet may further include generating second parity data based on the RS-coded data packet in which the portion of the known data sequence is replaced with the initialization data bits. The trellis-encoding the interleaved data packet may further include replacing the first parity data included in the interleaved data packet with the second parity data.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:

<figref idrefs="DRAWINGS">FIG. 1</figref> illustrates a block view of a conventional ATSC 8T-VSB transmitting system;

<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a structure of a general VSB transmission frame;

<figref idrefs="DRAWINGS">FIG. 3</figref> illustrates an overall block view of a digital television transmitter according to the present invention;

<figref idrefs="DRAWINGS">FIG. 4</figref> illustrates a block view of a data interleaver shown in <figref idrefs="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 5</figref> illustrates an operation example of the data interleaver shown in <figref idrefs="DRAWINGS">FIG. 3</figref> on the frame structure according to the present invention;

<figref idrefs="DRAWINGS">FIG. 6</figref> illustrates a detailed block view of a packet formatter shown in <figref idrefs="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 7</figref> illustrates a frame structure showing an example of inserting known data prior to interleaving according to the present invention;

<figref idrefs="DRAWINGS">FIG. 8</figref> illustrates the example of inserting known data by describing each corresponding segment;

<figref idrefs="DRAWINGS">FIG. 9</figref> illustrates a frame structure showing an example of inserting known data after interleaving according to the present invention;

<figref idrefs="DRAWINGS">FIG. 10</figref> illustrates a detailed block view of a trellis encoder according to an embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 11</figref> illustrates a detailed block view of an example of a trellis encoder shown in <figref idrefs="DRAWINGS">FIG. 10</figref>; and

<figref idrefs="DRAWINGS">FIG. 12</figref> illustrates a block view showing an overall structure of the digital television receiver according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In addition, although the terms used in the present invention are selected from generally known and used terms, some of the terms mentioned in the description of the present invention have been selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present invention is understood, not simply by the actual terms used but by the meaning of each term lying within.

In the present invention, the enhanced data may either consist of data including information such as program execution files, stock information, and so on, or consist of video/audio data. Additionally, the known data refer to data already known based upon a pre-determined agreement between the transmitter and the receiver. Furthermore, the main data consist of data that can be received from the conventional receiving system, wherein the main data include video/audio data.

<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates a structure of a general VSB transmission frame. Herein, one frame is configured of two fields. Each field includes one field synchronization segment and <b>312</b> data segments. The present invention relates to inserting known data in a predefined position within the data segment and transmitting the data, thereby enhancing the receiving performance of the digital television receiver.

<figref idrefs="DRAWINGS">FIG. 3</figref> illustrates an overall block view of a digital television (DTV) transmitter according to the present invention. The DTV transmitter includes an E-VSB pre-processor <b>301</b>, an E-VSB packet formatter <b>302</b>, a packet multiplexer <b>303</b>, a data randomizer <b>304</b>, an E-VSB post-processor <b>310</b>, a Reed-Solomon (RS) encoder <b>321</b>, a data interleaver <b>322</b>, a trellis encoding unit <b>323</b>, a backward-compatibility processor <b>324</b>, a frame multiplexer <b>325</b>, and a transmitter <b>330</b>. In the present invention having the above-described structure, main data are outputted to the packet multiplexer <b>303</b> in transport packet units, and enhanced data are outputted to the E-VSB pre-processor <b>301</b>. The E-VSB pre-processor <b>301</b> pre-processes the enhanced data, such as encoding additional error correction and inserting null data bits, and then outputs the pre-processed enhanced MPEG stream to the E-VSB packet formatter <b>302</b>.

The E-VSB packet formatter <b>302</b> aligns the pre-processed data and the pre-defined known data on a specific position of the packet in accordance with a set rule. Thereafter, the E-VSB packet formatter <b>302</b> outputs the aligned data to the packet multiplexer <b>303</b> in even packet units. The detailed operation of the E-VSB packet formatter <b>302</b> will be described in a later process. Furthermore, the packet multiplexer <b>303</b> multiplexes the enhanced data packet and the main data packet in accordance with a pre-defined multiplexing rule, the enhanced MPEG packet having the known data inserted therein and transmitted from the E-VSB packet formatter <b>302</b>. Then, the multiplexed data passes through the data randomizer <b>304</b> and is outputted to the E-VSB post-processor <b>310</b>. Herein, the E-VSB post-processor <b>310</b> includes a Reed-Solomon (RS) encoder <b>311</b>, a data interleaver <b>312</b>, an E-VSB convolutional encoder <b>313</b>, a data deinterleaver <b>314</b>, and a RS byte remover <b>315</b>. The RS encoder <b>311</b> RS-codes the data outputted from the data randomizer <b>304</b>. Thereafter, the RS encoder <b>311</b> adds a 20-byte parity data and outputs the data to the data interleaver <b>312</b>.

<figref idrefs="DRAWINGS">FIG. 4</figref> illustrates a block view of the data interleaver <b>312</b>, shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, according to an embodiment of the present invention. In this example, a convolutional interleaver having 52 branches and a unit memory byte number of M=4 is described. In the data interleaver <b>312</b>, when a first byte is inputted, the inputted first byte is directly outputted through a first branch, and a second byte is inputted through a second branch. Accordingly, a value prior to 52*4 bytes is outputted.

<figref idrefs="DRAWINGS">FIG. 5</figref> illustrates an operation example of the data interleaver shown in <figref idrefs="DRAWINGS">FIG. 3</figref> on the frame structure according to the present invention. Herein, the data is inputted in segment units from top to bottom, and the byte within the segment is inputted first to the left side and then to the right side. The numbers shown in <figref idrefs="DRAWINGS">FIG. 5</figref> indicate the outputted order from the interleaver. The data interleaver <b>312</b> is operated in units of 52 segments. The output data of the data interleaver <b>312</b> are outputted to the E-VSB convolutional encoder <b>313</b>, wherein the output data is E-VSB convolutional encoded. Then, the E-VSB convolutional encoded data pass through the data interleaver <b>314</b> and are outputted to the RS byte remover <b>315</b>, thereby removing (or deleting) the 20-byte parity. This is to recalculate the parity since the original data has been modified by the E-VSB convolutional encoder <b>313</b>.

More specifically, the output of the RS byte remover <b>315</b> is inputted to the RS encoder <b>321</b> so as to be RS-coded. Then, after the 20-byte parity is added once again, the data is outputted to the data interleaver <b>322</b>. The operation of the data interleaver <b>322</b> can be easily understood by referring to <figref idrefs="DRAWINGS">FIG. 3</figref> and <figref idrefs="DRAWINGS">FIG. 4</figref>. Therefore, a detailed description of the same will be omitted for simplicity.

The output of the data interleaver <b>322</b> is inputted to the trellis encoding unit <b>323</b>. The trellis encoding unit <b>323</b> encodes the inputted 2 bits to 3 bits and outputs the encoded data (i.e., 3 bits) to the frame multiplexer <b>325</b>. In order to make the data outputted from the trellis encoding unit <b>323</b> as the known data defined from the DTV transmitter/receiver, a memory within the trellis encoding unit <b>323</b> needs to be initialized with respect to the known data inserted in the enhanced packet. At this point, initialization is performed by a new set of data and not by the input data. Therefore, a new RS parity should be created and be replaced with the initial parity data. More specifically, this operation is performed by the backward-compatibility processor <b>324</b>. The initialization process of the trellis encoding unit <b>323</b> and the operation of the backward-compatibility processor <b>324</b> will also be described in detail in a later process.

The output of the trellis encoding unit <b>323</b> is inputted to the frame multiplexer <b>325</b>. Then, the frame multiplexer <b>325</b> inserts field and segment synchronization signals to the output data of the trellis encoding unit <b>323</b> and outputs the data to the transmitter <b>330</b>. The transmitter <b>330</b> includes a pilot inserter <b>331</b>, a VSB modulator <b>333</b>, and a radio frequency (RF) converter <b>334</b>. Since this structure is similar to the transmitting system of <figref idrefs="DRAWINGS">FIG. 1</figref>, a detailed description of the same will be omitted for simplicity.

Hereinafter, the operation of the packet formatter <b>302</b> will be described in detail. <figref idrefs="DRAWINGS">FIG. 6</figref> illustrates a detailed block view of the packet formatter shown in <figref idrefs="DRAWINGS">FIG. 3</figref> according to an embodiment of the present invention. The packet formatter <b>302</b> includes a known data generator <b>511</b> and a multiplexer <b>513</b>. The known data generator <b>511</b> creates the known data, and the multiplexer <b>513</b> multiplexes and outputs the data pre-processed by the E-VSB pre-processor <b>301</b> and the MPEG header byte. More specifically, the multiplexed and outputted known data are interleaved and trellis-encoded from the transmitting end, thereby being transmitted to the receiving end. In the VSB transmission frame structure of the receiving end, the frame structure being the last step prior to the final transmission, the transmitted known data is used as a separate reference data other than the synchronization data in a channel equalizer and a demodulator. Herein, in the related art receiver, only the synchronization data are used as the reference data. Thus, the receiving performance can be enhanced. Additionally, the output of the packet formatter <b>302</b> is outputted in 188-byte units. The first 4 bytes correspond to the MPEG header byte. And, the known data and the output data of the E-VSB pre-processor are multiplexed in the remaining 184 bytes.

<figref idrefs="DRAWINGS">FIG. 7</figref> illustrates a frame structure showing an example of inserting known data prior to interleaving according to the present invention. However, this does not correspond to the final frame that is to be transmitted. In other words, <figref idrefs="DRAWINGS">FIG. 7</figref> illustrates a portion of the data segments within the frame and, more specifically, illustrates an example of the known data being inserted by the packet formatter <b>302</b>. For a better understanding and simplicity of the description of the present invention, the frame structure shown in the example of <figref idrefs="DRAWINGS">FIG. 7</figref> consists of 52 segments, which corresponds to an interleaving depth.

Referring to <figref idrefs="DRAWINGS">FIG. 7</figref>, the frame structure broadly consists of 4 data areas. More specifically, the frame structure consists of a header area <b>701</b>, a payload area <b>702</b> in which only the E-VSB data can be present, a parity area <b>703</b>, and a known data area <b>704</b> in which the known data can be present. Herein, the known data area is divided into a first area <b>705</b> in which the trellis encoder can be initialized, and a second area <b>706</b> in which the trellis encoder cannot be initialized.

The first area <b>705</b> in which the trellis encoder can be initialized corresponds to a position of the bytes that are outputted from the data interleaver earlier than the parity bytes of the corresponding segment. At this point, when the inputted data is changed from the enhanced data or main data to the known data, a portion or all of the data in the first area <b>705</b> is replaced with an initialization data and inputted to the memory of the trellis encoding unit <b>323</b>. A portion of all of the first area <b>705</b> in which the trellis encoder can be initialized may include the known data and/or the enhanced data.

The second area <b>706</b> in which the trellis encoder cannot be initialized may include the known data or the general enhanced data. Herein, the area size of both data types may be adequately modified by the designer of the present invention. In other words, the amount of the known data and that of the enhanced data is relative to one another. Furthermore, the size of the first area <b>705</b> and the size of the second area <b>705</b> may differ in each segment.

In the example shown in the preferred embodiment of the present invention, the size of each area differs in accordance with a segment order within a VSB data field. <figref idrefs="DRAWINGS">FIG. 8</figref> illustrates the example of inserting known data by describing each corresponding segment. This is to enable, after a data interleaving process, the known data of each segment to be gathered (or grouped) in a specific area. For example, when the interleaving depth of a segment is 52, and when the order (e) of the segment is equal to or higher than 13 and equal to or lower than 30 (i.e., 13≦e≦30), the segment sequentially includes a header area, an area in which the trellis encoder cannot be initialized, an area in which the trellis encoder can be initialized, and a payload area. This order is repeated 4 times, and thereafter, a parity area is included.

When data is interleaved in the above-described structure by the data interleaver <b>322</b>, the corresponding frame structure is as shown in <figref idrefs="DRAWINGS">FIG. 9</figref>. More specifically, <figref idrefs="DRAWINGS">FIG. 9</figref> illustrates a frame structure showing an example of inserting known data after interleaving according to the present invention. Referring to <figref idrefs="DRAWINGS">FIG. 9</figref>, the data of the header areas are first included, and then the data of the known data areas are included. In other words, the known data which were scattered in each segment prior to the data interleaving process are grouped in a plurality of segments after the data interleaving process. The known data areas are followed by data of the parity areas and the data of the payload areas.

<figref idrefs="DRAWINGS">FIG. 10</figref> illustrates a detailed block view of a trellis encoder according to an embodiment of the present invention. More specifically, <figref idrefs="DRAWINGS">FIG. 10</figref> is an example of a detailed block view of the trellis encoding unit <b>323</b> that can be initialized and that trellis-encodes the data interleaved by the data interleaver as shown in <figref idrefs="DRAWINGS">FIG. 9</figref>. Referring to FIG. <b>10</b>, the trellis encoding unit <b>323</b> includes a multiplexer <b>611</b>, a trellis encoder <b>612</b>, and an initialization controller <b>613</b>. The multiplexer <b>611</b> multiplexes and outputs the interleaved data, the parity bytes outputted from the backward-compatibility processor <b>324</b>, and the initialization data bits in accordance with a predetermined rule. The initialization controller <b>613</b> generates initialization data bits for initializing the memory of the trellis encoder <b>612</b>, so as to output the generated initialization data bits to the multiplexer <b>611</b> and the backward-compatibility processor <b>324</b>.

More specifically, when the interleaved data are the known data, and the known data are positioned at the beginning of the known data sequence, to which data is consecutively inputted, then initialization of the trellis encoding unit <b>323</b> is required. More specifically, when a known data sequence is inputted to the trellis encoder <b>612</b> as the input data, various types of output sequences may be obtained depending upon the memory state of the trellis encoder <b>612</b>. Therefore, by first initializing the trellis encoder <b>612</b> to a predetermined value, when the known data sequence begins, and then inputting the known data, the known data output sequence may be obtained from the output of the trellis encoder <b>612</b>. Accordingly, when the memory of the trellis encoder <b>612</b> is required to be initialized, a portion of the known data should be replaced with the initialization data bits and outputted to the trellis encoder <b>612</b>. Accordingly, the memory of the trellis encoder <b>612</b> is initialized by the initialization data bits, and the output of the trellis encoder <b>612</b> includes the known data coded with a pattern desired by the DTV transmitter/receiver.

When the interleaved and outputted data are the known data, and when initialization is required, the multiplexer <b>611</b> replaces a portion of the interleaved data with the initialization data bits and outputs the data to the trellis encoder <b>612</b>. Additionally, on the parity position within each enhanced data segment, the multiplexer <b>611</b> outputs the parity data outputted from the backward-compatibility processor <b>324</b> to the trellis encoder <b>612</b>. In other instances, the multiplexer <b>611</b> outputs the interleaved data to the trellis encoder <b>612</b>. Thereafter, the trellis encoder <b>612</b> trellis-encodes the data outputted from the multiplexer <b>611</b> by symbol units. Herein, each symbol consists of 2 bits. For simplicity of the description, among the 2 bits, the upper bit will be referred to as ‘d<b>1</b>’, and the lower bit will be referred to as ‘d<b>0</b>’.

<figref idrefs="DRAWINGS">FIG. 11</figref> illustrates a detailed block view of an example of the trellis encoder <b>612</b> shown in <figref idrefs="DRAWINGS">FIG. 10</figref>. Herein, the trellis encoder <b>612</b> receives 2 input bits (d<b>1</b>, d<b>0</b>). Then, after coding (or encoding) the 2 input bits (d<b>1</b>, d<b>0</b>), the trellis encoder <b>612</b> outputs 3 bits (c<b>2</b>, c<b>1</b>, c<b>0</b>). Accordingly, the trellis encoder <b>612</b> includes a trellis coded modulation (TCM) encoder <b>621</b>, and a pre-coder <b>622</b>. Herein, the lower bit do of the input symbol is inputted to the TCM encoder <b>621</b>, and the upper bit d<b>1</b> of the input symbol is inputted to the pre-coder <b>622</b>. The TCM encoder <b>621</b> includes a line bypassing the input bit d<b>0</b> to a second output bit c<b>1</b>, a memory m<b>1</b> temporarily storing and outputting a first output bit c<b>0</b> that is fed-back, an adder adding the input bit d<b>0</b> to the memory m<b>1</b> and outputting the added bit, and a memory m<b>0</b> temporarily storing the bit outputted from the adder and outputting the bit as a first output bit c<b>0</b> and feeding-back the output bit to the memory m<b>1</b>.

The pre-coder <b>622</b> includes an adder, and a memory m<b>2</b>. The adder adds the input bit d<b>1</b> to the signal that is fed-back and outputting the input bit-added signal as a third output signal c<b>2</b>. And, the memory m<b>2</b> temporarily stores the third output signal c<b>2</b> that is outputted from the adder and feeds-back the adder. At this point, each memory (i.e., m<b>0</b> to m<b>2</b>) is provided with the same clock and operated in synchronization with the clocks

In the structure shown in <figref idrefs="DRAWINGS">FIG. 11</figref>, the lower bit d<b>0</b> is directly outputted as the second output bit c<b>1</b>. Simultaneously, the lower bit do is trellis-encoded by the two memories m<b>0</b> and m<b>1</b> and the adder of the TCM encoder <b>621</b>, so as to be outputted as the first output bit c<b>0</b>. The upper bit d<b>1</b> is pre-coded by the adder and the memory m<b>2</b> of the pre-coder <b>622</b>, so as to be outputted as the third bit c<b>2</b>. Therefore, the state of the memory m<b>2</b> of the trellis encoder <b>612</b> is determined only by the upper bit d<b>1</b>, and the state for each of the memories m<b>1</b> and m<b>0</b> is determined only by the lower bit d<b>0</b>.

As shown in <figref idrefs="DRAWINGS">FIG. 11</figref>, only one d<b>1</b> bit is required for initializing the memory m<b>2</b> of the trellis encoder <b>612</b> to a pre-determined value, and two d<b>0</b> bits are required for initializing the memory m<b>1</b> and m<b>0</b> of the trellis encoder <b>612</b> to a pre-determined value. Therefore, in order to initialize the memories m<b>2</b>, m<b>1</b>, and m<b>0</b> of the trellis encoder <b>612</b>, at least 2 input symbols are required.

Table 1 shown below describes the input of two symbols required for initializing the memory from an arbitrary m<b>2</b>m<b>1</b>m<b>0</b> state to a 000 state.

<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="42pt" align="left" /><colspec colname="1" colwidth="35pt" align="center" /><colspec colname="2" colwidth="140pt" align="center" /><thead><row>&lt;entry /&gt;<entry namest="offset" nameend="2" rowsep="1">TABLE 1</entry></row><row>&lt;entry /&gt;<entry namest="offset" nameend="2" align="center" rowsep="1" /></row><row>&lt;entry /&gt;<entry>m2m1m0</entry><entry>1^std1d0/2^ndd1d0</entry></row><row>&lt;entry /&gt;<entry namest="offset" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row>&lt;entry /&gt;<entry>0 0 0</entry><entry>00/00 or 10/10</entry></row><row>&lt;entry /&gt;<entry>0 0 1</entry><entry>00/01 or 10/11</entry></row><row>&lt;entry /&gt;<entry>0 1 0</entry><entry>01/00 or 11/10</entry></row><row>&lt;entry /&gt;<entry>0 1 1</entry><entry>01/01 or 11/11</entry></row><row>&lt;entry /&gt;<entry>1 0 0</entry><entry>00/10 or 10/00</entry></row><row>&lt;entry /&gt;<entry>1 0 1</entry><entry>00/11 or 10/01</entry></row><row>&lt;entry /&gt;<entry>1 1 0</entry><entry>01/10 or 11/00</entry></row><row>&lt;entry /&gt;<entry>1 1 1</entry><entry>01/11 or 11/01</entry></row><row>&lt;entry /&gt;<entry namest="offset" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Herein, for example, when the state is m<b>2</b>m<b>1</b>m<b>0</b>=111, in order to initialize the status 111 to 000, the d<b>1</b>d<b>0</b> input symbol should be consecutively inputted as 01, 11 or as 11, 01.

Accordingly, the initialization controller <b>613</b> receives the state value of the memory m<b>2</b>m<b>1</b>m<b>0</b> in the trellis encoder. Thereafter, the initialization controller <b>613</b> creates (or generates) an input symbol sequence required for the initialization by referring to Table 1 and outputs the input symbol sequence to the multiplexer <b>611</b>. More specifically, when initialization of the memory is required, the initialization controller <b>613</b> verifies the state of the memory m<b>2</b>m<b>1</b>m<b>0</b> and refers to Table 1, so as to generate (or create) and output the initialization data bits to the multiplexer <b>611</b>. At this point, 12 trellis encoders are included in the VSB transmitting system. Further, since 2 symbols are required for initializing the memory of each trellis encoder, a total of 24 input symbols are first used for initializing when the known data sequence begins. Conversely, it can be easily estimated that when the state to which the memory is to be initialized is not 000, two other symbol sequences different from the ones shown in Table 1 are required. Therefore, a detailed description of the same will be omitted for simplicity.

The initialization controller <b>613</b> outputs the initialization data bits to the backward-compatibility processor <b>324</b>. More specifically, since the memory is initialized by a new set of data and not by the interleaved data, the RS parity should be newly created and replaced with the original (or initial) parity data. This operation is performed by the backward-compatibility processor <b>324</b>. Herein, the backward-compatibility processor <b>324</b> receives the output of the RS encoder <b>321</b> and the output of the initialization controller <b>613</b> within the trellis encoding unit <b>323</b>, thereby creating a 20-byte parity and outputting the created parity to the multiplexer <b>611</b>. The output of the trellis encoding unit <b>323</b> is outputted to the frame multiplexer <b>325</b>. Thereafter, the frame multiplexer <b>325</b> inserts field and segment synchronization signals to the output data of the trellis encoding unit <b>323</b>, which are then transmitted through the transmitter <b>330</b>.

<figref idrefs="DRAWINGS">FIG. 12</figref> illustrates a block view showing an overall structure of the digital television receiver according to an embodiment of the present invention. More specifically, <figref idrefs="DRAWINGS">FIG. 12</figref> illustrates an example of a VSB receiving system that receives data transmitted from the VSB transmitting system, shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, and that demodulates and equalizes the received data so as to restore the transmitted data. The VSB receiving system includes a tuner <b>711</b>, a demodulator <b>712</b>, an equalizer <b>713</b>, a known data (or sequence) detector <b>714</b>, a Viterbi decoder <b>715</b>, a deinterleaver <b>716</b>, a Reed-Solomon (RS) decoder <b>717</b>, and a derandomizer <b>718</b>, The VSB receiving system also includes a main packet remover <b>719</b>, a E-VSB packet deformatter <b>720</b>, and an E-VSB data processor <b>721</b>.

The tuner <b>711</b> tunes the frequency of a particular channel. Subsequently, the tuner <b>711</b> down-converts the tuned frequency and outputs the tuned channel frequency to the demodulator <b>712</b>. The demodulator <b>712</b> performs carrier wave restoration and timing restoration of the tuned channel frequency wave, and outputs the processed channel frequency wave to the equalizer <b>713</b>. The equalizer <b>713</b> performs compensation for any channel distortion included in the demodulated signal and outputs the compensated signal to the Viterbi decoder <b>715</b>.

At this point, the known data detector <b>714</b> detects the known data, which have been inserted by the transmitting end, from the output data of the demodulator <b>712</b>. Then, the known data detector <b>714</b> outputs the detected known data to the demodulator <b>712</b> and the equalizer <b>713</b>. When the demodulator <b>712</b> uses the known data during the timing recovery or the carrier recovery, the demodulating performance may be enhanced. Similarly, when the equalizer <b>713</b> uses the known data for the channel equalization, the equalization performance may be enhanced.

The output of the equalizer <b>713</b> passes through the Viterbi decoder <b>715</b>, the deinterleaver <b>716</b> the RS decoder <b>717</b>, and the derandomizer <b>718</b>. Thereafter, the output data is outputted to a main MPEG decoder (not shown) and simultaneously outputted to the main packet remover <b>719</b>. The Viterbi decoder <b>715</b> Viterbi decodes the data outputted from the equalizer <b>713</b> and converts the Viterbi decoded data to bytes. Thereafter, the converted data are outputted to the deinterleaver <b>716</b>. The deinterleaver <b>716</b> performs an inverse process of the data interleaver of the DTV transmitter and outputs the deinterleaved data to the RS decoder <b>717</b>. The RS decoder <b>717</b> decodes the output of the deinterleaver <b>716</b> and removes the parity data from the input data and outputs the parity-removed data to the derandomizer <b>718</b>.

The derandomizer <b>718</b> performs an inverse process of the randomizer of the DTV transmitter on the output of the RS decoder <b>717</b>. Thereafter, the derandomizer <b>718</b> inserts the MPEG synchronization byte in the beginning of each packet, thereby outputting the data in 188-byte packet units. The output of the derandomizer <b>718</b> is simultaneously outputted to the main MPEG decoder (not shown) and to the main data packet remover <b>719</b>. Herein, the main MPEG decoder only decodes the packet(s) corresponding to the main MPEG. If the packet ID is a null packet ID or a reserved packet ID, which was used for the enhanced data packet, the main MPEG decoder does not perform the decoding process.

In the meantime, the main data packet remover <b>719</b> removes the 188-byte unit main data packet from the data outputted from the derandomizer <b>718</b> and outputs the processed data to the E-VSB packet deformatter <b>720</b>. Subsequently, the E-VSB packet deformatter <b>720</b> removes (or deletes) the 4-byte MPEG header and the known data place holder byte (or the known data byte) from the 188-byte packet outputted from the main data packet remover <b>719</b>. Thereafter, the E-VSB packet deformatter <b>720</b> outputs the processed data to the E-VSB data processor <b>721</b>. The E-VSB data processor <b>721</b> performs an inverse process of the E-VSB pre-processor <b>301</b> of the transmitting system, so as to process the data outputted from the E-VSB packet deformatter <b>720</b>. Subsequently, the E-VSB data processor <b>721</b> outputs the final output data.

As described above, the digital television (DTV) transmitter and the method of coding data in the DTV transmitter according to the present invention have the following advantages. More specifically, the DTV transmitter/receiver is highly protected against (or resistant to) any error that may occur when transmitting additional data through a channel, and the DTV transmitter/receiver is also highly compatible to the conventional VSB system. The present invention may also receive the additional data without any error even in channels having severe ghost effect and noise. Additionally, by inserting known data in a specific area of the data area and transmitting the processed data, the receiving performance of the DTV receiver liable to a frequent change in channel may be enhanced. Finally, the present invention is even more effective when applied to mobile and portable receivers, which are also liable to a frequent change in channel and which require protection (or resistance) against intense noise.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.