Method of phase shifting bits in a digital signal pattern

CROSS-REFERENCE TO RELATED APPLICATIONS

p-0002Not applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

p-0003Not applicable.

REFERENCE TO MICROFICHE APPENDIX

p-0004Not applicable.

BACKGROUND OF THE INVENTION

p-0005Jitter is the deviation from an ideal timing edge of the actual timing edge in a sequence of data bits that occurs at high frequencies (typically at frequencies greater than the bit rate divided by 2,500; however, other definitions of jitter, such as timing errors occurring above 10 MHz or timing errors that are not tracked by clock recovery). Jitter in a digital system is essentially a timing error that can affect the timing allocation within a bit cell. Jitter is typically measured at the differential zero crossings for balanced electrical signals, at the average voltage level for unbalanced signals, and at the average optical power level for optical signals. Jitter is often used as a figure of merit, and tracking jitter-induced errors over a period of time can provide an indication of system stability.

p-0006There are various types of jitter, such as random jitter, periodic jitter, and data-dependent jitter (“DDJ”). DDJ produces different amounts of jitter for different digital outputs. For example, a digital output of “00010001” would have a different amount of DDJ than a digital output of “11001100” from the same digital source because the latter digital output has more transitions, and hence contains more high-frequency components in its spectrum. The digital patterns with higher frequency content will be attenuated and phase shifted relative to the lower frequency patterns. Determining the level(s) and type(s) of jitter are important in characterizing components used in digital systems. In general, digital systems having higher transmission rates (typically expressed in Mb/s or Gb/s) have timing margins that are less tolerant to jitter.

p-0007There are a variety of techniques and instruments used for measuring jitter, such as real-time high-speed oscilloscopes, time sampling oscilloscopes, time interval analyzers, bit error ratio testers (“BERTs”), and digital communication analyzers (“DCAs”); however, different techniques often do not show good agreement. In other words, the jitter measured using one technique does not equal the jitter measured using another technique.

p-0008Variations in the frequency response of the test system can affect the measured jitter. For example, a test pattern source might have an output amplifier with a bandwidth that limits high-frequency components of jitter, or the test pattern source might have significant unquantified jitter. Similarly, the test receiver might contribute uncalibrated jitter that dominates a jitter measurement.

p-0009In telecommunications (e.g. SONET/SDH/OTN) and enterprise (e.g. Ethernet) applications, jitter specifications and measurements are documented through standards bodies. In the high-speed I/O arena, many new bus standards are being introduced with little commonality in specifying and measuring jitter. Similarly, characterization of high-speed serial electrical backplanes is gaining increased attention as their use increases for high-bandwidth interconnections. Jitter is often the limiting factor for electrical backplanes operating in the 1-10 Gb/s range.

BRIEF SUMMARY OF THE INVENTION

p-0010A method of phase shifting bits in a digital signal pattern combines a bit-wise phase-shift signal with an external clock signal to produce a perturbed clock signal. The perturbed clock signal is provided to a digital pattern source to generate a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0011<figref idrefs="DRAWINGS">FIG. 1A</figref> shows a jitter reference source.

p-0012<figref idrefs="DRAWINGS">FIG. 1B</figref> shows the jitter reference source of <figref idrefs="DRAWINGS">FIG. 1A</figref> in a digital test system.

p-0013<figref idrefs="DRAWINGS">FIG. 2</figref> shows a series of plots representing voltage versus time (both in arbitrary units) for the outputs from the BERT modules, and for the output of the power combiner shown in <figref idrefs="DRAWINGS">FIG. 1A</figref>.

p-0014<figref idrefs="DRAWINGS">FIG. 3</figref> shows plots of voltage versus time (both in arbitrary units) illustrating how V_SUMperturbs the sine wave output V_SYNTHof the synthesizer.

p-0015<figref idrefs="DRAWINGS">FIG. 4A</figref> is a flow chart of a method of phase shifting bits in a digital signal pattern.

p-0016<figref idrefs="DRAWINGS">FIG. 4B</figref> is a flow chart of a method of phase shifting bits in a digital signal pattern to compensate for DDJ in the digital signal pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

h-0008I. An Exemplary Jitter Reference Source

p-0017<figref idrefs="DRAWINGS">FIG. 1A</figref> shows a jitter reference source <b>10</b>. The jitter reference source includes a multi-channel digital pattern generator <b>12</b>, such as a parallel BERT (“ParBERT”). One example of a suitable ParBERT is the MODEL 81250 available from AGILENT TECHNOLOGIES, INC., of Palo Alto, Calif. The multi-channel digital pattern generator is alternatively an application-specific integrated circuit (“ASIC”) or programmable logic device, such as a field-programmable gate array (“FPGA”).

p-0018The multi-channel digital pattern generator <b>12</b> includes five ParBERT modules (B₀, B₁, B₂, B₃, B₄, also known as “channels”) <b>14</b>, <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b> and a clock module <b>24</b>. ParBERT module B₀<b>14</b> is a digital pattern source, and is clocked by the clock module <b>24</b>. The other ParBERT modules B₁, B₂, B₃, B₄produce synchronous digital signal patterns at different power levels that are combined in power combiners <b>26</b>, <b>28</b>, <b>30</b>. The correction channels are synchronized to each other and to the digital pattern source module B₀<b>14</b>. The power combiners are also known as “power splitters”, such as two-resistor and three-resistor power splitters/combiners. The four correction ParBERT channels are summed together in the binary ladder arrangement of the power combiners to give a variable compensation voltage that can be changed on a bit-by-bit basis. These ParBERT modules will be referred to as “correction channels” because their outputs are used to correct DDJ in the digital pattern source module <b>14</b> and/or a DUT in a test system. Alternatively, the outputs of the correction channels are used to simulate DDJ in a digital signal from the digital pattern source module.

p-0019The output <b>32</b> of the binary ladder is referred to as “power”, but is expressed in Volts, as is common in the art when using high-frequency systems having a characteristic system impedance, such as a fifty-ohm system impedance. For example, if the digital pattern output of B₁varies between −X Volts and X Volts, the digital pattern output of B₂varies between −X/2 Volts and X/2 Volts, the digital pattern output of B₃varies between −X/4 Volts and X/4 Volts, and the digital pattern output of B₄varies between −X/8 Volts and X/8 Volts, these four BERT channels provide a resolution of 1 part in 16 (i.e. 2ⁿsteps). More channels would provide greater resolution.

p-0020The output <b>32</b> of the last power combiner <b>30</b> is applied to an external clock signal <b>34</b> using a power combiner <b>36</b> to produce a perturbed clock signal <b>40</b>. The external clock signal is a sine wave generated by an external clock source <b>38</b>, such as a synthesizer or signal generator. The perturbed clock signal <b>40</b> is provided to the clock module <b>24</b> of the ParBERT, which distributes the perturbed clock signal <b>40</b> to the ParBERT modules <b>14</b>, <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b>. The digital pattern source module <b>14</b> generates a digital signal pattern <b>42</b> with timing changes arising from the perturbed clock signal <b>40</b>. In an alternative embodiment, the digital pattern source module <b>14</b> and clock module <b>24</b> are not part of the ParBERT, and a different clock signal, such as the unperturbed external clock signal <b>34</b>, is provided to the other ParBERT modules <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b>; however, the source output and the correction channels typically share a common timebase.

p-0021For example, an unperturbed clock signal is provided to the source output module, which generates a selected digital output pattern that is provided to a DUT (not shown). The digital output from the DUT is measured with a DCA (not shown) and the bit pattern with the worst-case DDJ is determined by evaluating the measured data. The worst-case DDJ is presumed to occur (assuming the DCA has much less DDJ than the digital source and/or the DUT) where the timing of the measured data deviates the most from the average timing. In other words, if the average timing of digital pulses in the measured data is 0.5 ps behind the nominal clock signal, perhaps from cable delay, for example, and a particular data sequence produces 2.5 ps of delay at a pulse edge (transition), then the DDJ is about 2.0 ps. If no other data sequence produces greater than 2.5 ps delay, that particular data sequence produces the worst-case DDJ. Data sequences that are not included in the digital output pattern from the source output module might produce different worst-case DDJ in alternative situations.

p-0022A digital level sufficient to correct the DDJ for the worst-case data sequence in the digital output pattern is determined. The appropriate digital level is determined by evaluating the slope of the sine wave output <b>34</b> from the external clock source <b>38</b> at the clock trigger voltage, and summing sufficient voltage with the sine wave output to phase-shift the timing of the transition to occur closer to the average pulse timing. In the embodiment illustrated in <figref idrefs="DRAWINGS">FIG. 1</figref>, the value is less than 2X when all correction channels are driven together. For example, if the output of B₁is X Volts, the output of B₂is X/2 Volts, the output of B₃is X/4 Volts and the output of B₄is X/8 Volts, then the output <b>32</b> of the binary ladder is 1⅞X Volts. The BERT modules <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b> are synchronized and de-skewed so that transitions on each of the correction channels align with a clock edge. If the pulses from the correction channels are sufficiently long, then perfect timing alignment is not required. In general, it is desirable that the sum of the outputs from the correction channels is settled (stable) when the clock trigger voltage is reached.

p-0023The sine wave (external clock signal <b>34</b>) from the external clock source <b>38</b> has a fairly slow risetime. Summing a positive digital voltage level (ref. <figref idrefs="DRAWINGS">FIGS. 2 and 3</figref>) through the power combiner <b>36</b> varies the edge timing of the perturbed clock signal <b>40</b> by raising the total voltage of the perturbed clock signal, thus changing the time at which the perturbed clock signal reaches the trigger voltage of the clock module <b>24</b>. The shift in the clock edge timing depends on the amplitude of the perturbing signal (e.g. voltage of output <b>32</b>) and the slope of the sine wave near the edge trigger voltage. A steeper slope will have less effect on the edge timing of the clock signal for a given digital voltage level. An alternative to summing multiple digital correction channels and adding them to a clock signal is to use a phase-shifter, such as a varactor-tuned delay line, to shift (perturb) the edge timing of the clock signal from the clock module <b>24</b>. A phase shifter is particularly desirable at fixed clock frequencies when relatively wide (e.g. about 2 pico-seconds (“ps”) to about 20 ps) timing edge shifts are desired.

p-0024In an alternative embodiment of the current invention, a quadrature hybrid coupler is used instead of a simple power combiner to produce the perturbed clock signal <b>40</b>. In this implementation, the quadrature hybrid coupler <b>36</b> produces a sine wave output and a cosine wave output from a continuous wave input (e.g. the clock signal <b>34</b>).

p-0025An optional arbitrary waveform generator <b>44</b> provides an arbitrary or pseudo-random waveform to the FM input <b>46</b> of the synthesizer <b>38</b>. The arbitrary waveform generator <b>44</b> is synchronized with the ParBERT <b>12</b>. The signal <b>48</b> from the arbitrary waveform generator <b>44</b> simulates periodic jitter, which is sometimes due to what is called Mux jitter and typically is at a frequency of some small number of bits (e.g. the bit rate divided by 16) and random jitter, which is typically on the order of about every 1000 bits and is typically negligible. In comparison, the DDJ is typically the largest jitter component in a high-bandwidth BERT, and can be about 10 ps at about 2-20 GHz, for example.

p-0026<figref idrefs="DRAWINGS">FIG. 1B</figref> shows the jitter reference source of <figref idrefs="DRAWINGS">FIG. 1A</figref> in a digital test system <b>50</b>. The ParBERT modules <b>14</b>, <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b> of the ParBERT <b>12</b> receive a common clock signal <b>40</b> from the clock module <b>24</b>. The outputs of the correction channels (ParBERT modules) <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b> are summed in a binary ladder including power combiners <b>26</b>, <b>28</b>, <b>30</b>. The output <b>32</b> of the binary ladder is combined with the sine wave output <b>34</b> from the external clock source <b>38</b>, to form a perturbed clock signal <b>40</b>.

p-0027The perturbed clock signal is used to introduce a selected amount of jitter into the clock signal <b>40</b>, and hence into the digital signal pattern <b>42</b> generated by the digital pattern source module <b>14</b>. The digital signal pattern <b>42</b> is provided to a DUT <b>0</b>.<b>52</b>, and the output <b>54</b> of the DUT <b>52</b> is measured by a DCA <b>56</b>. The jitter reference source can be used to compensate for jitter in the digital signal pattern <b>42</b> that arises from the digital pattern source module <b>14</b> and/or the DUT <b>52</b>, or can introduce a selected amount and type of jitter to digital signal pattern to evaluate the performance of the DUT <b>52</b> and/or DCA <b>56</b>.

p-0028<figref idrefs="DRAWINGS">FIG. 2</figref> shows a series of plots <b>100</b>, <b>102</b>, <b>104</b>, <b>106</b>, <b>108</b> representing voltage versus time (both in arbitrary units) for the outputs from the BERT modules <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b>, and for the output <b>32</b> of the power combiner <b>30</b> shown in <figref idrefs="DRAWINGS">FIG. 1A</figref>. BERT module B₁produces a digital signal at X Volts <b>110</b> or at −X Volts <b>111</b>, where X is an arbitrary value. Providing positive and negative voltages allows both advancing and delaying the clock trigger timing (ref. <figref idrefs="DRAWINGS">FIG. 3</figref> and associated description). In alternative embodiments, the outputs of the corrections channels all produce a positive voltage or all produce a negative voltage. In other embodiments, the pulses are asymmetrical about 0 Volts, such as from −⅞X Volts to 1⅛X Volts, for one or more of the correction channels.

p-0029In some embodiments, X is selected that so that the summation of voltage levels from the correction channels provides a phase shift sufficient to compensate for the worst-case DDJ in a digital signal pattern, either from a digital pattern source or from a DUT coupled to a digital pattern source. In other embodiments, X is selected to simulate a known amount of DDJ, such as to provide a known distribution (e.g. a Gaussian distribution having a standard deviation equal to a selected timing shift) of DDJ in a digital signal pattern. In the second case, the versatility of the ParBERT modules allows adding selected jitter on a transition-by-transition (i.e. “bit-wise”) basis.

p-0030The bit-wise signal is referred to as a “phase-shift signal” in either case for convenience of discussion, whether it is generating a selected digital pattern to simulate jitter or correcting for jitter. In some applications the bit-wise phase-shift signal applies selected amounts of phase shift to only a few bits, or only one bit, in the digital signal pattern. In other applications, the bit-wise phase-shift signal applies selected amounts of phase shift to most bits, or all bits, in the digital signal pattern. In some applications, the phase-shift signal applies selected amounts of phase shift to many bits in the digital signal pattern to simulate or correct for DDJ, and applies a residual amount (e.g. a least-significant bit) of phase shift to the remainder of the bits in the digital signal pattern.

p-0031The signals from the correction channels are represented as idealized pulses for convenience of illustration and discussion. ParBERT module B₂produces a digital signal at either X/2 Volts <b>112</b> or −X/2 Volts <b>113</b>. ParBERT module B₃produces a digital signal at X/4 Volts <b>114</b> or −X/4 Volts <b>115</b>, and ParBERT module B₄produces a digital signal at X/8 Volts <b>116</b> or −X/8 Volts <b>117</b>. In an alternative embodiment, the amplitude (voltage) of the digital output signal levels are not ½ⁿfactors of each other.

p-0032The output <b>32</b> from the power combiner <b>30</b> (ref. <figref idrefs="DRAWINGS">FIG. 1</figref>) “B_SUM” (i.e. the output from the binary ladder) is shown in plot <b>108</b> (“output plot”). The voltage of the output plot varies according to the sum of the synchronized outputs from ParBERT modules B₁-B₄. The combined voltages are shown as being added without loss for purposes of discussion. In practice, some amount of signal loss occurs in the binary ladder; however, the loss for each path through the binary ladder is about the same, since each digital signal travels through two power combiners. The output levels of each ParBERT module are individually adjustable.

p-0033Some pulses are negative, while some pulses are positive. For example, pulse <b>188</b> is 1⅞ Volts, and pulse <b>120</b> is −1⅞ Volts. Providing both positive and negative pulses allows advancing and delaying the timing clock transition edges in some embodiments. In other embodiments, it might be desirable to only advance or only delay the clock timing transition edges. In yet other embodiments, the worst-case DDJ timing delay might be different from the worst-case DDJ timing advance, and the pulse amplitudes are not symmetrical about zero Volts. Similarly, the slope of the sine wave from the external clock source might vary near the clock trigger point, and the amplitudes of the BERT modules may be corrected to compensate for this variation. In other cases, it may be desirable to provide a nominal offset, such as an offset equal to the least-significant bit (e.g. −X/8 <b>122</b>), which is optionally compensated for by cable delay in a digital system.

p-0034<figref idrefs="DRAWINGS">FIG. 2</figref> shows that a wide variety of voltage levels are obtained by various combinations of the pulses from the BERT modules. In this example, eight positive levels (1⅞, 1⅝, etc.) and eight negative levels are possible, for a total of 16 levels between 1⅞X and −1⅞X. Basically, the four ParBERT modules act as a synchronized four-bit digital-to-analog converter that is synchronized to the output module and is capable of operating at very high frequencies (e.g. 10 GHz and above).

p-0035In a further embodiment, after determining the correct value for X (i.e. the value sufficient to correct for worst-case DDJ in the digital signal pattern), the digital signal pattern is evaluated on a bit-by-bit basis to determine the appropriate phase-shift, if any, to reduce the DDJ in the digital pattern. This process is typically automated, and the digital outputs of the correction channels are generated according to computer-readable instructions in a computer memory. The computer memory could be incorporated in to a ParBERT, or into an ASIC of FPGA, for example.

p-0036In other words, referring to <figref idrefs="DRAWINGS">FIG. 1B</figref>, the uncorrected digital pattern from the source or source/DUT is measured with the DCA. The average transition edge is determined and the data transition (bit) having the worst-case DDJ is identified. The amplitude of the phase-shift signal that will be combined with the sine wave external clock signal is determined, and amplitudes of the correction channels are set to achieve the desired phase-shift signal. The DDJ of the remaining transitions (bits) are determined, and the correction channels are programmed to provide synchronized outputs (see <figref idrefs="DRAWINGS">FIG. 2</figref>, plots <b>100</b>, <b>102</b>, <b>104</b>, <b>106</b>) that sum to provide the desired phase-shift signal (see <figref idrefs="DRAWINGS">FIG. 1A</figref>, ref. num. <b>32</b>; <figref idrefs="DRAWINGS">FIG. 2</figref>, plot <b>108</b>). Each correction channel reads a data file that produces the desired digital stream. Similarly, the digital pattern source module reads a data file that produces the desired digital pattern output. The correction channels and the digital pattern source module are synchronized so that the desired phase shift to the clock signal to the digital pattern source module occurs at the proper time.

p-0037Referring to <figref idrefs="DRAWINGS">FIG. 1A</figref>, the clock signal <b>40</b> generated by the clock module <b>24</b> according to the perturbed external clock signal <b>40</b> is provided to the correction channels (ParBERT modules <b>16</b>, <b>18</b>, <b>20</b>, <b>22</b>). The timing of the outputs from the correction modules is typically set so that the combined output <b>32</b> is stable (settled) near the trigger voltage of the clock module <b>24</b>. Offsetting the transitions (bits) in the phase-shift signal from the transitions (bits) in the digital signal pattern is achieved in a variety of ways, such as by cable delays and/or skewing the digital signal pattern behind the phase-shift signal, for example. Thus, jitter on the phase-shift signal does not affect how bits on the digital signal output are phase shifted because the jitter (i.e. transition edges of the phase-shift signal) is relative far away (in time) from the trigger point of the clock.

p-0038<figref idrefs="DRAWINGS">FIG. 3</figref> shows plots of voltage versus time (both in arbitrary units) illustrating how V_SUM(see <figref idrefs="DRAWINGS">FIG. 1</figref>, ref. num. <b>32</b>, <figref idrefs="DRAWINGS">FIG. 2</figref>, ref. num. <b>108</b>) perturbs the sine wave output V_SYNTHof the synthesizer (see <figref idrefs="DRAWINGS">FIG. 1</figref>, ref. num. <b>38</b>). The clock module (see <figref idrefs="DRAWINGS">FIG. 1</figref>, ref. num <b>24</b>) triggers when the external clock signal reaches a trigger voltage V_ton the rising edge of the sine wave. If the sine wave output <b>34</b> is not perturbed, the clock edge occurs at to <b>130</b>. Another clock edge is triggered at t₁<b>132</b>, when the sine wave crosses V_ton the rising edge again. Alternatively, triggering is done on a falling edge, at a negative voltage, and/or at the zero crossings.

p-0039If a digital pulse <b>134</b> from the combined digital output (V_SUM) having an amplitude of V_jis added to the sine wave <b>34</b> from the synthesizer, a perturbed sine wave (V_TOTAL) <b>34</b>′ is created. The trigger voltage now occurs earlier, at t₀′ <b>136</b>. The subsequent clock edge still occurs at t₁because no digital pulse occurred over this portion of the sine wave. The addition of the digital pulse raises V_TOTALfor the duration of the pulse (pulse width). It is generally desirable that the pulse provide a known phase shift to the clock trigger. The pulse width is exaggerated for purposes of illustration. In particular, the leading edge <b>135</b> and trailing edge <b>137</b> of the pulse <b>134</b> occur well before and after the trigger voltage t₀′, in other words, the pulse <b>134</b> has settled by the time the clock circuit triggers. Allowing the pulse to settle before V_TOTALreaches V_tprovides a known, repeatable offset to V_TOTALand hence repeatable phase shifting.

p-0040By adding and subtracting voltages from the sine wave output on a bit-by-bit basis, the clock transition timing of the on the digital signal output from the jitter reference source (see <figref idrefs="DRAWINGS">FIG. 1</figref>, ref. num. <b>42</b>) is advanced and delayed on a bit-by-bit basis. If the amplitude of the pulse <b>134</b> were higher, the advance would be greater, and if its amplitude were lower, the advance would be less.

h-0009II. Exemplary Methods

p-0041<figref idrefs="DRAWINGS">FIG. 4A</figref> is a flow chart of a method <b>400</b> of phase shifting bits in a digital signal pattern. A bit-wise phase-shift signal is applied to a clock signal to produce a perturbed clock signal (step <b>402</b>). The perturbed clock signal is provided to a digital pattern source (step <b>404</b>) and the digital pattern source generates a shifted digital signal pattern (step <b>406</b>) wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal. Referring to <figref idrefs="DRAWINGS">FIG. 2</figref>, the bit-wise phase-shift signal (e.g. B_SUM, plot <b>108</b>) provides a selected digital level for transitions associated with bit patterns in digital signal pattern, such as from the digital source module <b>14</b> in the ParBERT shown in <figref idrefs="DRAWINGS">FIG. 1A</figref>. These transitions occurs between bits on the digital signal pattern, hence the phase-shift signal is bit-wise. It is not necessary to apply a correction (phase shift) to each bit (since the digital signal pattern may include portions of several 1's and several 0's, with no transitions between bits of the same digital value). Similarly, it is not necessary to apply a correction to each transition, since some transitions might not generate significant DDJ, such as DDJ below the resolution limit of the bit-wise phase-shift signal.

p-0042<figref idrefs="DRAWINGS">FIG. 4B</figref> is a flow chart of a method <b>420</b> of phase shifting bits in a digital signal pattern to compensate for DDJ in the digital signal pattern. The DDJ of the digital signal pattern is measured (step <b>422</b>) and the worst-case DDJ is determined (step <b>424</b>). For example, the transition in the digital signal pattern that produces the greatest deviation from the average transition timing is determined. A digital level sufficient to correct the worst-case DDJ is selected (step <b>426</b>). The digital level is selected according to the timing error of the transition and the sensitivity of clock trigger timing when the digital level is added to or subtracted from the external clock signal.

p-0043In a further embodiment, a jitter reference source is programmed to generate the digital level in the bit-wise phase-shift signal (step <b>428</b>). In a yet further embodiment, digital signal levels sufficient to compensate a plurality of data-dependent jitter transitions in the digital signal pattern are calculated (step <b>430</b>). The jitter reference source generates the bit-wise phase-shift signal to compensate (i.e. reduce the jitter of) the plurality of DDJ transitions in the digital signal pattern (step <b>432</b>). In a particular embodiment, the step of generating the bit-wise phase-shift signal comprises sub-steps of generating a plurality of digital signals from a plurality of synchronized digital pattern generators (step <b>434</b>) and combining the plurality of digital signals (step <b>436</b>), such as with a binary ladder.

p-0044While the preferred embodiments of the present invention have been illustrated in detail, it should be apparent that modifications and adaptations to these embodiments might occur to one skilled in the art without departing from the scope of the present invention as set forth in the following claims.