Method and apparatus for generating a phase dependent control signal

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of pending U.S. patent application Ser. No. 11/203,511, filed Aug. 12, 2005, which is a continuation of U.S. patent application Ser. No. 10/186,471, filed Jun. 28, 2002, issued Mar. 21, 2006 as U.S. Pat. No. 7,016,451 B2, which is a continuation of U.S. patent application Ser. No. 09/260,212, filed Mar. 1, 1999, issued Oct. 22, 2002 as U.S. Pat. No. 6,470,060 B1. These applications and patents are each incorporated by reference herein.

TECHNICAL FIELD

This invention relates to generating a control signal and, more particularly, to generating a control signal based on the phase relationship between two input clock signals, and to memory devices and computer systems using such control signal generators.

BACKGROUND OF THE INVENTION

Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.

Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.

Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.

System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.

A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus. A master clock signal transmitted to each memory device is used to synchronize data transfer between the processor and memory device and also serves as a basis from which to generate internal clock signals coordinating internal memory operations.

One of the factors limiting the access speed of SLDRAM memory devices is the speed at which the command buffer of each device can store and process the command packets. The processing speed of the command buffer is dependent on the control of the relative timing between transmission of the command packets from the processor and an internal clock signal ICLK of the memory device used to trigger a latch in the command buffer to capture the command signals. Both the command signals and the ICLK signal are delayed relative to receipt of the command packet on a command bus and a command clock signal CMDCLK. Furthermore, the amount of the delay is highly variable, and it is difficult to control. If the delay of the internal clock signal ICLK cannot be precisely controlled, it may cause the latch in the command buffer to latch invalid command signals. Thus, the speed at which command packets can be applied to the memory device is limited by the delays in the memory device. Similar problems exist for other control signals in the memory device that control the operation of the memory device during each clock cycle, such as latching of data in the memory device and in a memory controller.

Consequently, the operation of a SLDRAM memory architecture necessitates the generation of a sequence of clock signals having predetermined phases relative to a master clock signal. Phase-locked and delay locked loops have been employed to ensure the precise phase relationship between clock signals. In such a closed loop, there is typically a phase detector receiving two clock signals, and a voltage controlled delay circuit through which one clock signal passes. The voltage controlled delay circuit receives control signals from the phase detector that are used adjust the variable delay value in order to establish a predetermined phase relationship between the two clock signals. For example, where the desired phase relationship between two clock signals is zero degrees, the phase detector will detect any phase difference between the two clock signals and generate a control signal that is transmitted to the voltage controlled delay circuit. The delay circuit will adjust the delay value according to the control signal until the clock signal passing through the voltage controlled delay circuit is synchronized with the other clock signal. The clock control circuitry in an SLDRAM is described in greater detail in U.S. patent application Ser. Nos. 08/879,847, 08/890,055, 08/933,324, 08/994,461, 09/146,716, and 09/150,079, which are incorporated herein by reference.

A single phase detector connected to a CMOS inverter has been used as a means of providing a control signal to the above-described voltage controlled delay circuits. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, clock signals CLK<b>1</b> and CLK<b>2</b> are applied to two pulse generating circuits <b>11</b>, <b>12</b>, each of which includes a NAND gate <b>16</b> receiving a respective clock signal directly and through three series connected inverters <b>18</b>, <b>20</b>, <b>22</b>. The output of each pulse generating circuit <b>11</b>, <b>12</b> set and reset a flip-flop <b>26</b> formed by cross-coupled NAND gates <b>28</b>, <b>30</b>. A single output of the flip-flop <b>26</b> is connected to the gates of an inverter <b>36</b> formed by a PMOS transistor <b>38</b> and an NMOS transistor <b>40</b>. A current source <b>44</b> supplies current to the source of the PMOS transistor <b>38</b>, and a current sink <b>46</b> draws current from the source of the NMOS transistor <b>40</b>. When the output from the flip-flop <b>26</b> is low, the PMOS transistor <b>38</b> is turned ON and the NMOS transistor <b>40</b> is turned OFF. In this condition, a conductive path is created for the current source <b>44</b> to couple current to a capacitor <b>48</b>. A control signal VOUT is generated by the capacitor <b>48</b>. When the current source <b>44</b> is applying current to the capacitor <b>48</b>, the voltage of the control signal VOUT increases linearly. In the alternative case where the output from the flip-flop <b>26</b> is high, the PMOS transistor <b>38</b> is switched OFF and the NMOS transistor <b>40</b> is switched ON. The current sink <b>46</b> is then coupled to the capacitor <b>48</b> to draw current from the capacitor <b>48</b>. The voltage of the control signal VOUT then decreases linearly. As a result, the control signal VOUT has a sawtooth waveform component.

The problem with using a single phase detector connected to an inverter <b>36</b>, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, is that even after the voltage controlled delay circuit has been adjusted so the clock signals have the predetermined phase relationship, the circuit will nevertheless continue to generate a sawtooth ripple voltage at its output. The sawtooth waveform component of the control signal VOUT is transmitted to the voltage controlled delay circuit (not shown in <figref idref="DRAWINGS">FIG. 1</figref>), which is forced to constantly adjust the delay value, and consequently, the phase relationship between the two clock signals CLK<b>1</b> and CLK<b>2</b>. The closed loop system will oscillate around a center-point and continue to “hunt” for the optimum control voltage value.

The result is a “phase jitter” imparted to clock signals used to latch command and data signals. Although the phase jitter introduced by the sawtooth ripple voltage may be acceptable in some applications, in high speed memory applications where the clock frequencies are high and the need to control the phase relationship between clock signals is critical, the clocks signals may fail to correctly latch command and data signals.

To accommodate the problems associated with the sawtooth ripple, the memory system designer may relax the timing requirements of the memory system by slowing down the clock frequencies and reducing the operating speed of the memory device. However, this approach defeats the primary purpose of developing high speed memory systems. Therefore, there is a need for a phase detector that generates a control signal that does not vary when the input clock signals have been adjusted to a predetermined phase relationship.

SUMMARY OF THE INVENTION

A phase detector used for generating a control signal based on the phase relationship between two clock signals. The phase detector includes two phase detector circuits that each provide to a charge pump or a phase dependent signal source select signals based on the phase relationship of the clock signals. The charge pump receives the select signals and produces a current output signal according to combination of the select signals from the phase detector circuits. The current output signal may be converted into a control signal by connecting a capacitor to the output of the charge pump. Significantly, the phase detector produces a non-varying control signal when the two clock signals have a predetermined phase relationship. The use of two phase detectors and the charge pump to generate control signals avoids the presence of a sawtooth ripple voltage at the output of the charge pump.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a logic diagram of a conventional phase detector circuit and charge pump.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating a phase detector including two phase detector circuits connected to a charge pump.

<figref idref="DRAWINGS">FIG. 3</figref> is a logic diagram of the phase detector circuits of <figref idref="DRAWINGS">FIG. 2</figref> in accordance with an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 4</figref>, comprising <figref idref="DRAWINGS">FIGS. 4</figref><i>a</i>-<b>4</b><i>c</i>, is a timing diagram showing several of the waveforms present in the phase detector circuits.

<figref idref="DRAWINGS">FIG. 5</figref> is a logic diagram of the charge pump of <figref idref="DRAWINGS">FIG. 2</figref> in accordance with an embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of a clock generator circuit using an embodiment of the phase detector of <figref idref="DRAWINGS">FIG. 2</figref>.

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram of a computer system using a plurality of DRAMs, each of which includes the phase detector of <figref idref="DRAWINGS">FIG. 2</figref>.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of a phase detector <b>10</b> in accordance with the present invention is illustrated in <figref idref="DRAWINGS">FIG. 2</figref>. The phase detector includes two single-to-dual signal converters <b>102</b>, <b>104</b> that receive input clock signals CLK<b>1</b>, CLK<b>2</b>, respectively, and produce complementary clock signals CLK<b>1</b>*, CLK<b>2</b>* and non-complementary clock signals CLK<b>1</b>, CLK<b>2</b> based on the original input clock signals. The single-to-dual signal converters may be implemented using a variety of designs known to one skilled in the art. For example, an inverter and transfer gate having the same propagation delay connected in parallel will produce a complementary and a non-complementary signal from an input clock signal. The CLK<b>1</b>, CLK<b>1</b>*, CLK<b>2</b>, CLK<b>2</b>* signals are transmitted to two phase detector circuits <b>100</b>, <b>101</b> that produce select signals OUT<b>1</b>, OUT<b>1</b>*, OUT<b>2</b>, OUT<b>2</b>* and transmits them to a phase dependent signal source or a charge pump <b>200</b> via signal lines <b>106</b>, <b>107</b>, <b>108</b>, <b>109</b>, respectively. The charge pump <b>200</b> in turn generates an output current IOUT according to the OUT<b>1</b>, OUT<b>1</b>* signals from the phase detector circuit <b>100</b>, and the OUT<b>2</b>, OUT<b>2</b>* signals from the phase detector circuit <b>101</b>. The IOUT current may be converted into a control signal V₀by capacitor <b>20</b> connected to an output <b>280</b>, and the control signal V₀may be used to adjust the delay value of a voltage controlled delay circuit.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates an embodiment of the phase detector circuits <b>100</b>, <b>101</b> in greater detail. Each detector circuit <b>100</b>, <b>101</b> consists of two signal transition detectors <b>110</b>, <b>120</b> that generate a trigger pulse upon detecting a low-to-high transition of an input clock signal it receives. Each detector circuit <b>100</b>, <b>101</b> also includes a dual output flip-flop <b>150</b> that is set and reset by the trigger pulses it receives from the signal transitions detectors <b>110</b>, <b>120</b>. Each flip-flop <b>150</b> is formed by a pair of cross-coupled NAND gates <b>152</b>, <b>154</b>. The output from the phase detector circuits <b>100</b>, <b>101</b> are applied to NAND gates <b>165</b>, <b>166</b> through inverters <b>161</b>-<b>164</b>. Each NAND gate <b>165</b>, <b>166</b> also receives a respective input signal from the flip-flop <b>150</b>. The combination of inverters <b>161</b>-<b>164</b> and NAND gates <b>165</b>, <b>166</b> creates a buffer circuit that will cause the respective NAND gates <b>165</b>, <b>166</b> to immediately switch upon receiving a trigger pulse from the respective signal transition detector, as explained below.

Each phase detector circuit <b>100</b>, <b>101</b> receives a pair of active-low control signals, SETA*, RSTA*, and SETB*, RSTB*, respectively. The SETA* and RSTA* signals are applied to the phase detector circuit <b>100</b>, and the SETB* and RSTB* signals are applied to the phase detector circuit <b>101</b>. The control signals are generated by a control circuit (not shown), and are used to put each phase detector circuit <b>100</b>, <b>101</b> into a predetermined state. Signal RSTA* is provided directly to the NAND gate <b>152</b> of the flip-flop <b>150</b> and the NAND gate <b>113</b> of the signal transition detector <b>120</b>, and signal SETA* is provided directly to the NAND gate <b>154</b> of the flip-flop <b>150</b> and the NAND gate <b>113</b> of the signal transition detector <b>110</b>. The RSTB*, SETB* signals are similarly provided to the respective NAND gates of the phase detector circuit <b>101</b>.

To illustrate the operation of the control signals, consider the effect the SETA*, RSTA* signals have on phase detector circuit <b>100</b>. During normal operation of the phase detector circuit <b>100</b>, the RSTA* and SETA* signals are both high. In this situation, the NAND gates <b>113</b> of the signal transition detectors <b>110</b>, <b>120</b> behave as inverters, and the NAND gates <b>152</b>, <b>154</b> behave as simple two input NAND gates. However, when the SETA* signal goes low, the output of the NAND gates <b>113</b><i>a </i>and <b>154</b> are forced high. Consequently, the NAND gate <b>118</b><i>a </i>outputs a high to the NAND gate <b>152</b>, and the NAND gate <b>118</b><i>b </i>outputs a low that sets the flip-flop <b>150</b>. The OUT<b>1</b> signal is then forced high and the OUT<b>1</b>* signal is forced low. In a similar manner, when the RSTA* signal goes low, the flip-flop <b>150</b> is reset so that the OUT<b>1</b> signal is forced low and the OUT<b>1</b>* signal is forced high. Control signals RSTB* and SETB* operate in the same manner for the phase detector circuit <b>101</b> by forcing the OUT<b>2</b>, OUT<b>2</b>* signals to a predetermined state when active. To simplify the explanation of the operation of the signal transition detectors <b>110</b>, <b>120</b>, it will be assumed that the SETA*, RSTA*, SETB*, and RSTB* signals are inactive (i.e., at a high signal level).

In operation, the CLK<b>1</b>, CLK<b>2</b> signals are initially low thereby applying a low signal directly to one input of the NAND gates <b>118</b><i>b</i>, <b>118</b><i>c </i>and causing the inverters <b>116</b><i>a</i>, <b>116</b><i>d </i>to apply low signals to the other input of the NAND gates <b>118</b><i>a</i>, <b>118</b><i>d</i>, respectively. Thus, the NAND gates <b>118</b><i>a</i>-<i>d </i>initially output a high signal. When the respective clock signal goes high, e.g., the CLK<b>1</b> signal, the NAND gate <b>118</b><i>c </i>outputs a low signal until the high signal has propagated through inverter <b>112</b><i>c</i>, NAND gate <b>113</b><i>c</i>, and through series inverters <b>114</b><i>c</i>, <b>115</b><i>c</i>, <b>116</b><i>c</i>. The inverter of <b>116</b><i>c </i>then applies a low signal to the NAND gate <b>118</b><i>c</i>, thereby causing the output of the NAND gate <b>118</b><i>c </i>to again go high. Thus, the signal transition detector <b>110</b> outputs a low-going pulse responsive to the CLK<b>1</b> signal. The low-going pulse has a width equal to the total propagation delay through inverter <b>112</b>, NAND gate <b>113</b>, and series inverters <b>114</b>, <b>115</b>, <b>116</b>. The signal transition detectors <b>110</b>, <b>120</b> in the phase detector circuit <b>100</b>, and the signal transition detector <b>120</b> in the phase detector circuit <b>101</b>, each operate in the same manner to output a low pulse responsive to the rising edge of the clock signal to which it is connected.

The low-going pulse from each of the signal transition detectors <b>110</b>, <b>120</b> sets or resets the flip-flops <b>150</b>. More specifically, each flip-flop <b>150</b> is set by each pulse from the respective signal transition detector <b>110</b>, thereby causing the NAND gate <b>152</b> to output a high signal and the NAND gate <b>154</b> to output a low signal. Each flip-flop <b>150</b> is reset by each pulse from the respective signal transition detector <b>120</b>, thereby causing the NAND gate <b>152</b> to output a low signal and NAND gate <b>154</b> to output a high signal. The output of NAND gates <b>152</b>, <b>154</b> are then inverted by NAND gates <b>165</b>, <b>166</b>, respectively, of the buffer circuit to provide the OUT<b>1</b>, OUT<b>1</b>*, OUT<b>2</b>, OUT<b>2</b>* signals to the charge pump <b>200</b>. As a result, the OUT<b>1</b> signal is high during the period between the rising edge of the CLK<b>2</b> signal and the falling edge of the CLK<b>1</b> signal (i.e., the rising edge of the CLK<b>1</b>* signal). In a similar manner, the OUT<b>2</b> signal generated by the detector circuit <b>101</b> is high during the period between the falling edge of the CLK<b>2</b> signal (i.e., the rising edge of the CLK<b>2</b>* signal) and the rising edge of the CLK<b>1</b> signal.

To illustrate the operation of the phase detector circuits <b>100</b>, <b>101</b>, consider three situations: first, where CLK<b>1</b> and CLK<b>2</b> are in phase; second, where CLK<b>1</b> is leading CLK<b>2</b> by φ; and third, where CLK<b>1</b> is lagging CLK<b>2</b> by φ.

The phase relationship when the CLK<b>1</b> and CLK<b>2</b> signals are in phase is illustrated in <figref idref="DRAWINGS">FIG. 4</figref><i>a</i>. As explained above, the OUT<b>1</b> signal from the phase detector circuit <b>100</b> switches from low to high on the rising edge of the CLK<b>2</b> signal, and from high to low on the falling edge of the CLK<b>1</b> signal. Also, the OUT<b>2</b> signal from the phase detector circuit <b>101</b> switches from low to high on the falling edge of the CLK<b>2</b> signal, and from high to low on the rising edge of the CLK<b>1</b> signal. Since the CLK<b>1</b> signal is shown in <figref idref="DRAWINGS">FIG. 4</figref><i>a </i>as being in phase with the CLK<b>2</b> signal, the duty cycles of the OUT<b>1</b> and OUT<b>2</b> signals are both 50 percent, and the two signals will never be at the same logic level simultaneously.

Now consider the case where CLK<b>1</b> is leading CLK<b>2</b> by φ, as shown in <figref idref="DRAWINGS">FIG. 4</figref><i>b</i>. When CLK<b>1</b> is leading CLK<b>2</b> by φ, the OUT<b>1</b> signal from the phase detector circuit <b>100</b> and the OUT<b>2</b> signal from phase the detector circuit <b>101</b> have duty cycles less than 50 percent, and may be at a low logic level simultaneously. Finally, consider the case where CLK<b>1</b> is lagging CLK<b>2</b> by φ, as shown in <figref idref="DRAWINGS">FIG. 4</figref><i>c</i>. When CLK<b>1</b> is lagging CLK<b>2</b> by φ, the resulting OUT<b>1</b> and OUT<b>2</b> signals from phase detector circuits <b>100</b> and <b>101</b>, respectively, have duty cycles greater than 50 percent. Thus, the OUT<b>1</b> and OUT<b>2</b> signals may be at a high logic level simultaneously.

The OUT<b>1</b>, OUT<b>1</b>*, OUT<b>2</b>, OUT<b>2</b>* signals are transmitted from the phase detector circuits <b>100</b>, <b>101</b> on signal lines <b>106</b>, <b>107</b>, <b>108</b>, <b>109</b>, respectively, to the input of a charge pump, such as a charge pump <b>200</b>, as shown in <figref idref="DRAWINGS">FIG. 5</figref>. The charge pump <b>200</b> includes a charging circuit <b>205</b>, a current source <b>270</b>, and a current sink <b>272</b>. The function of the charging circuit <b>205</b> is to direct the current of the current source <b>270</b> and current sink <b>272</b> into, or out of the capacitor <b>20</b> (<figref idref="DRAWINGS">FIG. 2</figref>), respectively, depending upon the relative duty cycles of the OUT<b>1</b> and OUT<b>2</b> signals. Significantly, no current flows into or out of the capacitor <b>20</b> when the CLK<b>1</b> and CLK<b>2</b> signals are in phase. Thus, the resulting control signal may have virtually no ripple when the phase detector <b>10</b> (<figref idref="DRAWINGS">FIG. 2</figref>) is used in a voltage controlled delay circuit, as explained above. A clock signal generated using the voltage controlled delay circuit has significantly less phase jitter compared to a clock signal generated by a voltage controlled delay circuit using the phase detector of <figref idref="DRAWINGS">FIG. 1</figref>.

The charge pump <b>200</b> includes transistors <b>245</b>-<b>248</b> on the left leg of the charging circuit <b>205</b> to form a compensation circuit <b>206</b> to compensate for current and voltage changes in a current driving circuit formed by transistors <b>243</b>, <b>244</b>, <b>249</b>, and <b>250</b> on the right leg of the charging circuit <b>205</b>. The compensation circuit <b>206</b> is provided so that the voltage across the charging circuit <b>205</b> is relatively constant during operation, regardless of where the currents of the current source <b>270</b> and the current sink <b>272</b> are being directed.

A voltage follower <b>260</b> is connected between the output <b>280</b> of the charging circuit <b>205</b> and node <b>262</b> of the compensation circuit <b>206</b>. The voltage follower <b>260</b> provides a current path from the current source <b>270</b> to ground when current from the current sink <b>272</b> is being directed out of the capacitor <b>20</b>. The voltage follower <b>260</b> also provides a current path from the current sink <b>272</b> to the positive supply when current from the current source <b>270</b> is directed to the output <b>280</b>. As will be explained in greater detail below, both of these situations occur where the CLK<b>1</b> and CLK<b>2</b> signals are not in phase. As a result, the current through the charging circuit <b>205</b> is through two PMOS transistors and two NMOS transistors when current is being directed into or out of the capacitor <b>20</b>, namely, the transistors <b>242</b>, <b>244</b>, <b>247</b>, <b>251</b> or the transistors <b>241</b>, <b>245</b>, <b>250</b>, <b>252</b>. Similarly, in the situations where no current is being directed into or out of the capacitor <b>20</b>, the current through the charging circuit <b>205</b> is also through two PMOS transistors and two NMOS transistors, namely, the transistors <b>242</b>, <b>243</b>, <b>248</b>, <b>251</b> or the transistors <b>241</b>, <b>246</b>, <b>249</b>, <b>252</b>. Consequently, the operating points of the active transistors will remain relatively constant, and any capacitive charge pumping on the internal nodes of the charging circuit <b>205</b> will be minimized. It will be appreciated by one ordinarily skilled in the art that the transistors of the charging circuit <b>205</b> must be scaled accordingly.

To illustrate the operation of the charge pump <b>200</b> in conjunction with the phase detector circuits <b>100</b>, <b>101</b>, consider again the three situations that were described earlier: where CLK<b>1</b> and CLK<b>2</b> are in phase; where CLK<b>1</b> is leading CLK<b>2</b> by φ; and where CLK<b>1</b> is lagging CLK<b>2</b> by φ.

As shown in <figref idref="DRAWINGS">FIG. 4</figref><i>a</i>, when OUT<b>1</b> is low and OUT<b>2</b> is high the current provided by the current source <b>270</b> and sunk by the current sink <b>272</b> bypasses the output <b>280</b> of the charging circuit <b>205</b> and simply flows through the transistors <b>242</b>, <b>243</b>, <b>248</b>, <b>251</b> (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>a </i>as “<b>0</b>(A)”). Similarly, when OUT<b>1</b> is high and OUT<b>2</b> is low current flows from the current source <b>270</b> to the current sink <b>272</b> through the transistors <b>241</b>, <b>246</b>, <b>249</b>, <b>252</b> (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>a </i>as “<b>0</b>(B)”). In either case, the charging circuit <b>205</b> does not charge or discharge the capacitor <b>20</b> so the voltage on the capacitor <b>20</b> remains constant.

As shown in <figref idref="DRAWINGS">FIG. 4</figref><i>b</i>, when both the OUT<b>1</b> and OUT<b>2</b> signals are low, the charging circuit <b>205</b> directs the current provided by the current source <b>270</b> through the PMOS transistors <b>242</b>, <b>244</b> to charge the capacitor <b>20</b> (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>b </i>as “I+”). A path for the current from the current sink <b>272</b> is provided through the voltage follower <b>260</b> and the NMOS transistors <b>247</b>, <b>251</b>. During the time the OUT<b>1</b> and OUT<b>2</b> signals are at different logic levels, the charging circuit <b>205</b> does not charge or discharge the capacitor <b>20</b> so the voltage on the capacitor <b>20</b> remains constant, as was previously explained (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>b </i>as <b>0</b>(A) or <b>0</b>(B)).

As shown in <figref idref="DRAWINGS">FIG. 4</figref><i>c</i>, when both the OUT<b>1</b> and OUT<b>2</b> signals are high, the NMOS transistors <b>250</b>, <b>252</b> provide a conductive path for the current sink <b>272</b> to sink current from the capacitor <b>20</b> (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>c </i>as “I−”). A current path for the current of the current source <b>270</b> is provided through the voltage follower <b>260</b> and the PMOS transistors <b>241</b>, <b>245</b>. As mentioned before, whenever the OUT<b>1</b> and OUT<b>2</b> signals are at different logic levels, the charging circuit <b>205</b> does not charge or discharge the capacitor <b>20</b> so the voltage on the capacitor <b>20</b> remains constant (indicated in <figref idref="DRAWINGS">FIG. 4</figref><i>c </i>as <b>0</b>(A) or <b>0</b>(B)).

Any change in the control voltage V₀depends upon whether current is flowing into or out of the capacitor <b>20</b>, as explained above. When the CLK<b>1</b> and CLK<b>2</b> signals are in phase, as illustrated in <figref idref="DRAWINGS">FIG. 4</figref><i>a</i>, OUT<b>1</b> and OUT<b>2</b> never have the same logic level so no current flows either into or out of the capacitor <b>20</b>. In contrast, when the CLK<b>1</b> signal and the CLK<b>2</b> signal have different phases, OUT<b>1</b> and OUT<b>2</b> are both high or both low for a portion of each cycle. As illustrated in <figref idref="DRAWINGS">FIG. 4</figref><i>b</i>, when the CLK<b>1</b> signal leads the CLK<b>2</b> signal, OUT<b>1</b> and OUT<b>2</b> are low for more than 50 percent of each cycle so that OUT<b>1</b> and OUT<b>2</b> are both low for a portion of each cycle. As a result, as explained above, current flows into the capacitor <b>20</b>, thereby increasing the control voltage V₀. Similarly, when the CLK<b>1</b> signal lags the CLK<b>2</b> signal as illustrated in <figref idref="DRAWINGS">FIG. 4</figref><i>c</i>, OUT<b>1</b> and OUT<b>2</b> are high for more than 50 percent of each cycle so that OUT<b>1</b> and OUT<b>2</b> are both high for a portion of each cycle. As a result, current flows out of the capacitor <b>20</b>, thereby decreasing the control voltage V₀.

The discussion of the phase detector <b>10</b> has so far only considered the case where the CLK<b>1</b> and CLK<b>2</b> signals are adjusted so that they are approximately in phase. However, the phase detector <b>10</b> may be modified to produce a control signal that adjust the CLK<b>1</b> and CLK<b>2</b> signals to have a 180 degrees phase relationship. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the CLK<b>1</b>* and CLK<b>2</b> signals are transmitted to nodes <b>95</b>, <b>96</b> of the phase detector circuit <b>100</b>, while the CLK<b>1</b> and CLK<b>2</b>* signals are transmitted to nodes <b>97</b>, <b>98</b> of the phase detector circuit <b>101</b>, resulting in a phase detector that generates a non-varying control signal when the CLK<b>1</b> and CLK<b>2</b> signals are in phase. However, when the CLK<b>1</b> and CLK<b>1</b>* signals are reconnected to the nodes <b>95</b> and <b>97</b>, respectively, or the CLK<b>2</b> and CLK<b>2</b>* signals are reconnected to the nodes <b>98</b> and <b>96</b>, respectively, the phase detector circuits <b>100</b>, <b>101</b> transmit the OUT<b>1</b>, OUT<b>1</b>*, OUT<b>2</b>, OUT<b>2</b>* signals to the charge pump <b>200</b> so that the phase detector <b>10</b> generates a non-varying control signal when the CLK<b>1</b> and CLK<b>2</b> signals have a 180 degree phase relationship.

The current source <b>270</b> and the current sink <b>272</b> of the charge pump <b>200</b> may be of any current source circuit known in the art. In a preferred embodiment, a high-swing cascode current mirror, as described in “CMOS Circuit Design, Layout, and Simulation,” published by IEEE Press, is used for both the current source <b>270</b> and the current sink <b>272</b>. The use of this particular current source is meant for illustrative purposes only, and is not intended to limit the scope of the present invention.

The charge pump <b>200</b> (<figref idref="DRAWINGS">FIG. 2</figref>) has been described with respect to the embodiment illustrated in <figref idref="DRAWINGS">FIG. 5</figref>. However, an integrator circuit using an operational amplifier may also be used for the charge pump <b>200</b>. Such an integrator circuit is formed by coupling a capacitor across the output of the operational amplifier and the inverting input. The OUT<b>1</b> and OUT<b>2</b> signals generated by the phase detector circuits <b>100</b> and <b>101</b> are applied through two resistors of equal resistance to the non-inverting input of the operational amplifier, and the OUT<b>1</b>* and OUT<b>2</b>* signals are applied through two resistors of equal resistance to the inverting input. The resulting charge pump will generate increasing and decreasing control signals when the CLK<b>1</b> and CLK<b>2</b> signals are not in phase, and generate a control signal with virtually no ripple when the clock signals are in phase.

Shown in <figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of a clock generator circuit that may be used in packetized DRAMs to provide a sequence of clock signals that have predetermined phases relative to a master clock signal. The clock generator circuit contains a first delay-locked loop <b>301</b> and a second delay-locked loop <b>302</b>, each having a phase detector <b>10</b> of <figref idref="DRAWINGS">FIG. 2</figref>. A multiplexer <b>330</b> having a plurality of output lines coupled to respective clock drivers <b>314</b><i>a</i>-<i>n </i>may be coupled to the first delay-lock loop <b>301</b> to couple one of the clock signals produced by the multi-tap voltage controlled delay circuit <b>310</b> to a clock output terminal <b>316</b> for use, for example, with a latch <b>340</b> to latch command data CMD DATA in packetized DRAM. The multiplexer <b>330</b> couples the input of each of the clock drivers <b>314</b><i>a</i>-<i>n </i>to any one of the clock signals produced by the multi-tap voltage controlled delay circuit <b>310</b>.

The first delay-locked loop includes a multi-tap voltage controlled delay circuit <b>310</b> and a first phase detector <b>10</b><i>a</i>. The multi-tap voltage controlled delay circuit <b>310</b> generates a sequence of clock signals on output lines <b>312</b><i>a</i>-<b>312</b><i>n </i>that are increasingly delayed from a first clock signal on line <b>312</b><i>a </i>to a last clock signal on line <b>312</b><i>n</i>. Two of the clock signals, preferably the first and last clock signals, are locked to each other using the delay-locked loop <b>301</b> so that they have a predetermined phase with respect to each other. For example, the first clock signal on line <b>312</b><i>a </i>and the last clock signal on line <b>312</b><i>n </i>may be locked so that they are the inverse of each other, that is, the predetermined phase relationship is 180 degrees from each other. Alternatively, the predetermined phase relationship could be 360 degrees so the first and last clock signals are in phase. The first phase detector <b>10</b><i>a </i>compares the phase of the clock signals on lines <b>312</b><i>a </i>and <b>312</b><i>n </i>and generates the first control signal as a function of the phase difference therebetween. The first control signal is provided to the multi-tap voltage-controlled delay circuit <b>310</b> on line <b>311</b> to adjust the relative delay between the clock signal on line <b>312</b><i>a </i>and line <b>312</b><i>n</i>. The phase detector <b>10</b><i>a </i>will continue to provide the first control signal until the first and last clock signals have obtained the predetermined phase relationship.

Likewise, the second delay-locked loop <b>302</b> includes a second voltage controlled delay circuit <b>320</b> and a second phase detector <b>10</b><i>b</i>. A second delay-locked loop locks a clock signal from the multi-tap voltage controlled circuit <b>310</b> to a master clock signal CMD CLK on line <b>305</b> so that the increasingly delayed clock signals of the multi-tap voltage controlled delay circuit <b>310</b> have phase delays with respect to the CMD CLK signal. The clock signal from the multi-tap voltage controlled circuit <b>310</b> is provided to an input of the second phase detector <b>10</b><i>b </i>through a simulated multiplexer <b>317</b> and a clock driver <b>318</b>. The relative phase delays of the simulated multiplexer <b>317</b> and the clock driver <b>318</b> are nearly identical to that of the multiplexer <b>330</b> and the clock drivers <b>314</b><i>a</i>-<i>n</i>. Consequently, the phase detector <b>10</b><i>b </i>will receive a clock signal having the same relative phase delay as a clock signal output by the clock drivers <b>314</b><i>a</i>-<i>n. </i>

For example, the second delay-lock loop <b>302</b> may delay lock the first clock signal on line <b>312</b><i>a </i>to the CMD CLK signal so that they have substantially the same phase, that is, the predetermined phase relationship is zero degrees from each other. The voltage controlled delay circuit <b>320</b> receives the CMD CLK signal and generates a reference clock signal on line <b>322</b> having a delay relative to the CMD CLK signal that is a function of a second control signal on line <b>321</b>. The clock signal on line <b>322</b> is provided to the multi-tap voltage controlled circuit <b>310</b> and used to generate the sequence of increasingly delayed clock signals <b>312</b><i>a</i>-<b>312</b><i>n. </i>

The second phase detector <b>10</b><i>b </i>compares the phase of the CMD CLK signal to the phase of the first clock signal on line <b>312</b><i>a </i>and generates a second control signal as a function of the difference therebetween. The clock signal provided to the phase detector <b>10</b><i>b </i>is delayed through the simulated multiplexer <b>317</b> and the clock driver <b>318</b> approximately the same amount as the clock signals output by the clock drivers <b>314</b><i>a</i>-<i>n</i>. The second control signal is used to adjust the delay value of the voltage controlled delay circuit <b>320</b>. The second control signal is provided by the second phase detector <b>10</b><i>b </i>until the CMD CLK signal and the first clock signal from the multi-tap voltage controlled circuit <b>310</b> have obtained the predetermined phase relationship. The clock generator circuit of <figref idref="DRAWINGS">FIG. 6</figref> is described in greater detail in U.S. patent application Ser. No. 08/879,847, which, as mentioned above, has been incorporated herein by reference.

A computer system using the phase detector <b>10</b> of <figref idref="DRAWINGS">FIG. 2</figref> in each of a plurality of packetized DRAMs <b>401</b> is shown in <figref idref="DRAWINGS">FIG. 7</figref>. With reference to <figref idref="DRAWINGS">FIG. 7</figref> the computer system <b>400</b> includes a processor <b>402</b> having a processor bus <b>404</b> coupled to three packetized dynamic random access memory or SLDRAMs <b>401</b><i>a</i>-<i>c</i>. The computer system <b>400</b> also includes one or more input devices <b>410</b>, such as a keypad or a mouse, coupled to the processor <b>402</b> through a bus bridge <b>412</b> and an expansion bus <b>414</b>, such as an industry standard architecture (“ISA”) bus or a Peripheral component interconnect (“PCI”) bus. The input devices <b>410</b> allow an operator or an electronic device to input data to the computer system <b>400</b>. One or more output devices <b>420</b> are coupled to the processor <b>402</b> to display or otherwise output data generated by the processor <b>402</b>. The output devices <b>420</b> are coupled to the processor <b>402</b> through the expansion bus <b>414</b>, bus bridge <b>412</b> and processor bus <b>404</b>. Examples of output devices <b>420</b> include printers and video display units. One or more data storage devices <b>422</b> are coupled to the processor <b>402</b> through the processor bus <b>404</b>, bus bridge <b>412</b>, and expansion bus <b>414</b> to store data in or retrieve data from storage media (not shown). Examples of storage devices <b>422</b> and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.

In operation, the processor <b>402</b> communicates with the memory devices <b>401</b><i>a</i>-<i>c </i>via the processor bus <b>404</b> by sending the memory devices <b>401</b><i>a</i>-<i>c </i>command packets that contain both control and address information. Data is coupled between the processor <b>402</b> and the memory devices <b>401</b><i>a</i>-<i>c</i>, through a data bus portion of the processor bus <b>404</b>. Although all the memory devices <b>401</b><i>a</i>-<i>c </i>are coupled to the same conductors of the processor bus <b>404</b>, only one memory device <b>401</b><i>a</i>-<i>c </i>at a time reads or writes data, thus avoiding bus contention on the processor bus <b>404</b>. Bus contention is avoided by each of the memory devices <b>401</b><i>a</i>-<i>c </i>and the bus bridge <b>412</b> having a unique identifier, and the command packet contains an identifying code that selects only one of these components.

The computer system <b>400</b> also includes a number of other components and signal lines which have been omitted from <figref idref="DRAWINGS">FIG. 7</figref> in the interests of brevity. For example, as explained above, the memory devices <b>401</b><i>a</i>-<i>c </i>also receive a command or master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device <b>401</b><i>a</i>-<i>c</i>, and a FLAG signal signifying the start of a command packet.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, the signal transition detector circuits <b>110</b>, <b>120</b> have been described as generating a negative trigger pulse upon detecting a transition of an input signal. However, using cross-coupled NOR gates instead of cross-coupled NAND gates for the flip-flop <b>150</b> allows the use of a signal transition detector that generates a positive trigger pulse. Also, the charge pump <b>200</b> shown in <figref idref="DRAWINGS">FIG. 5</figref> is described as generating a current output signal IOUT having a positive polarity when CLK<b>1</b> is leading CLK<b>2</b>, and having a negative polarity when CLK<b>1</b> is lagging CLK<b>2</b>. However, the connection of the OUT<b>1</b>, OUT<b>1</b>*, OUT<b>2</b>, OUT<b>2</b>* signals to the transistors <b>241</b>-<b>252</b> of the charging circuit <b>205</b> may be modified so that the IOUT signal will have a negative polarity when CLK<b>1</b> is leading CLK<b>2</b>, and have a positive polarity when CLK<b>1</b> is lagging CLK<b>2</b>. Accordingly, the invention is not limited except as by the appended claims.