Nonvolatile semiconductor memory

CROSS REFERENCE TO RELATED APPLICATION

0001This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-349045, filed on Dec. 2, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

0002The present invention relates to a nonvolatile semiconductor memory and a method of fabricating the same and, more particularly, to the structure of a gate electrode in an electrically programmable device and a method of fabricating the same.

0003Some electrically programmable nonvolatile semiconductor memories have a stacked gate structure including a floating gate electrode, inter-gate insulating film, and control gate electrode, in which an element region is formed in self-alignment with the floating gate electrode, and the inter-gate insulating film is formed on the upper surface and on portions of the side surfaces of the floating gate electrode.

0004This type of device is conventionally fabricated by the following procedure.

0005First, a gate insulating film, a polysilicon film serving as a floating gate electrode, and a mask material are formed on a semiconductor substrate. The mask material is patterned by photolithography or the like. The obtained mask material is used as a mask to etch the floating gate electrode and gate insulating film in self-alignment with each other. In addition, the semiconductor substrate is etched to form a groove for an element isolation region.

0006Subsequently, an insulating film is buried in the element isolation region and planarized by CMP (Chemical Mechanical Polishing) or the like, and the mask material is removed.

0007The insulating film buried in the element isolation region is etched back to make the upper surface of the insulating film in the element isolation region lower than that of the floating gate electrode.

0008An inter-gate insulating film is formed, and a polysilicon layer serving as a control gate electrode and a tungsten silicide film are deposited.

0009The gate electrode is patterned by removing unnecessary portions of the control gate electrode, inter-gate insulating film, and floating gate electrode.

0010After that, a semiconductor device is completed by forming interlayer dielectric films, contacts, interconnection layers, and the like.

0011Unfortunately, the conventional nonvolatile memory and the method of fabricating the same have the following problem.

0012If generally used anisotropic etching is used to etch the inter-gate insulating film subsequently to patterning of the gate electrode, the inter-gate insulating film on the side surface of the floating gate electrode readily remains after the etching because the effective film thickness (vertical component) of the inter-gate insulating film on the side surface is large. If the inter-gate insulating film remains, the floating gate electrode material readily remains when the floating gate electrode is etched after that. If the floating gate electrode material remains, an electrical shortcircuit occurs between adjacent gates, and this causes an operation error of the device.

0013A reference disclosing the conventional nonvolatile semiconductor memory is as follows.

0014Yong-Sik Yim, Kwang-Shik Shin, “70 nm NAND Flash Technology with 0.025 μm²Cell Size for 4 Gb Flash Memory”, Semiconductor R & D Center, Samsung Electronics Co., LTD.

SUMMARY OF THE INVENTION

0015According to one aspect of the invention, there is provided a nonvolatile semiconductor memory comprising: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of said floating gate electrode; and a control gate electrode formed on said floating gate electrode via said inter-gate insulating film, wherein a portion from the upper surface of said floating gate electrode to at least a middle of the portion of the side surface which is covered with said inter-gate insulating film has a tapered shape largely inclined to a direction perpendicular to a surface of said semiconductor substrate, compared to the other portion of the side surface.

0016According to one aspect of the invention, there is provided a nonvolatile semiconductor memory comprising: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of said floating gate electrode; and a control gate electrode formed on said floating gate electrode via said inter-gate insulating film, wherein a portion from the upper surface of said floating gate electrode to at least a middle of the portion of the side surface which is covered with said inter-gate insulating film has a shape which increases, toward the upper surface, an inclination angle to a direction perpendicular to a surface of said semiconductor substrate, unlike the other portion of the side surface.

0017According to one aspect of the invention, there is provided a nonvolatile semiconductor memory fabrication method comprising: forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film; removing a portion of an upper surface of the second insulating film in the element isolation region to expose an upper surface and a portion of a side surface of the floating gate electrode, and processing a portion from the exposed upper surface to the exposed side surface of the floating gate electrode such that the portion has one of a tapered shape having an inclination angle to a direction perpendicular to a surface of the semiconductor substrate, and an arcuate shape; forming an inter-gate insulating film on the exposed upper surface and the exposed side surface of the floating gate electrode; depositing a control gate electrode material on the inter-gate insulating film; and forming a stacked gate structure by etching the control gate electrode material, the control gate electrode, the inter-gate insulating film, and the floating gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

0018<figref idref="DRAWINGS">FIG. 1</figref> is a sectional view showing the longitudinal sectional structure of a nonvolatile semiconductor memory according to the first embodiment of the present invention;

0019<figref idref="DRAWINGS">FIG. 2</figref> is a plan view showing the planar structure of the nonvolatile semiconductor memory according to the first embodiment;

0020<figref idref="DRAWINGS">FIG. 3</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0021<figref idref="DRAWINGS">FIG. 4</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0022<figref idref="DRAWINGS">FIG. 5</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0023<figref idref="DRAWINGS">FIG. 6</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0024<figref idref="DRAWINGS">FIG. 7</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0025<figref idref="DRAWINGS">FIG. 8</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0026<figref idref="DRAWINGS">FIG. 9</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0027<figref idref="DRAWINGS">FIG. 10</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the first embodiment;

0028<figref idref="DRAWINGS">FIG. 11</figref> is a sectional view showing the longitudinal sectional structure of a nonvolatile semiconductor memory according to the reference example of the present invention;

0029<figref idref="DRAWINGS">FIG. 12</figref> is a plan view showing the planar structure of the nonvolatile semiconductor memory according to the reference example;

0030<figref idref="DRAWINGS">FIG. 13</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0031<figref idref="DRAWINGS">FIG. 14</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0032<figref idref="DRAWINGS">FIG. 15</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0033<figref idref="DRAWINGS">FIG. 16</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0034<figref idref="DRAWINGS">FIG. 17</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0035<figref idref="DRAWINGS">FIG. 18</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0036<figref idref="DRAWINGS">FIG. 19</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0037<figref idref="DRAWINGS">FIG. 20</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0038<figref idref="DRAWINGS">FIG. 21</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0039<figref idref="DRAWINGS">FIG. 22</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0040<figref idref="DRAWINGS">FIG. 23</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0041<figref idref="DRAWINGS">FIG. 24</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0042<figref idref="DRAWINGS">FIG. 25</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the reference example;

0043<figref idref="DRAWINGS">FIG. 26</figref> is a sectional view showing the longitudinal sectional structure of a nonvolatile semiconductor memory according to the second embodiment of the present invention;

0044<figref idref="DRAWINGS">FIG. 27</figref> is a plan view showing the planar structure of the nonvolatile semiconductor memory according to the second embodiment;

0045<figref idref="DRAWINGS">FIG. 28</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the second embodiment;

0046<figref idref="DRAWINGS">FIG. 29</figref> is a sectional view showing the longitudinal sectional structure of a nonvolatile semiconductor memory according to the third embodiment of the present invention;

0047<figref idref="DRAWINGS">FIG. 30</figref> is a plan view showing the planar structure of the nonvolatile semiconductor memory according to the third embodiment;

0048<figref idref="DRAWINGS">FIG. 31</figref> is a sectional view showing a longitudinal sectional structure in a predetermined step of a method of fabricating the nonvolatile semiconductor memory according to the third embodiment; and

0049<figref idref="DRAWINGS">FIG. 32</figref> is a sectional view showing a longitudinal sectional structure of the nonvolatile semiconductor memory according to a modification of the third embodiment.

DETAILED DESCRIPTION OF THE INVENTION

0050Embodiments of the present invention will be explained below with reference to the accompanying drawings.

First Embodiment

0051<figref idref="DRAWINGS">FIGS. 1 and 2</figref> show a nonvolatile semiconductor memory according to the first embodiment of the present invention.

0052<figref idref="DRAWINGS">FIG. 1</figref> is a sectional view, and <figref idref="DRAWINGS">FIG. 2</figref> is a plan view. <figref idref="DRAWINGS">FIG. 1</figref> shows a longitudinal section taken along a line A-A in <figref idref="DRAWINGS">FIG. 2</figref>

0053This semiconductor device comprises, in the surface portion of a semiconductor substrate <b>11</b>, element isolation regions <b>22</b>, element regions <b>21</b> isolated from each other by the element isolation regions <b>22</b>, a floating gate electrode <b>13</b> formed on the surface of each element region <b>21</b> via a gate insulating film <b>12</b>, and a control gate electrode <b>32</b> formed on the surfaces of the element isolation regions <b>22</b> and on the surfaces of the floating gate electrodes <b>13</b> on the element regions <b>21</b> via an inter-gate insulating film <b>31</b>.

0054This gate electrode has a stacked gate structure formed by stacking the floating gate electrode <b>13</b>, inter-gate insulating film <b>31</b>, and control gate electrode <b>32</b>. The element region <b>21</b> is formed in self-alignment with the floating gate electrode <b>13</b>. The inter-gate insulating film <b>31</b> is formed on the upper surface of the floating gate electrode <b>13</b> and from the upper surface to the middle of each side surface of the floating gate electrode <b>13</b>.

0055Also, the floating gate electrode <b>13</b> has a tapered shape such that a portion having a height H<b>1</b>, where the inter-gate insulating film <b>31</b> is formed, from the upper surface to the middle of the side surface of the floating gate electrode <b>13</b> makes an inclination angle θ with the direction perpendicular to the surface of the semiconductor substrate <b>11</b>. A portion having a height H<b>2</b>, where the inter-gate insulating film <b>31</b> is not formed, of the side surface of the floating gate electrode <b>13</b> is perpendicular to the surface of the semiconductor substrate <b>11</b>.

0056A method of fabricating the nonvolatile semiconductor memory according to the first embodiment will be explained below with reference to <figref idref="DRAWINGS">FIGS. 3 to 10</figref> showing sections in different steps. <figref idref="DRAWINGS">FIGS. 3 to 10</figref> are sectional views of portions between adjacent gates.

0057First, as shown in <figref idref="DRAWINGS">FIG. 3</figref>, a gate insulating film <b>12</b>, a polysilicon film <b>13</b> serving as a floating gate electrode, and a mask material <b>14</b> are sequentially formed on a semiconductor substrate <b>11</b>. The mask material <b>14</b> is made of, e.g., a silicon nitride film.

0058As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the mask material <b>14</b> is patterned into a desired shape by photolithography or the like. The floating gate electrode <b>13</b> and gate insulating film <b>12</b> are etched in self-alignment with the mask material <b>14</b>, and the semiconductor substrate <b>11</b> is etched to form grooves for element isolation regions <b>22</b>. Subsequently, an insulating film is buried in the element isolation regions <b>22</b> and planarized by, e.g., CMP.

0059After that, the mask material <b>14</b> is removed as shown in <figref idref="DRAWINGS">FIG. 5</figref>. When a silicon nitride film is used as the mask material <b>14</b>, the mask material is removed using, e.g., hot phosphoric acid.

0060As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the insulating films buried in the element isolation regions <b>22</b> are etched back. This makes the upper surfaces of the element isolation regions <b>22</b> lower than those of the floating gate electrodes <b>13</b>. In this stage, the side surfaces of the floating gate electrodes <b>13</b> are perpendicular to the surface of the semiconductor substrate <b>11</b>. The floating gate electrodes <b>13</b> in this state are etched to incline their side surfaces.

0061This etching uses, e.g., conditions which isotropically etch polysilicon. Consequently, the upper end corners of each floating gate electrode <b>13</b> are etched away to form a tapered shape having an angle θ as shown in <figref idref="DRAWINGS">FIG. 6</figref>.

0062This etching for inclining the side surfaces of the floating gate electrodes <b>13</b> can be performed either after or simultaneously with etch back of the insulating films buried in the element isolation regions <b>22</b>.

0063Etch back of the insulating films buried in the element isolation regions <b>22</b> is performed under the conditions that the selectivity of the insulating films to the polysilicon films is high, i.e., the insulating films are selectively etched while the polysilicon films are left behind. As a consequence, the floating gate electrodes <b>13</b> remain even after etch back. However, etch back may also be performed under the conditions that the selectivity is low, i.e., the polysilicon films are also more or less etched together with the insulating films.

0064Subsequently, an inter-gate insulating film <b>31</b> is formed on the surface as shown in <figref idref="DRAWINGS">FIG. 7</figref>.

0065In addition, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, a polysilicon film serving as a control gate electrode <b>32</b> and a tungsten silicide film are formed. The control gate electrode <b>32</b> is patterned into the shape of a control gate electrode by etching.

0066Unnecessary portions of the control gate electrode <b>32</b> and inter-gate insulating film <b>31</b> are removed from the state shown in <figref idref="DRAWINGS">FIG. 8</figref>, thereby obtaining a state shown in <figref idref="DRAWINGS">FIG. 9</figref>.

0067Then, unnecessary portions of the floating gate electrodes <b>13</b> are removed as shown in <figref idref="DRAWINGS">FIG. 10</figref>. The gate electrode is patterned into a gate electrode shape by thus removing the unnecessary gate electrode portions.

0068After the gate electrode patterning step, a semiconductor device as shown in <figref idref="DRAWINGS">FIG. 1</figref> is fabricated through general semiconductor device fabrication steps such as the formation of interlayer dielectric films, contacts, and interconnection layers.

Reference Example

0069<figref idref="DRAWINGS">FIGS. 11 and 12</figref> respectively show the sectional structure and planar structure of a nonvolatile semiconductor memory according to a reference example. <figref idref="DRAWINGS">FIG. 11</figref> shows a longitudinal section taken along a line B-B in <figref idref="DRAWINGS">FIG. 12</figref>.

0070This semiconductor device comprises, in the surface portion of a semiconductor substrate <b>111</b>, element isolation regions <b>122</b>, element regions <b>121</b> isolated from each other by the element isolation regions <b>122</b>, a floating gate electrode <b>113</b> formed on the surface of each element region <b>121</b> via a gate insulating film <b>112</b>, and a control gate electrode <b>132</b> formed on the surfaces of the element isolation regions <b>122</b> and on the surfaces of the floating gate electrodes <b>113</b> on the element regions <b>121</b> via an inter-gate insulating film <b>131</b>.

0071This device has a stacked gate structure formed by stacking the floating gate electrode <b>113</b>, inter-gate insulating film <b>131</b>, and control gate electrode <b>132</b>. The element region <b>121</b> is formed in self-alignment with the floating gate electrode <b>113</b>. The inter-gate insulating film <b>131</b> is formed on the upper surface of the floating gate electrode <b>113</b> and from the upper surface to the middle of each side surface of the floating gate electrode <b>113</b>.

0072Unlike the floating gate electrode <b>13</b> of the first embodiment described above, the side surfaces of the floating gate electrode <b>113</b> of this reference example are perpendicular to the surface of the semiconductor substrate <b>111</b>.

0073A method of fabricating the semiconductor device according to the reference example will be explained below.

0074As shown in <figref idref="DRAWINGS">FIG. 13</figref>, a gate insulating film <b>112</b>, a polysilicon film <b>113</b> serving as a floating gate electrode, and a mask material <b>114</b> are sequentially formed on a semiconductor substrate <b>111</b>.

0075As shown in <figref idref="DRAWINGS">FIG. 14</figref>, the mask material <b>114</b> is patterned, and the floating gate electrode <b>113</b>, gate insulating film <b>112</b>, and semiconductor substrate <b>111</b> are etched in self-alignment with the mask material <b>114</b>, thereby forming grooves for element isolation regions <b>122</b>. An insulating film is buried in the element isolation regions <b>122</b> and planarized by, e.g., CMP.

0076The mask material <b>114</b> is removed as shown in <figref idref="DRAWINGS">FIG. 15</figref>, and the insulating films buried in the element isolation regions <b>122</b> are etched back as shown in <figref idref="DRAWINGS">FIG. 16</figref>. This makes the upper surfaces of the element isolation regions <b>122</b> lower than those of the floating gate electrodes <b>113</b>.

0077In the first embodiment described above, as shown in <figref idref="DRAWINGS">FIG. 6</figref>, the floating gate electrodes <b>13</b> are etched to incline their side surfaces in this stage.

0078By contrast, the reference example does not perform this etching. As shown in <figref idref="DRAWINGS">FIG. 16</figref>, therefore, the side surfaces of the floating gate electrodes <b>113</b> remain perpendicular to the surface of the semiconductor substrate <b>111</b>.

0079Steps after that are the same as in the first embodiment. That is, an inter-gate insulating film <b>131</b> is formed on the surface as shown in <figref idref="DRAWINGS">FIG. 17</figref>, and a polysilicon film serving as a control gate electrode <b>132</b> and a tungsten silicide film are formed as shown in <figref idref="DRAWINGS">FIG. 18</figref>. The control gate electrode <b>132</b> is patterned into a gate electrode shape by etching. A state shown in <figref idref="DRAWINGS">FIG. 19</figref> is obtained by removing the control gate electrode <b>132</b> and inter-gate insulating film <b>131</b>, and the floating gate electrodes <b>113</b> are removed as shown in <figref idref="DRAWINGS">FIG. 20</figref>. The gate electrode is patterned by thus removing the unnecessary gate electrode portions.

0080After that, the semiconductor device is completed through fabrication steps such as the formation of interlayer dielectric films, contacts, and interconnection layers.

0081The nonvolatile memory according to this reference example has the following problems.

0082(1) If generally used anisotropic etching is used to etch the inter-gate insulating film <b>131</b> subsequently to patterning of the gate electrode, residues <b>131</b> of the inter-gate insulating film <b>131</b> readily remain on the side surfaces of the floating gate electrodes <b>113</b> after the etching as shown in <figref idref="DRAWINGS">FIG. 21</figref>, because the effective film thickness (vertical component) of the inter-gate insulating film <b>131</b> on the side surfaces is large. If the residues <b>131</b> form, as shown in <figref idref="DRAWINGS">FIG. 22</figref>, residues <b>132</b> readily form when the floating gate electrodes <b>113</b> are etched after that. If the residues <b>132</b> made of the electrode material exist, an electrical shortcircuit occurs between adjacent gates, and this causes an operation error of the device.

0083(2) If the etching amount is increased to prevent the formation of the residues <b>131</b> of the inter-gate insulating film <b>131</b> when etching the inter-gate insulating film <b>131</b> subsequently to patterning of the gate electrode, the upper surfaces of the insulating films in the element isolation regions <b>122</b> are etched away as shown in <figref idref="DRAWINGS">FIG. 23</figref>. If the side surfaces of the element regions <b>121</b> are exposed, an operation error occurs.

0084In the reference example as described above, the side surfaces of the floating gate electrode <b>113</b> are perpendicular to the surface of the semiconductor substrate <b>111</b>. In the first embodiment, however, the side surfaces of the floating gate electrode <b>13</b> incline to the surface of the semiconductor substrate <b>11</b>. This makes the vertical component of the thickness of the inter-gate insulating film <b>31</b> smaller than that of the inter-gate insulating film <b>131</b> of the reference example.

0085Accordingly, the first embodiment can avoid the problem that the inter-gate insulating film <b>31</b> readily remains after etching. This makes it possible to prevent the problem as described as item (1) above in which an electrical shortcircuit occurs between adjacent gate electrodes owing to insufficient etching of the inter-gate insulating film <b>131</b>, or the problem as described as item (2) above in which the side surfaces of the element region <b>121</b> are exposed because excess etching of the inter-gate insulating film <b>131</b> simultaneously etches the upper surface of the insulating film in the element isolation region <b>122</b>.

0086A case in which the inter-gate insulating film <b>131</b> is etched subsequently to patterning of the gate electrode and then the floating gate electrodes <b>113</b> are etched to incline their side surfaces as shown in <figref idref="DRAWINGS">FIG. 24</figref> in the reference example will be explained below.

0087(3) If generally used anisotropic etching is used to etch the floating gate electrodes <b>113</b>, the insulating films buried in the element isolation regions <b>122</b> cover, in the form of eaves, the floating gate electrodes <b>113</b> at the ends of the element regions. As shown in <figref idref="DRAWINGS">FIG. 25</figref>, therefore, the floating gate electrodes <b>113</b> in these portions remain as residues <b>133</b>. Consequently, an electrical shortcircuit occurs between adjacent gates, and this causes an operation error of the device.

0088In the first embodiment, however, the portion where the inter-gate insulating film <b>31</b> is not formed of the side surface of the floating gate electrode <b>13</b> is perpendicular to the surface of the semiconductor substrate <b>11</b>. After the inter-gate insulating film <b>31</b> and floating gate electrodes <b>13</b> are etched after gate patterning, therefore, this prevents the insulating films buried in the element isolation regions <b>122</b> from remaining in the form of eaves as shown in <figref idref="DRAWINGS">FIGS. 24 and 25</figref>. This makes it possible to prevent the occurrence of an electrical shortcircuit between gates resulting from insufficient processing of the floating gate electrodes.

Second Embodiment

0089A nonvolatile semiconductor memory according to the second embodiment of the present invention will be explained below with reference to <figref idref="DRAWINGS">FIGS. 26 and 27</figref>.

0090<figref idref="DRAWINGS">FIG. 26</figref> is a sectional view, and <figref idref="DRAWINGS">FIG. 27</figref> is a plan view. <figref idref="DRAWINGS">FIG. 26</figref> shows a longitudinal section taken along a line C-C in <figref idref="DRAWINGS">FIG. 27</figref>.

0091This semiconductor device comprises, in the surface portion of a semiconductor substrate <b>211</b>, element isolation regions <b>222</b>, element regions <b>221</b> isolated from each other by the element isolation regions <b>222</b>, a floating gate electrode <b>213</b> formed on the surface of each element region <b>221</b> via a gate insulating film <b>212</b>, and a control gate electrode <b>232</b> formed on the surfaces of the element isolation regions <b>222</b> and on the surfaces of the floating gate electrodes <b>213</b> on the element regions <b>221</b> via an inter-gate insulating film <b>231</b>.

0092This device has a stacked gate structure formed by stacking the floating gate electrode <b>213</b>, inter-gate insulating film <b>231</b>, and control gate electrode <b>232</b>. The element region <b>221</b> is formed in self-alignment with the floating gate electrode <b>213</b>. The inter-gate insulating film <b>231</b> is formed on the upper surface of the floating gate electrode <b>213</b> and from the upper surface to the middle of each side surface of the floating gate electrode <b>213</b>.

0093In the first embodiment, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the floating gate electrode <b>13</b> has a tapered shape such that the portion having the height H<b>1</b>, where the inter-gate insulating film <b>31</b> is formed, from the upper surface to the middle of the side surface of the floating gate electrode <b>13</b> makes the inclination angle θ with the direction perpendicular to the surface of the semiconductor substrate <b>11</b>. The portion having the height H<b>2</b>, where the inter-gate insulating film <b>31</b> is not formed, of the side surface of the floating gate electrode <b>13</b> is perpendicular to the surface of the semiconductor substrate <b>11</b>. That is, the boundary between the tapered portion having the height H<b>1</b> and the untapered portion having the height H<b>2</b> matches the boundary where the inter-gate insulating film <b>31</b> is formed.

0094On the other hand, in the second embodiment, the floating gate electrode <b>213</b> is tapered such that, of a portion having height H<b>11</b>+height H<b>12</b>, where the inter-gate insulating film <b>231</b> is formed, from the upper surface to the side surface of the floating gate electrode <b>213</b>, a portion having the height H<b>11</b> formed to the middle of the side surface makes the inclination angle θ with the direction perpendicular to the surface of the semiconductor substrate <b>211</b>. A portion having height H<b>12</b>+height H<b>13</b> of the side surface is perpendicular to the surface of the semiconductor substrate <b>211</b>.

0095Fabrication steps of the second embodiment are the same as the first embodiment until the steps shown in <figref idref="DRAWINGS">FIGS. 1 to 5</figref>. After that, in the first embodiment as shown in <figref idref="DRAWINGS">FIG. 6</figref>, the etching amount is large when inclining the side surface by isotropically etching the floating gate electrode <b>13</b> made of polysilicon. Therefore, the boundary between the inclined portion having the height H<b>1</b> and the uninclined vertical portion having the height H<b>2</b> substantially matches the surface of the element isolation region <b>22</b>.

0096In the second embodiment as shown in <figref idref="DRAWINGS">FIG. 28</figref>, the side surface is inclined by isotropically etching the floating gate electrode <b>213</b> in the same manner as in the first embodiment. However, the height H<b>11</b> of the inclined portion is made smaller than the height H<b>1</b> in the first embodiment by making the etching amount smaller than that in the first embodiment.

0097In the second embodiment, therefore, the boundary between the inclined portion having the height H<b>11</b> and the uninclined vertical portion having height H<b>12</b>+height H<b>13</b> is higher than the surface (the boundary between H<b>12</b> and H<b>13</b>) of the element isolation region <b>222</b>.

0098Etching for inclining the side surfaces of the floating gate electrodes <b>213</b> can be performed either after or simultaneously with etch back of the insulating films buried in the element isolation regions <b>222</b>.

0099As in the first embodiment, etch back of the insulating films in the element isolation regions <b>222</b> is performed under the conditions that the selectivity of the insulating films to the polysilicon of the floating gate electrodes <b>213</b> is high, i.e., the insulating films are selectively etched with the polysilicon is left behind. As a consequence, the floating gate electrodes <b>213</b> remain even after etch back. However, etching may also be performed under the conditions that the polysilicon is also more or less etched together with the insulating films.

0100In the second embodiment, the side surfaces of the floating gate electrodes <b>213</b> can be partially inclined by using conditions having a low selectivity to the middle of etch back (from the upper surface to the height H<b>11</b>), and using conditions having a high selectivity in etch back to the height H<b>11</b> after that.

Third Embodiment

0101A nonvolatile semiconductor memory according to the third embodiment of the present invention will be explained below with reference to <figref idref="DRAWINGS">FIGS. 29 and 30</figref>.

0102<figref idref="DRAWINGS">FIG. 29</figref> is a longitudinal sectional view, and <figref idref="DRAWINGS">FIG. 30</figref> is a plan view. <figref idref="DRAWINGS">FIG. 29</figref> shows a longitudinal section taken along a line D-D in <figref idref="DRAWINGS">FIG. 29</figref>.

0103This semiconductor device comprises, in the surface portion of a semiconductor substrate <b>311</b>, element isolation regions <b>322</b>, element regions <b>321</b> isolated from each other by the element isolation regions <b>322</b>, a floating gate electrode <b>313</b> formed on the surface of each element region <b>321</b> via a gate insulating film <b>312</b>, and a control gate electrode <b>332</b> formed on the surfaces of the element isolation regions <b>322</b> and on the surfaces of the floating gate electrodes <b>313</b> on the element regions <b>321</b> via an inter-gate insulating film <b>331</b>.

0104This device has a stacked gate structure formed by stacking the floating gate electrode <b>313</b>, inter-gate insulating film <b>331</b>, and control gate electrode <b>332</b>. The element region <b>321</b> is formed in self-alignment with the floating gate electrode <b>313</b>. The inter-gate insulating film <b>331</b> is formed on the upper surface of the floating gate electrode <b>313</b> and from the upper surface to the middle of each side surface of the floating gate electrode <b>313</b>.

0105In the third embodiment, a portion having a height H<b>21</b>, where the inter-gate insulating film <b>331</b> is formed, from the upper surface to the middle of the side surface of the floating gate electrode <b>313</b> has an arcuate sectional shape. A portion having a height H<b>22</b>, where the inter-gate insulating film <b>331</b> is not formed, of the side surface of the floating gate electrode <b>313</b> is perpendicular to the surface of the semiconductor substrate <b>311</b>.

0106This sectional shape is not limited to an arcuate shape. That is, that portion of the side surface of the floating gate electrode <b>313</b> which is covered with the inter-gate insulating film <b>331</b> need only have a shape which increases, toward the upper surface, the inclination angle to the direction perpendicular to the surface of the semiconductor substrate <b>311</b>.

0107Fabrication steps of the third embodiment are the same as the first embodiment until the steps shown in <figref idref="DRAWINGS">FIGS. 1 to 5</figref>.

0108After that, in the third embodiment as shown in <figref idref="DRAWINGS">FIG. 31</figref>, the upper corners of the portion having the height H<b>21</b> of the floating gate electrode <b>313</b> are rounded by using e.g., conditions which isotropically etch the polysilicon forming the floating gate electrode <b>313</b>.

0109Etching for rounding the upper corners of the floating gate electrodes <b>313</b> can be performed either after or simultaneously with etch back of the insulating films buried in the element isolation regions <b>322</b>.

0110The nonvolatile semiconductor memories and the methods of fabricating the same according to the above embodiments can prevent operation errors of the devices.

0111The above embodiments are merely examples and do not limit the present invention, so these embodiments can be variously modified within the technical scope of the invention. For example, the materials of the films used in the first to third embodiments are not limited and can also be other materials.

0112As a modification of the third embodiment, as shown in <figref idref="DRAWINGS">FIG. 32</figref>, of a portion having height H<b>31</b>+height H<b>32</b>, where the inter-gate insulating film <b>331</b> is formed, from the upper surface to the middle of the side surface of the floating gate electrode <b>313</b>, a portion having the height H<b>31</b> formed to the middle of the side surface can also have an arcuate sectional shape. Of the side surface of the floating gate electrode <b>313</b>, a portion having the height H<b>32</b> where the inter-gate insulating film <b>331</b> is formed and a portion having the height H<b>33</b> where the inter-gate insulating film <b>331</b> is not formed are perpendicular to the surface of the semiconductor substrate <b>311</b>.

0113Furthermore, the sectional shape of this portion having the height H<b>31</b> is not limited to an arcuate shape and need only be a shape which increases, toward the upper surface, the inclination angle to the direction perpendicular to the surface of the semiconductor substrate <b>311</b>.