Semiconductor device and method for forming a metal line in the semiconductor device
Summary by NHIP
Wide-Line Metal Formation
The method forms a metal line by etching a groove into a metal layer, then etching the layer to create a lower line wider than the groove. The metal layer comprises aluminum and/or titanium nitride with a thickness of about 4,000 Å-6,000 Å and a groove depth of about 500 Å-1,500 Å.
Claim Score by NHIP
Abstract
Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device according to a method including: (i) forming a metal layer on a semiconductor substrate; (ii) forming a groove on an upper surface of the metal layer by etching the metal layer; (iii) etching the metal layer so as to form a groove-engraved lower metal line that is wider than the groove; (iv) forming an insulator layer covering the semiconductor substrate and the groove-engraved lower metal line; (v) etching the insulator layer so as to form a contact hole exposing the groove; and (vi) forming a contact electrode filling the contact hole and an upper metal line connected thereto, above the insulator layer.

Term
Term ended
Expired 5 August 2026, 0.1 years ago.
- Priority
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15 claims: 3 independent, 12 dependent
- 1A method of forming a metal line in a semiconductor device, comprising:forming a metal layer on a semiconductor substrate;forming a groove in an upper surface of the metal layer by etching the metal layer;etching the metal layer so as to form a lower metal line having a width greater than a width of the groove;forming an insulator layer covering the semiconductor substrate and the lower metal line;etching the insulator layer to form a contact hole exposing at least part of the groove and a top surface of the lower metal line;and forming a contact electrode filling the contact hole and an upper metal line connected thereto above the insulator layer.
- 7Broadest claimClaim Score 72, broad(NHIP)A semiconductor device, comprising:a semiconductor substrate;a lower metal line on the semiconductor substrate and having a groove at a top surface thereof;an insulator layer above the lower metal line having a contact hole therein exposing at least a part of the groove and a top surface of the lower metal line;a contact electrode in the contact hole;and an upper metal line in contact with the contact electrode.
- 13A method, comprising:partially etching a metal layer on a semiconductor substrate to form a plurality of grooves or indentations in an upper surface of the metal layer at a plurality of first locations, the grooves or indentations having a first width;fully etching the metal layer at a plurality of second locations so as to form a plurality of lower metal lines having a second width, the second width being greater than the first width, and the second locations not coinciding with the first locations;forming an insulator layer over the lower metal line;and etching the insulator layer to form a plurality of contact holes exposing the indentation or at least part of the groove and a top surface of the metal line.
Independent claims3
33 paragraphs in 5 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATION
0001This application claims priority to and the benefit of Korean Patent Application 10-2004-0067373 filed in the Korean Intellectual Property Office on Aug. 26, 2004, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
0002(a) Field of the Invention
0003The present invention generally relates to a semiconductor device and a method for forming a metal line in the semiconductor device. More particularly, the present invention relates to a semiconductor device and a method for forming a metal line in the semiconductor device having an advantage of reduced contact resistance.
0004(b) Description of the Related Art
0005As semiconductor devices become more integrated, metal lines are usually fabricated in a multi-layer structure.
0006<figref idref="DRAWINGS">FIG. 2A</figref> to <figref idref="DRAWINGS">FIG. 2E</figref> are cross-sectional views showing sequential stages of a conventional method for forming a metal line in a semiconductor device.
0007Referring to <figref idref="DRAWINGS">FIG. 2A</figref>, metal layer <b>204</b> may be formed on semiconductor substrate <b>202</b> by depositing a metal material thereon by a physical vapor deposition (PVD) method, an ion beam method, an electron beam method, or a radio-frequency (RF) sputtering method, for example. Then, photoresist pattern <b>206</b> for etching the metal layer <b>204</b> can be formed on metal layer <b>204</b>.
0008Subsequently, as shown in <figref idref="DRAWINGS">FIG. 2B</figref>, metal layer <b>204</b> can be dry etched according to photoresist pattern <b>206</b>. Thus, lower metal line <b>204</b><i>a </i>may be formed on semiconductor substrate <b>202</b>. Then, a cleaning process is performed and photoresist pattern <b>206</b> may be removed.
0009As shown in <figref idref="DRAWINGS">FIG. 2C</figref>, insulator layer <b>208</b> can be formed on semiconductor substrate <b>202</b> and lower metal line <b>204</b><i>a </i>by depositing an insulating material, such as a high density plasma (HDP) oxide layer. Then, a surface of insulator layer <b>208</b> may be planarized by a chemical mechanical polishing (CMP) process, for example.
0010In addition, as shown in <figref idref="DRAWINGS">FIG. 2D</figref>, photoresist pattern <b>210</b> for forming a contact hole can be formed on insulator layer <b>208</b>.
0011Now, insulator layer <b>208</b> may be etched using photoresist pattern <b>210</b> and, accordingly, contact hole <b>212</b> for a contact to lower metal line <b>204</b><i>a </i>may be formed, as shown in <figref idref="DRAWINGS">FIG. 2E</figref>. Then, photoresist pattern <b>210</b> can be removed.
0012Here, a metal material can then be filled into contact hole <b>212</b> so as to form a contact electrode (not shown), and then an upper metal line (not shown) can be formed by depositing a metal material by various methods, such as an ion beam method, an electron beam method, or an RF sputtering method.
0013A continuing trend in semiconductor devices is that an available area per device has been reduced due to higher integration of the semiconductor devices. Thus, a size of a contact hole connecting two metal lines or a semiconductor substrate and a metal line has been also reduced. Furthermore, widths of metal lines have also been reduced. Therefore, in this case, contact resistance may be excessively increased when a semiconductor device is made according to such a conventional method. That is, an effective contact area may be problematic for a semiconductor device that has been highly integrated.
0014The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form prior art or other information that may be already known in this or any other country to a person of ordinary skill in the art.
SUMMARY OF THE INVENTION
0015An object of embodiments of the present invention is to provide a semiconductor device and a method for forming a metal line in a semiconductor device having an advantage of reduced contact resistance by increasing an effective contact area of a contact hole in the semiconductor device.
0016An exemplary method for forming a metal line in a semiconductor device according to an embodiment of the present invention can include: (i) forming a metal layer on a semiconductor substrate; (ii) forming a groove on an upper surface of the metal layer by etching the metal layer; (iii) etching the metal layer so as to form a groove-engraved lower metal line that is wider than the groove; (iv) forming an insulator layer covering the semiconductor substrate and the groove-engraved lower metal line; (v) etching the insulator layer so as to form a contact hole exposing the groove of the groove-engraved lower metal line; and (vi) forming a contact electrode filling the contact hole and an upper metal line connected thereto above the insulator layer.
0017The metal layer may be formed to a thickness of about 4,000 Å-6,000 Å, for example. A BCl3 or Cl2 gas may be used for etching the metal layer and etch selectivity of the metal layer may be maintained to a level of at least 1:1 with respect to the photoresist. The groove of the metal layer may be etched to a depth of about 500 Å-1,500 Å, for example.
0018An exemplary semiconductor device according to an embodiment of the present invention can include: (i) a semiconductor substrate; (ii) a lower metal line formed on the semiconductor substrate and engraved with a groove at a top thereof; (iii) an insulator layer formed above the lower metal line and formed with a contact hole exposing the groove; (iv) a contact electrode filling the contact hole; and (v) an upper metal line connected with the contact electrode. The metal layer may be formed to a thickness of 4,000 Å-6,000 Å, for example. The groove of the metal layer may be etched to a depth of 500 Å-1,500 Å, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
0019<figref idref="DRAWINGS">FIG. 1A</figref> to <figref idref="DRAWINGS">FIG. 1G</figref> are cross-sectional views showing sequential stages of a method for forming a metal line in a semiconductor device according to an exemplary embodiment of the present invention.
0020<figref idref="DRAWINGS">FIG. 2A</figref> to <figref idref="DRAWINGS">FIG. 2E</figref> are cross-sectional views showing sequential stages of a conventional method for forming a metal line in a semiconductor device.
DETAILED DESCRIPTION OF THE EMBODIMENTS
0021An embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings.
0022<figref idref="DRAWINGS">FIG. 1A</figref> to <figref idref="DRAWINGS">FIG. 1G</figref> are cross-sectional views showing sequential stages of a method for forming a metal line in a semiconductor device according to an exemplary embodiment of the present invention.
0023Referring to <figref idref="DRAWINGS">FIG. 1A</figref>, metal layer <b>104</b> may be formed on semiconductor substrate <b>102</b> by depositing a metal material by using any of various methods, such as an ion beam method, an electron beam method, an RF sputtering method, or a physical vapor deposition (PVD) method. Then, photoresist pattern <b>106</b> defining a groove region can be formed on metal layer <b>104</b>. Alternatively, photoresist pattern <b>106</b> may define an indentation, such as a spot, square or oval. For example, the spot may have substantially the same shape as a subsequently formed contact hole, which may maximize the increase in the contact surface (or interface) area when the indentation is fully exposed by the contact hole. Here, metal layer <b>104</b> may have a thickness of about 4,000 Å-6,000 Å, and photoresist pattern <b>106</b> may have a thickness of less than about 2,000 Å, but generally greater than a depth of the groove or indentation. Metal layer <b>104</b> may comprise a metal, such as aluminum (Al) or an aluminum-copper alloy, which may have an adhesive and/or barrier layer on either or both sides thereof, such as a titanium adhesive layer/titanium nitride (TiN) barrier layer/bulk aluminum layer/titanium adhesive layer/titanium nitride (TiN) barrier layer stack.
0024Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, a groove <b>107</b> having a predetermined width may be formed by etching metal layer <b>104</b> to a predetermined depth. The groove (or other indentation) <b>107</b> is generally defined by photoresist pattern <b>106</b>. Then, a cleaning process can be performed and photoresist pattern <b>106</b> may be removed (or vice versa). Here, groove <b>107</b> formed on the metal layer <b>104</b> may have a depth of about 500 Å-1,500 Å, for example.
0025Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1C</figref>, a photoresist pattern <b>108</b> defining a region wider than groove <b>107</b> can be formed on metal layer <b>104</b>.
0026Then, as shown in <figref idref="DRAWINGS">FIG. 1D</figref>, a lower metal line <b>104</b><i>a </i>having groove <b>107</b> thereon can be formed by dry etching metal layer <b>104</b> according to photoresist pattern <b>108</b>. Consequently, as is apparent from a comparison of <figref idref="DRAWINGS">FIGS. 1B and 1D</figref>, a plurality of grooves or indentations <b>107</b> may be formed by partially etching first locations in the upper surface of metal layer <b>104</b>, and the metal layer <b>104</b> is fully etched in second locations that are not coincident with the first locations where the grooves or indentations <b>107</b> are formed.
0027Here, the etchant for etching metal layer <b>104</b> may comprise BCl<sub>3 </sub>and/or Cl<sub>2 </sub>gas (generally activated in a plasma), and an etch selectivity of the metal layer <b>104</b> is at least 1:1 with respect to the photoresist <b>108</b>. Here, etch selectivity denotes of a ratio of etch rates of the two layers (usually of the metal layer <b>104</b> to the photoresist <b>108</b>). For example, when the etch rate of metal layer <b>104</b> is 1,000 Å/min and the etch rate of photoresist pattern <b>108</b> is also 1,000 Å/min, the etch selectivity of the two layers becomes 1:1. However, conditions for plasma etching the metal layer <b>104</b> are generally sufficient to provide an etch selectivity of greater than 1:1 (e.g., ≧1.5:1, ≧2:1, ≧3:1, etc.). Subsequently, a cleaning process can be performed and photoresist pattern <b>108</b> is removed (in either order).
0028Then, as shown in <figref idref="DRAWINGS">FIG. 1E</figref>, insulator layer <b>110</b> may be formed over semiconductor substrate <b>102</b> and lower metal line <b>104</b><i>a </i>by depositing an insulating material, such as an HDP oxide layer, by a PVD method or a chemical vapor deposition (CVD) method, for example. Then, a top surface of insulator layer <b>110</b> may be planarized by a CMP process. Next, photoresist pattern <b>112</b> for forming contact hole <b>113</b> (see <figref idref="DRAWINGS">FIG. 1F</figref>) exposing groove <b>107</b> of lower metal line <b>104</b><i>a </i>can be formed on insulator layer <b>110</b>.
0029Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1F</figref>, contact hole <b>113</b> may be formed by etching insulator layer <b>110</b> according to photoresist pattern <b>112</b> formed on insulator layer <b>110</b>. Then, a cleaning process can be performed and photoresist pattern <b>112</b> removed (in either order).
0030Subsequently, as shown in <figref idref="DRAWINGS">FIG. 1G</figref>, contact electrode <b>114</b> can be formed by filling a metal material in contact hole <b>113</b>, generally by a chemical vapor deposition (CVD) method. The contact electrode may comprise, for example, tungsten (W), and before depositing the bulk contact electrode material, the contact hole may be first lined with an adhesive and/or barrier layer, such as a titanium adhesive layer and/or titanium nitride (TiN) barrier layer. A metal layer can be formed thereabove by depositing a metal material by any of various methods, such as an ion beam method, an electron beam method, or an RF sputtering method. Then, an upper metal line <b>116</b> may be formed by etching the metal layer according to a photoresist pattern (not shown). Then, the photoresist pattern (not shown) can be removed.
0031As described above, according to an exemplary embodiment of the present invention, a groove or other indentation may be formed on an upper surface of a lower metal line, thereby reducing contact resistance since an effective contact area of a contact electrode formed above the lower metal line is increased.
0032In addition, reliability of a semiconductor device made according to the present invention may be enhanced by the lowered contact resistance.
0033While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Contents5
6 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US4860084A | Cites | United States of America | Search report |
| US4948459A | Cites | United States of America | Search report |
| US5008216A | Cites | United States of America | Applicant |
| US5008730A | Cites | United States of America | Applicant |
| US5082801A | Cites | United States of America | Search report |
| US5403779A | Cites | United States of America | Applicant |
| US5409861A | Cites | United States of America | Search report |
| US5494853A | Cites | United States of America | Search report |
| US5633198A | Cites | United States of America | Search report |
| US5716888A | Cites | United States of America | Search report |
| US5889328A | Cites | United States of America | Applicant |
| US5952723A | Cites | United States of America | Search report |
| US6083842A | Cites | United States of America | Search report |
| US7148572B2 | Cites | United States of America | Search report |
4 members in 2 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 1020040067373 | Republic of Korea | – | |
| 20040067373 | Republic of Korea | A | |
| 20040067373 | Republic of Korea | A | |
| 1020040067373 | – | – | – |
| KR20040067373 | – | – | – |
Members4
| Document | Office | Kind | |
|---|---|---|---|
| US2006046466A1 | United States of America | A1 | |
| KR20060018971A | Republic of Korea | A | |
| US7595265B2This record | United States of America | B2 | |
| KR101101192B1 | Republic of Korea | B1 |
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Numbers
- Publication
- 7595265
- Publication, DOCDB
- 7595265
- Publication, EPODOC
- US7595265
- Application
- 11212998
- Application, DOCDB
- 21299805
- Application, EPODOC
- US20050212998
Titles
- English
- Semiconductor device and method for forming a metal line in the semiconductor device
Patent term adjustment
- A delay
- +350 daysthe office missed an examination deadline
- B delay
- +49 dayspendency past three years
- Applicant delay
- −55 days
- Net adjustment
- 344 days
Classification
- CPC, 3
- H01L21/76885
- H01L21/3205
- H01L21/76838
- IPC, 1
- H01L21 44
- USPC, 6
- 438669000
- 257775000
- 257E21589
- 257E29112
- 438666000
- 438720000