Memory device for protecting memory cells during programming

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent application Ser. No. 11/552,426, filed Oct. 24, 2006 now U.S. Pat. No. 7,391,638, entitled “MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING”, which is herein incorporated by reference.

This application is related to U.S. application Ser. No. 11/552,441, filed Oct. 24, 2006, and entitled “METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING,” which is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to memory devices and, more particularly, to programming non-volatile memory devices.

2. Description of the Related Art

Memory devices that provide persistent data storage use non-volatile memory cells. The memory devices can typically be implemented by semiconductor chips. The semiconductor chips can be used internal to electronic systems or can be used within memory cards that can be removably attached to electronic systems. Memory cards are commonly used to store digital data for use with various products (e.g., electronic products). Memory cards often use Flash type or EEPROM type memory cells to store the data. Memory cards have a relatively small form factor and have been used to store digital data for electronic products (e.g., portable consumer electronic products). A major supplier of memory cards is SanDisk Corporation of Sunnyvale, Calif.

Several methods are known for programming non-volatile memory cells. One method applies a programming pulse of a sufficiently long duration to program a memory cell. In order to guarantee that every memory cell is able to be programmed using this method, programming time and power are set for worst-case conditions. Accordingly, this “over-provisioning” approach can result in excessive average programming time and power. In another method, a series of short, high-voltage programming pulses is applied to a memory cell. After each programming pulse, a nominal-voltage reading pulse is applied to determine whether the memory cell is in a programmed state. If the memory cell is in a programmed state, no further programming pulses are applied. Otherwise, an additional programming pulse is applied, and the sequence of reading and programming continues until the memory cell is eventually in a programmed state. One disadvantage of this approach is the time and power overhead associated with switching between program and read voltages. Another disadvantage of this approach is that the use of short programming pulses (as compared to a long, continuous programming pulse) tends to be less energy efficient.

More recently, a method for programming non-volatile memory cells made use of detection circuits. While a particular memory cell is being programmed, a detection circuit determines whether the memory cell is in a programmed state. Once the memory cell is detected to have reached the programmed state, the programming of the memory cell is terminated. Additional details on this method for programming are provided in U.S. Pat. No. 6,574,145. However, in programming memory cells, the memory cells can be subjected to high voltages and high power which are problematic when the memory cells become programmed and the programming voltage has not yet been removed. Although the programming voltage will be removed in due time after a memory cell has been programmed, the excessive power can cause damage to the already programmed memory cell.

Thus, there is still a need for improved memory devices and programming methods.

SUMMARY OF THE INVENTION

The invention relates to improved circuitry and methods for programming memory cells of a memory device. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. The invention can be particularly useful for use with two-terminal memory cells.

The invention can be implemented in numerous ways, including as a method, system, device or apparatus. Several embodiments of the invention are discussed below.

As a memory device, one embodiment of the invention includes at least: a non-volatile memory element; a current monitor configured to monitor a program current flowing through the non-volatile memory element; and a current limiter configured to restrict the current flowing through the non-volatile memory element.

As a memory device, another embodiment of the invention includes at least: a memory array including a plurality of layers of memory cells stacked vertically above one another in a single chip; a detection circuit operative to detect, while a memory cell of the memory array is being programmed, when the memory cell is in a programmed state; and a memory cell protection circuit operative to protect the memory cell of the memory array against excessive electrical energy at least while the memory cell is being programmed.

As a memory device having an array of memory elements accessible via at least one bitline and at least one wordline, one embodiment of the invention includes at least: a first field-effect transistor having first, second and third terminals, the first terminal connected to a first potential; a second field-effect transistor having first, second and third terminals, the first terminal connected to the second terminal of the first field-effect transistor, and the second terminal connected to a bitline; a memory element connected to a wordline and to the bitline; a third field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a first node, and the third terminal connected to the third terminal of the first field-effect transistor; a fourth field-effect transistor having first, second and third terminals, the first terminal connected to the first node, the second terminal connected to a second potential; a fifth field-effect transistor having first, second and third terminals, the first terminal connected to a first current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the fourth field-effect transistor, the first terminal further being connected to the third terminal; a sixth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to a second node, and the third terminal connected to the third terminal of the first field-effect transistor; a seventh field-effect transistor having first, second and third terminals, the first terminal connected to the second node, the second terminal connected to the second potential; an eighth field-effect transistor having first, second and third terminals, the first terminal connected to a second current source, the second terminal connected to the second potential, and the third terminal is connected to the third terminal of the seventh field-effect transistor, the first terminal further being connected to the third terminal; program control circuitry connected to the second node; and a ninth field-effect transistor having first, second and third terminals, the first terminal connected to the first potential, the second terminal connected to the third terminal of the first field-effect transistor, and the third terminal connected to the program control circuitry, wherein the third terminal of the second field-effect transistor is connected to the first node.

As an electronic system, one embodiment of the invention includes at least: a data acquisition device; and a data storage device removably coupled to the data acquisition device. The data storage device stores data acquired by the data acquisition device. The data storage device includes at least: an array of data storage elements; a detection circuit operative to detect, while a data storage element of the array is being programmed, when the data storage element is in a programmed state; and a protection circuit operative to protect the data storage element of the array against excessive electrical energy at least while the memory cell is being programmed.

Other aspects and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a memory device according to one embodiment of the invention.

<figref idref="DRAWINGS">FIG. 2</figref> is a flow diagram of a memory programming process according to one embodiment of the invention.

<figref idref="DRAWINGS">FIG. 3</figref> is a schematic diagram of a memory device according to one embodiment of the invention.

<figref idref="DRAWINGS">FIG. 4</figref> is a schematic diagram of a memory device according to another embodiment of the invention.

<figref idref="DRAWINGS">FIG. 5</figref> is a schematic diagram of a memory device according to another embodiment of the invention.

<figref idref="DRAWINGS">FIG. 6</figref> is a schematic diagram of a memory device according to another embodiment of the invention.

<figref idref="DRAWINGS">FIG. 7</figref> is a schematic diagram of a memory device according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to improved circuitry and methods for programming memory cells of a memory device. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. The invention can be particularly useful for use with two-terminal memory cells.

Embodiments of this aspect of the invention are discussed below with reference to <figref idref="DRAWINGS">FIGS. 1-7</figref>. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments.

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a memory device <b>100</b> according to one embodiment of the invention. The memory device <b>100</b> includes a memory element <b>102</b>. The memory element <b>102</b> is, for example, a non-volatile memory element. One implementation for a non-volatile memory element is a diode or antifuse type memory element. The memory element <b>102</b> is typically part of a memory array. The various memory elements within the memory array can be accessed by way of bitlines <b>104</b> and wordlines <b>106</b>. Hence, the memory element <b>102</b> is shown as being coupled between a bitline <b>104</b> and a wordline <b>106</b>. When programming the memory element <b>102</b>, a voltage is applied across the memory element <b>102</b> to invoke a physical characteristic change in the memory element <b>102</b>. As an example, when the memory element <b>102</b> corresponds to an antifuse type device, the programming of the memory element <b>102</b> is referred to as “popping” or “blowing” the antifuse.

The memory device <b>100</b> includes a programming switch <b>108</b>. The programming switch <b>108</b> couples to a voltage potential (Vp) used for programming. When the programming switch <b>108</b> is enabled by a program control circuit <b>110</b>, a program current (Ipmg) is supplied from the voltage potential (Vp) to a current monitor <b>112</b>. The current monitor <b>112</b> monitors the program current (Ipmg) that flows through the memory element <b>102</b>. Here, in this embodiment, the amount of current flowing through the memory element <b>102</b> provides an indication of whether or not the memory element <b>102</b> has been programmed. In other words, while the memory element <b>102</b> is being programmed by the program current (Ipmg), the current monitor <b>112</b> monitors the level of the program current (Ipmg). The monitored current level detected by the current monitor <b>112</b> is supplied to the program control circuit <b>110</b>. The program control circuit <b>110</b> based on the monitored current level determines whether the memory element <b>102</b> has been completely programmed. When the program control circuit <b>110</b> determines that the memory element <b>102</b> has been programmed, the program control circuit <b>110</b> can signal the programming switch <b>108</b> to deactivate the programming. In one embodiment, the program control circuit <b>110</b> can impose a delay prior to deactivating the programming.

The memory device <b>100</b> also includes a current limiter <b>114</b>. The current limiter <b>114</b> operates to limit the maximum amount of current that is permitted to be used when programming the memory element <b>102</b>. In other words, the current limiter <b>114</b> prevents the program current (Ipmg) from exceeding a maximum current level. The current limiter <b>114</b> thus protects the memory element <b>102</b> from damage during or after programming of the memory element <b>102</b>.

Besides providing protection for a memory element during programming, a current limiter can also protect a memory element when not being programmed. For example, in some embodiments, a pre-charging is performed in advance of programming to improve the programming. Hence, the protection for the memory cells can also be used to protect the memory elements during pre-charging.

The programming of the memory cells can be efficient with regard to programming time and power. For example, a memory cell can be pre-charged rapidly since the current used for pre-charge can be set to the maximum level that the memory cell can withstand. Additionally, in programming a memory cell, programming occurs only for as long as it is needed. That is, unlike a fixed program duration, once a memory cell becomes programmed, its programming can be stopped. Further, programming bandwidth (the number of memory cells that can be programmed per unit time) can be high. In one embodiment, a plurality of memory cells along a wordline can be programmed simultaneously.

The memory element being programmed can relate to a non-volatile memory cell (i.e., a memory cell whose data is not lost or altered when electrical power is removed). Although any suitable memory array can be used, in one embodiment, the memory cell is part of a three-dimensional memory array, which can provide economies in terms of reduced size and associated reductions in manufacturing cost. In one implementation, the memory array can include a vertical array of layers as memory cells. The memory array can be part of a compact, modular memory device used with portable consumer electronic products. In one embodiment, the memory cell is field-programmable. A field-programmable memory cell is a memory cell that is fabricated in an initial, un-programmed digital state and can be switched to an alternative, programmed digital state at a time after fabrication. Although any suitable type of memory cell can be used, in one embodiment, the memory cell is a write-once memory cell comprising an antifuse and a diode, for example as described in U.S. Pat. Nos. 6,034,882 and 6,515,888, both of which are hereby incorporated by reference. In its un-programmed state, the antifuse is intact, and the memory cell holds a Logic 1. When suitable voltages are applied to the appropriate wordline and bitline, the antifuse of the memory cell is blown, and the diode is connected between the wordline and the bitline. This places the memory cell in a programmed (Logic 0) state. Alternatively, the un-programmed state of the memory cell can be Logic 0, and the programmed state can be Logic 1. Memory cells that support multiple programmed states can also be used. If the memory is of the write-once type, the initial, un-programmed digital state cannot be restored once the memory cell is switched to the programmed digital state. Instead of being write-once, the memory cell can be write-many (re-writeable). Unlike the digital state of a write-once memory cell, the digital state of a write-many memory cell can be switched between “un-programmed” and “programmed” digital states. When referring to write-many memory cells, the un-programmed digital state refers to the digital state of the memory cell before a programming operation. Accordingly, the un-programmed digital state can refer to either Logic 0 or Logic 1 (in a two-state memory cell) and does not necessarily refer to the digital state in which that memory cell was fabricated.

<figref idref="DRAWINGS">FIG. 2</figref> is a flow diagram of a memory programming process <b>200</b> according to one embodiment of the invention. The memory programming process <b>200</b> is, for example, associated with programming a memory element, such as a memory element within a memory array provided within a memory device.

The memory programming process <b>200</b> initially activates <b>202</b> programming of a memory element. The memory element is one of a plurality of memory elements provided within a memory device. For example, the memory element to be programmed can pertain to the memory element <b>102</b> of the memory device <b>100</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>.

A decision <b>204</b> then determines whether a program current (programming current) is greater than or equal to a maximum current. When the decision <b>204</b> determines that the program current is greater than or equal to the maximum current, the program current is limited <b>206</b> to the maximum current. Following the block <b>206</b>, or following the decision <b>204</b> when the program current is not greater than or equal to the maximum current, a decision <b>208</b> determines whether the program current is greater than or equal to a sense current. The sense current is an amount of current used to sense whether the programming element has been programmed. When the decision <b>208</b> determines that the program current is not greater than or equal to the sense current, then the memory programming process <b>200</b> returns to repeat the decision <b>204</b> and subsequent blocks so that the programming of the memory element can continue. In doing so, the memory element is protected from damage by the block <b>206</b> which prevents the program current from exceeding the maximum current. On the other hand, when the decision <b>208</b> determines that the program current is greater than the sense current, then programming of the memory element is deactivated <b>210</b>. Here, the programming of the memory element is deactivated <b>210</b> because the memory element has been programmed. In other words, when the program current reaches the level of the sense current, then the memory element is programmed. Following the block <b>210</b>, the memory programming process <b>200</b> ends.

Hence, in one embodiment, the programming of a memory element is efficient and effective. First, the program current used during programming can be high since the program current is guaranteed not to exceed the maximum current for the memory element. The high program current leads to rapid programming of the memory element. Second, the program time for the memory element is optimized to the memory element itself. That is, when the memory element becomes programmed, the programming of the memory element ceases.

<figref idref="DRAWINGS">FIG. 3</figref> is a schematic diagram of a memory device <b>300</b> according to one embodiment of the invention. The memory device <b>300</b> includes a memory element <b>302</b>. As depicted in <figref idref="DRAWINGS">FIG. 3</figref>, the memory element <b>302</b> is being programmed (written). The memory element <b>302</b> is coupled between a bitline <b>304</b> and a wordline <b>306</b>, which enables selection of the memory element <b>302</b> from a plurality of memory elements in the memory device <b>300</b>. The memory element <b>302</b> is programmed by supplying a programming voltage across the memory element <b>302</b> which induces a program current (Ipmg) through the memory element <b>302</b>. The program current (Ipmg) is supplied by a field-effect transistor (FET) <b>308</b>.

The program current (Ipmg) is also limited by a FET <b>310</b>. The FET <b>310</b> is controlled by a node <b>312</b>. The node <b>312</b> is provided between a FET <b>314</b> and a current source (Imax) <b>316</b>. When the program current (Ipmg) exceeds the maximum current (Imax), the node <b>312</b> is pulled high by the FET <b>314</b>. As a result, in such case, the FET <b>310</b> operates to restrict or stop the program current (Ipmg) from reaching the memory element <b>302</b>.

The memory device <b>300</b> also includes a FET <b>318</b> that couples between the programming potential (Vp) and a node <b>320</b>. The node <b>320</b> is also coupled to ground by way of a sense current source (Is) <b>322</b>. When the program current (Ipmg) exceeds the sense current (Is), the second node <b>320</b> is pulled high by the FET <b>318</b>. In such case, the program control circuit <b>324</b> can cause a FET <b>326</b> to turn off the FET <b>308</b>, thereby ceasing programming of the memory element <b>302</b>. Additionally, when the second node <b>320</b> is pulled high by the FET <b>318</b>, the program control circuit <b>324</b> can cause a FET <b>328</b> to turn off, thereby disconnecting the gate of the FET <b>308</b> from the drain of the FET <b>308</b>. The program control circuit <b>324</b> can turn off the FET <b>328</b> via an inverter <b>330</b>. In one implementation, the program control circuit <b>324</b> can induce a delay and thus need not be immediately responsive to a change in voltage level of the second node <b>320</b>.

<figref idref="DRAWINGS">FIG. 4</figref> is a schematic diagram of a memory device <b>400</b> according to another embodiment of the invention. The memory device <b>400</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref> is generally similar to the memory device <b>300</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. However, the memory device <b>400</b> includes additional implementation details that can be provided in accordance with one embodiment of the invention.

The memory device <b>400</b> includes a memory element <b>402</b>. The memory element <b>402</b> is coupled between a bitline <b>404</b> and a wordline <b>406</b>. The memory device <b>400</b> operates, in one mode, to program the memory element <b>402</b> by applying a voltage across the memory element <b>402</b>. The result of the voltage across the memory element <b>402</b> is to effectuate programming of the memory element. In one implementation, as the memory element <b>402</b> is being programmed, the program current (Ipmg) passing through the memory element <b>402</b> increases. At some point, the level of the program current (Ipmg) can signal that the memory element <b>402</b> has been adequately programmed.

The memory device <b>400</b> includes a first FET <b>408</b> that couples to a voltage potential (Vp) suitable for programming. The first FET <b>408</b> is utilized to provide the program current (Ipmg) that is used to program the memory element <b>402</b>. A second FET <b>410</b> couples between the first FET <b>408</b> and the memory element <b>402</b>. The second FET <b>410</b> is utilized to limit the amount of current that can flow through to the memory element <b>402</b>. In other words, the FET <b>410</b> is controlled to limit the program current (Ipmg) to a maximum level. A third FET <b>412</b> is also provided to bias a gate terminal of the FET <b>408</b>. A source terminal of the FET <b>408</b> is coupled to the voltage potential (Vp) and a drain terminal of the FET <b>408</b> is coupled to a drain terminal of the FET <b>410</b> at a node <b>413</b>. A source terminal of the FET <b>410</b> is coupled to the memory element <b>402</b> by way of the bitline <b>404</b>. A drain terminal of the FET <b>412</b> is coupled to the voltage potential (Vp), a gate terminal of the FET <b>412</b> is connected to the node <b>413</b>, and a source terminal of the FET <b>412</b> is coupled to the gate terminal of the FET <b>408</b> as well as to a bias current source (Ibias) <b>414</b>.

To control the FET <b>410</b>, the memory device <b>400</b> also includes a FET <b>415</b>, a node <b>416</b>, and FETs <b>418</b> and <b>420</b>. The FET <b>415</b> has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET <b>408</b>, and a drain terminal connected to the node <b>416</b>. The gate terminal of the FET <b>410</b> also connects to the node <b>416</b>. The FETs <b>418</b> and <b>420</b> are connected to form a current mirror circuit for a maximum reference current (Imax).

During operation, the program current (Ipmg) that passes from the source terminal to the drain terminal of the FET <b>408</b> is mirrored to the FET <b>415</b>. This program current (Ipmg) is compared to a maximum current (Imax) at the node <b>416</b>. If the program current exceeds the maximum current, the node <b>416</b> is pulled high so as to restrict or prevent the program current (Ipmg) from being provided to the memory element <b>402</b>.

The memory device <b>400</b> also includes a FET <b>422</b>, a node <b>424</b>, and FETs <b>426</b> and <b>428</b>. The FET <b>422</b> has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET <b>408</b> and a drain terminal connected to a node <b>424</b>. The FETs <b>426</b> and <b>428</b> provide a current mirror circuit for a sense reference current (Is). A drain terminal of the FET <b>426</b> is coupled to the node <b>424</b>. The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET <b>408</b> is mirrored to the FET <b>422</b>. Hence, the node <b>424</b> can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node <b>424</b> is pulled high. When the node <b>424</b> is pulled high, a program control circuit <b>430</b> understands that the programming of the memory element <b>402</b> has been completed. At this point, either immediately or following a predetermined delay, the program control circuit <b>430</b> can instruct a FET <b>432</b> to disable further programming of the memory element <b>402</b>. The FET <b>432</b> has its source terminal connected to the voltage potential (Vp) and a drain terminal connected to the gate terminal of the FET <b>408</b>. Further, the gate terminal of the FET <b>432</b> is connected to the program control circuit <b>430</b>.

To reduce power consumption, the current mirror circuits can use a different ratio than the programming circuitry. For example, the channel width for the FETs <b>415</b> and <b>422</b> can be made smaller than the channel width of the FET <b>408</b>, thereby producing lower currents in the current mirror circuits which in turn reduces power consumption. As another example, the FET <b>408</b> could be manufactured to be N-times that of the FETs <b>415</b> and <b>422</b>, where N is the desired current ratio. In such an example, the FET <b>408</b> can be implemented using N transistors used in parallel relative to using one transistor for the FETs <b>415</b> and <b>422</b>.

<figref idref="DRAWINGS">FIG. 5</figref> is a schematic diagram of a memory device <b>500</b> according to another embodiment of the invention. The memory device <b>500</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref> provides separate circuitry for monitoring programming and limiting program current as do the memory device <b>300</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> and the memory device <b>400</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>. The memory device <b>500</b> utilizes a double current mirror design.

The memory device <b>500</b> includes a memory element <b>502</b>. The memory element <b>502</b> is coupled between a bitline <b>504</b> and a wordline <b>506</b>. The memory device <b>500</b> operates, in one mode, to program the memory element <b>502</b> by applying a voltage across the memory element <b>502</b>. The result of the voltage across the memory element <b>502</b> is to effectuate programming of the memory element <b>502</b>. In one implementation, as the memory element <b>502</b> is being programmed, the program current (Ipmg) passing through the memory element <b>502</b> increases. At some point, the level of the program current (Ipmg) can signal that the memory element <b>502</b> has been adequately programmed.

The memory device <b>500</b> includes a first FET <b>508</b> that couples to a voltage potential (Vp) suitable for programming. The first FET <b>508</b> is utilized to provide the program current (Ipmg) that is used to program the memory element <b>502</b>. A second FET <b>510</b> couples between the first FET <b>508</b> and the memory element <b>502</b>. The second FET <b>510</b> is utilized to limit the amount of current that can flow through to the memory element <b>502</b>. In other words, the FET <b>510</b> is controlled to limit the program current (Ipmg) to a maximum level. A source terminal of the FET <b>508</b> is coupled to the voltage potential (Vp) and a drain terminal of the FET <b>508</b> is coupled to a drain terminal of the FET <b>510</b>. A source terminal of the FET <b>510</b> is coupled to the memory element <b>502</b> by way of the bitline <b>504</b>. A third FET <b>512</b>, a fourth FET <b>514</b> and a current source (Imax) <b>516</b> are connected in series to bias a gate terminal of the FET <b>510</b> such that the program current (Ipmg) does not exceed the maximum current (Imax). The FETs <b>510</b> and <b>512</b> are connected to form a current mirror circuit for a maximum reference current (Imax).

The memory device <b>500</b> also includes a FET <b>518</b>, a current source (Is) <b>520</b> and a node <b>522</b>. The FET <b>518</b> has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET <b>508</b> and a drain terminal connected to the node <b>522</b>. The FETs <b>508</b> and <b>510</b> provide another current mirror used to compare the program current (Ipmg) with a sense reference current (Is). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET <b>508</b> is mirrored to the FET <b>518</b>. Hence, the node <b>522</b> can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node <b>522</b> is pulled high. When the node <b>522</b> is pulled high, a program control circuit (not shown) understands that the programming of the memory element <b>502</b> has been completed. At this point, either immediately or following a predetermined delay, the program control circuit can disable further programming of the memory element <b>502</b>.

<figref idref="DRAWINGS">FIG. 6</figref> is a schematic diagram of a memory device <b>600</b> according to another embodiment of the invention. The memory device <b>600</b> illustrated in <figref idref="DRAWINGS">FIG. 6</figref> provides separate circuitry for monitoring programming and limiting program current. The memory device <b>600</b> utilizes a current mirror and a replicated memory element current path.

The memory device <b>600</b> includes a memory element <b>602</b>. The memory element <b>602</b> is coupled between a bitline <b>604</b> and a wordline <b>606</b>. The memory device <b>600</b> operates, in one mode, to program the memory element <b>602</b> by applying a voltage across the memory element <b>602</b>. The result of the voltage across the memory element <b>602</b> is to effectuate programming of the memory element <b>602</b>. In one implementation, as the memory element <b>602</b> is being programmed, the program current (Ipmg) passing through the memory element <b>602</b> increases. At some point, the level of the program current (Ipmg) can signal that the memory element <b>602</b> has been adequately programmed.

The memory device <b>600</b> includes a first FET <b>608</b> that couples to a voltage potential (Vp) suitable for programming. The first FET <b>608</b> is utilized to provide the program current (Ipmg) that is used to program the memory element <b>602</b>. A source terminal of the FET <b>608</b> is coupled to the voltage potential (Vp) and a drain terminal of the FET <b>608</b> is coupled to the memory element <b>602</b> by way of the bitline <b>604</b>. A second FET <b>61</b><b>0</b> and a current source (Imax) <b>612</b> are connected in series. A source terminal of the FET <b>610</b> is coupled to the voltage potential (Vp) and a drain terminal of the FET <b>610</b> is coupled to the current source (Imax) <b>612</b>. The gate terminals of the FETs <b>608</b> and <b>610</b> are connected together. The FET <b>610</b> and the current source (Imax) <b>612</b> operate to bias a gate terminal of the FET <b>608</b> such that the program current (Ipmg) does not exceed the maximum current (Imax). In other words, the FETs <b>608</b> and <b>610</b> are connected to form a current mirror circuit that operates to prevent the program current (Ipmg) from exceeding a maximum reference current (Imax).

The memory device <b>600</b> also includes a FET <b>614</b>, a comparator <b>616</b> and a FET <b>518</b> to replicate the memory element current path. The FETs <b>614</b> and <b>618</b> are connected in series between the voltage potential (Vp) and ground. A node <b>615</b> is provided at the connection of the FETs <b>614</b> and <b>618</b>. The comparator <b>616</b> compares the voltage at the node <b>615</b> with the voltage at node <b>617</b>, which is at the connection of the FET <b>608</b> and the memory element <b>602</b>. The output of the comparator <b>616</b> serves to bias the gate terminal of the FET <b>618</b> such that a monitored current (Im) is substantially the same (i.e., replicated) as the program current (Ipmg). Further, the memory device includes a FET <b>620</b> and current source (Is) <b>622</b>. The current source (Is) <b>622</b> is connected to the voltage potential (Vp) and to a node <b>624</b>. The FET <b>620</b> is connected between the node <b>622</b> and ground. The gate of the FET <b>620</b> is connected to the gate of the FET <b>618</b> such that a mirrored monitored current (Im′) is drawn from the node <b>624</b> by the FET <b>620</b>. Hence, the node <b>624</b> can determine whether the program current (Ipmg) exceeds the sense reference current (Is). When the program current (Ipmg) exceeds the sense reference current (Is), the node <b>622</b> is pulled low. When the node <b>622</b> is pulled low, a program control circuit (not shown) understands that the programming of the memory element <b>602</b> has been completed. At this point, either immediately or following a predetermined delay, the program control circuit can disable further programming of the memory element <b>602</b>.

<figref idref="DRAWINGS">FIG. 7</figref> is a schematic diagram of a memory device <b>700</b> according to another embodiment of the invention. The memory device <b>700</b> illustrated in <figref idref="DRAWINGS">FIG. 7</figref> provides monitoring for both programming current and excessive current.

The memory device <b>700</b> includes a memory element <b>702</b>. The memory element <b>702</b> is coupled between a bitline <b>704</b> and a wordline <b>706</b>. The memory device <b>700</b> operates, in one mode, to program the memory element <b>702</b> by applying a voltage across the memory element <b>702</b>. The result of the voltage across the memory element <b>702</b> is to effectuate programming of the memory element <b>702</b>. In one implementation, as the memory element <b>702</b> is being programmed, the program current (Ipmg) passing through the memory element <b>702</b> increases. At some point, the level of the program current (Ipmg) can signal that the memory element <b>702</b> has been adequately programmed.

The memory device <b>700</b> includes a first FET <b>708</b> that couples to a voltage potential (Vp) suitable for programming. The first FET <b>708</b> is utilized to provide the program current (Ipmg) that is used to program the memory element <b>702</b>. A second FET <b>710</b> couples between the first FET <b>708</b> and the memory element <b>702</b>. The second FET <b>510</b> can be utilized to limit the amount of current that can flow through to the memory element <b>702</b>. For example, the FET <b>710</b> can be controlled to limit the program current (Ipmg) to a maximum level. A source terminal of the FET <b>708</b> is coupled to the voltage potential (Vp) and a drain terminal of the FET <b>708</b> is coupled to a drain terminal of the FET <b>710</b>. A source terminal of the FET <b>710</b> is coupled to the memory element <b>702</b> by way of the bitline <b>704</b>.

The memory device <b>700</b> also includes a FET <b>712</b> and a current source (Is) <b>714</b> and a node <b>716</b>. The FET <b>712</b> has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET <b>708</b> and a drain terminal connected to the node <b>716</b>. The FETs <b>708</b> and <b>712</b> provide a first current mirror used to compare a mirrored program current (Ipmg′) with a sense reference current (Is). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET <b>708</b> is mirrored to the FET <b>712</b>. Hence, the node <b>716</b> can determine whether the mirrored program current (Ipmg′) exceeds the sense reference current (Is). When the mirrored program current (Ipmg′) exceeds the sense reference current (Is), the node <b>716</b> is pulled high. When the node <b>716</b> is pulled high, a program control circuit <b>718</b> understands that the programming of the memory element <b>702</b> has been completed. At this point, either immediately or following a predetermined delay, the program control circuit <b>718</b> can disable further programming of the memory element <b>702</b> in any of a number of ways (including through use of the FET <b>710</b>).

Still further, the memory device <b>700</b> also includes a FET <b>720</b> and a current source (Imax) <b>722</b> and a node <b>724</b>. The FET <b>720</b> has a source terminal connected to the voltage potential (Vp), a gate terminal connected to the gate terminal of the FET <b>708</b> and a drain terminal connected to the node <b>724</b>. The FETs <b>708</b> and <b>720</b> provide a second current mirror used to compare a mirrored program current (Ipmg″) with a maximum current (Imax). The program current (Ipmg) that passes from the source terminal to the drain terminal of the FET <b>708</b> is mirrored to the FET <b>720</b>. Hence, the node <b>724</b> can determine whether the mirrored program current (Ipmg″) exceeds the maximum current (Imax). When the mirrored program current (Ipmg″) exceeds the maximum current (Is), the node <b>724</b> is pulled high. When the node <b>724</b> is pulled high, a current limit control <b>726</b> understands that the program current is excessive and should be limited. At this point, the current limit control <b>726</b> can disable further programming of the memory element <b>702</b>. For example, as shown in <figref idref="DRAWINGS">FIG. 7</figref>, the current limit control <b>726</b> can supply a control signal (CTRL) to the gate of the FET <b>710</b> so that the program current (Ipmg) does not exceed the maximum current (Imax). In this embodiment, the limiting of the program current (Ipmg) is not directly provided in an analog domain as one or more other embodiments, but is instead provided by feedback control (e.g., in a digital domain) which has some inherent delay.

The invention can be particularly useful for use with two-terminal memory cells. Two-terminal memory cells, for example, can be formed from polysilicon diodes, transition metal oxide (e.g., NiO) memory elements, and chalcogenide-based memory elements. Two-terminal memory arrays can be formed in a compact manner when arranged into cross-point memory arrays. Additional details on some two-terminal memory cells are provided in the following papers which are hereby incorporated herein by reference: (i) Pirovano et al., “Electronic Switching in Phase-Change Memories,” IEEE Transactions on Electronic Devices, Vol. 51, No. 3, March 2003; (ii) Baek et al., “Multi-layer Cross-point Binary Oxide Resistive Memory (OXRRAM) for Post-NAND Storage Application,” IEEE International Electron Devices Meeting, IEEE, 2005; (iii) Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” IEEE International Electron Devices Meeting, IEEE 2004; and (iv) Hwang et al., “Writing Current Reduction for High-density Phase-change RAM,” IEEE International Electron Devices Meeting, IEEE, 2003. Additional details are also provided in U.S. Pat. No. 6,891,748, which is hereby incorporated herein by reference.

Additional details on detecting whether a memory cell being programmed is in a programmed state are provided in U.S. Pat. No. 6,574,145, which is hereby incorporated herein by reference. For additional information on program current control when programming memory elements, see (i) U.S. patent application Ser. No. 11/552,462, filed Oct. 24, 2006, and entitled “METHOD FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS”, which is hereby incorporated herein by reference; and (ii) U.S. patent application Ser. No. 11/552,472, filed Oct. 24, 2006, and entitled “MEMORY DEVICE FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS”, which is hereby incorporated herein by reference.

The invention is suitable for use with both single-level (binary) memories and multi-level (multi-state) memories. In multi-level memories, each data storage element stores two or more bits of data.

As used herein “operatively connected” refers to direct or indirect electrical connection between electrical components.

The various features, aspects, embodiments or implementations can be used alone or in any combination.

The invention can further pertain to an electronic system that includes a memory system as discussed above. A memory system is a system that includes at least a memory device that provides data storage. Memory systems (i.e., memory cards) are commonly used to store digital data for use with various electronics products. The memory system is often removable from the electronic system so the stored digital data is portable. The memory systems according to the invention can have a relatively small form factor and be used to store digital data for electronics products (e.g., consumer electronic products) that acquire data, such as cameras, hand-held or notebook computers, network cards, network appliances, set-top boxes, hand-held or other small media (e.g., audio) players/recorders (e.g., MP3 devices), personal digital assistants, mobile telephones, and medical monitors.

The advantages of the invention are numerous. Different embodiments or implementations may yield one or more of the following advantages. One advantage of the invention is that a programming current used to program a memory element (i.e., memory cell) is limited so as not exceed a maximum current. This serves to protect the memory element from potentially damaging high current levels, such as while programming the memory element or at other times. Another advantage of the invention is that sensing current to monitor programming of a memory element can be provided separate from limiting programming current to a maximum current. Still another advantage of the invention is that a higher programming voltage can be used for faster programming since the program current is otherwise limited to the maximum current. Another advantage of the invention is that memory elements to be programmed can be pre-charged while protecting the memory elements from excessive currents. Yet another advantage of the invention is that programming time to program a memory element can be optimized.

The many features and advantages of the present invention are apparent from the written description. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence, all suitable modifications and equivalents may be resorted to as falling within the scope of the invention.