Method and apparatus of reporting memory bit correction

BACKGROUND OF THE INVENTION

p-0002Mobile devices such as, for example, laptop computers, handheld devices, personal data assistance (PDA), data terminals, pocket personal computers and the like may include a processor and/or a computing platform. The processor and/or the computing platform may consume high battery power which may reduce the operation hours of such devices. In order to reduce the high power consumption from the battery, a power control mechanism to control power consumption of the processor may be used. The power control mechanism may reduce the power consumption by providing a lower voltage and/or a lower frequency to the processor and/or a computing platform. The low voltage may cause recoverable and/or unrecoverable errors in the processor and/or in a cache memory the computing platform.

p-0003The processor and/or the computing platform may include an on-die cache Memory. Random Access Memory (RAM) cells of the cache memory may limit the lowest possible voltage at which the processor may be operated. The RAM cells in on-die processor cache memories may be manufactured from devices designed with the smallest possible size supported by the fabrication process used to manufacture the processor, and the devices may be, as a side effect, very sensitive to variations that normally occur during manufacturing, causing a few cells to deviate significantly from the average in terms of the minimum voltage required for them to operate correctly. The variations may cause a failure of a bit in the cache memory line.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0004The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanied drawings in which:

p-0005<figref idrefs="DRAWINGS">FIG. 1</figref> is a schematic block diagram of a computer system according to an exemplar embodiment of the present invention;

p-0006<figref idrefs="DRAWINGS">FIG. 2</figref> is a schematic diagram demonstrating a memory and control bits according to some exemplary embodiments of the present invention;

p-0007<figref idrefs="DRAWINGS">FIG. 3</figref> is a schematic illustration of an architecture of a machine check register and a soft bit fix count register, according to some exemplary embodiments of the invention;

p-0008<figref idrefs="DRAWINGS">FIG. 4</figref> is a schematic flowchart of a method of managing a single bit fail in a memory line according to exemplary embodiments of the invention;

p-0009<figref idrefs="DRAWINGS">FIG. 5</figref> is a schematic illustration of a time table to reflect changes in time in a status of registers according to exemplary embodiments of the present invention, and helpful for demonstrating the method of <figref idrefs="DRAWINGS">FIG. 4</figref>;

p-0010<figref idrefs="DRAWINGS">FIG. 6</figref> is a schematic flowchart of a method of reporting a single bit fail in a memory line according to exemplary embodiments of the invention; and

p-0011<figref idrefs="DRAWINGS">FIG. 7</figref> is a schematic illustration of a time table to reflect changes in time in a status of registers according to exemplary embodiments of the present invention; and helpful in demonstrating the method of <figref idrefs="DRAWINGS">FIG. 6</figref>;

p-0012It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION OF THE INVENTION

p-0013In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

p-0014Some portions of the detailed description, which follow, are presented in terms of algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art.

p-0015Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. In addition, the term “plurality” may be used throughout the specification to describe two or more components, devices, elements, parameters and the like. For example, “plurality of instructions” describes two or more instructions.

p-0016It should be understood that the present invention may be used in a variety of applications. Although the present invention is not limited in this respect, the circuits and techniques disclosed herein may be used in many apparatuses such as computer systems, processors, CPU, memories, chipset graphics controllers or the like. Processors intended to be included within the scope of the present invention include, by way of example only, a reduced instruction set computer (RISC), a processor that have a pipeline, a complex instruction set computer (CISC) and the like.

p-0017Some embodiments of the invention may be implemented, for example, using a machine-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine (for example, by a processor and/or by other suitable machines), cause the machine to perform a method and/or operations in accordance with embodiments of the invention. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory (CD-ROM), Compact Disk Recordable (CD-R), Compact Disk Rewriteable (CD-RW), optical disk, magnetic media, various types of Digital Versatile Disks (DVDs), a tape, a cassette, or the like. The instructions may include any suitable type of code, for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, or the like, and may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, e.g., C, C++, Java, BASIC, Pascal, Fortran, Cobol, assembly language, machine code, or the like.

p-0018Turning firstly to <figref idrefs="DRAWINGS">FIG. 1</figref>, a block diagram of a computer system <b>100</b> according to an exemplary embodiment of the invention is shown. Although the scope of the present invention is not limited in this respect, computer system <b>100</b> may be a personal computer (PC), a personal digital assistant (PDA), an Internet appliance, a cellular telephone and/or any other computing device. In one exemplary embodiment of the invention, computer system <b>100</b> may include a main processing unit <b>110</b> powered by a power supply <b>120</b>. Main processing unit <b>110</b> may include a multi core processing unit <b>130</b> electrically coupled by a system interconnect <b>135</b> to a memory device <b>140</b> and one or more interface circuits <b>150</b>. For example, the system interconnect <b>135</b> may be an address/data bus, if desired. It should be understood that interconnects other than buses may be used to connect multi core processing unit <b>130</b> to memory device <b>140</b>. For example, one or more dedicated lines and/or a crossbar may be used to connect multi processing unit <b>130</b> to memory device <b>140</b>. Memory device <b>140</b> may include a dynamic random access memory (DRAM), a non-volatile memory, or the like. In one example, memory device <b>140</b> may store a software program which may be executed by multi core processing unit <b>130</b>, if desired.

p-0019Although the scope of the present invention is not limited in this respect, interface circuit(s) <b>150</b> may include an Ethernet interface and/or a Universal Serial Bus (USB) interface, and/or the like. In some exemplary embodiments of the invention, one or more input devices <b>155</b> may be connected to interface circuits <b>150</b> for entering data and commands into the main processing unit <b>110</b>. For example, input devices <b>160</b> may include a keyboard, mouse, touch screen, track pad, track ball, isopoint, a voice-recognition system, and/or the like.

p-0020Although the scope of the present invention is not limited in this respect, the output devices <b>170</b> may be operably coupled to main processing unit <b>110</b> via one or more of interface circuits <b>150</b> and may include one or more displays, printers, speakers, and/or other output devices, if desired. For example, one of the output devices may be a display. The display may be a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display or any other type of graphic display.

p-0021According to some embodiments of the invention, computer system <b>100</b> may include one or more storage devices <b>160</b>. For example, computer system <b>100</b> may include one or more hard drives, one or more compact disk (CD) drives, one or more digital versatile disk drives (DVD), and/or other computer media input/output (I/O) devices, if desired.

p-0022Exemplary computer system <b>100</b> may exchange data with other devices via a network connection to a network <b>165</b>. The network connection may include any type of network connection, such as, for example, an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, a wireless network interface card, etc. Network <b>165</b> may be any type of network, such as, for example, the Internet, a telephone network, a cable network, a wireless network such as, for example, a network complying IEEE standard 802.11 a/b/g, 1999, and/or the like. According to exemplary embodiment of the present invention the wireless network interface card (NIC) may provide a network connectivity to the computer system <b>100</b>, if desired.

p-0023According to some embodiments of the invention, multi core processing unit <b>130</b> may include one or more CPU's (not shown), if desired. Multi core processing unit <b>130</b> may include and/or be coupled to a cache memory <b>180</b>, such as, for example, a level two (L2) cache, or the like. In some embodiment of the invention, cache memory <b>180</b> may include a plurality of lines.

p-0024A write or read operation on a cache memory line may fail because one of the bits of the cache memory line may include an error. For example, some failures may be experienced at all times and some may occur only at low voltage.

p-0025According to embodiments of the present invention, a single bit fail in a line which includes the error may be detected and/or corrected by error correcting code ECC) information. For example, ECC information may be stored in one of the registers of a bit fail reporting module <b>190</b> with a tag and a line of cache memory <b>180</b>. When an entry of cache memory <b>180</b> is read, the tag and the line may be checked against their stored ECC data The ECC may correct and/or fix the error in the bit. For simplicity of reading, the corrected bit may be referred to herein as a single bit fix (SBF). The SBF may be reported to bit fail reporting module <b>190</b>. Although the scope of the present invention is not limited in this respect, the ECC may operate on a range of 32 bytes and cache <b>180</b> may include 64 bytes. Thus, according to this example, the ECC may detect two bits per cache line.

p-0026According to some embodiment of the invention, bit fail reporting module <b>190</b> may include registers and counters. Bit fail reporting module <b>190</b> may report SBF to an operating system (OS) of computer system <b>100</b>, if desired. It should be understood that, according to embodiments of the present invention, bit fail reporting module <b>190</b> may be implemented by hardware, or by software, or by any combination of hardware and/or software.

p-0027Turning to <figref idrefs="DRAWINGS">FIG. 2</figref>, a schematic block diagram of a memory <b>200</b> according to some exemplary embodiments of the present invention is shown. According to some exemplary embodiments of the invention, memory <b>200</b> may include a cache.

p-0028Although the scope of the present invention is not limited in this respect, the cache memory may include a Level 1 (L1) cache and/or a level 2 (L2) cache and/or a level 3 cache, for example, a Large Level Cache (LLC), if desired. Memory <b>200</b> may include lines <b>210</b>, which may include bits <b>230</b>. According to one exemplary embodiment of the invention, some bits may fail by flipping their state. For example, bit <b>220</b> may change its value from “0” to “1” (or vice versa). With embodiments of the present invention, the failed bit may be corrected by the ECC and may be referred to as SBF.

p-0029Although the scope of the present invention is not limited in this respect, lines <b>210</b> of memory <b>200</b> may include one or more status bits, for example, status bits <b>240</b> and <b>245</b>. Status bits <b>240</b> and <b>245</b> may be depicted as ECN<b>1</b> and ECN<b>0</b>, respectively. ECN<b>1</b> and ECN<b>0</b> may designate detection and correction of SBF in lines <b>210</b>. For example, ECN<b>1</b> (e.g., status bit <b>240</b>) may be used to count ECC history. It should be understood that the change in values of ECN<b>1</b> and ECN<b>0</b> allows to track the line status (e.g. line <b>210</b>) according to the flow of an algorithm of detecting, correcting and reporting the SBF, although the scope of the present invention is not limited in this respect.

p-0030According to some exemplary embodiments of the invention, a status bits state table <b>250</b> may show values of status bits <b>240</b> and <b>245</b> with regard to writing to lines <b>210</b> of memory <b>200</b> and with regard to the flow of the algorithm of detecting, correcting and reporting SBF. In a first line of table <b>250</b>, status bits ECN<b>1</b> and ECN<b>0</b> may be at “0”, which may designate first time writing into a bit in a line and/or to the line. If a correction to the bit has been made, for example, by the ECC, the ECN<b>0</b> status bit may be updated from “0” to “1”, as demonstrated by the comment “first time correction” in the second line of table <b>250</b>. If the second write to a line having a corrected bit is successful (third line of table <b>250</b>), the ECN<b>0</b> status bit may be update from “1” to “0” and the ECN<b>0</b> status bit may be update from “0” to “1”. If a second bit fail occurs in the same cache line (last line of table <b>250</b>), then ECN<b>1</b> may be updated from “0” to “1”.

p-0031Although the scope of the present invention is not limited in this respect, when the status of both the ECN<b>0</b> and ECN<b>1</b> status bits is “1”, this may indicate on a hard failure of the cache line. The line with the failure may be reported as an SBF. According to some embodiments of the present invention, the line marked as SBF in table <b>250</b> may be disabled for writing.

p-0032Turning to <figref idrefs="DRAWINGS">FIG. 3</figref>, an illustration of a machine check architecture (MCA) register <b>300</b> and a soft bit fix count register <b>310</b> according to some exemplary embodiments of the invention is shown. Although the scope of the present invention is not limited in to this embodiment, MCA register <b>300</b> may be one of the registers of a machine check architecture (MCA) of a processor, for example, a cache status register (CACHE_MC_STATUS).

p-0033According to this exemplary embodiment of the invention, MCA register <b>300</b> may include the following functions: bits <b>0</b> to <b>15</b> may indicate an MCA Error Code; bits <b>16</b> to <b>31</b> may indicate a Model Specific Error Code, for example, error codes of SBF, ECC and the like; bits <b>32</b> to <b>35</b>, <b>36</b> and <b>37</b> may indicate status of ways of a cache memory (e.g. memory <b>200</b>); bits <b>38</b> to <b>51</b> may be used as an ECC counter to count a soft error rate (ESER_CNT); bit <b>52</b> may be used as an overflow (OVF) bit of the ESER_CNT; bits <b>53</b> to <b>56</b> may be reserved for any other information; bit <b>57</b> may indicate Processor Context corrupts (PCC); for example, the PCC bit may be set to “1” if a damaging error occurs in the backside bus logic (BBL); bit <b>58</b>, an ADDRV bit, may indicate that CACHe_MC_ADDR register exists; bit <b>59</b> may indicate that MISC register is not set; bit <b>60</b> EN may indicate that an error is enabled; bit <b>61</b> may indicate, for example, that the processor was not able to correct the error condition and/or that a Serious Error that has damaged the BBL unit has occurred; bit <b>62</b> may indicate that an MCA error occurred while the result of a previous error was still in the error reporting register bank, and bit <b>63</b> may indicate that the information within other status registers is valid. It should be understood that MCA register <b>300</b> may be implemented by a hardware and/or by software and/or by any combination of hardware and software.

p-0034In at least one exemplary embodiment of the present invention, SBF count register <b>310</b> may count defected lines that were corrected by the SBF mechanism. SBF count register <b>310</b> may include a first counter, CNT<b>2</b>, to count corrected errors that repeated a second time in a cache line(e.g., bits <b>6</b>:<b>0</b>) and a second counter, CNT<b>1</b>, to count corrected errors that happened for the first time in a cache line (e.g., bit <b>24</b>:<b>11</b>). Other bits of SBF count register <b>310</b> (e.g., bits <b>10</b>:<b>7</b> and <b>30</b>:<b>25</b>) may be reserved. Bit <b>31</b> of register <b>310</b> may reflect a value of a SBF_NEVER_USED fuse which may be set if no SBF has been detected during production and/or testing, although the scope of the present invention is not limited to this example.

p-0035Turning to <figref idrefs="DRAWINGS">FIG. 4</figref> and <figref idrefs="DRAWINGS">FIG. 5</figref>. <figref idrefs="DRAWINGS">FIG. 4</figref> is a method of managing a single bit fail (SBF) according to exemplary embodiments of the invention. <figref idrefs="DRAWINGS">FIG. 5</figref> illustrates a time table <b>500</b> showing changes in time in the status of registers of exemplary embodiments of the present invention, in time, and helpful for demonstrating the method of <figref idrefs="DRAWINGS">FIG. 4</figref>. According to an exemplary embodiment of the invention, table <b>500</b> may show cache line status bits ECN<b>1</b> and ECN<b>0</b> (e.g., bits <b>240</b>, <b>245</b>) and a report register (e.g., CACHE_MC_STATUS register <b>300</b>) having counters, flags, status and/or information fields.

p-0036According to this exemplary embodiment, at time T<b>0</b> the cache status bits ECN<b>0</b> , ECN<b>1</b> and report register counters and fields may be reset to “0”. At time T<b>1</b>, a write to the cache (e.g. cache <b>200</b>) may be done (text block <b>400</b>). At time T<b>2</b>, a read and a correction of the cache line may be done. If it is a first time correction (decision block <b>405</b> of <figref idrefs="DRAWINGS">FIG. 4</figref>) then the first time correction of the line may be reported to the report register (text block <b>410</b>). A first counter (e.g., CNT<b>1</b>) may count the error correction and may be updated by changing its status from “0” to “1”, if desired (text block <b>415</b>).

p-0037According to this example, an ESER_CNT (e.g., counter of CACHE_MC_STATUS register as is shown in table <b>500</b>) may display the result a binary minus operation of CNT<b>1</b>−CNT<b>2</b>. Counters CNT<b>1</b> and CNT<b>2</b> may be at SBF count register <b>310</b> , if desired (text block <b>420</b>). The cache line may be marked as first time corrected and/or as a soft fail (text block <b>430</b>). For example, the marking of first time correction may be done by updating cache status bits ECNT [<b>1</b>:<b>0</b>], by writing into field “Model Specific” of the report register the value “0007” and/or by writing to field “MCAOD” of the report register the value “010A”, if desired.

p-0038According to this example, at time T<b>2</b> a read operation of the cache line may be done and the ECC mechanism may correct a bit fail in the cache line. At time T<b>3</b>, another read and correction to the cache line may be done. It should be understood that updating of the first and second counters of this reading and correcting of the cache line (e.g., of status bits ECN<b>0</b> and ENC<b>1</b>) may be disabled for example, by the ECC mechanism, and the reporting at the report register may be disabled too. At time T<b>4</b>, a rewrite to the corrected cache line may be done (text block <b>435</b>). The second counter (e.g., CNT<b>2</b> of SBF count register <b>310</b>) may be updated, for example, by changing its state from “0” to “1”. ESER_CNT counter may display CNT<b>1</b>−CNT<b>2</b> which may represent a decrement of ESER_CNT, if desired. At time T<b>5</b>, a read and correction of this cache line may be done. If the correction is a second time correction of the same cache line (decision block <b>440</b>) then the failure may be identified as a hard bit error (text block <b>450</b>). The ECN<b>1</b> status bit of the cache line may be incremented and together with ECN<b>0</b> , the failure may be reported as SBF (text block <b>455</b>). The second counter (e.g., CNT<b>2</b>) may be updated, or example by changing its state from “0” to “1”, if desired (text block <b>460</b>). In the report register, ESER_CNT may be updated according to the state of the first and second counters (e.g., CNT<b>1</b>−CNT<b>2</b>, text block <b>465</b>) and the cache line may be marked as SBF (text line <b>470</b>). For example, the marking may done by updating the state of status bits ECN<b>1</b> and ENC<b>0</b> of the corroded cache line, by writing the value “0008” to the “Model specific” field of the report register and by writing the value “100E” to the “MCACOD” field of the report register (e.g., report register <b>300</b>).

p-0039Although the scope of the present invention is not limited in this respect, for example, a write after reading and correcting the corrected cache line for the third time may done (text block <b>475</b>). If a third time correction of a bit of the cache line may occur (decision block <b>480</b>) for example, at time T<b>6</b>, the report of the third time correction to the report register may be disabled (text block <b>485</b>). An update of the ESER_CNT counter may be also disabled (text block <b>490</b>).

p-0040According to embodiments of the present invention, the operations of writing and reading lines of a cache memory, detecting and correcting bit failures in a cache memory line, updating the status bits of the cache line, updating counters and fields of a report register, updating counters of an SBF counters register and disabling the updating and reporting of the registers and the status bits for a third time correction of cache memory line after a second time write to a corrected cache line and/or after repeated corrections to the corrected cache line after a first write may be done do for example by a bit fail reporting unit of <b>190</b> of main processing unit <b>110</b>, if desired.

p-0041Turning to <figref idrefs="DRAWINGS">FIG. 6</figref> and <figref idrefs="DRAWINGS">FIG. 7</figref>. <figref idrefs="DRAWINGS">FIG. 6</figref> is a method to update a counter of a single bit fix (SBF) according to exemplary embodiments of the invention. <figref idrefs="DRAWINGS">FIG. 7</figref> is a time table <b>700</b> to reflect changes in time in the status of registers according to exemplary embodiments of the present invention, helpful in demonstrating the method of <figref idrefs="DRAWINGS">FIG. 6</figref>.

p-0042According to an exemplary embodiment of the invention, table <b>700</b> may show cache line status bits ECN<b>0</b> and ECN<b>1</b> (e.g., bits <b>240</b>, <b>245</b>), a report register (e.g., CACHE_MC_STATUS register <b>300</b>) having counters, flags, status and/or information fields, and an SBF count register (e.g. SBF count register <b>310</b>).

p-0043According to this exemplary embodiment, SBF count register may include counters CNT<b>1</b> and CNT<b>2</b>. The first counter CNT<b>1</b> may count the total number of ECC corrections of bits in the cache memory lines. The second counter, CNT<b>2</b> may count the total number of reported as defected cache memory lines. For example, line reported as SBF, until the count may exceed a threshold value, for example, a value of <b>127</b>.

p-0044According to the method of <figref idrefs="DRAWINGS">FIG. 6</figref>, if a read operation and correction operation to a corrected line are performed (decision block <b>600</b>), and if the upper limit of SBF has exceeded the threshold, for example, if the value of counter CNT<b>2</b> is equal to <b>127</b> (decision block <b>610</b>), then for each write operation to the error corrected cache line, for example, at times T<b>502</b>, T<b>504</b>, T<b>507</b>, T<b>509</b> of table <b>700</b>, the correction of the write operation may be reported as a single ECC (text block <b>620</b>). For example, the number of defected cache memory line after the threshold exceeded may be reported. In addition, an update of the first counter (e.g., CNT<b>1</b>) may be done (text block <b>630</b>). The value of the ESER_CNT counter may be updated according to ESER_CNT=CNT<b>1</b>−CNT<b>2</b> (text block <b>620</b>), if desired. Furthermore, at the report register, the ESER_CNT counter may count the number of corrections that have been made to the memory lines after the threshold is exceeded.

p-0045According to embodiments of the invention, the method may be repeated for each cycle of write, read and correction of the cache line as is shown at a time T<b>503</b> to T<b>509</b> of table <b>700</b>. According to this example, the ESER_CNT counter may count the errors after the SBF threshold is exceeded. The CNT<b>1</b> counter may count the total number of the SBF errors, although the scope of the present invention is in no way limited in this respect.

p-0046While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as falls within the true spirit of the invention.