Charge-domain pipelined analog-to-digital converter

INCORPORATED BY REFERENCE

p-0002This application claims the benefit of U.S. Provisional Application No. 60/901,597, filed on Feb. 15, 2007, U.S. Provisional Application No. 60/881,392, filed on Jan. 19, 2007, U.S. Provisional Application No. 60/881,967, filed on Jan. 23, 2007 and U.S. Provisional Application No. 60/900,675, filed on Feb. 9, 2007. The entire teachings of the above application(s) are incorporated herein by reference.

BACKGROUND OF THE INVENTION

p-0003In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. This capability is well-suited to performing analog-to-digital conversion using pipeline algorithms.

p-0004Charge-domain circuits are implemented as charge-coupled devices (CCDs), as MOS bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains to MOS BBDs.

p-0005Pipelined analog-to-digital converters (ADCs) are well-known in the general field of ADC design. They are widely used in applications in which high sample rates and high resolution must be combined. Pipelined ADCs implement the well-known successive-approximation analog-to-digital (A/D) conversion algorithm, in which progressively-refined estimates of an input signal are made at sequential times. In the pipelined version of this algorithm, one or several bits are resolved at each pipeline stage, the quantized estimate is subtracted from the signal, and the residue is propagated to the next pipeline stage for further processing. A commonly-used variation of the basic successive-approximation algorithm is the RSD algorithm, in which the resolution of each stage is finer than the stage's nominal bit-weight. This algorithm provides intrinsic digital code redundancy, which makes possible the relaxing of precision requirements on the comparators at each stage.

p-0006Pipelined ADCs have been implemented using a variety of circuit techniques, including switched-capacitor circuits and charge-domain circuits. The present invention pertains to charge-domain pipelined ADCs. All of the well-known algorithms used in conventional pipelined ADCs can be implemented using the circuit techniques of this invention

SUMMARY OF THE INVENTION

p-0007In the prior art, most pipelined ADCs have been implemented using switched-capacitor circuit techniques. In these circuits, signals are represented as voltages stored temporarily on capacitors. Signal pipelining is achieved through the use of MOS switches and op-amps. These methods consume relatively large amounts of power and are limited in sample-rate due to the requirement of using op-amps.

p-0008Charge-domain pipelined ADCs have the advantage of not requiring op-amps as essential components of the pipeline. Instead, they transfer charge packets directly from each pipeline stage to the next with essentially unity charge gain.

p-0009Prior-art charge-domain pipelined ADCs have been limited in accuracy or operating speed by various architectural deficiencies. BBD-based ADCs have suffered from non-linearity and other inaccuracies due to the imprecise nature of BBD charge transfer between pipeline stages. CCD-based implementations have suffered from excess power consumption due to the requirement of driving numerous CCD gates with high-speed clock signals.

p-0010The present invention provides an improved ADC implementation using MOS BBDs. This implementation achieves lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. In one embodiment it provides high-speed and high-accuracy (A/D) conversion by employing an improvement on conventional BBDs known as a “boosted” charge-transfer circuit

BRIEF DESCRIPTION OF THE DRAWINGS

p-0011The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.

p-0012<figref idrefs="DRAWINGS">FIG. 1</figref> shows a simplified circuit diagram of a BBD charge-pipeline stage.

p-0013<figref idrefs="DRAWINGS">FIG. 2</figref> illustrates voltage waveforms associated with <figref idrefs="DRAWINGS">FIG. 1</figref>.

p-0014<figref idrefs="DRAWINGS">FIG. 3</figref> shows a two-stage BBD charge pipeline.

p-0015<figref idrefs="DRAWINGS">FIG. 4</figref> illustrates voltage waveforms associated with <figref idrefs="DRAWINGS">FIG. 3</figref>.

p-0016<figref idrefs="DRAWINGS">FIG. 5</figref> shows a BBD charge-pipeline stage including conditional charge addition.

p-0017<figref idrefs="DRAWINGS">FIG. 6</figref> illustrates voltage waveforms associated with <figref idrefs="DRAWINGS">FIG. 5</figref>.

p-0018<figref idrefs="DRAWINGS">FIG. 7</figref> shows a BBD charge-pipeline stage including conditional charge addition, with the added charge composed of two independent components.

p-0019<figref idrefs="DRAWINGS">FIG. 8</figref> shows a single-ended BBD charge-pipeline stage including charge comparison.

p-0020<figref idrefs="DRAWINGS">FIG. 9</figref> shows a differential BBD charge-pipeline stage including charge comparison.

p-0021<figref idrefs="DRAWINGS">FIG. 10</figref> shows one stage of a differential charge-pipeline ADC which resolves one bit per stage.

p-0022<figref idrefs="DRAWINGS">FIG. 11</figref> shows one stage of a differential charge-pipeline ADC which implements the RSD algorithm.

DETAILED DESCRIPTION OF THE INVENTION

p-0023A description of example embodiments of the invention follows. The teachings of all patents, published applications and references cited herein are incorporated by reference in their entirety.

p-0024MOS BBD pipelines are conventionally implemented using common-gate FETs as the charge-transfer devices, which convey charge from one pipeline stage to the next. In a previous patent application by the same inventor (U.S. patent application Ser. No. 11/807,914, filed May 30, 2007 entitled “Boosted Charge Transfer Circuit”) which is hereby incorporated by reference in its entirety, an improved class of charge-transfer circuits is disclosed and explained in detail. The ADC of the present invention can be implemented using either conventional or boosted charge-transfer circuits; the preferred embodiment employs the boosted charge-transfer circuit, which provides higher operating speed and accuracy. In the following discussion and figures charge-transfer circuits are represented abstractly and some behavioral aspects of these circuits are mentioned, but no details of the operation of such circuits are provided.

p-0025In the following description, all circuits are discussed assuming electrons as the signal-charge carriers and NFETs for signal-charge transfer. Identical circuits can be applied equally well using holes as charge carriers, by employing PFETs and reversed signal and control voltage polarities.

p-0026The basic principle of a BBD pipeline of the general type employed in this invention is described with the aid of <figref idrefs="DRAWINGS">FIG. 1</figref>, which depicts a single stage of such a pipeline. In this stage charge is stored on capacitor <b>5</b>, which is connected between storage node <b>2</b> and voltage V_C1. Charge enters the stage via charge-transfer circuit <b>1</b>, and later exits the stage via charge-transfer circuit <b>3</b>. Voltage V_C1is a digital clock signal which controls the timing of charge processing in the stage. Other digital clock signals, not shown, may be used to control the activity of the charge-transfer circuits.

p-0027Operating waveforms of the pipeline stage are shown in <figref idrefs="DRAWINGS">FIG. 2</figref>. At time t₀clock voltage V_C1has a positive value <b>25</b>. V₂, the voltage of storage-node <b>2</b> in <figref idrefs="DRAWINGS">FIG. 1</figref>, is also at a high initial voltage <b>21</b>. At t₁negative charge begins to be transferred from the previous stage (to the left of <figref idrefs="DRAWINGS">FIG. 1</figref>) via charge-transfer circuit <b>1</b> into the stage shown. As this negative charge accumulates on capacitor <b>5</b>, V₂falls to a more negative value. The voltage of node <b>2</b> settles to a relatively high value <b>22</b>A if a relatively small negative charge was transferred; with a larger charge transferred, node <b>2</b> settles to a more negative voltage <b>22</b>B. At time t₂charge transfer into the stage is complete. The voltage of node <b>2</b> is related to the charge by the well-known expression Q=CV, where is the total capacitance of node <b>2</b>. In <figref idrefs="DRAWINGS">FIG. 1</figref>, C is comprised of C₅, the capacitance of capacitor <b>5</b>, plus any parasitic capacitance of node <b>2</b>; such parasitic capacitance is usually small and is neglected in this discussion.

p-0028Charge transfer out of the stage begins at time t₃when clock voltage V_C1switches to a low state. Capacitor <b>5</b> couples this voltage transition to node <b>2</b>, driving V₂low as well. Charge-transfer circuit <b>3</b> absorbs charge from capacitor <b>5</b>, limiting the negative excursion of node <b>2</b>, and eventually causing node <b>2</b> to settle to voltage <b>23</b> at t₄. Voltage <b>23</b> is a characteristic of charge-transfer circuit <b>3</b>, and is independent of the amount of charge which had been stored on node <b>2</b>. Charge-transfer circuit <b>3</b> transfers the charge absorbed from capacitor <b>5</b> to node <b>4</b> which is part of the stage following the one shown. After t₄charge transfer is complete.

p-0029Finally, at time t₅, clock voltage V_C1returns to its initial state (voltage <b>25</b>). Its positive-going transition is coupled to node <b>2</b> by capacitor <b>5</b>, raising node <b>2</b> to voltage <b>24</b>. Neglecting parasitic capacitance, no charge flows onto or off of node <b>2</b> during this transition; the voltage change of V₂is therefore equal to the voltage change of V_C1during the transition at t₅. Since V₂'s value at the start of this transition, voltage <b>23</b>, is independent of charge processed, voltage <b>24</b> is likewise independent of charge processed. This transition completes the operating cycle; the resulting voltage <b>24</b> at node <b>2</b> is thus the initial voltage for the next cycle. Thus the initial voltage state of the stage is constant cycle-to-cycle, and voltage <b>21</b>=voltage <b>24</b>. Consequently the initial and final charge on node <b>2</b> are also equal, and the charge transferred out is equal to the charge transferred in.

p-0030In summary: charge is transferred into the stage shown in <figref idrefs="DRAWINGS">FIG. 1</figref> during t₁-t₂; between times t₂and t₃it is temporarily stored on capacitor <b>5</b>, and is manifested as the value of V₂; during times t₃-t₄this charge is completely transferred to the next stage; at t₅the stage returns to its initial state, ready again to receive incoming charge. Thus the basic stage shown acts as a shift register for analog charge packets.

p-0031It should be understood that practical circuits depart in many details from this idealized description. Such departures include non-zero parasitic capacitance and imperfect charge transfer, for example. These effects, however, do not change the basic operating principles described above; and these principles can be applied in practical circuits with sufficient accuracy for useful purposes.

p-0032Conventional BBD charge pipelines have generally employed simple two-phase digital clock signals which simultaneously controlled the charge-storage capacitors and the charge-transfer FETs. Pipeline circuits such as that of <figref idrefs="DRAWINGS">FIG. 1</figref> and others described below also operate using a two-phase clocking system. In these circuits, however, it is desirable to provide independent control of the activity of the charge-transfer circuits and of other clocked events in the stage such as capacitor switching. For this reason, the circuits of the present invention employ additional clock signals which control charge-transfer circuit activity. These signals and their function will be explained with the aid of <figref idrefs="DRAWINGS">FIGS. 3 and 4</figref>.

p-0033<figref idrefs="DRAWINGS">FIG. 3</figref> shows a pipeline segment containing two successive stages, each like the basic pipeline stage of <figref idrefs="DRAWINGS">FIG. 1</figref>. This pipeline segment consists of first charge-transfer circuit <b>31</b>, first storage node <b>32</b>, and first capacitor <b>35</b>, together constituting the first pipeline stage; second charge-transfer circuit <b>33</b>, second storage node <b>34</b>, and second capacitor <b>36</b>, together constituting the second pipeline stage; and third charge-transfer circuit <b>37</b>, which is the entry point of a next pipeline stage which is not shown. Clock voltages V_C1and V_C2drive the two capacitors respectively; and digital clock signals S_CT1and S_CT2control the charge-transfer circuits.

p-0034The waveforms associated with the operation of the circuit of <figref idrefs="DRAWINGS">FIG. 3</figref> are shown in <figref idrefs="DRAWINGS">FIG. 4</figref>. The waveforms pertaining to the first stage in <figref idrefs="DRAWINGS">FIG. 3</figref>, V₃₂and V_C1, are identical with those of V₂and V_C1respectively in <figref idrefs="DRAWINGS">FIG. 2</figref>. The waveforms pertaining to the second stage in <figref idrefs="DRAWINGS">FIG. 3</figref>, V₃₄and V_C2, are similar, but shifted by one-half of the clock cycle from those of the first stage. Thus the two stages of <figref idrefs="DRAWINGS">FIG. 3</figref> operate on alternate half-cycles of the complete clock cycle. During the first half-cycle shown, when charge is transferring via charge-transfer circuit <b>31</b> into the first stage in <figref idrefs="DRAWINGS">FIG. 3</figref>, charge is transferring via charge-transfer circuit <b>37</b> out of the second stage (into the next stage, not shown). Likewise, during the second half-cycle, while charge is transferring out of the first stage via charge-transfer circuit <b>33</b>, it is being transferred into the second stage.

p-0035In order to control the direction of charge transfer, it is necessary to selectively enable the appropriate charge-transfer circuits. The digital signals S_CT1and S_CT2provide this control. As shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, S_CT1is asserted (high) during the interval t₁-t₂.This control signal enables charge-transfer circuits <b>31</b> and <b>37</b>, which are active during this interval as described above. During the corresponding interval in the second half-cycle, t₃-t₄, S_CT2is asserted, enabling charge-transfer circuit <b>33</b>. The exact means by which the digital signals S_CT1and S_CT2act to control the activity of the charge-transfer circuits is not pertinent to this invention. Some examples of such control are described in the aforementioned patent application (U.S. patent application Ser. No. 11/807,914, filed May 30, 2007 entitled “Boosted Charge Transfer Circuit”).

p-0036The two-phase operating mode just described is used in all of the pipeline circuits described below, together with control (by signals equivalent to S_CT1and S_CT2) of the charge-transfer circuits. In the interest of clarity, these details are not repeated in subsequent figures or descriptions.

p-0037In order to form a charge-domain ADC from a pipeline composed of stages similar to <figref idrefs="DRAWINGS">FIG. 1</figref>, a minimum of two operations in addition to charge storage and shifting are required: charges must be compared to a reference value, typically another charge; and a reference charge must be conditionally added to the signal charge (this ‘addition’ may be of either sign). In the ADC of this invention, these two operations are carried out in each of several pipeline stages. Implementation of these operations is explained below, beginning with the conditional addition of charge.

p-0038The basic principle employed for conditional charge addition is depicted in <figref idrefs="DRAWINGS">FIG. 5</figref>, with operating waveforms shown in <figref idrefs="DRAWINGS">FIG. 6</figref>. For the purposes of this discussion, a single-ended stage is shown. In practical ADC designs, differential operation is usually preferred; both modes are possible within the scope of this invention.

p-0039The pipeline stage shown in <figref idrefs="DRAWINGS">FIG. 5</figref> retains all the elements shown in <figref idrefs="DRAWINGS">FIG. 1</figref>. In addition, <figref idrefs="DRAWINGS">FIG. 5</figref> includes two new elements: capacitor <b>6</b> (with value C₆) connected between charge-storage node <b>2</b> and voltage V_QR1; and switch <b>7</b> connected between node <b>2</b> and voltage V_P. Switch <b>7</b> is controlled by a periodic digital clock signal (identified as S₇in <figref idrefs="DRAWINGS">FIG. 6</figref>).

p-0040<figref idrefs="DRAWINGS">FIG. 6</figref> shows the operating waveforms of the circuit of <figref idrefs="DRAWINGS">FIG. 5</figref>. The initial conditions in <figref idrefs="DRAWINGS">FIG. 6</figref> are similar to those in <figref idrefs="DRAWINGS">FIG. 2</figref>: V_C1is at high voltage <b>45</b> and V₂, the voltage of node <b>2</b>, is at high voltage <b>41</b>. In addition, V_QR1is at high voltage <b>47</b>, and switch <b>7</b> is in an off state, indicated by the low value of its control signal S₇in <figref idrefs="DRAWINGS">FIG. 6</figref>. As in <figref idrefs="DRAWINGS">FIG. 2</figref>, charge is transferred into the stage between t₁and t₂, causing V₂to fall in proportion to the incoming charge, settling at voltage <b>42</b>. The change in V₂due to incoming charge is inversely proportional to the total capacitance of node <b>2</b> as explained above. In <figref idrefs="DRAWINGS">FIG. 5</figref> (neglecting parasitic capacitance) this total capacitance is C=C₅+C₆.

p-0041After the charge is transferred in, the new features of <figref idrefs="DRAWINGS">FIG. 5</figref> come into play. At time t_3Avoltage V_QR1conditionally switches from its high state <b>47</b> to low state <b>48</b>. This conditional transition of V_QR1is coupled via C₆to node <b>2</b> where, because of capacitive division, it produces a similar but smaller voltage change. The voltage at node <b>2</b> changes to voltage <b>49</b> (dashed line) if V_QR1switches, and remains at voltage <b>42</b> (solid line) if it does not.

p-0042At time t₃, V_C1switches from high voltage <b>45</b> to low voltage <b>46</b>, instigating charge transfer out of the stage. As explained with reference to <figref idrefs="DRAWINGS">FIG. 2</figref>, node <b>2</b> is driven to a lower voltage due to coupling via capacitor <b>5</b>. Charge-transfer circuit <b>3</b> removes charge from node <b>2</b> and transfers it to the next stage. By t₄V₂settles to voltage <b>43</b> which is independent of the charge previously on node <b>2</b>, and charge transfer out of the stage is complete.

p-0043At t₅both V_C1and V_QR1return to their initial high states (voltages <b>45</b> and <b>47</b> respectively). This transition is identical for V_C1in every clock cycle. V_QR1, however, may already be at its high voltage <b>47</b>, depending on whether or not it switched at t_3A. Thus the positive step coupled to node <b>2</b> at t₅can have different values, depending on the state of V_QR1, resulting in a different final voltage. The added switch <b>7</b> in <figref idrefs="DRAWINGS">FIG. 5</figref> is used to restore the voltage (and charge) on node <b>2</b> to a repeatable state regardless of the state of V_QR1at t₅. Switch <b>7</b> is turned on, as indicated by the high state of its control signal S<b>7</b>, during t₅-t₆, thus establishing a repeatable voltage at node <b>2</b> to begin the next cycle, so voltage <b>44</b>=voltage <b>41</b>. With an ideal switch, voltage <b>44</b>=V_P; practical MOS switches introduce a small ‘pedestal’ so that voltage <b>44</b>≠V_P. This non-ideality is, however, repeatable cycle-to-cycle, so the voltage <b>44</b>=voltage <b>41</b> condition is still met in practical circuits.

p-0044Unlike the case of <figref idrefs="DRAWINGS">FIG. 1</figref> where the charge transferred into the stage was subsequently transferred out without alteration, the outgoing charge in the circuit of <figref idrefs="DRAWINGS">FIG. 5</figref> differs in general from the incoming charge: <br /><i>Q</i>_OUT<i>=Q</i>_IN<i>+C</i>₆<i>ΔV</i>_QR1<i>+Q</i>_CONST  Equation 1<br /> where C₆is the capacitance of capacitor <b>6</b>, ΔV_QR1is the change in V_QR1at t_3A, and Q_CONSTis a fixed charge which depends on V_P, voltages <b>43</b>, <b>45</b>, and <b>46</b>, and the capacitor values. As is apparent in <figref idrefs="DRAWINGS">FIG. 6</figref>, ΔV_QR1is equal to (voltage <b>48</b>-voltage <b>47</b>) if V_QR1switches, and is equal to zero if it does not. Note that both C₆ΔV_QR1and Q_CONSTcan be either positive or negative quantities.

p-0045When the circuit of <figref idrefs="DRAWINGS">FIG. 5</figref> is used to form one stage of a pipelined ADC, the quantity (voltage <b>48</b>-voltage <b>47</b>) is made equal to a reference voltage; for convenience it will be called V_R1. Correspondingly, the quantity C₆V_R1becomes a reference charge, since C₆is fixed in a given instantiation. Thus the conditional choice of ΔV_QR1=V_R1or ΔV_QR1=0 at t_3Acorresponds in Equation 1 to the conditional addition of a reference charge C₆V_R1to the incoming charge packet Q_IN. The circuit of <figref idrefs="DRAWINGS">FIG. 5</figref> thus provides one of the two operations required for charge-domain ADC implementation.

p-0046Note that the exact position of time t_3Ais not critical to the operation of the circuit of <figref idrefs="DRAWINGS">FIG. 5</figref>. The conditional transition of V_QR1can occur at any time between t₀and t₃with no change in circuit performance; under some practicable conditions it may also occur in the t₃-t₄interval.

p-0047In some ADC implementations it is desirable to provide more than one conditional charge addition in a single pipeline stage. An example of such a stage is shown in <figref idrefs="DRAWINGS">FIG. 7</figref>. This circuit includes, in addition to the elements in <figref idrefs="DRAWINGS">FIG. 5</figref>, additional capacitor <b>6</b>A and voltage source V_QR2. The operation of such a stage is identical to that of <figref idrefs="DRAWINGS">FIG. 5</figref>, except that at t_3Aeach of the voltages V_QR1and V_QR2undergoes an independent conditional transition, of size V_R1or V_R2respectively. The resulting charge transfer function of the stage is given by: <br /><i>Q</i>_OUT<i>=Q</i>_IN<i>+C</i>₆<i>ΔV</i>_QR1<i>+C</i>_6A<i>ΔV</i>_QR2<i>+Q</i>_CONST  Equation 2<br /> The same principle can be extended to any number of capacitors and V_Rvalues.

p-0048The remaining operation required for charge-domain ADC operation is charge comparison. <figref idrefs="DRAWINGS">FIG. 8</figref> shows a circuit which provides this operation. The circuit of <figref idrefs="DRAWINGS">FIG. 8</figref> is identical to that of <figref idrefs="DRAWINGS">FIG. 1</figref>, with the addition of voltage comparator <b>8</b> and latch <b>9</b>.

p-0049Comparator <b>8</b> compares the voltage of node <b>2</b> with a reference voltage V_RC. As was pointed out in connection with <figref idrefs="DRAWINGS">FIGS. 1 and 2</figref>, the voltage at node <b>2</b> after t₂depends on the amount of charge transferred into the stage: in <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, two different incoming charge quantities result in voltages <b>22</b>A and <b>22</b>B respectively at node <b>2</b>. Because of this dependence, voltage comparator <b>8</b> accomplishes a compison of charge on node <b>2</b> vs. a reference. Latch <b>9</b> captures the result of this comparison at a time between t₂and t₃defined by the digital clock signal V_C2, and provides a digital output voltage V_B.

p-0050As was mentioned above, many practical charge-domain pipelined ADCs employ differential circuitry. In such circuitry, signals are represented by pairs of charges whose difference is proportional to the signal. This arrangement permits representation of bipolar signals with unipolar charge packets, and can also provide dynamic range and noise-immunity benefits.

p-0051<figref idrefs="DRAWINGS">FIG. 9</figref> illustrates a differential pipeline stage which is functionally similar to the single-ended stage of <figref idrefs="DRAWINGS">FIG. 8</figref>. The circuit of <figref idrefs="DRAWINGS">FIG. 9</figref> contains two charge pipelines, each identical to that of <figref idrefs="DRAWINGS">FIG. 1</figref>. The upper pipeline contains elements <b>1</b>A, <b>2</b>A, <b>3</b>A, <b>4</b>A and <b>5</b>A, equivalent to elements <b>1</b>, <b>2</b>, <b>3</b>, <b>4</b>, and <b>5</b> in <figref idrefs="DRAWINGS">FIG. 1</figref>. The lower pipeline contains elements <b>1</b>B . . . <b>5</b>B, also equivalent to elements <b>1</b> . . . <b>5</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>. The latch <b>9</b> in this circuit serves the same function as in <figref idrefs="DRAWINGS">FIG. 8</figref>. In this differential configuration, however, the comparator <b>8</b> compares the voltages of the two charge storage nodes <b>2</b>A and <b>2</b>B, rather than comparing to a fixed reference as in <figref idrefs="DRAWINGS">FIG. 8</figref>. Thus the comparator decision in <figref idrefs="DRAWINGS">FIG. 9</figref> is based on the sign of the differential charge signal during the t₂-t₃interval.

p-0052The several circuit configurations described above provide all the operations needed to carry out pipelined charge-domain A/D conversion: namely charge storage and transfer, charge comparison, and conditional and constant charge addition. These operations can be combined in various ways to carry out a variety of ADC algorithms. Two examples of ADCs based on these operations are given below: one which implements a basic one-bit conversion per pipeline stage; and one which implements an RSD (sometimes called “1.5 bit”) conversion per pipeline stage.

p-0053<figref idrefs="DRAWINGS">FIG. 10</figref> illustrates a differential charge-domain pipeline ADC stage which resolves one bit per stage. The circuit shown combines the basic differential pipeline, comparator, and latch of <figref idrefs="DRAWINGS">FIG. 9</figref> with the conditional charge-addition capability of <figref idrefs="DRAWINGS">FIG. 5</figref> (used here in differential form). These elements are all identified similarly to the corresponding elements in the previous figures, and operate in the same manner. In addition the circuit of <figref idrefs="DRAWINGS">FIG. 10</figref> includes a block of logic circuitry consisting of inverter <b>71</b> and OR-gates <b>72</b> and <b>73</b>, plus level-shifters <b>74</b> and <b>75</b>.

p-0054In operation, each of the two pipelines operates like the circuit of <figref idrefs="DRAWINGS">FIG. 5</figref>, with V_QR1Aand V_QR1Beach functioning for its respective pipeline like V_QR1in <figref idrefs="DRAWINGS">FIG. 5</figref>. The logic block in <figref idrefs="DRAWINGS">FIG. 10</figref> causes either V_QR1Aor V_QR1B(but not both) to switch from a high to a low state at the appropriate time. The exact high and low voltages, V_Hand V_L, are provided in response to the logic levels at the OR-gate outputs by the level shifters <b>74</b> and <b>75</b>. Operating waveforms for each of the two pipelines in this circuit are the same as those in <figref idrefs="DRAWINGS">FIG. 6</figref>. Clock voltage V_C3determines the timing of V_QR1A/Bswitching, equivalent to t_3Ain <figref idrefs="DRAWINGS">FIG. 6</figref>. Latch <b>9</b> is clocked (by clock voltage V_C2) at a time before or coincident with V_QR1A/Bswitching.

p-0055As a result of these operating conditions, the two pipelines in <figref idrefs="DRAWINGS">FIG. 10</figref> process charge in accordance with the following equations: <br /><i>Q</i>_OUTA<i>=Q</i>_INA<i>+C</i>₆<i>ΔV</i>_QR1A<i>+Q</i>_CONST  Equation 3A<br /><i>Q</i>_OUTB<i>=Q</i>_INB<i>+C</i>₆<i>ΔV</i>_QR1B<i>+Q</i>_CONST  Equation 3B<br /> where C₆is the value of capacitors <b>6</b>A and <b>6</b>B and ΔV_QR1Aand ΔV_QR1Bare equal either to ΔV_R=V_L−V_H, or to zero. (It is assumed here for simplicity that the values of capacitors <b>6</b>A and <b>6</b>B are equal, and that both are driven by the same value of ΔV_QR; neither of these constraints are essential.) The dependence of the conditional charges in equations 3A and 3B on the comparator decision can be expressed as: <br /><i>C</i>₆<i>ΔV</i>_QR1A<i>=bC</i>₆<i>ΔV</i>_R  Equation 4A<br /><i>C</i>₆<i>ΔV</i>_QR1B=(1−<i>b</i>)<i>C</i>₆<i>ΔV</i>_R  Equation 4B<br /> where b is the value of the output bit decision, with value 1 or 0.

p-0056In the differential pipeline configuration, the signal is represented by the difference between the “A” charge and the “B” charge: Q=Q_A−Q_B. Thus Equations 3A, 3B, 4A and 4B may be combined to express the overall stage transfer function for differential signal charge: <br /><i>Q</i>_OUT<i>=Q</i>_IN+(2<i>b−</i>1)<i>C</i>₆<i>ΔV</i>_R<i>=Q</i>_IN+(2<i>b−</i>1)<i>Q</i>_STAGE  Equation 5<br /> where we have defined Q_STAGE=C₆ΔV_R. Equation 5 shows that the stage either adds Q_STAGEto the incoming charge (if b=1) or subtracts Q_STAGEfrom the incoming charge (if b=0). This operation is recognizable as one step in the well-known successive-approximation algorithm for A/D conversion, as applied to a signed signal.

p-0057A pipeline of N such stages thus produces the charge transfer function: <br /><i>Q</i>_OUT(N)<i>=Q</i>_IN+(2<i>b</i>₁−1)<i>Q</i>_STAGE(1)+(2<i>b</i>₂−1)<i>Q</i>_STAGE(2). . . +(2<i>b</i>_N−1)<i>Q</i>_STAGE(N)  Equation 6

p-0058If each stage-charge Q_STAGE(k+1)is smaller than the preceding one, Q_STAGE(k), then this series of charge comparisons and (signed) additions converges towards Q_OUT(N)=0. In particular, if the stage-charges are scaled such that Q_STAGE(k+1)=(½)·Q_STAGE(k), then the sequence of comparator decisions b₁, b₂, . . . b_Nconstitute the bits of an N-bit offset-binary approximation to the ratio Q_IN/2Q_STAGE(1). In this case, the full-scale-range that can be approximated is −2Q_STAGE(1)≦Q_IN&lt;2Q_STAGE(1).

p-0059One property of this algorithm is that, for pipeline input signals that are within the full-scale range of the conversion process, the output differential charge from each stage (k) obeys the condition: <br />|Q_OUT(k)|≦|Q_STAGE(k)|  Equation 7

p-0060Thus each successive stage needs to process less differential charge than the previous stage. For binary stage scaling, each successive stage needs to process at most half the charge of the previous stage. This fact makes possible another advantage of the present invention.

p-0061As was pointed out above, the voltage change at the charge storage node (node <b>2</b> in <figref idrefs="DRAWINGS">FIG. 5</figref>, for example) is ΔV=Q_IN/C, where C is the total capacitance at the node. In a practical charge-domain circuit, the maximum voltage change ΔV at the storage node must be constrained within limits dictated by the semiconductor process used, available clock voltages, etc. For a given charge entering the stage, such limits impose a minimum possible size on total node capacitance in the stage; if we call the maximum allowable voltage swing at the charge storage node ΔV_MAX, then we can express the limit on node capacitance as: <br /><i>C</i>_NODE<i>>Q</i>_IN<i>/ΔV</i>_MAX  Equation 8

p-0062A large C_NODEvalue, however, has a disadvantage: it reduces the voltage presented to the comparator by a given charge signal. Consequently for a given comparator voltage resolution (limited by voltage noise or offset, for example) the minimum resolvable charge is inversely proportional to C_NODE. It would be desirable to reduce C_NODEas much as possible, in order to maximize charge resolution (and thus overall ADC resolution in effective bits). Thus the constraint in Equation 8 is in conflict with the goal of high ADC resolution.

p-0063The present invention provides a means of satisfying Equation 8 while providing high ADC resolution. Equation 7 indicates that the differential charge signal which each stage in a pipeline needs to process is reduced compared to the previous stage. (It is reduced by a factor of two in a binary pipeline.) Thus the minimum allowable node capacitance required to satisfy Equation 8 with respect to the differential signal charge is smaller for each successive pipeline stage. In order to exploit this opportunity, however, not only the differential charge, but the individual charges comprising the differential pair must be reduced at each successive stage.

p-0064The common-mode (CM) charge at each stage is defined as the average of these two charge packets. Even though the signal charge (i.e., the charge-packet difference) is reduced at each stage by the combined actions of comparator and charge addition, the CM charge is not. Using its definition, we can combine Equations 3A, 3B, 4A and 4B and the definition of Q_STAGEto obtain:

p-0065<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mtable><mtr><mtd><mrow><msub><mi>Q</mi><mrow><mi>CM</mi><mo>-</mo><mi>OUT</mi></mrow></msub><mo>=</mo><mi /><mo>⁢</mo><mrow><mrow><mn>1</mn><mo>/</mo><mn>2</mn></mrow><mo>⁢</mo><mrow><mo>(</mo><mrow><msub><mi>Q</mi><mi>OUTA</mi></msub><mo>+</mo><msub><mi>Q</mi><mi>OUTB</mi></msub></mrow><mo>)</mo></mrow></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo>⁢</mo><mrow><mrow><mn>1</mn><mo>/</mo><mn>2</mn></mrow><mo>⁢</mo><mrow><mo>{</mo><mtable><mtr><mtd><mrow><mrow><mo>(</mo><mrow><msub><mi>Q</mi><mi>INA</mi></msub><mo>+</mo><msub><mi>Q</mi><mi>INB</mi></msub></mrow><mo>)</mo></mrow><mo>+</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mrow><mo>[</mo><mrow><mi>b</mi><mo>+</mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>b</mi></mrow><mo>)</mo></mrow></mrow><mo>]</mo></mrow><mo>⁢</mo><msub><mi>C</mi><mn>6</mn></msub><mo>⁢</mo><mi>Δ</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><msub><mi>V</mi><mi>R</mi></msub></mrow><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><msub><mi>Q</mi><mi>CONST</mi></msub></mrow></mrow></mtd></mtr></mtable><mo>}</mo></mrow></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo>⁢</mo><mrow><msub><mi>Q</mi><mrow><mi>CM</mi><mo>-</mo><mi>IN</mi></mrow></msub><mo>+</mo><mrow><mrow><mn>1</mn><mo>/</mo><mn>2</mn></mrow><mo>⁢</mo><msub><mi>C</mi><mn>6</mn></msub><mo>⁢</mo><mi>Δ</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><msub><mi>V</mi><mi>R</mi></msub></mrow><mo>+</mo><msub><mi>Q</mi><mi>CONST</mi></msub></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo>⁢</mo><mrow><msub><mi>Q</mi><mrow><mi>CM</mi><mo>-</mo><mi>IN</mi></mrow></msub><mo>+</mo><mrow><mrow><mn>1</mn><mo>/</mo><mn>2</mn></mrow><mo>⁢</mo><msub><mi>Q</mi><mi>STAGE</mi></msub></mrow><mo>+</mo><msub><mi>Q</mi><mi>CONST</mi></msub></mrow></mrow></mtd></mtr></mtable></mtd><mtd><mrow><mi>Equation</mi><mo>⁢</mo><mstyle><mspace width="1.1em" height="1.1ex" /></mstyle><mo>⁢</mo><mn>9</mn></mrow></mtd></mtr></mtable></math></maths>

p-0066Equation 9 shows that the CM charge changes at each stage by a fixed amount characteristic of that stage. (This amount is independent of the stage's bit decision.) As discussed above, Q_STAGEdepends on C₆and ΔV_R, while Q_CONSTdepends on C₅and several other voltages. Thus it is possible to select values of C₆and V_P, for example, to cause Q_CM-OUTto decrease from stage to stage just as Q_STAGEdoes. The result is that the total capacitance of each stage can be made smaller than the previous one; for binary scaling, it can be approximately one-half the size.

p-0067The pipelined ADC architecture incorporating this charge and capacitance reduction from stage to stage is termed a “tapered pipeline”. It has several important advantages over prior-art BBD-based ADCs: by reducing total capacitance for a series of stages, it reduces operating power; for the same reason it reduces the total “kTC” noise added in the pipeline (thus improving ADC resolution); it increases the charge resolution of comparators in later stages of the pipeline, thus making possible higher overall resolution; and it reduces the total capacitance required for the pipeline, thus reducing circuit area.

p-0068In order to exploit the increased comparator charge resolution available in later pipeline stages in a tapered pipeline, an algorithm must be employed which prevents inexact comparator decisions in early stages from compromising precision of the final A/D conversion. A well-known solution to this requirement is the employment of redundancy, such that later stages are able to correct for inexact early decisions. A widely-used algorithm based on this concept is the RSD (sometimes referred to as the “1.5 bit-per-stage”) algorithm. In this approach, each pipeline stage has two independent comparators with differing thresholds, and two corresponding pairs of conditionally-switched capacitors. The RSD algorithm has been widely implemented in switched-capacitor pipelines, but not previously in charge-domain pipelines. Its use in a BBD charge pipeline is one feature of the present invention.

p-0069<figref idrefs="DRAWINGS">FIG. 11</figref> illustrates one stage of a differential charge-domain pipeline ADC stage which implements the RSD algorithm. It is similar to the circuit of <figref idrefs="DRAWINGS">FIG. 10</figref>, except that the comparator, latch, logic block, and conditionally-switched capacitors are duplicated. Moreover, the two comparators are provided with shifted thresholds, such that each one switches at a specific charge imbalance between the “A” and “B” storage nodes, rather than switching at the point of balance as in <figref idrefs="DRAWINGS">FIG. 10</figref>. The comparators typically, although not necessarily, have thresholds symmetrical about the balance point, as indicated in <figref idrefs="DRAWINGS">FIG. 11</figref>. The two latched comparator decisions are output from the stage as digital signals b and b′.

p-0070Assuming that the stage of <figref idrefs="DRAWINGS">FIG. 11</figref> is placed in a pipeline where its input charge range is the same as that of the binary stage of <figref idrefs="DRAWINGS">FIG. 10</figref>, then each of the conditionally-switched capacitors in <figref idrefs="DRAWINGS">FIG. 11</figref> is half the size of the corresponding capacitors in <figref idrefs="DRAWINGS">FIG. 10</figref>. Thus, if both comparators in <figref idrefs="DRAWINGS">FIG. 11</figref> are driven to the same decision, indicating a large charge difference between the “A” and “B” storage nodes, then both output bits b and b′ have the same value, and both conditionally-switched capacitors on the same branch of the differential charge pair are switched. In this case the stage charge transfer function is given by Equation 5, just as with the circuit of <figref idrefs="DRAWINGS">FIG. 10</figref>. If the input charge is nearly balanced, however, then b and b′ are complementary, and a charge of ½Q_STAGEis added to each outgoing charge packet. In this case the outgoing (differential) signal charge is not changed (Q_OUT=Q_IN).

p-0071One result of these operations is that the stage's output charge still obeys Equation 7. Another is that the extra bit resolved per stage provides the desired redundancy, so that later bit-decisions can be used to correct earlier, less exact ones. Thus the improved charge resolution in later stages, provided by the tapered pipeline, can be used to provide overall improved ADC resolution. The charge scaling from stage to stage in this example is still a factor of 2, just as with the binary pipeline ADC described above.

p-0072<figref idrefs="DRAWINGS">FIGS. 8 and 9</figref> illustrate two examplary applications of the principles of this invention to A/D conversion. Similar methods, based on the same principles, will be apparent to those familiar with the current ADC art. Examples include pipeline ADCs resolving two or more bits per stage, by using multiple comparators and conditionally-switched capacitor pairs.

p-0073The tapered-pipeline principle has been described principally with reference to a differential charge pipeline. In some applications, such as those where the input signal to be converted is a single-ended charge (as in an imager), a single-ended ADC pipeline configuration is preferable. The tapered-pipeline principle can be applied equally well to such applications.

p-0074While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.