Voltage regulator

BACKGROUND

p-0002Embodiments disclosed herein relate generally to voltage regulators and in particular to on-chip voltage regulators. Successive generations of processors are increasing the demands on loads such as phase locked loop (PLL) blocks, which require a regulated supply. Accordingly, improved regulator circuits are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0003Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

p-0004<figref idrefs="DRAWINGS">FIG. 1</figref> is a schematic diagram of a regulator circuit according to some embodiments.

p-0005<figref idrefs="DRAWINGS">FIG. 2</figref> is a more detailed schematic diagram of the regulator circuit of <figref idrefs="DRAWINGS">FIG. 1</figref> according to some embodiments.

p-0006<figref idrefs="DRAWINGS">FIG. 3</figref> is a block diagram of a system having a processor chip with a regulator circuit in accordance with some embodiments of the invention.

DETAILED DESCRIPTION

p-0007Regulator embodiments are disclosed that can provide high power supply rejection ratio (PSRR) over wide frequency bands in a stable configuration. In fact, in some embodiments, output voltages within 200 mV of a supply rail may be attained.

p-0008<figref idrefs="DRAWINGS">FIG. 1</figref> shows a schematic diagram of a regulator <b>100</b> according to some embodiments of the invention. Regulator <b>100</b> is a two gm-stage regulator formed from a first amplifier stage <b>105</b>, a second amplifier stage <b>110</b>, and an output section <b>115</b>. The first stage <b>105</b> is coupled to the second stage at the output (N<b>1</b>) of the first stage <b>105</b>. The output section <b>115</b> is coupled to the second stage's output (V_OUT), which serves as the output of the regulator.

p-0009The output (V_OUT) is an analog supply voltage that may be used for any suitable application such as for supplying a regulated voltage to a phase locked loop (PLL). A reference voltage (V_REF) is coupled to an input of the first sage and determines the value of the regulated voltage that is provided at V_OUT. The reference voltage may be provided, for example, by an on-chip circuit that produces a stable, filtered reference voltage (e.g., 0.8 V). The output section <b>115</b> comprises voltage divider resistors R<b>2</b>/R<b>3</b> for setting the output voltage (V_OUT) based on their values relative to one another and on the value of V_REF. For example, a 1:2 ratio of R<b>2</b> to R<b>3</b> with a 0.8 V referenced would result in an output (V_OUT) of 1.2 V. The output section <b>115</b> also includes a relatively large capacitor C<b>2</b> (e.g., 300 pF) for filtering noise at the output.

p-0010The first stage <b>105</b> includes an amplifier <b>107</b>, which may comprise any suitable amplifier circuit; it comprises a differential amplifier in the depicted figure. The differential amplifier has two voltages at its input, and converts them to two currents at the output. It also includes a resistor R<b>1</b> (e.g., 1K Ohm) and capacitor C<b>1</b> (e.g., 2 pF) coupled in series between node N<b>1</b> and ground for compensation purposes. A first primary pole, resulting from amplifier <b>107</b>, is associated with N<b>1</b>, while a second primary pole results from the output section and a coupled load (not shown). Thus, resistor R<b>1</b> and capacitor C<b>1</b> may be used to insert a zero into the regulator system to separate these first and second poles. This allows the bandwidth of the first stage to be raised while maintaining system stability, which serves to improve the regulator's PSRR.

p-0011The second amplifier stage <b>110</b> comprises transistors M<b>5</b>B, M<b>7</b>A, and M<b>7</b>B coupled together in a common current path. (It should be noted that a “current path” may include, without limitation, elements whose currents are coupled directly together or indirectly together such as with current mirrors, folding elements, and non-conducting coupler devices to mention just a few.) Transistor M<b>5</b>B serves primarily as the gm driver, transistor M<b>7</b>B serves as an output transistor, and transistor M<b>7</b>A serves to mirror current from M<b>5</b>B to the output through output transistor M<b>7</b>B. In the depicted embodiment, M<b>7</b>B is scaled to M<b>7</b>A by a ratio of 4:1, which causes it to drive four times the current mirrored by M<b>7</b>A and thus M<b>5</b>B, as well. This ratio is a function of the design parameters, and in no way is considered a limitation of this invention. It should be noted that a current mirror serves to replicate a current, or a scaled version of the current from one branch of the circuit to another.

p-0012The output transistor, M<b>7</b>B, may be required to drive large currents with a relatively small V_DS(e.g., less than 200 mV). for additional reasons (e.g., low parasitic capacitances to reduce high frequency supply noise), it is desirable to have a reasonably short channel length in M<b>7</b>B. On the other hand, PSRR is improved with a higher channel length because R_OUTfor the second stage (which is proportional to PSRR) increases with channel length. Thus, a channel length tradeoff is made in consideration of these two conflicting parameters. (In some embodiments, the sizing of M<b>7</b>B is 4000 um/0.2 um.) Unfortunately, even with a favorable tradeoff, PSRR resulting from the second stage (M<b>7</b>B in particular) may be insufficient. Accordingly, in some embodiments (as discussed below), the first stage amplifier <b>105</b> may be configured to enhance regulator PSRR (e.g., with increased bandwidth) while maintaining required system performance and stability.

p-0013<figref idrefs="DRAWINGS">FIG. 2</figref> shows a more detailed schematic of the first amplifier stage <b>105</b> within regulator <b>100</b> according to some embodiments. In this figure, the second amplifier stage <b>110</b> is essentially the same except that it has an added cascode transistor M<b>6</b> coupled between M<b>5</b>B and M<b>7</b>A and thus, it will not be further discussed.

p-0014In order to provide good PSRR without degrading stability performance, amplifier <b>105</b> is designed to have a relatively low gain (e.g., 20 to 30 dB) with a relatively high bandwidth. As will be discussed in greater detail herein, one of the ways this is accomplished is by providing it with a low ROUT at node N<b>1</b>, which decreases its DC gain.

p-0015The first stage <b>105</b> generally comprises a differential amplifier section <b>201</b>, a mirror driver section <b>211</b>, a low-R_OUT, pull-down output section <b>213</b>, and a pull-up output section <b>215</b>. The differential amplifier section <b>201</b> has first and second inputs: reference voltage (VREF) and a feedback voltage (FB) fed back from the regulator output section <b>115</b>. It is coupled to the pull-up section <b>215</b> and mirror driver section <b>211</b>, which in turn is coupled to the low R_OUT, pull-down output section <b>213</b> to drive it based on the differential amplifier <b>201</b>. In operation, the differential amplifier <b>201</b> causes the pull-up output section <b>215</b> to pull up the voltage at N<b>1</b> when the feedback voltage (FB) is less than the reference voltage (V_REF). Conversely, it causes the mirror driver section <b>211</b> to drive the low R_OUT, pull-down section <b>213</b> to pull down the output voltage at N<b>1</b> when the voltage at FB is greater than V_REF. In this way, it controls the voltage at N<b>1</b> to appropriately drive the second stage amplifier <b>110</b> through M<b>5</b>B in order to cause the regulator output (V_OUT) to suitably track V_REF.

p-0016In the depicted embodiment, the first stage <b>105</b> has several features that allow it to enhance regulator PSRR. To begin with, it has a relatively low output resistance (R_OUT), by way of the pull-down output section <b>213</b>, which lowers the first stage's DC gain and thus allows it to have an increased bandwidth while not violating regulator stability requirements. In addition, the differential amplifier section <b>201</b> has a dynamic current source for increasing its strength when the current load at V_OUTis higher and decreasing it when the current load is lower. This takes advantage of the fact that the second primary pole (at V_OUT) goes to higher frequency as the current load increases and goes to lower frequency as the current load decreases. Thus, more amplification at the first amplifier stage <b>105</b> can be tolerated while maintaining system stability as the output load current increases. Finally, the differential input section <b>201</b> also may include a gm reducing section <b>204</b>, which allows the differential amplifier to drive sufficient current at a reduced DC gain thereby allowing it to have an even higher bandwidth. (As used herein, the term “gm reducing section” refers to any circuit to lower the gm in an amplifier without significantly reducing its current capability.) It should be noted that not all of these features are necessarily present in all embodiments of the invention. Different embodiments may have different combinations, depending on a given design and design requirements.

p-0017In the depicted embodiment, the differential amplifier section <b>201</b> comprises transistors M<b>1</b>A and M<b>1</b>B, each of which provides current to a branch of the differential amplifier, a gm reducing section <b>204</b> (formed from transistors M<b>1</b>C and M<b>1</b>D), reference tail-current source <b>204</b>, and feedback tail-current source <b>206</b> coupled to one another as indicated. (A tail current source is any transistor or circuit which supplies current to a differential stage). Transistors M<b>1</b>A and M<b>1</b>B, in cooperation with the reference tail-current source <b>204</b>, which is biased at a fixed level (e.g., 30 micro amps), operate as a conventional differential amplifier. Transistor M<b>5</b>A, which is scaled to M<b>5</b>B, functions as a dynamic tail-current source for the differential amplifier to dynamically provide it with source current in proportion to the current demand at V_OUT. Its current mirrors the current in M<b>5</b>B, which is in a common current path with the output driving transistor M<b>7</b>B. Thus, since the current in M<b>5</b>A is effectively mirrored by M<b>5</b>B, its current corresponds to the regulator output current, which is in the same output current path as M<b>5</b>B. In some embodiments, the feedback tail-current source M<b>5</b>A provides current ranging between 0 and 500 micro amps to the differential amplifier <b>201</b>.

p-0018The gm reducing circuit <b>202</b> comprises transistors MIC and MID cross-coupled to transistors MIA and MIB to lower the effective differential amplifier gm without choking M<b>5</b>A. Relatively large current is desired for the current sources (especially the dynamic source <b>206</b>) because it implies a low output resistance and thus low DC gain, allowing higher bandwidth for the differential amplifier section <b>201</b>. Thus, sufficient drain/source voltage is needed for M<b>5</b>A to operate in saturation. However, not a lot of voltage may necessarily be available. (Note that V_REF, may, for example, be at 0.8V.) Therefore, it is desirable for M<b>1</b>A and M<b>1</b>B to be designed to have reasonably small V_DSATvalues. However, without relatively large gm values, M<b>1</b>A and M<b>1</b>B could not provide large current with low V_DSATvalues. But a large gm is not desired because it results in a higher DC gain and thus less bandwidth capability. Accordingly, the gm reducing circuit (M<b>1</b>C and M<b>1</b>D), with its cross-coupled configuration, operates to divert current from one branch to the other to provide (or sink) sufficient overall current at the current sources without requiring a large differential amplifier gm. (In some embodiments, transistors M<b>1</b>A and M<b>1</b>B are three times larger than M<b>1</b>C and M<b>1</b>D.)

p-0019The low R_OUTpull-down output section <b>213</b> is configured to provide an appropriate voltage range at the gate of M<b>5</b>B (node N<b>1</b>) based on current driven through it by the mirror driver section <b>211</b>. It comprises scaled transistors M<b>3</b>A/M<b>3</b>B, each being diode connected, and scaled transistors M<b>4</b>A/M<b>4</b>B, coupled as shown between M<b>3</b>A/M<b>3</b>B and ground. M<b>3</b>A, M<b>3</b>B, M<b>4</b>A, and M<b>4</b>B are sized such that at the voltages needed to drive M<b>5</b>B, M<b>4</b>B will substantially be in a linear region. This occurs with M<b>3</b>A and M<b>3</b>B being in saturation (which results since they are diode connected) controllably forcing M<b>4</b>A and M<b>4</b>B to operate in linear regions. M<b>3</b>B and M<b>3</b>A are considered diode connected, since their gates are connected to their drains.

p-0020The linear region of transistor operation is a mode of operation where the transistor has a low Rout, or output resistance/impedance, as is well known by those skilled in the art. This is distinguished from the saturation mode, where the transistor generally has a high R_OUT. (An exception to this, as is well known in the art, is when a transistor is diode connected resulting in it having a relatively low R_OUT.) The linear region is defined by Vds&lt;V_GS−V_T, where V_GSis the gate-source voltage, V_DSis the drain-source voltage and V_Tis the threshold voltage. Transistor M<b>4</b>B is forced in the linear region, since the feedback loop will bias N<b>1</b> at a voltage slightly above V_T, so that M<b>5</b>B will have enough voltage at it's gate to drive the required current to the output. The V_GSof M<b>3</b>B is at least V_T, since it is diode connected. This leaves a small V_DSfor M<b>4</b>B. Thus M<b>4</b>B, M<b>3</b>B and M<b>5</b>B in this configuration can be sized to guarantee-by-design that M<b>4</b>B is in the linear region.

p-0021With M<b>4</b>B operating in a linear region, it is able to provide a suitable voltage range at N<b>1</b>, while having a relatively low resistance. with M<b>3</b>B being diode connected (and thus having a low resistance as well), the series combination of M<b>3</b>B and M<b>4</b>B also has a relatively low resistance. This results in a low DC output resistance (R_OUT) for the first amplifier stage <b>105</b>. This low Rout results in a low first amplifier stage DC gain thereby allowing for a higher bandwidth driving N<b>1</b>, which enhances regulator PSRR. (With such a low DC gain, the imbalance in the voltages at N<b>1</b> and N<b>2</b> will typically cause a systematic offset at the output. Fortunately, this can be corrected by the feedback tail current source <b>206</b> (M<b>5</b>A). At high output currents, the current in the entire circuit is raised, and the voltage at N<b>2</b> increases to match the increase of N<b>1</b>. Under these conditions, the second primary (output) pole is at a higher frequency, so it is possible to increase the gain and bandwidth of the first stage without adversely affecting stability. This dynamic biasing also helps to keep M<b>4</b>B in the linear region for higher N<b>1</b> voltages.)

p-0022(It should be appreciated that while the low R_OUToutput section is disposed in the pull-down portion of the first-stage, it alternatively could be placed in any suitable part of the first amplifier stage. For example, it could instead be placed in the pull-up section, which also would provide a low output resistance for the first amplifier stage <b>105</b>.)

p-0023The mirror driver section <b>211</b> generally comprises scaled, current mirror connected transistors M<b>2</b>A/M<b>2</b>D and a conventional cascode transistor M<b>8</b>A. As indicated, the mirror driver section is in a common current path with the V_REFbranch of differential amplifier <b>201</b> and the low R_OUTpull-down output section <b>213</b> to drive the pull-down section in response to voltage changes between V_REFand FB at the differential amplifier section <b>201</b>.

p-0024Likewise, the pull-up output section <b>215</b> generally comprises scaled, mirror connected transistors M<b>2</b>B/M<b>2</b>C and a conventional cascode transistor M<b>8</b>B. The pull-up output section <b>215</b> is in a common current path with the FB branch of the differential amplifier <b>201</b>, which supplies it with current in response to the voltage difference between V_REFand FB. It turns on with greater current, relative to M<b>4</b>B, to pull up the voltage at N<b>1</b> when the voltage at FB is less than V_REF. Conversely, it turns on with less current, relative to M<b>4</b>B, resulting in the voltage at N<b>1</b> decreasing when the voltage at FB is greater than V_REF.

p-0025With reference to <figref idrefs="DRAWINGS">FIG. 3</figref>, one example of a computer system is shown. The depicted system generally comprises a processor <b>302</b> that is coupled to a power supply <b>304</b>, a wireless interface <b>306</b>, and memory <b>308</b>. It is coupled to the power supply <b>304</b> to receive from it power when in operation. It is coupled to the wireless interface <b>306</b> and to the memory <b>308</b> with separate point-to-point links to communicate with the respective components. It comprises one or more voltage regulators <b>303</b> according to some embodiments of the invention. For example, in some embodiments, it is coupled to a phase locked loop circuit to provide it with a suitable regulated voltage supply.

p-0026It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.

p-0027The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.

p-0028Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Along these lines, while ground references are primarily shown. Any suitable supply reference (e.g., negative or positive voltages could alternatively be used if appropriate.) Furthermore, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.