Image display apparatus and driving method thereof

BACKGROUND OF THE INVENTION

p-0002The present invention relates to a liquid crystal image display apparatus; and, more particularly, the invention relates to a liquid crystal image display apparatus which can display an image with low power consumption.

p-0003A conventional image display apparatus will be described with reference to <figref idrefs="DRAWINGS">FIG. 19</figref>, which is a diagram showing the construction of a TFT liquid crystal panel using conventional technology. Pixels <b>100</b> each having a liquid crystal capacitor <b>101</b> and a pixel switch <b>102</b> are arranged in the form of a matrix, and a gate of the pixel switch <b>102</b> is connected to a gate line shift register <b>104</b> through a gate line <b>103</b>. Further, a drain of the pixel switch <b>102</b> is connected to a DA converter <b>106</b> through a signal line <b>105</b>. On the other hand, each of memory cells of a frame memory arranged in the form of a matrix is composed of a memory capacitor <b>111</b> and a memory switch <b>112</b>, and a gate of the memory switch is connected to a word line shift register <b>114</b> through a word line <b>113</b> and a word line selection switch <b>115</b> arranged at the end of the word line. On the other hand, one end of each of the memory switches is connected to a data line <b>116</b>. A data input circuit <b>117</b> is arranged at one end of the data line <b>116</b>, and a sense amplifier <b>108</b> and a latch circuit <b>107</b> are arranged at the other end of the data line <b>116</b>. An output of the latch circuit <b>107</b> is connected to the DA converter <b>106</b>. The above-described constituent elements are formed using poly-Si TFT on a single substrate.

p-0004The operation of the TFT liquid crystal panel will be described. At the time of writing, image data from the data input circuit <b>117</b> is written in the memory cells on a row selected by the word line shift register <b>114</b> and the word line selection switch <b>115</b>, similar to a general DRAM (dynamic random access memory). Similarly, the image data of the memory cells on the row selected by the word line shift register <b>114</b> and the word line selection switch <b>115</b> is input to the sense amplifier <b>108</b> through the data line <b>116</b> so as to be latched by the latch circuit <b>107</b>. The latched image data is converted to an analogue signal by the DA converter <b>106</b> and is output to the signal line <b>105</b>. At that time, the gate line shift register <b>104</b> is scanned in synchronism with the word line shift register <b>114</b>, and the gate line shift register <b>104</b> sets the pixel switch <b>102</b> on a given row to the ON-state through the gate line <b>103</b>. Thereby, the analogue signal is written in the liquid crystal capacitor <b>101</b> of the given pixel <b>100</b>, and, accordingly, the image can be displayed using the liquid crystal based on the read-out image data.

p-0005The above-described apparatus is described in detail, for example, in Japanese Patent Application Laid-open No. 11-85065 (1999).

p-0006According to the conventional technology described above, by driving the word line <b>113</b> of the frame memory and the gate line <b>103</b> of the pixel portion with an equal driving frequency, it is possible to avoid interference noise caused by leaking of a word line clock signal of the frame memory into the displayed image. However, low power consumption of the image display apparatus is not sufficiently taken into consideration. This problem will be described below.

p-0007From the viewpoint of improving the yield by reducing the area and the number of pixels, the frame memory is not formed by a SRAM (static random access memory), but is typically formed by a DRAM, as described above. However, when a general DRAM cell structure, which is typically composed of one transistor and one capacitor, is used, a circuit having a large penetration current can not help being employed as the sense amplifier <b>108</b>, because it is necessary to amplify a very small signal below several tens mV. This is a big problem from the viewpoint of low power consumption of the device.

p-0008Further, from the viewpoint of driving the DRAM cell, in contrast to the conventional example in which writing, refreshing and reading are separately considered, power consumption must be further reduced by organically combining writing, refreshing and reading or by modifying the driving method.

SUMMARY OF THE INVENTION

p-0009According to an embodiment in accordance with the present invention, an image display apparatus comprises a plurality of display pixels arranged in the form of a matrix in order to perform image display, the display pixels each having a pixel electrode and a pixel switch connected to the pixel electrode in series; a plurality of memory elements for storing display data; an image signal generating means for outputting a given image signal based on the display data; a group of signal lines for connecting the image signal generating means to the group of pixel switches; and a display image selection means for writing the image signal in a given display pixel through the group of signal lines and the group of pixel switches. Each basic unit of the memory element comprises a memory switch; a memory capacitor connected to the memory switch; an amplifier FET having a gate which is connected to the memory capacitor; and a refreshing operation means for performing a preset refreshing operation on a signal charge stored in the memory capacitor.

p-0010After the introduction of 4 kbit-DRAM products into the market, employment of (one transistor+one capacitor) cells has become general in the field of DRAM design in order to make the dimension of the memory cell as small as possible. On the other hand, the idea of the above-mentioned construction of a memory cell is effective for an image display apparatus which needs to achieve a power saving and be small area compatible.

p-0011According to an embodiment in accordance with the present invention, in an image display apparatus that comprises a plurality of display pixels arranged in the form of a matrix in order to perform image display, the display pixels each having a pixel electrode and a pixel switch connected to the pixel electrode in series; an image signal generating means for outputting a given image signal based on display data, the image signal generating means having a plurality of memory elements for storing the display data; a group of signal lines for connecting the image signal generating means to the group of pixel switches; and a display image selection means for writing the image signal in a given display pixel through the group of signal lines and the group of pixel switches; and, in which each basic unit of the memory element comprises a memory switch; a memory capacitor connected to the memory switch; and a refreshing operation means for performing a preset refreshing operation on a signal charge stored in the memory capacitor; the method of driving the image display apparatus includes reading the display data from the memory element during the refreshing operation to the memory element using the refreshing operation means.

BRIEF DESCRIPTION OF DRAWINGS

p-0012<figref idrefs="DRAWINGS">FIG. 1</figref> is a schematic diagram showing the construction of a first embodiment of a liquid crystal display panel.

p-0013<figref idrefs="DRAWINGS">FIG. 2</figref> is a circuit diagram showing the circuit of a basic unit of a memory cell in the first embodiment.

p-0014<figref idrefs="DRAWINGS">FIG. 3</figref> is a circuit diagram showing the construction of a single unit of a latch circuit in the first embodiment.

p-0015<figref idrefs="DRAWINGS">FIG. 4</figref> is a circuit diagram showing the circuit of a clocked inverter in the first embodiment.

p-0016<figref idrefs="DRAWINGS">FIG. 5</figref> is a circuit diagram showing the construction of a single unit of DA converter in the first embodiment.

p-0017<figref idrefs="DRAWINGS">FIG. 6</figref> is a diagram showing the layout of a pixel in the first embodiment.

p-0018<figref idrefs="DRAWINGS">FIG. 7</figref> is a diagram showing the layout memory cell in the first embodiment.

p-0019<figref idrefs="DRAWINGS">FIG. 8</figref> is a timing chart showing the operation timings in the first embodiment.

p-0020<figref idrefs="DRAWINGS">FIG. 9</figref> is a schematic diagram showing the construction of a second embodiment of a liquid crystal display panel.

p-0021<figref idrefs="DRAWINGS">FIG. 10</figref> is a circuit diagram showing the circuit of a basic unit of a memory cell in a third embodiment.

p-0022<figref idrefs="DRAWINGS">FIG. 11</figref> is a schematic diagram showing the construction of a fourth embodiment of a liquid crystal display panel.

p-0023<figref idrefs="DRAWINGS">FIG. 12</figref> is a schematic diagram showing the construction of a fifth embodiment of a liquid crystal display panel.

p-0024<figref idrefs="DRAWINGS">FIG. 13</figref> is a circuit diagram showing the construction of a single unit of a latch circuit in the fifth embodiment.

p-0025<figref idrefs="DRAWINGS">FIG. 14</figref> is a schematic diagram showing the construction of a sixth embodiment of a liquid crystal display panel.

p-0026<figref idrefs="DRAWINGS">FIG. 15</figref> is a circuit diagram showing the circuit of a basic unit of a memory cell in the sixth embodiment.

p-0027<figref idrefs="DRAWINGS">FIG. 16</figref> is a schematic diagram showing the construction of a seventh embodiment of a liquid crystal display panel.

p-0028<figref idrefs="DRAWINGS">FIG. 17</figref> is a circuit diagram showing the construction of a single unit of a latch circuit in the seventh embodiment.

p-0029<figref idrefs="DRAWINGS">FIG. 18</figref> is a block diagram showing the construction of an eighth embodiment of an image browser.

p-0030<figref idrefs="DRAWINGS">FIG. 19</figref> is a schematic diagram showing the construction of a liquid crystal panel using a conventional technology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

p-0031A first embodiment in accordance with the present invention will be described with reference to <figref idrefs="DRAWINGS">FIG. 1</figref> to <figref idrefs="DRAWINGS">FIG. 8</figref> and Table 1 and table 2.

p-0032Initially, the construction of the present embodiment will be described. <figref idrefs="DRAWINGS">FIG. 1</figref> is a diagram showing the construction of the embodiment of a polycrystalline Si-TFT liquid crystal display panel.

p-0033Pixels <b>10</b> each having a liquid crystal capacitor <b>1</b> and a pixel switch <b>2</b> are arranged in the form of a matrix, and the gate of the pixel switch <b>2</b> is connected to a gate line register <b>4</b> through a gate line <b>3</b>. The drain of the pixel switch <b>2</b> is connected to a DA converter <b>6</b> through a signal line <b>5</b>. On the other hand, each of the memory cells <b>11</b> of a frame memory arranged in the form of a matrix is connected to a word line <b>12</b> and read-out line <b>13</b>, both extending in the x-axis direction, and data lines <b>22</b> and a common drain line <b>21</b>, both extending in the y-axis direction. Therein, a word line buffer <b>14</b> is arranged at one end of the word line <b>12</b>, and a read-out line buffer <b>15</b> is arranged at one end of the read-out line <b>13</b>; and, a memory y-address decoder <b>18</b> and a memory shift register <b>19</b> are selectively connected to both buffers. The word line buffer <b>14</b> and the read-out line buffer <b>15</b> each are selectively accessed by the buffer selection switch <b>16</b>, and the memory y-address decoder <b>18</b> and the memory shift register <b>19</b> are selectively accessed by the address selection switch <b>17</b>. On the other hand, a data line reset circuit <b>23</b> and a data line input switch <b>24</b> are arranged at one end of the data line <b>22</b>; the other end of the data line input switch <b>24</b> is connected to a data line input line <b>25</b>; and the gate of the data line input switch <b>24</b> is connected to a memory x-address decoder <b>26</b>. On the other hand, a latch circuit <b>7</b> is arranged at the other end of the data line <b>22</b>, and the output of the latch circuit <b>7</b> is input to the DA converter <b>6</b> through a data line <b>22</b>B. Therein, the gate line shift register <b>4</b> and the memory shift register <b>19</b> are driven by a clock pulse from a common input terminal <b>20</b>.

p-0034Each of the constituent elements described above is formed on a single glass substrate using poly-Si TFT, and a CMOS switch constructed using a polycrystalline Si TFT is employed for each of the switches. Here, a description of the structures necessary for forming the TFT panel, such as a color filter, a back light structure, etc. will be omitted for the sake of simplifying the description.

p-0035<figref idrefs="DRAWINGS">FIG. 2</figref> is a diagram showing the circuit structure of a basic unit of the memory cell <b>11</b>. A memory switch <b>33</b>, having a gate which is connected to the word line <b>12</b>, is arranged in the data line <b>22</b>, and the other end of the memory switch <b>33</b> is connected to a memory capacitor <b>31</b> and the gate of a memory amplifier <b>32</b>. The source of the memory amplifier <b>32</b> is connected to the other end of the memory capacitor <b>31</b> and at the same time to an output switch <b>34</b>. The output switch <b>34</b> is a diode-connected n-channel poly-Si TFT, and the other end of the output switch <b>34</b> is connected to the data line <b>22</b>. Further, the memory capacitor <b>31</b> is also an n-channel poly-Si TFT, and the channel side is on the source side of the memory amplifier <b>32</b>. The memory cell <b>11</b> is composed of three basic units, as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, but this is because the image data handled here is 3, bits.

p-0036The construction of the latch circuit <b>7</b> will be described with reference to <figref idrefs="DRAWINGS">FIG. 3</figref>, <figref idrefs="DRAWINGS">FIG. 4</figref> and Table 1.

p-0037<figref idrefs="DRAWINGS">FIG. 3</figref> is a diagram showing the construction of a single unit of the latch circuit which is arranged in the end portion of the data line <b>22</b>. The data line <b>22</b> is connected to a CMOS inverter <b>36</b>, and the output of the CMOS inverter <b>36</b> is connected to a clocked inverter <b>37</b> driven by a signal pulse φ<b>1</b> and to a clocked inverter <b>38</b> driven by a signal pulse φ<b>2</b>. Further, the output of the clocked inverter <b>37</b> is fed back to the data line <b>22</b>, and the clocked inverter <b>38</b> outputs to the data line <b>22</b>B.

p-0038<figref idrefs="DRAWINGS">FIG. 4</figref> shows the circuit structure of the clocked inverter driven by the signal pulse φ<b>1</b> as described above. Since the clocked inverter is driven by p-channel poly-Si TFTs <b>42</b>, <b>43</b> and n-channel poly-Si TFTs <b>44</b>, <b>45</b> and a complementary signal pulse, the clocked inverter has three kinds of output states, namely, high and low states of a CMOS inverter and an output disconnection state (or floating state).

p-0039Table 1 shows values of the channel width W and the channel length L of the CMOS inverter <b>36</b> in the single unit of the latch circuit shown in <figref idrefs="DRAWINGS">FIG. 3</figref>. Therein, by making the values of W/L of the p-channel poly-Si TFTs and the n-channel poly-Si TFTs composing the CMOS inverter <b>36</b> extremely unbalanced, the value of the input threshold necessary for inverting the output of the CMOS inverter <b>36</b> can be set to a very small value. More specifically, the CMOS inverter <b>36</b> is driven by 5 V/0 V, but the input threshold is designed so as to be driven by 1 V, not 2.5 V.

p-0040<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="84pt" align="left" /><colspec colname="1" colwidth="133pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="1" rowsep="1">TABLE 1</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>W/L</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="56pt" align="left" /><colspec colname="1" colwidth="28pt" align="center" /><colspec colname="2" colwidth="133pt" align="center" /><tbody valign="top"><row><entry /><entry>pMOS</entry><entry> 4/20</entry></row><row><entry /><entry>nMOS</entry><entry>20/4 </entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

p-0041The construction of the DA converter <b>6</b> will be described below with reference to <figref idrefs="DRAWINGS">FIG. 5</figref>.

p-0042<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram showing the construction of a single unit (a repetitive unit) of the DA converter <b>6</b> which corresponds to 6 lines of the data line <b>22</b>B. In the present embodiment, since 3-bit image data is expressed by one set of 3 lines of the data line <b>22</b>B, the DA converter for two sets of image data is included in the one single unit of the DA converter. Each of the data lines <b>22</b>B is selectively connected to a positive voltage selection circuit <b>47</b> or a negative voltage selection circuit <b>48</b> through an inverse input switch <b>46</b>, and the outputs of the positive voltage selection circuit <b>47</b> and the negative voltage selection circuit <b>48</b> are connected to the signal line <b>5</b> through an inverse output switch <b>52</b>. Therein, analogue gray scale voltages generated in a gray scale voltage generating resistor <b>53</b> are input to the positive voltage selection circuit <b>47</b> and the negative voltage selection circuit <b>48</b> through gray scale power source lines <b>49</b>; and, accordingly, the positive voltage selection circuit <b>47</b> and the negative voltage selection circuit <b>48</b> have the function to output analogue voltage values corresponding to the 3-bit image data. The gray scale voltage generating resistor <b>53</b> is formed particularly using a low-resistance poly-Si thin film doped with boron (B). This is a structure similar to the source and the drain thin films of the p-channel poly-Si TFT used in the present embodiment. If the gate wire or a general metallic wire is used for the gray scale voltage generating resistor <b>53</b>, the electric power consumption and the area of the gray scale voltage generating resistor <b>53</b> are substantially increased because the resistance of the gate wire and the general metallic wire is too small. On the other hand, since phosphorus (P) is apt to segregate in grain boundaries of poly-Si during a thermal process, such as an activation process, the resistance is apt to be changed due to variation of the crystals; and, accordingly, misalignment of color is apt to occur due to deviation of the values of gray scale power source voltage from the design values. However, since boron (B) does not allow such segregation to occur, the resistance values are stable, and, in addition, the sheet resistance value is an appropriate value of several kΩ/□. Therefore, the poly-Si thin film doped with boron (B) is most suitable for the gray scale voltage generating resistor <b>53</b>, because the electric power consumption is small, and the area is not large, and the values of generated gray scale power source voltage are stable. Table 2 shows measured values of dispersion in sheet resistance of a boron (B) doped poly-Si thin film and a phosphorus (P) thin film. Since the dispersion in sheet resistance of the phosphorus (P) thin film is above 4 times as large as that of the boron (B) doped poly-Si thin film, it is preferable to use the boron (B) doped poly-Si thin film for the gray scale voltage generating resistor <b>53</b>.

p-0043<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="98pt" align="left" /><colspec colname="1" colwidth="119pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="1" rowsep="1">TABLE 2</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row><row><entry /><entry>sheet resistance: σ (%)</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="28pt" align="left" /><colspec colname="1" colwidth="70pt" align="left" /><colspec colname="2" colwidth="119pt" align="char" char="." /><tbody valign="top"><row><entry /><entry>B doped poly-Si film</entry><entry>3.7</entry></row><row><entry /><entry>P doped poly-Si film</entry><entry>20.5</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

p-0044The construction of the pixel <b>10</b> will be described with reference to <figref idrefs="DRAWINGS">FIG. 6</figref>, which is a diagram showing the layout of the pixel <b>10</b>, in which only the wires and the TFT portions are illustrated in order to simplify the explanation. Particularly, the low-resistance wire using Al is illustrated by a bold line, and the contact hole is illustrated by a square. The signal line <b>5</b> is connected to the drain of the n-channel poly-Si TFT composing the pixel switch <b>2</b> with a contact hole, and the gate of the pixel switch <b>2</b> is formed together with the gate line <b>3</b> in a one-piece structure. The source of the pixel switch <b>2</b> is connected to an ITO (not shown) through a pixel electrode <b>56</b>. The pixel electrode <b>56</b> is made of Al having a high reflectivity; and, the present polycrystalline Si-TFT liquid crystal display panel can be used as a transmission type panel when the back light is turned on, and it also can be used as a reflection type panel when the back light is not turned on. Particularly, the display of the reflection type is characterized by low electric power consumption; and, needless to say, such low electric power consumption is the main object of the present invention and is a very important consideration.

p-0045The construction of the memory cell <b>11</b> will be described below, while comparing it to the construction of the pixel <b>10</b>.

p-0046<figref idrefs="DRAWINGS">FIG. 7</figref> is a diagram showing the layout of the memory cell <b>11</b>, and it illustrates only one basic unit of the memory cell for the sake of simplification. The low-resistance wire using Al is illustrated by a bold line, and the contact hole is illustrated by a square, similarly to <figref idrefs="DRAWINGS">FIG. 6</figref>. The data line <b>22</b> is connected to one end of a memory switch <b>33</b> in which the gate thereof is formed by the word line <b>12</b>. The other end of the memory switch <b>33</b> is connected to the gate of a memory amplifier <b>32</b> through an Al wire, and at the same time the Al wire forms a memory capacitor <b>31</b>. The source of the memory amplifier <b>32</b> is connected to the data line <b>22</b> through an output switch <b>34</b> of a diode-connected n-channel poly-Si TFT. Further, the drain of the memory amplifier <b>32</b> is connected to the common drain line <b>21</b> through a read-out switch <b>61</b> controlled by a read-out line <b>13</b> at one end of the memory cell <b>11</b>. In order to prevent a large current from transiently flowing in the common drain line <b>21</b>, as to be described later, the common drain line <b>21</b> is not arranged in parallel to the word line <b>12</b>, but arranged in parallel to the data line <b>22</b>.

p-0047The operation of the present embodiment will be described with reference to <figref idrefs="DRAWINGS">FIG. 8</figref>, which is a chart showing operation timings of various portions in the present invention. In <figref idrefs="DRAWINGS">FIG. 8</figref>, the time axis on the left hand side expresses the operations of “writing to the memory”, “reading out from the memory”, “writing to the memory” and “pause”. Further, items not particularly mentioned correspond to a waveform having an amplitude of 5V.

p-0048Initially, the operation of “writing to the memory” will be described. The R/W selection pulse switches the address selection switch <b>17</b> to the memory y-address decoder <b>18</b>, and the memory y-address decoder <b>18</b> is connected to the read-out line buffer <b>15</b> through the buffer selection switch <b>16</b> to turn on the read switch <b>61</b>, on the selected address row. The reset pulse turns on the data line reset circuit <b>23</b> to reset the data line <b>22</b>, to 0 V. Next, the voltage on the common drain line <b>21</b> rises up to apply the high level voltage (for example, 5V) to the drain of the memory amplifier <b>32</b> of the memory cell on the above-mentioned address row. However, if the memory capacitor <b>31</b> has been written at the high level voltage at that time, the memory amplifier <b>32</b> is turned on to propagate the high level voltage to the data line <b>22</b>. Therein, the memory capacitor also serves as a bootstrap capacitor having a function to boost the gate voltage of the memory amplifier <b>32</b>. On the other hand, if the memory capacitor <b>31</b> has been written at the low level voltage (for example, 0 V), the memory amplifier <b>32</b> is kept in the OFF-state, and, accordingly, the high level voltage of the common drain line <b>21</b> is not output to the data line <b>22</b>. Therein, if the voltage of the common drain line <b>21</b> is returned to the low level after that, the voltage written in the data line is held as it is. Next, when the signal latch pulse φ<b>1</b> is input, the latch circuit shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, provided for each of the data lines <b>22</b>, is put into operation to determine the voltage of the data line to the high level voltage or the low level voltage by operation of the clocked inverter <b>37</b>. Therein, the reason why the threshold of the inverter <b>36</b> is lowered is to cover the voltage output from the memory amplifier <b>32</b> to the data line <b>22</b> when the voltage is insufficient. Therein, similarly to the signal latch pulse φ<b>1</b>, the buffer selection switch <b>16</b> is switched to the word line buffer <b>14</b> to set the word line <b>12</b> on the given row to the high voltage level. Thereby, the image data written in the data line <b>22</b> is rewritten in the same memory capacitor <b>31</b>. After that, when a data input pulse is input, the memory x-address decoder <b>26</b> turns on the data line input switch of the selected address, and, as a result, the data on the data line <b>22</b> on the selected row is rewritten to a new written data which is input through the data input line <b>25</b>. By the above-mentioned operation, the data of the memory cell of which the address (x, y) is selected is rewritten to the new data, and the data of the other memory cells having the same y-address is not changed.

p-0049Next, the operation of “reading out from the memory” will be described below. The R/W selection pulse switches the address selection switch <b>17</b> to the memory shift register <b>19</b>, and the memory shift register <b>19</b> is connected to the read-out line buffer <b>15</b> through the buffer selection switch <b>16</b> to turn on the read switch <b>61</b> on the selected address row. Then, the reset pulse turns on the data line reset circuit <b>23</b> to reset the data line <b>22</b> to 0 V, and the common drain line <b>21</b> rises up to output the data of the memory cell to the data line <b>22</b>, and the voltage of the data line is determined to be the high level voltage or the low level voltage by the signal latch pulse φ<b>1</b>, which is the same processes as described in the operation of “writing to the memory” above. Therein, when the buffer selection switch <b>16</b> is switched to the word line buffer <b>14</b> to set the word line <b>12</b> on the given row to the high voltage level, the image data written in the data line <b>22</b> is rewritten in the same memory capacitor <b>31</b>. This corresponds to the refresh operation to the memory cell (i.e., a rewrite operation is performed to refresh), to be described later. When the output latch pulse φ<b>2</b> is output, the image data is output to the data line <b>22</b>B through the clocked inverter <b>38</b>. By the above-mentioned operation, the data of the memory cells on the row selected by the memory shift register <b>19</b> is refreshed, and, at the same time, the data is output to the data line <b>22</b>B.

p-0050In the operation of “reading out from the memory”, the operation of the gate line shift register <b>4</b> sequentially selecting the gate lines <b>3</b> is identical with the operation of the memory shift register <b>19</b>, sequentially selecting the read-out lines <b>13</b> and the word lines <b>12</b>. Therefore, the image data output to the data line <b>22</b>B is written in the liquid crystal capacitor <b>1</b> through the DA converter <b>6</b> and the pixel switch <b>2</b> on the selected row during the horizontal scanning period after that. Further, the selection of a row of the memory cells by the memory shift register <b>19</b> is performed periodically every 1/60 second of 1 field period. Therefore, the operation of “reading out from the memory” of the memory cell can be used as the refresh operation.

p-0051The operation of the DA converter <b>6</b>, the construction of which has been described with reference to <figref idrefs="DRAWINGS">FIG. 5</figref>, will be described below in detail. The inverse input switch <b>46</b> and the inverse output switch <b>52</b> are switched pairing with each other every field period, and the circuit used for the same row of the memory cell or the same row of the pixel is alternatively exchanged between the positive voltage selection circuit <b>47</b> and the negative voltage selection circuit <b>48</b>. This is because it is necessary to switch the positive and negative voltage output to the signal line <b>5</b> in order to perform alternating current drive of the liquid crystal capacitor. However, the area occupied by the DA converter can be made smaller by alternatively using the voltage selection circuits <b>47</b>, <b>48</b>.

p-0052Finally, the operation of “pause” will be described. In a case where it is not a time of reading to the memory cell and written data is not being transmitted, all the clocks are stopped, as shown in <figref idrefs="DRAWINGS">FIG. 8</figref>. At that time, the consumption of electric power around the memory during this period can be made essentially zero, because there is no circuit under operation.

p-0053In the operations described above, during the writing of the high level voltage to the memory capacitor <b>31</b> through the memory switch <b>33</b> or during the applying of the high level voltage to the drain of the memory amplifier <b>32</b> through the read-out switch <b>61</b>, the high level voltage can be written or applied only up to the memory switch <b>33</b> or the position ((gate electrode applied voltage)−(the threshold voltage Vth of the TFT)) of the read-out switch <b>61</b>. Therefore, in the present embodiment, the phenomenon is avoided by setting the driving voltage of the word line <b>12</b> and the read-out line <b>13</b> higher than that for the other circuits. More specifically, the driving voltage of the word line <b>12</b> and the read-out line <b>13</b> is set to 10 V, while the other pulses are 5-Volt driven. Even if such a high driving voltage is used, an increase in the electric power consumption to the total electric power is very small because the capacity of the word lines <b>12</b> and the read-out lines <b>13</b> is not so large.

p-0054In the case where the DRAM structure is employed for the memory cell, as described above, there arises a problem of leakage current from the memory capacitor <b>31</b> to the memory switch <b>33</b> due to light irradiation. Particularly, in the case where the operation of refreshing is in synchronism with the operation of writing to the pixel, as in the present invention, the required capacity of the memory capacitor <b>31</b> sometimes becomes abnormally large. Therefore, it is preferable that a black matrix shielding film is formed on the reverse surface of the glass substrate <b>8</b>, particularly, on the portion of the memory cell array. Otherwise, a similar effect can be obtained by designing the optical system of the reverse surface so that light of the back light may not reach the memory cell array. Light shielding in the upper portion of the memory cell array can be similarly considered.

p-0055In the present embodiment, each of the circuit blocks is constructed on a glass substrate using polycrystalline Si-TFT elements. However, it is obvious that a quartz substrate or a transparent plastic substrate may be used instead of the glass substrate, and that an opaque substrate, such as an Si substrate, etc., may be used by limiting the liquid crystal display method to the reflecting type.

p-0056Further, of course, it is possible that the n-type and the p-type of the TFTs in the various kinds of circuits described above and the voltage relations may be inversely constructed, or that other circuit structures may be employed without deviating from the principle of the present invention.

p-0057Although it has been assumed in the above description that the image display data is of 3 bits and the gray scale voltage lines <b>49</b> are 8 parallel wires supplied with different gray scale voltages, it is obvious that the gray scale voltage lines are 2ⁿparallel wires supplied with different gray scale voltages, when the image display data is n-bit.

p-0058In addition, although in the present embodiment CMOs switches are used for the various kinds of switches and n-type TFT switches are used for the pixel TFTS, the present invention can be applied when any kinds of switch structures, including p-type TFTs, are used. Further, it is needless to say that various kinds of layout configurations can be applied without departing from the scope of the present invention.

Embodiment 2

p-0059A second embodiment in accordance with the present invention will be described below with reference to <figref idrefs="DRAWINGS">FIG. 9</figref>.

p-0060Since the main structure and the main operation of the second embodiment of a polycrystalline Si-TFT liquid crystal display panel shown in <figref idrefs="DRAWINGS">FIG. 9</figref> are similar to those of the first embodiment, the description thereof is omitted here. The main differences between the present embodiment and the first embodiment are that the structure of the memory cell <b>62</b> is different, and the drive wires of the memory shift register <b>19</b> and the gate line shift register <b>4</b> are separated. Description will be made below concerning these points.

p-0061The present embodiment is characterized by the fact that, in the layout of the memory cells, the 3-bit unit cells composing image data are horizontally aligned in a row, and the memory capacitor is provided as a real capacitor, and not a TFT gate capacitor. The present embodiment can substantially shorten the memory width in the y-direction by the memory cell arrangement described above, and it can be operated with strong stability against noise because the memory capacitor can obtain a sufficient capacitance value even if the voltage of writing to the memory cell is a low level voltage. Therein, by using an ITO film in the pixel, it is possible to further provide a memory capacitor using the grounded ITO film in order to further increase the memory capacity. By additionally providing a wire to which a DC voltage is applied, a capacitor independent of the above-mentioned capacitor can be also provided using the wire, though there is a problem in that the structure becomes complicated.

p-0062Since the drive wires of the memory shift register <b>19</b> and the gate line shift register <b>4</b> are separately provided, the writing operation to the pixel array can be performed, for example, at a speed one-half of a speed of the refreshing, while the refreshing operation of the memory cell is being performed in a necessary timing. By doing so, the present embodiment can further reduce the electric power consumption.

Embodiment 3

p-0063A third embodiment in accordance with the present invention will be described below with reference to <figref idrefs="DRAWINGS">FIG. 10</figref>.

p-0064Since the main structure and the main operation of the third embodiment of a polycrystalline Si-TFT liquid crystal display panel are similar to those of the first embodiment, the description thereof is omitted here. The main difference between the present embodiment and the first embodiment is the circuit structure of the basic unit of the memory cell <b>62</b>. Description will be made below concerning this point.

p-0065<figref idrefs="DRAWINGS">FIG. 10</figref> is a diagram showing the circuit structure of the basic unit of the memory cell in the third embodiment, which corresponds to <figref idrefs="DRAWINGS">FIG. 2</figref> in the first embodiment. The difference between the present embodiment and the first embodiment is that the output switch <b>34</b> is changed to a p-n junction diode <b>63</b> formed on the poly-Si thin film from the diode-connected n-channel poly—Si TFT. The p-n junction diode <b>63</b> is formed by providing an impurity zone of approximately 2 μm length between a p-type impurity zone and an n-type impurity zone. Since the present embodiment simplifies the structure of the basic unit of the memory cell by using the p-n junction diode <b>63</b>, both a reduction of the memory area and an improvement in the production yield can be attained.

Embodiment 4

p-0066A fourth embodiment in accordance with the present invention will be described with reference to <figref idrefs="DRAWINGS">FIG. 11</figref>, which is a diagram showing the construction of the fourth embodiment of the polycrystalline Si-TFT liquid crystal display panel.

p-0067Since the main structure and the main operation of the present embodiment are similar to those of the first embodiment, the description thereof is omitted here. The main difference between the present embodiment and the first embodiment is the circuit structure of the memory cell. Description will be made below concerning this point.

p-0068In the present embodiment, the common drain line <b>21</b> and the read-out switch <b>61</b> are eliminated; and, at the same time, the memory amplifier <b>64</b> is directly driven by the read-out line <b>13</b>, the output switch <b>65</b> is formed by a general n-channel poly-Si TFT and the gate is connected to the read-out line <b>13</b>. According to the present embodiment, the structure of the memory cell can be simplified, and both a reduction of the memory area and an improvement in the production yield can be attained. However, in the present embodiment, the read-out current to all the data lines <b>22</b> through the memory amplifier <b>64</b> needs to be supplied from one read-out line <b>13</b> in all cases. Therefore, it is necessary to reduce the resistance of the output of the read-out line buffer <b>15</b> and to reduce the resistance of the read-out line <b>13</b>.

Embodiment 5

p-0069A fifth embodiment in accordance with the present invention will be described with reference to <figref idrefs="DRAWINGS">FIG. 12</figref> and <figref idrefs="DRAWINGS">FIG. 13</figref>.

p-0070<figref idrefs="DRAWINGS">FIG. 12</figref> is a diagram showing the construction of the fifth embodiment of the polycrystalline Si-TFT liquid crystal display panel. Since the main structure and the main operation of the present embodiment are similar to those of the first embodiment, the description thereof is omitted here. The main differences between the present embodiment and the first embodiment are that the reset voltage of the data line reset circuit <b>65</b> is not 0 V, but is a high level voltage, one end of the memory amplifier <b>68</b> is grounded to 0 V through the common drain line <b>66</b>, the output switch <b>69</b> is constructed by a general n-channel poly-Si TFT and the gate is connected to the read-out line <b>13</b>, and the basic structure of the latch circuit <b>67</b> is changed, as will be described later with reference to <figref idrefs="DRAWINGS">FIG. 13</figref>.

p-0071In the present embodiment, since the voltage applied to the memory amplifier <b>68</b> is inverted, the output of the memory amplifier <b>68</b>, is driven as the drain side. As a result, it is possible to solve the problem existing in the first embodiment that the TFT can be operated only up to the position ((gate electrode applied voltage)−(the threshold voltage Vth of the TFT)) at the time of a read-out operation. As a result, the memory cell circuit can be stably operated without setting the drive voltage of the word line <b>12</b> and the read-out line <b>13</b> higher than that of the other circuits. However, in the present embodiment, the output voltage to the data line <b>22</b> is a low level voltage when the write voltage to the memory capacitor <b>31</b> is the high level voltage, and the output voltage to the data line <b>22</b> becomes a high level voltage when the write voltage to the memory capacitor <b>31</b> is a low level voltage. That is, the write voltage level is inverted at every refresh operation if it is left as it is. Therefore, in the present embodiment, the latch circuit <b>67</b> is modified as described below.

p-0072<figref idrefs="DRAWINGS">FIG. 13</figref> is a diagram showing the structure of the single unit of the latch circuit, which corresponds to <figref idrefs="DRAWINGS">FIG. 3</figref> in the first embodiment. The data line <b>22</b> is input to a clocked inverter <b>70</b> driven by inverting the signal pulse φ<b>1</b>, and the output of the clocked inverter <b>70</b> is input to a CMOS inverter <b>71</b>. The output of the CMOS inverter <b>71</b> is connected to clocked inverters <b>72</b>, <b>73</b> driven by the signal pulse φ<b>1</b> and a clocked inverter <b>74</b> driven by a signal pulse φ<b>2</b>. Further, the output of the clocked inverter <b>72</b> is fed back to the input of the CMOS inverter <b>71</b>, the output of the clocked inverter <b>73</b> is fed back to the data line <b>22</b>, and the clocked inverter <b>74</b> is output to the data line <b>22</b>B. In the present embodiment, by employing the construction described above, the voltage level of the data line <b>22</b> is inverted at the time when the latch pulse φ<b>1</b> is input. By employing the latch circuit, the present embodiment can set the drive voltage of the word line <b>12</b> and the read-out line 1.3 to a value equal to the drive voltage for the other circuits, for example, to 5 V, while the write voltage level is prevented from being inverted for every refresh operation.

Embodiment 6

p-0073A sixth embodiment in accordance with the present invention will be described with reference to <figref idrefs="DRAWINGS">FIG. 14</figref> and <figref idrefs="DRAWINGS">FIG. 15</figref>. <figref idrefs="DRAWINGS">FIG. 14</figref> is a diagram showing the construction of the sixth embodiment of the polycrystalline Si-TFT liquid crystal display panel, and <figref idrefs="DRAWINGS">FIG. 15</figref> is a diagram showing the circuit of the basic unit of the memory cell <b>75</b>.

p-0074Since the main structure and the main operation of the present embodiment are similar to those of the first embodiment, the description thereof is omitted here. The main differences between the present embodiment and the first embodiment are that one end of the memory amplifier <b>77</b> is fixed to a DC high level voltage through the common drain line <b>76</b>, and output switch <b>78</b> is constructed as a general poly-Si TFT, the gate is connected to the read-out line <b>13</b>, and further that the gate of the n-channel poly-Si TFT composing the memory capacitor <b>79</b> is connected to the common drain line <b>76</b>.

p-0075The operation of the present embodiment is different from the operation of the first embodiment in that the memory amplifier <b>77</b> is simultaneously put into operation when the output switch <b>78</b> is selected and turned on because the drain side of the memory amplifier <b>77</b> is fixed to the high level voltage. However, the operation of the present embodiment is essentially similar to the operation of the first embodiment.

p-0076The present embodiment has an advantage in that the structure of the memory cell <b>75</b> is simplified compared with that of the first embodiment, because the DC voltage is applied to the one end of the memory amplifier <b>77</b> through the common drain line <b>76</b>. Further, the present embodiment has an advantage in that the capacity of the memory capacitor becomes large so as to stabilize the operation, particularly when writing to the memory cell is at the low level, because the construction of the memory capacitor <b>79</b> is a n-channel poly-Si TFT of which the gate is connected to the common drain line <b>76</b>.

Embodiment 7

p-0077A seventh embodiment in accordance with the present invention will be described with reference to <figref idrefs="DRAWINGS">FIG. 16</figref> and <figref idrefs="DRAWINGS">FIG. 17</figref>.

p-0078<figref idrefs="DRAWINGS">FIG. 16</figref> is a diagram showing the construction of the seventh embodiment of the polycrystalline Si-TFT liquid crystal display panel. Since the main structure and the main operation of the present embodiment are similar to those of the fifth embodiment, the description thereof is omitted here. The main difference between the present embodiment and the fifth embodiment are that the data line <b>22</b>, to which one end of the memory switch <b>80</b> is connected, is different from the data line <b>22</b> to which the memory switch <b>33</b> is connected, and the basic structure of the latch circuit <b>81</b> is changed, as will be described later with reference to <figref idrefs="DRAWINGS">FIG. 17</figref>.

p-0079The difference in operation of the present embodiment from that of the fifth embodiment is that the data line <b>22</b> for inputting the image data to the memory cell <b>79</b> is different from the data line <b>22</b> for outputting the image data from the memory cell <b>79</b>. Therefore, the structure of the latch circuit used is modified as shown in <figref idrefs="DRAWINGS">FIG. 17</figref>.

p-0080<figref idrefs="DRAWINGS">FIG. 17</figref> is a diagram showing the construction of one unit of the latch circuit in the present embodiment, and it corresponds to <figref idrefs="DRAWINGS">FIG. 13</figref> in the fifth embodiment. The data line <b>22</b> is input to a clocked inverter <b>84</b> driven by inversion of the signal pulse φ<b>1</b>, and the output of the clocked inverter <b>84</b> is input to a CMOS inverter <b>86</b>. The output of the CMOS inverter <b>86</b> is connected to clocked inverters <b>83</b>, <b>85</b> driven by the signal pulse φ<b>1</b> and to a clocked inverter <b>82</b> driven by the signal pulse φ<b>2</b>. The output of the clocked inverter <b>85</b> is fed back to the input of the CMOS inverter <b>86</b>, the output of the clocked inverter <b>83</b> is fed back to another corresponding data line <b>22</b>, and the clocked inverter <b>82</b> outputs to the data line <b>22</b>B. In the present embodiment, by employing the structure described above, the voltage level of the data line <b>22</b> is simultaneously inverted when the latch pulse φ<b>1</b> is input, and it is written in the other corresponding data line <b>22</b>. As described above, by employing the latch circuit <b>81</b> described above, the present embodiment can return the image data read out to the other data line <b>22</b> to the original data line <b>22</b>, and, at the same time, it can set the drive voltage of the word line <b>12</b> and the read-out line <b>13</b> to a value equal to the drive voltage for the other circuits, for example, to 5 V, while the write voltage level is prevented from being inverted at every refresh operation.

Embodiment 8

p-0081An eighth embodiment in accordance with the present invention will be described below with reference to <figref idrefs="DRAWINGS">FIG. 18</figref>, which is a diagram showing the construction of an image browser.

p-0082Compressed image data is input from the outside to a wireless interface (I/F) circuit <b>87</b> as wireless data based on the bluetooth standard, and the output of the wireless I/F circuit <b>87</b> is connected to a frame memory <b>89</b> through a central processing unit (CPU) and decoder <b>88</b>. Further, the output of the CPU and decoder <b>88</b> is connected to a row selection circuit <b>93</b> and a data input circuit <b>92</b> through an interface (I/F) circuit <b>91</b> provided on the polycrystalline Si liquid crystal display panel <b>90</b>, and an image display area <b>94</b> is driven by the row selection circuit <b>93</b> and the data input circuit <b>92</b>. Further, an electric power source <b>95</b> and a light source <b>96</b> are arranged in an image viewer <b>97</b>. Therein, the polycrystalline Si liquid crystal display panel <b>90</b> has the same construction and the same operation as that of the first embodiment previously described.

p-0083The operation of the eighth embodiment will be described below. The wireless I/F circuit <b>87</b> acquires compressed image data from the outside, and transmits the data to the CPU and decoder <b>88</b>. The CPU and decoder <b>88</b> respond to the operation of a user to execute driving of the image viewer <b>97</b> or decoding of compressed image data depending on necessity. The decoded image data is temporally accumulated in the frame memory <b>89</b>, and the image data and the timing pulse for displaying the accumulated image are output to the I/F circuit <b>91</b> according to an instruction of the CPU and decoder <b>88</b>. The I/F circuit <b>91</b> displays the image on the image display area by driving the row selection circuit <b>93</b> and the data input circuit <b>92</b> using these signals. Since this operation is the same as that described in the first embodiment, detailed explanation thereof will be omitted here. The light source <b>96</b> is a back light to the liquid crystal display, but the light source <b>96</b> does not need to be lighted when the liquid crystal display is operated in the reflecting mode. A secondary battery is included in the electric power source <b>95</b>, and it supplies electric power for driving the whole apparatus.

p-0084According to the eighth embodiment, a high-quality image can be displayed with low power consumption based on compressed image data.

p-0085According to the present invention, it is possible to reduce consumed electric power of the image display apparatus.