Distributed multiple-channel alignment scheme

TECHNICAL FIELD

p-0002The present invention relates to signal processing, and, in particular, to schemes for synchronizing multiple data channels, e.g., for combination into a single, higher-speed data channel.

BACKGROUND

p-0003In high-speed communication, it is quite common to place the data from one data stream into several slower data streams, for example, for transmission over cables or a backplane to another circuit board. During transmission, the data streams may incur different path delays. As such, a channel-alignment process may be needed to synchronize the different low-speed data streams before they can be recombined into a single high-speed data stream. In the SONET/SDH standard, a frame pulse may be used as an alignment signal, while other packet transmission protocols may rely on other mechanisms, such as a programmable code group, as an alignment signal.

p-0004According to one traditional approach, channel alignment is accomplished by designing a dedicated alignment circuit (e.g., implemented using ASIC-type circuitry) for each group of channels to be synchronized. In one exemplary prior-art architecture that supports up to eight different low-speed channels, there are seven alignment circuits: one 8-channel alignment circuit, two 4-channel alignment circuits, and four 2-channel alignment circuits. The seven alignment circuits can support the following different modes of operation: <ul><li id="ul0001-0001" num="0000"><ul><li id="ul0002-0001" num="0004">Synchronize all eight channels using the 8-channel alignment circuit.</li><li id="ul0002-0002" num="0005">Synchronize four channels using one of the 4-channel alignment circuits, while synchronizing the other four channels using the other 4-channel alignment circuit.</li><li id="ul0002-0003" num="0006">Synchronize four channels using one of the 4-channel alignment circuits, synchronize another two channels using one of the 2-channel alignment circuits, and synchronize the remaining two channels using another of the 2-channel alignment circuits.</li><li id="ul0002-0004" num="0007">Use each of the four 2-channel alignment circuits to synchronize a different pair of channels. &lt;br /&gt; While this scheme provides an acceptable solution when there are only eight channels to be synchronized, the number of alignment circuits needed to support different alignment modes becomes unacceptably large with increasing numbers of channels. For example, for 32 channels, an analogous channel-alignment scheme would require 36 different channel-alignment circuits: one 32-channel circuit, one 28-channel circuit, one 24-channel circuit, one 20-channel circuit, two 16-channel circuits, two 12-channel circuits, four 8-channel circuits, eight 4-channel circuits, and sixteen 2-channel circuits. </li></ul></li></ul>

p-0005Another traditional approach is to use programmable logic (e.g., FPGA-type logic) to implement each different alignment circuit for each different operating mode. While this solution provides the flexibility needed to support any desired channel-synchronization configuration, it does so at the cost of increased die area and processing time associated with FPGA-type programmable logic as opposed to smaller, faster ASIC-type circuitry.

SUMMARY

p-0006In one embodiment, the present invention is a channel-alignment circuit comprising a controller and a plurality of channel-alignment blocks. Each channel-alignment block is adapted to synchronize two or more channels. The controller is adapted to coordinate the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a block diagram of a channel-alignment circuit according to one embodiment of the present invention;

<figref idrefs="DRAWINGS">FIG. 2</figref> presents Table I, which shows the different channel-alignment operating modes for the channel-alignment circuit of <figref idrefs="DRAWINGS">FIG. 1</figref>;

<figref idrefs="DRAWINGS">FIG. 3</figref> shows a flow diagram representing one possible processing scenario for the channel-alignment circuit of <figref idrefs="DRAWINGS">FIG. 1</figref> for the example of synchronization of Group 3 consisting of the eight channels processed by Quads <b>0</b> and <b>4</b>;

<figref idrefs="DRAWINGS">FIG. 4</figref> shows a timing diagram corresponding to the example of <figref idrefs="DRAWINGS">FIG. 3</figref>;

<figref idrefs="DRAWINGS">FIG. 5</figref> shows a more-detailed schematic diagram of the circuitry within the controller and the quads of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_start[3:0] signals;

<figref idrefs="DRAWINGS">FIG. 6</figref> shows a more-detailed schematic diagram of the circuitry within the controller and the quads of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_done[3:0] signals;

<figref idrefs="DRAWINGS">FIG. 7</figref> shows a more-detailed schematic diagram of the circuitry within the controller and the quads of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_clock[3:0] signals; and

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a block diagram corresponding to a configuration in which channel-alignment circuits, each similar to the circuit of <figref idrefs="DRAWINGS">FIG. 1</figref>, of two different chips are configured to support the synchronization of up to 64 different channels.

DETAILED DESCRIPTION

p-0016Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments.

p-0017<figref idrefs="DRAWINGS">FIG. 1</figref> shows a block diagram of a channel-alignment circuit <b>100</b>, according to one embodiment of the present invention. Channel-alignment circuit <b>100</b> has alignment controller <b>102</b> and eight different 4-channel alignment blocks (also referred to herein as “quads”) <b>104</b>(<b>0</b>)-(<b>7</b>), where each quad <b>104</b> is capable of synchronizing a different set of four input channels. For simplicity, alignment block <b>104</b>(<b>0</b>) is also referred to herein as “Quad <b>0</b>,” alignment block <b>104</b>(<b>1</b>) as “Quad <b>1</b>,” and so on.

p-0018While each quad is capable of synchronizing up to four received channels, each quad can also be configured to process fewer than four channels by configuring the quad to ignore one, two, or three of its channels. The remaining channels can be—but do not have to be—part of a multiple-quad alignment group. To increase the flexibility of alignment processing within a quad, a secondary alignment circuit for two channels may also be provided in each quad. In one implementation, if the secondary alignment circuit is used to align two channels, then those two channels cannot be part of a multiple-quad alignment group. The secondary alignment circuit can be used when the quad's primary alignment circuit is programmed to handle fewer than three channels. As such, a quad having a secondary alignment channel can be configured to simultaneously and independently synchronize two different pairs of its input channels: one pair by the quad's primary alignment circuit and the other pair by the quad's secondary alignment circuit.

p-0019While each quad can be configured to operate independently from the other quads, controller <b>102</b> provides the capability to coordinate the synchronization of channels between two or more different quads. In this case, two or more quads can be considered to form a group of quads, where all of the selected channels in all of the quads in the group are synchronized together. In the particular implementation of <figref idrefs="DRAWINGS">FIG. 1</figref>, controller <b>102</b> supports up to four different groups of quads, where each quad can be independently assigned to none or any of the four groups.

p-0020Channel-alignment circuit <b>100</b> supports 22 different operating modes in which up to 32 channels are simultaneously synchronized in a variety of combinations of up to four groups of quads as summarized in Table I of <figref idrefs="DRAWINGS">FIG. 2</figref>. For example, Mode 1 supports a single group: Group 0, in which up to 32 channels in all eight quads are synchronized. Mode 2 also supports a single group: Group 0, in which up to 28 channels in seven of the eight quads are synchronized. Mode 3 supports two groups: Group 0, in which up to 24 channels in six quads are synchronized, and Group 1, in which up to 8 channels in the remaining two quads are synchronized. And so on, until Mode 21, which also supports a single group: Group 0, in which up to 8 channels in two quads are synchronized, and Mode 22, which has no groups of two or more quads.

p-0021Note that, for each mode, each quad in a group can be independently configured to process fewer than four channels by configuring the quad to ignore one, two, or three of its input channels. Thus, although Mode 1, for example, can be used to synchronize all 32 channels together, it can, in theory, also be used to configure numbers of channels fewer than 32 by configuring one or more of the quads to ignore one or more of their input channels.

p-0022Note that, for a given mode of operation, channels within a group are synchronized with one another, but different channel groups are not synchronized with one another, even though the different groups are simultaneously synchronized. For example, in Mode 8, the up to 16 channels in Group 0 are synchronized with one another, and the up to 16 channels in Group 1 are synchronized with one another, but the channels of Group 0 are not (in general) synchronized with the channels of Group 1. Moreover, different channel groups that are to be aligned simultaneously can be, but do not have to be, clocked by completely asynchronous clocks, thereby allowing asynchronous operation between groups.

p-0023Note further that, in many of the operating modes (i.e., Modes 2, 4, 6-7, 9, 11-12, 14-17, and 19-22), one or more of the eight quads are not associated with any groups. During these operating modes, each “non-grouped” quad can be simultaneously operated independently (of the one or more groups and one or more other non-grouped quads) to synchronize (1) up to four of its input channels or (2) two pairs of its input channels. At one extreme, Mode 22 could be implemented with each quad synchronizing two pairs of input channels to provide a total of 16 pairs of synchronized channels. Moreover, although channel-alignment circuit <b>100</b> can, in theory, be implemented with one, two, three, or four single-quad groups (i.e., groups having only one quad each), such operations are not needed since individual quads can always be implemented independently without relying on controller <b>102</b>.

p-0024Note further that two or more operating modes may have the same number of groups, but different numbers of quads in those groups. For example, Mode 5 has two groups: Group 0 with 5 quads and Group 1 with 3 quads, and Mode 6 has two groups: Group 0 with 5 quads and Group 1 with 2 quads. These two modes have the same number of groups (i.e., 2), but different numbers of quads in those groups (i.e., 5 and 3 vs. 5 and 2). Note that these two operating modes are said to have different numbers of quads in their groups even though Group 0 in both modes has the same number of quads (i.e., 5).

p-0025Note further that, with the exception of Modes 18 and 22, each operating mode listed in Table I could in theory be implemented in a number of different ways. For example, in alternative implementations, Mode 1 could be implemented with Group 1 having all 8 quads, or with Group 2 having all 8 quads, or with Group 3 having all 8 quads. For simplicity, all of these variations are assumed to correspond to a single operating mode in this discussion.

p-0026Note further that, in general, operating modes can be implemented with different numbers of quads. For example, while Mode 12 has four quads in a single group, any combination of quads can be assigned to that single group, e.g., Quads <b>0123</b>, <b>1234</b>, <b>0247</b>, etc.

p-0027In certain embodiments, each block in each group can be configured such that any one or more selected channels in the group are disabled, while any remaining channels in the group are enabled, where the controller coordinates the synchronization of all enabled channels in each group. During synchronization processing of a group, a block in the group having an enabled channel can be re-configured to disable that channel without adversely affecting the synchronization of other previously enabled channels in the group. In addition, during synchronization processing of a group, a block in the group having a disabled channel can be re-configured to enable that channel, wherein any currently enabled channels in the group are automatically re-aligned.

p-0028<figref idrefs="DRAWINGS">FIG. 1</figref> also shows a number of different signals transmitted to and from controller <b>102</b> and/or quads <b>104</b>. These various signals are defined as follows: <ul><li id="ul0003-0001" num="0000"><ul><li id="ul0004-0001" num="0032">cascade_en[7:0]: Eight-bit control signal, where each bit corresponds to a different quad and “1” indicates that the corresponding quad is part of a group.</li><li id="ul0004-0002" num="0033">casc_enx: One-bit control signal, where “1” indicates that Quad x is in a group. Note that casc_enx is bit x of cascade_en[7:0].</li><li id="ul0004-0003" num="0034">grp_in_selx[1:0]: Two-bit control signal that indicates which group Quad x is in. For example, group_in_sel5[1:0]=(11) indicates that Quad <b>5</b> is in Group 3.</li><li id="ul0004-0004" num="0035">quad_in_sely[2:0]: Three-bit control signal that indicates which of the eight quad clock signals to select for Group y. For example, quad_in_sel3[2:0]=(101) indicates that the clock signal from Quad <b>5</b> (i.e., quad_clock_—5) is selected to be the clock signal for Group 3.</li><li id="ul0004-0005" num="0036">quad_start_x: One-bit control signal, where “1” indicates that Quad x has received and detected an alignment pulse in at least one of its four input channels.</li><li id="ul0004-0006" num="0037">quad_done_x: One-bit control signal, where “1” indicates that Quad x has received and detected at least one alignment pulse in each of its four input channels.</li><li id="ul0004-0007" num="0038">quad_clock_x: Clock signal recovered by Quad x from one of its four input channels.</li><li id="ul0004-0008" num="0039">grp_start[3:0]: Four-bit control signal, where each bit corresponds to a different group and “1” indicates that an alignment pulse has been received and detected in at least one of the input channels in that group.</li><li id="ul0004-0009" num="0040">grp_done[3:0]: Four-bit control signal, where each bit corresponds to a different group and “1” indicates that at least one alignment pulse has been received and detected in each of the channels in that group.</li><li id="ul0004-0010" num="0041">grp_clock[3:0]: Four group clock signals, each clock signal corresponding to a different group. &lt;br /&gt; For simplicity, <figref idrefs="DRAWINGS">FIG. 1</figref>, like <figref idrefs="DRAWINGS">FIGS. 5-7</figref> below, does not show all of the signals (e.g., the four different input channels, four different output channels, and four different recovered clock signals) associated with each quad. </li></ul></li></ul>

p-0029<figref idrefs="DRAWINGS">FIG. 3</figref> shows a flow diagram representing one possible processing scenario for channel-alignment circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> for the example of synchronization of Group 3 consisting of Quads <b>0</b> and <b>4</b>. <figref idrefs="DRAWINGS">FIG. 4</figref> shows a simulated timing diagram corresponding to the example of <figref idrefs="DRAWINGS">FIG. 3</figref> and generated using a zero-delay simulation where signals propagate with zero time delay. Note that this example deals only with Group 3. Channel-alignment circuit <b>100</b> may be configured to simultaneously synchronize one, two, or three other groups involving a total of up to 24 other channels, but those groups are not relevant to this example. In <figref idrefs="DRAWINGS">FIG. 4</figref>: <ul><li id="ul0005-0001" num="0000"><ul><li id="ul0006-0001" num="0043">grp_clk[3] refers to the clock signal of grp_clock[3:0] corresponding to Group 3;</li><li id="ul0006-0002" num="0044">grp_start(3) refers to the bit of grp_start[3:0] corresponding to Group 3;</li><li id="ul0006-0003" num="0045">grp_done(3) refers to the bit of grp_done[3:0] corresponding to Group 3;</li><li id="ul0006-0004" num="0046">For each quad, align_pulse_in_x shows the location of alignment pulses in input channel x of that quad; and</li><li id="ul0006-0005" num="0047">For each quad, align_pulse_out_x shows the location of alignment pulses in output channel x of that quad.</li></ul></li></ul>

p-0030Referring again to <figref idrefs="DRAWINGS">FIG. 3</figref>, at the start of synchronization processing (e.g., prior to the timing diagram of <figref idrefs="DRAWINGS">FIG. 4</figref>), the relevant control signals have the following values: <ul><li id="ul0007-0001" num="0000"><ul><li id="ul0008-0001" num="0049">cascade_en[7:0]=(xxx1xxx1) indicating that Quad <b>0</b> and Quad <b>4</b> are each in a group, where (“x”<img id="CUSTOM-CHARACTER-00001" he="3.13mm" wi="3.56mm" file="US07532646-20090512-P00001.TIF" alt="custom character" img-content="character" img-format="tif" />“don't care” for this particular example of Group 3).</li><li id="ul0008-0002" num="0050">grp_in_sel0[1:0]=(11) indicating that Quad <b>0</b> is in Group 3;</li><li id="ul0008-0003" num="0051">grp_in_sel4[1:0]=(11) indicating that Quad <b>4</b> is in Group 3;</li><li id="ul0008-0004" num="0052">quad_start_<b>0</b>=“0” indicating that Quad <b>0</b> has not received and detected an alignment pulse yet;</li><li id="ul0008-0005" num="0053">quad_start_<b>4</b>=“0” indicating that Quad <b>4</b> has not received and detected an alignment pulse yet;</li><li id="ul0008-0006" num="0054">quad_done_<b>0</b>=“0” indicating that Quad <b>0</b> has not received and detected alignment pulses in all four input channels yet;</li><li id="ul0008-0007" num="0055">quad_done_<b>4</b>=“0” indicating that Quad <b>4</b> has not received and detected alignment pulses in all four input channels yet;</li><li id="ul0008-0008" num="0056">quad_clock_<b>0</b>=“x” indicating that Quad <b>0</b> has not yet selected a clock signal from one of its four input channels;</li><li id="ul0008-0009" num="0057">quad_clock_<b>4</b>=“x” indicating that Quad <b>4</b> has not yet selected a clock signal from one of its four input channels;</li><li id="ul0008-0010" num="0058">grp_start[3:0]=(0xxx) indicating that Group 3 has not received and detected an alignment pulse yet;</li><li id="ul0008-0011" num="0059">grp_done[3:0]=(0xxx) indicating that Group 3 has not received and detected alignment pulses in all of its input channels yet;</li><li id="ul0008-0012" num="0060">grp_clock[3:0]=(xxxx) indicating that the controller has not yet selected a clock signal for Group 3; and</li><li id="ul0008-0013" num="0061">quad_in_sel3[2:0]=(xxx) indicating that the controller has not yet selected a clock signal for Group 3.</li></ul></li></ul>

p-0031At step <b>302</b> of <figref idrefs="DRAWINGS">FIG. 3</figref>, Quad <b>0</b> selects one of the clock signals recovered from its four input channels as quad_clock_—0. At step <b>304</b>, Quad <b>4</b> selects one of the clock signals recovered from its four input channels as quad_clock_—4. Note that, depending on the particular implementation, the circuitry for recovering the various clock signals from the different input channels may be implemented either internal or external to the corresponding quads. At step <b>306</b>, controller <b>102</b> selects one of quad_clock_—0 and quad_clock_—4 for use as grp_clk[3] (i.e., the clock for Group 3). This is basically the situation at the start of the timing diagram of <figref idrefs="DRAWINGS">FIG. 4</figref>.

p-0032At step <b>308</b>, Quad <b>0</b> receives its first alignment pulse, in this case, in its input channel 0 (at about 260 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). (Note that the times shown in <figref idrefs="DRAWINGS">FIG. 4</figref> are intended to designate relative—not absolute—timing. As such, the fact that the first alignment pulse appears at 260 ns is not intended to imply that the overall processing of alignment circuit <b>100</b> began only 260 ns prior to the arrival of that first alignment pulse.) Quad <b>0</b> detects this first alignment pulse and sets quad_start_—0 to “1” (at about 272 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). As shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, immediately after this, controller <b>102</b> sets grp_start[3] to “1”.

p-0033At step <b>310</b>, Quad <b>4</b> receives its first alignment pulse, in this case, in its input channel 0 (at about 264 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). Quad <b>4</b> detects this first alignment pulse and sets quad_start_<b>4</b> to “1” (at about 280 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>).

p-0034At step <b>312</b>, after having already received at least one alignment pulse in three of its four input channels, Quad <b>0</b> receives the first alignment pulse in the last of its four input channels, in this case, in its input channel 3 (at about 292 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). Quad <b>0</b> detects this last alignment pulse and sets quad_done_—0 to “1” (at about 304 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>).

p-0035At step <b>314</b>, after having already received at least one alignment pulse in three of its four input channels, Quad <b>4</b> receives the first alignment pulse in the last of its four input channels, in this case, in its input channel 2 (at about 300 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). Quad <b>4</b> detects this last alignment pulse and sets quad_done_<b>4</b> to “1” (at about 312 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>). As shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, immediately after this, controller <b>102</b> sets grp_done[3] to “1”.

p-0036At step <b>316</b>, Quads <b>0</b> and <b>4</b> synchronize their eight channels to the selected group clock, as indicated by the alignment of the eight pulses in the eight different mca_rxd_—0_x signals at about 352 ns in <figref idrefs="DRAWINGS">FIG. 4</figref>.

p-0037<figref idrefs="DRAWINGS">FIG. 5</figref> shows a more-detailed schematic diagram of the circuitry within controller <b>102</b> and quads <b>104</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_start[3:0] signals. In particular, <figref idrefs="DRAWINGS">FIG. 5</figref> explicitly shows the circuitry associated with Quad <b>0</b> and Quad <b>1</b>. Although not explicitly depicted, similar circuitry exists for the other six quads.

p-0038In addition to signals defined earlier, <figref idrefs="DRAWINGS">FIG. 5</figref> also indicates the following signals: <ul><li id="ul0009-0001" num="0000"><ul><li id="ul0010-0001" num="0070">quadx_in_groupy: One-bit control signal, where “1” indicates that Quad x is in Group y. Note that, for a given quad, at most one of the four quadx_in_groupy signals can be a “1” at any given time (although all four can be “0”). For example, if quad<b>0</b>_in_group0 is “1”, then quad<b>0</b>_in_group1, quad<b>0</b>_in_group2, and quad<b>0</b>_in_group3 must all be “0”.</li><li id="ul0010-0002" num="0071">multi_quad_start: One-bit control signal, internal to each quad, where, if Quad x is part of a group (as indicated by case_enx=“1”), then multi_quad_start=“1” indicates that an alignment pulse has been received and detected in at least one of the input channels in that group. If Quad x is not part of a group (as indicated by case_enx=“0”), then Quad x ignores the value of multi_quad_start.</li></ul></li></ul>

p-0039To support the generation of the grp_start[3:0] signals, controller <b>102</b> has four 8-input OR gates <b>502</b>(<b>0</b>)-(<b>3</b>) (one for each of the four different possible groups) and thirty-two 2-input AND gates <b>504</b> (four for each quad, eight for each group, and only eight of which are explicitly depicted in <figref idrefs="DRAWINGS">FIG. 5</figref>), and each quad <b>104</b> has a (4×1) multiplexer (mux) <b>506</b>.

p-0040As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, for Quad x, each AND gate <b>504</b> receives quad_start_x from Quad x and the corresponding quadx_in_groupy. Since, for Quad x, at most one value of quadx_in_groupy can be “1”, when quad_start_x=“1”, at most one of the four AND gates associated with Quad x will pass the value of quad_start_x to the corresponding OR gate <b>502</b>. If any of the eight inputs of an OR gate <b>502</b> is “1”, then the output of that OR gate will also be “1”. Each OR gate <b>502</b> generates a different corresponding bit of grp_start[3:0]. Thus, a bit of grp_start[3:0] is asserted when any of the quad_start signals is asserted for the quads in the corresponding group. Within each quad, the four bits of grp_start[3:0] are applied to the four inputs of mux <b>506</b>, which generates multi_quad_start based on the value of grp_in_selx[1:0].

p-0041<figref idrefs="DRAWINGS">FIG. 6</figref> shows a more-detailed schematic diagram of the circuitry within controller <b>102</b> and quads <b>104</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_done[3:0] signals. In particular, <figref idrefs="DRAWINGS">FIG. 6</figref> explicitly shows the circuitry associated with Quad <b>0</b> and Quad <b>1</b>. Although not explicitly depicted, similar circuitry exists for the other six quads.

p-0042In addition to signals defined earlier, <figref idrefs="DRAWINGS">FIG. 6</figref> also indicates the following signals: <ul><li id="ul0011-0001" num="0000"><ul><li id="ul0012-0001" num="0076">quadx_not_in_groupy: One-bit control signal, where “1” indicates that Quad x is not in Group y. Note that, for a given quad, at most one of the four quadx_not_in_groupy signals can be a “0” at any given time (although all four can be “1”). For example, if quad<b>0</b>_not_in_group0 is “0”, then quad<b>0</b>_not_in_group1, quad<b>0</b>_not_in_group2, and quad<b>0</b>_not_in_group3 must all be “1”.</li><li id="ul0012-0002" num="0077">multi_quad_done: One-bit control signal, internal to each quad, where, if Quad x is part of a group (as indicated by case_enx=“1”), then multi_quad_done=“1” indicates that at least one alignment pulse has been received and detected in all of the input channels in that group. If Quad x is not part of a group (as indicated by case_enx=“0”), then Quad x ignores the value of multi_quad_done.</li></ul></li></ul>

p-0043To support the generation of the grp_done[3:0] signals, controller <b>102</b> has four 8-input AND gates <b>602</b>(<b>0</b>)-(<b>3</b>) (one for each of the four different possible groups) and thirty-two 2-input OR gates <b>604</b> (four for each quad, eight for each group, and only eight of which are explicitly depicted in <figref idrefs="DRAWINGS">FIG. 6</figref>), and each quad <b>104</b> has a (4×1) mux <b>606</b>.

p-0044As shown in <figref idrefs="DRAWINGS">FIG. 6</figref>, for Quad x, each OR gate <b>604</b> receives quad_done_x from Quad x and the corresponding quadx_not_in_groupy. Since, for Quad x, at most one value of quadx_not_in_groupy can be “0”, when quad_done_x=“1”, at most one of the four OR gates associated with Quad x will pass the value of quad_done_x to the corresponding AND gate <b>602</b>. If all of the eight inputs of an AND gate <b>602</b> is “1”, then the output of that AND gate will also be “1”. Each AND gate <b>602</b> generates a different corresponding bit of grp_done[3:0]. Thus, a bit of grp_done[3:0] is asserted when all of the quad_done signals are asserted for the quads in the corresponding group. Within each quad, the four bits of grp_done[3:0] are applied to the four inputs of mux <b>606</b>, which generates multi_quad_done based on the value of grp_in_selx[1:0].

p-0045<figref idrefs="DRAWINGS">FIG. 7</figref> shows a more-detailed schematic diagram of the circuitry within controller <b>102</b> and quads <b>104</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> involved in the generation of the grp_clock[3:0] signals. In particular, <figref idrefs="DRAWINGS">FIG. 7</figref> explicitly shows the circuitry associated with Quad <b>0</b> and Quad <b>1</b>. Although not explicitly depicted, similar circuitry exists for the other six quads.

p-0046In addition to signals defined earlier, <figref idrefs="DRAWINGS">FIG. 7</figref> also indicates the following signal: <ul><li id="ul0013-0001" num="0000"><ul><li id="ul0014-0001" num="0082">multi_quad_clock: Clock signal, internal to each quad, where, if Quad x is part of a group (as indicated by case_enx=“1”), then Quad x uses multi_quad_clock to align its four input channels. If Quad x is not part of a group (as indicated by case_enx=“0”), then Quad x ignores multi_quad_clock and aligns its four input channels using quad_clock_x.</li></ul></li></ul>

p-0047To support the generation of the grp_clock[3:0] signals, controller <b>102</b> has four 8-input muxes <b>702</b>(<b>0</b>)-(<b>3</b>) (one for each of the four different possible groups), and each quad <b>104</b> has a (4×1) mux <b>704</b>.

p-0048As shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, all eight quad_clock_x signals are applied to the eight inputs of each mux <b>702</b>, which generates a corresponding clock signal of grp_clock[3:0] based on the value of quad_in_selx[2:0]. Within each quad, the four clock signals of grp_clock[3:0] are applied to the four inputs of mux <b>704</b>, which generates multi_quad_clock based on the value of grp_in_selx[1:0].

p-0049As described previously, channel-alignment circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> supports the multitude of synchronization configurations associated with the 22 different operating modes of Table I with only eight 4-channel alignment blocks (i.e., quads <b>104</b>). To support the same range of synchronization configurations, the prior-art ASIC-based scheme would require 36 channel-alignment blocks: one 32-channel block, one 28-channel block, one 24-channel block, one 20-channel block, two 16-channel blocks, two 12-channel blocks, four 8-channel blocks, eight 4-channel blocks, and sixteen 2-channel blocks. Moreover, in the embodiment of <figref idrefs="DRAWINGS">FIG. 1</figref>, the same channel-alignment block design can be used for all eight blocks, while, in the equivalent prior-art scheme, nine different channel-alignment block designs are required (one for 32 channels, one of 28 channels, one for 24 channels, one for 20 channels, one for 16 channels, one for 12 channels, one for 8 channels, one for 4 channels, and one for 2 channels).

p-0050Channel-alignment circuits of the present invention, such as circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>, can be (but do not have to be) implemented in a single integrated circuit (IC) chip. Depending on the particular implementation, such a chip may include only ASIC-type circuitry or the chip may include programmable-circuitry, such as FPGA-type circuitry, in addition to ASIC-type circuitry, such as in a field-programmable system chip (FPSC), which includes significant amounts of both ASIC-type and FPGA-type circuitry. In either case, the present invention is preferably (although not necessarily) implemented using ASIC-type circuitry.

p-0051The invention can be extended to include configurations of two or more different IC chips, each having its own channel-alignment circuit analogous to circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>, where the multi-chip configuration supports the synchronization of different channels from different chips in one or more channel groups.

p-0052<figref idrefs="DRAWINGS">FIG. 8</figref> shows a block diagram corresponding to a configuration <b>800</b> in which channel-alignment circuits, each similar to circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>, on two different chips <b>802</b> and <b>804</b> are configured to support the synchronization of up to 64 different channels. In this case, the controller on one of the chips may be configured to act as the master, and the other controller on the other chip as the slave, in order to coordinate channel-alignment processing across chip boundaries. Such an extension of the invention might involve the definition of additional control and clock signals (such as group alignment signals and group alignment clocks) to pass information between the different chips.

p-0053Although the present invention has been described in the context of channel-alignment circuit <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1</figref> which has eight 4-channel alignment blocks and supports up to four different groups of channels, the present invention can also be implemented in other contexts that differ from the circuit of <figref idrefs="DRAWINGS">FIG. 1</figref> in one or more of the following ways: <ul><li id="ul0015-0001" num="0000"><ul><li id="ul0016-0001" num="0090">Channel-alignment circuits having a maximum number of groups other than (i.e., great than or less than) four;</li><li id="ul0016-0002" num="0091">Channel-alignment circuits having a number of channel-alignment blocks other than eight;</li><li id="ul0016-0003" num="0092">Channel-alignment circuits having a number of channels per channel-alignment block other than four; and</li><li id="ul0016-0004" num="0093">Channel-alignment circuits where different channel-alignment blocks have different numbers of channels, as opposed to all channel-alignment blocks having the same number of channels. For example, a channel-alignment circuit could have two 8-channel alignment blocks and four 4-channel alignment blocks.</li></ul></li></ul>

p-0054Although the present invention has been described in the context of FPGAs, ASICs, and FPSCs, those skilled in the art will understand that the present invention can be implemented in the context of other types of devices, such as, without limitation, programmable logic devices (PLDs), mask-programmable gate arrays (MPGAs), simple programmable logic device (SPLDs), and complex programmable logic devices (CPLDs).

p-0055The present invention may be implemented as circuit-based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPSC), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer.

p-0056Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.

p-0057It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.