US7528053B2

Three-dimensional package and method of making the same

Summary by NHIP

Wafer Stacking Package Method

The method creates three-dimensional packages by stacking wafers containing blind holes filled with metal and lined with isolation layers. Distinctive steps include removing metal to form a space, etching the second surface to expose conductive layers, and applying solder with a lower melting point than the metal before reflow.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

US7528053B2, drawing sheet 1 — Sheet 1 of 12

Term

0.9 yearsleft in the term

Expires 6 August 2027, including 223 days of term adjustment.

22 claims: 2 independent, 20 dependent

1
Broadest claimClaim Score 41, average(NHIP)A method of making a three-dimensional package, comprising the following steps:(a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;(b) forming at least one blind hole on the first surface of the wafer;(c) forming an isolation layer on the side wall of the blind hole;(d) forming a conductive layer covering the pad, the protection layer, and the isolation layer;(e) forming a dry film on the conductive layer, wherein the dry film has an opening at the position corresponding to the blind hole;(f) filling the blind hole with a metal;(g) removing the dry film, and patterning the conductive layer;(h) removing a part of the metal in the blind hole, so as to form a space;(i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer;(j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal;(k) stacking a plurality of the wafers, and performing a reflow process;and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional package structures.
12
A method of making a three-dimensional package, comprising the following steps:(a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;(b) forming at least one blind hole on the first surface of the wafer;(c) forming an isolation layer on the side wall of the blind hole;(d) forming a conductive layer covering the pad, the protection layer, and the isolation layer;(e) forming a dry film on the conductive layer, wherein the dry film has an opening at the position corresponding to the blind hole;(f) filling the blind hole with a metal;(g) removing the dry film, and patterning the conductive layer;(h) removing a part of the metal in the blind hole, so as to form a space;(i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer;(j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal;(k) cutting the wafer to form a plurality of units;and (l) stacking a plurality of the units, and performing a reflow process, so as to form a plurality of three-dimensional package structures.

Independent claims2

57 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to a package and a method of making the same, and more particularly to a three-dimensional package and a method of making the same.

00032. Description of the Related Art

0004Referring to <figref idref="DRAWINGS">FIG. 1</figref>, it shows a schematic view of a three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655. The conventional three-dimensional package 1 comprises a first unit 10 and a second unit 20. The first unit 10 comprises a first wafer 11, at least one first hole 12, a first conductive layer 13 and a first solder 14. The first wafer 11 has a first surface 111 and a second surface 112. The first surface 111 has at least one first pad (not shown) and a first protection layer 113 exposing the first pad. The first hole 12 penetrates the first wafer 11. The first conductive layer 13 is disposed on the side wall of the first hole 12 and covers the first pad and the first protection layer 113. The first solder 14 is disposed in the first hole 12 and is electrically connected to the first pad via the first conductive layer 13. The upper end of the first solder 14 extends above the first surface 111 of the first wafer 11, and the lower end extends below the second surface 112 of the first wafer 11.

0005The second unit 20 is stacked on the first unit 10. The second unit 20 comprises a second wafer 21, at least one second hole 22, a second conductive layer 23 and a second solder 24. The second wafer 21 has a first surface 211 and a second surface 212. The first surface 211 has at least one second pad (not shown) and a second protection layer 213 exposing the second pad. The second hole 22 penetrates the second wafer 21. The second conductive layer 23 is disposed on the side wall of the second hole 22 and covers the second pad and the second protection layer 213. The second solder 24 is disposed in the second hole 22 and is electrically connected to the second pad via the second conductive layer 23. The upper end of the second solder 24 extends above the first surface 211 of the second wafer 21, and the lower end of the second solder 24 extends below the second surface 212 of the second wafer 21. The lower end of the second solder 24 is aligned with and contacts the upper end of the first solder 14. After performing a reflow process, the first unit 10 and the second unit 20 are joined to form a conventional three-dimensional package 1, as shown in <figref idref="DRAWINGS">FIG. 2</figref>.

0006In the conventional three-dimensional package 1, the first solder 14 and the second solder 24 are formed by disposing the first wafer 11 and the second wafer 21 above a solder bath, and the solder enters the first hole 12 and the second hole 22 according to the capillary phenomenon so as to form the first solder 14 and the second solder 24.

0007The disadvantages of the conventional three-dimensional package 1 are described as follows. As the first solder 14 and the second solder 24 are formed according to the capillary phenomenon, the upper and the lower ends of the foregoing solders are in a hemispherical shape (<figref idref="DRAWINGS">FIG. 1</figref>). As such, when the first unit 10 and the second unit 20 are aligned and joined, alignment becomes more difficult and the joining between the first unit 10 and the second unit 20 after reflow is not stable. Moreover, after the joining of the first unit 10 and the second unit 20, the overall height cannot be effectively reduced due to the excess hemispherical solders.

0008Therefore, it is necessary to provide a three-dimensional package and a method of making the same to solve the above problems.

SUMMARY OF THE INVENTION

0009The main objective of the invention is to provide a method of making a three-dimensional package, which comprises the following steps:

0010(a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;

0011(b) forming at least one blind hole on the first surface of the wafer;

0012(c) forming an isolation layer on the side wall of the blind hole;

0013(d) forming a conductive layer covering the pad, the protection layer and the isolation layer;

0014(e) forming a dry film on the conductive layer, wherein the dry film has an opening at the position corresponding to the blind hole;

0015(f) filling the blind hole with a metal;

0016(g) removing the dry film and patterning the conductive layer;

0017(h) removing a part of the metal in the blind hole to form a space;

0018(i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer;

0019(j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal;

0020(k) stacking a plurality of the wafers, and performing a reflow process; and

0021(l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.

0022As such, the lower end of the conductive layer is exposed below the second surface of the wafer. Therefore, during the reflow process after stacking, the lower end of the conductive layer and the solder thereon are inserted into the space of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional package after joining.

0023Another objective of the present invention is to provide a three-dimensional package structure, which has a first unit and a second unit. The first unit comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal and a first solder.

0024The first wafer has a first surface and a second surface. The first surface has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The first conductive layer covers the first pad, a part of the first protection layer, and the first isolation layer. The lower end of the first conductive layer extends below the second surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal.

0025The second unit is stacked on the first unit. The second unit comprises a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The second wafer has a first surface and a second surface. The first surface has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole.

0026The second conductive layer covers the second pad, a part of the second protection layer and the second isolation layer. The lower end of the second conductive layer extends below the second surface of the second wafer and contacts the upper end of the first solder. The second metal is disposed in the second hole and is electrically connected to the second pad via the second conductive layer. The second space is disposed on the second metal in the second hole.

BRIEF DESCRIPTION OF THE DRAWINGS

0027<figref idref="DRAWINGS">FIG. 1</figref> shows a schematic view of the three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655;

0028<figref idref="DRAWINGS">FIG. 2</figref> shows a schematic view of the three-dimensional package after reflow disclosed in U.S. Pat. No. 4,499,655;

0029<figref idref="DRAWINGS">FIG. 3</figref> shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention;

0030<figref idref="DRAWINGS">FIGS. 4 to 17</figref> show the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention;

0031<figref idref="DRAWINGS">FIG. 18</figref> shows a schematic flow chart of the method for making a three-dimensional package according to the second embodiment of the present invention;

0032<figref idref="DRAWINGS">FIGS. 19 to 20</figref> show the schematic views of a part of the steps of the method for making a three-dimensional package according to the second embodiment of the present invention; and

0033<figref idref="DRAWINGS">FIG. 21</figref> shows a cross-sectional view of the three-dimensional package according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0034Referring to <figref idref="DRAWINGS">FIG. 3</figref>, it shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention. Referring to <figref idref="DRAWINGS">FIGS. 4 to 17</figref>, the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention are shown. First, referring to <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, as shown in step S301, a wafer 31 is provided. The wafer 31 has a first surface 311 and a second surface 312. The first surface 311 has at least one pad 32 and a protection layer 33 exposing the pad 32.

0035Then, referring to <figref idref="DRAWINGS">FIGS. 3 and 5</figref>, as shown in step S302, at least one blind hole 34 is formed in the first surface 311 of the wafer 31. In the present embodiment, the blind hole 34 is disposed beside the pad 32. However, in other applications, the blind hole 34 can penetrate the pad 32.

0036Next, referring to <figref idref="DRAWINGS">FIGS. 3 and 6</figref>, as shown in step S303, an isolation layer 35 is formed on the side wall of the blind hole 34.

0037Afterward, referring to <figref idref="DRAWINGS">FIGS. 3 and 7</figref>, as shown in step S304, a conductive layer 36 is formed to cover the pad 32, the protection layer 33, and the isolation layer 35. The conductive layer 36 is made of Ti, Cu, Cu/Ti alloy, or other metals.

0038Then, referring to <figref idref="DRAWINGS">FIGS. 3 and 8</figref>, as shown in step S305, a dry film 37 is formed on the conductive layer 36. The dry film 37 has an opening 371 at the position corresponding to the blind hole 34.

0039After that, referring to <figref idref="DRAWINGS">FIGS. 3 and 9</figref>, as shown in step S306, the blind hole 34 is filled with a metal 38 (e.g., copper). In the present embodiment, the blind hole 34 is filled with the metal 38 by plating. However, it should be understood that the blind hole 34 can be filled with the metal 38 by other manners.

0040Then, referring to <figref idref="DRAWINGS">FIGS. 3 and 10</figref>, as shown in step S307, the dry film 37 is removed, and the conductive layer 36 is patterned.

0041Afterward, referring to <figref idref="DRAWINGS">FIGS. 3 and 11</figref>, as shown in step S308, a part of the upper end of the metal 38 in the blind hole 34 is removed, so as to form a space 39. In the embodiment, a part of the upper end of the metal 38 in the blind hole 34 is removed by etching. It should be understood that a part of the upper end of the metal 38 in the blind hole 34 is can be removed by other manners.

0042Then, as shown in step S309, a part of the second surface 312 of the wafer 31 and a part of the isolation layer 35 are removed to expose a part of the conductive layer 36. Referring to <figref idref="DRAWINGS">FIG. 12</figref>, in the present embodiment, the second surface 312 of the wafer 31 is ground by means of backside grinding until the second surface 312 and the lower end of the isolation layer 35 are at the same level, i.e., the lower end of the isolation layer 35 is exposed on the second surface 312. Then, the second surface 312 of the wafer 31 and the lower end of the isolation layer 35 are etched to expose the lower end of the conductive layer 36. At this moment, the lower end of the conductive layer 36 extends below the second surface 312 of the wafer 31, as shown in <figref idref="DRAWINGS">FIG. 13</figref>. However, it should be understood that in other applications, the second surface 312 of the wafer 31 can be directly etched to expose the lower end of the conductive layer 36, without using the backside grinding method.

0043Afterward, referring to <figref idref="DRAWINGS">FIGS. 3 and 14</figref>, preferably, as shown in step S310, a barrier layer 40 is formed on the lower end of the conductive layer 36, and covers the lower end of the exposed conductive layer 36. The barrier layer 40 is Ni, Cr, Cr/Cu alloy, or other metals. It should be understood that this step is optional.

0044Next, referring to <figref idref="DRAWINGS">FIGS. 3 and 15</figref>, as shown in step S311, a solder 41 is formed on the lower end of the conductive layer 36. The material of the solder 41 is different from the metal 38. The material of the solder 41 includes but is not limited to Sn/Pb alloy, and the melting point thereof is lower than that of the metal 38. The solder 41 is attached to the barrier layer 40 or the lower end of the exposed conductive layer 36.

0045Then, referring to <figref idref="DRAWINGS">FIGS. 3 and 16</figref>, as shown in step S312, a plurality of the wafers 31 are stacked. The solder 41 of the upper wafer 31 is aligned to the space 39 of the conductive layer 36 of the lower wafer 31.

0046Finally, referring to <figref idref="DRAWINGS">FIGS. 3 and 17</figref>, as shown in step S313, the reflow process is performed to make the wafers 31 joined by welding the conductive layer 36, the solder 41 and the metal 38. Finally, as shown in step S314, the stacked wafer 31 is cut to form a plurality of three-dimensional package structures 42. Preferably, as shown in step S315, at least one solder ball 43 is formed below the three-dimensional package structure 42. The solder ball 43 is disposed on the lower end of the conductive layer 36 in the lower wafer 31. It should be understood that this step is optional.

0047Referring to <figref idref="DRAWINGS">FIG. 18</figref>, it shows a schematic flow chart of the method for making a three-dimensional package structure according to the second embodiment of the present invention. The steps S401 to S411 are identical to steps S301 to S311 of the first embodiment. The difference between this embodiment and the first embodiment is described as follows. Referring to <figref idref="DRAWINGS">FIGS. 18 and 19</figref>, as shown in step S412, the wafer 31 is cut to form a plurality of units 44, 45. Then, in step S413 the units 44, 45 are stacked, wherein the solder 41 of the upper unit 44 is aligned with the space 39 of the conductive layer 36 of the lower unit 45. Finally, in step S414 the reflow process is performed to form a plurality of three-dimensional package structures 42, as shown in <figref idref="DRAWINGS">FIG. 20</figref>. The three-dimensional package structure 42 (<figref idref="DRAWINGS">FIG. 20</figref>) made according to this embodiment is identical to the three-dimensional package structure 42 (<figref idref="DRAWINGS">FIG. 17</figref>) made according to the first embodiment.

0048Preferably, in the step S415, at least one solder ball 43 is formed below the three-dimensional package structure 42. The solder ball 43 is disposed on the lower end of the conductive layer 36 in the lower wafer 31. It should be understood that this step is optional.

0049Referring to <figref idref="DRAWINGS">FIG. 21</figref>, it shows a cross-sectional view of the three-dimensional package structure according to the present invention. The three-dimensional package structure 5 in this figure is identical to the three-dimensional package structure 42 in <figref idref="DRAWINGS">FIGS. 17 and 20</figref>. However, for the convenience of illustration, the identical elements are identified by different reference numbers. The three-dimensional package structure 5 comprises a first unit 50 and a second unit 60. The first unit 50 comprises a first wafer 51, at least one first hole 52, a first isolation layer 53, a first conductive layer 54, a first metal 55 and a first solder 56.

0050The first wafer 51 is a wafer or a chip, and has a first surface 511 and a second surface 512. The first surface 511 has at least one first pad 513 and a first protection layer 514 exposing the first pad 513. The first hole 52 penetrates the first wafer 51. In the present embodiment, the first hole 52 is disposed beside the first pad 513. Alternatively, the first hole 52 can penetrate the first pad 513.

0051The first isolation layer 53 is disposed on the side wall of the first hole 52. The first conductive layer 54 covers the first pad 513, a part of the first protection layer 514 and the first isolation layer 53. The lower end of the first conductive layer 54 extends below the lower end of the second surface 512 of the first wafer 51. Preferably, the first unit 50 further comprises a first barrier layer (not shown) covering the lower end of the first conductive layer 54.

0052The first metal 55 (e.g., copper) is disposed in the first hole 52 and is electrically connected to the first pad 513 via the first conductive layer 54. The first solder 56 is disposed on the first metal 55 in the first hole 52. The material of the first solder 56 is different from the first metal 55. The material of the first solder 56 includes but is not limited to Sn/Pb alloy, and the melting point thereof is lower than that of the first metal 55.

0053The second unit 60 is stacked above the first unit 50. The second unit 60 comprises a second wafer 61, at least one second hole 62, a second isolation layer 63, a second conductive layer 64, a second metal 65 and a second space 66. The second wafer 61 is a wafer or a chip with a first surface 611 and a second surface 612. The first surface 611 has at least one second pad 613 and a second protection layer 614 exposing the second pad 613. The second hole 62 penetrates the second wafer 61. In the present embodiment, the second hole 62 is disposed beside the second pad 613. However, in other applications, the second hole 62 can penetrate the second pad 613.

0054The second isolation layer 63 is disposed on the side wall of the second hole 62. The second conductive layer 64 covers the second pad 613, a part of the second protection layer 614, and the second isolation layer 63. The lower end of the second conductive layer 64 extends below the second surface 612 of the second wafer 61 and contacts the upper end of the first solder 56. Preferably, the second unit 60 further comprises a second barrier layer (not shown) covering the lower end of the second conductive layer 64.

0055The second metal 65 is disposed in the second hole 62 and is electrically connected to the second pad 613 via the second conductive layer 64. The second space 66 is disposed above the second metal 65. Moreover, if desired, the second space 66 of the second hole 62 is filled with a second solder (not shown). Preferably, the three-dimensional package structure 5 further comprises at least one solder ball 43 disposed on the lower end of the first conductive layer 54.

0056In the three-dimensional package structure 5, the lower end of the second conductive layer 64 is exposed below the second surface 612 of the second unit 60. Therefore, during the reflow process, the lower end of the second conductive layer 64 and the solder thereon are “inserted” into the space on the first metal 55, so as to enhance the joint between the second conductive layer 64 and the first metal 55. Further, the first hole 52 and the second hole 62 can be designed as a taper shape to enhance the joining. Moreover, the lower end of the second conductive layer 64 is inserted into the space on the first metal 55, so the overall height of the three-dimensional package structure 5 after joining can be effectively reduced.

0057While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.

Contents4

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Document	Office	Kind	Date
95102835A	Taiwan Province of China	–	2006-01-25
95102835	Taiwan Province of China	A	2006-01-25

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Document	Office	Kind
US2007172985A1	United States of America	A1	2007-07-26
US2007172986A1	United States of America	A1	2007-07-26
TW200729416A	Taiwan Province of China	A	2007-08-01
TWI287273B	Taiwan Province of China	B	2007-09-21
US7446404B2	United States of America	B2	2008-11-04
US7528053B2This record	United States of America	B2	2009-05-05

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2009-03-23	Issue Fee Payment VerifiedN084	N084
2009-03-23	Issue Fee Payment ReceivedIFEE	IFEE
2008-12-22	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2008-12-18	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2008-12-18	Case Docketed to Examiner in GAUDOCK	DOCK
2008-12-10	Date Forwarded to ExaminerFWDX	FWDX
2008-12-05	Response after Ex Parte Quayle ActionA.QU	A.QU
2008-10-07	Mail Ex Parte Quayle Action (PTOL - 326)MCTEQ	MCTEQ
2008-10-01	Quayle actionCTEQ	CTEQ
2008-09-11	Case Docketed to Examiner in GAUDOCK	DOCK
2008-09-11	Decision Made by Classification DivisionTI1052	TI1052
2008-09-11	Request for Classification Division DecisionTI1054	TI1054
2008-09-03	Transfer Inquiry to GAUTI1050	TI1050
2008-07-28	Electronic Information Disclosure StatementEIDS.	EIDS.
2008-07-28	Information Disclosure Statement consideredIDSC	IDSC
2008-07-28	Electronic Information Disclosure StatementEIDS.	EIDS.
2008-07-28	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2008-06-13	Information Disclosure Statement consideredIDSC	IDSC
2008-06-13	Electronic Information Disclosure StatementEIDS.	EIDS.
2008-06-13	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2008-02-08	Information Disclosure Statement consideredIDSC	IDSC
2008-02-08	Reference capture on IDSRCAP	RCAP
2008-02-08	Information Disclosure Statement (IDS) FiledM844	M844
2008-02-08	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2007-07-26	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2007-02-06	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2007-01-29	Application Dispatched from OIPEOIPE	OIPE
2007-01-29	Application Is Now CompleteCOMP	COMP
2007-01-14	Cleared by OIPE CSRL194	L194
2007-01-05	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2006-12-26	Information Disclosure Statement consideredIDSC	IDSC
2006-12-26	Request for Foreign Priority (Priority Papers May Be Included)RQPR	RQPR
2006-12-26	Reference capture on IDSRCAP	RCAP
2006-12-26	Information Disclosure Statement (IDS) FiledM844	M844
2006-12-26	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-12-26	Initial Exam Team nnIEXX	IEXX

5 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2020-11-05	Maintenance fee paymentMAFP	MAFP
2016-11-07	Fee paymentFPAY	FPAY
2012-11-05	Fee paymentFPAY	FPAY
2009-04-15	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2006-12-26	AssignmentAS	AS