US7528044B2

CMOSFET with hybrid-strained channels

Summary by NHIP

Hybrid-strained CMOSFET manufacturing

The method manufactures a CMOS device with independently strained channels using distinct silicon-germanium-carbon layers over n-type and p-type wells. The first layer contains more than twenty mol percent germanium while the second layer contains more than two mol percent germanium.

Claim Score by NHIP

Read claim 6, the broadest

Abstract

Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

US7528044B2, drawing sheet 1 — Sheet 1 of 7

Term

Term ended

Expired 23 January 2025, 1.7 years ago.

6 claims: 3 independent, 3 dependent

1
A method of manufacturing a microelectronic device comprising:forming a silicon substrate with first and second wells of different dopant characteristics;forming a first epitaxial silicon-germanium-carbon layer of a first formulation of silicon-germanium-carbon proximate to the first well;and forming a second epitaxial silicon-germanium-carbon layer of a second formulation of silicon-germanium-carbon distinct from the first formulation proximate to the second well.
5
A method of manufacturing a microelectronic device comprising:forming a silicon substrate with first and second wells of different dopant characteristics;forming a first epitaxial silicon-germanium-carbon layer of a first formulation proximate to the first well;and forming a second epitaxial silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well;wherein a dopant characteristic in the first well is n-type and a dopant characteristic in the second well is p-type, and further comprising: forming isolation regions in the top portion of the silicon substrate with a shallow trench process;forming at least one hard mask over one of the wells thereby selectively forming the first epitaxial silicon-germanium-carbon layer wherein the formulation comprises more than twenty mol percent germanium over the first well and the second epitaxial silicon-germanium-carbon layer wherein the formulation comprises more than two mol percent carbon over the second well;forming a silicon capping layer;forming an insulator layer;and forming a gate structure proximate to the first and second wells.
6
Broadest claimClaim Score 73, broad(NHIP)A method of manufacturing a microelectronic device sequentially comprising:forming a silicon substrate with first and second wells of different dopant characteristics;forming an epitaxial layer of a first formulation of silicon-germanium-carbon over the first and second wells;masking a first portion of the epitaxial layer overlying the first well;and modifying a second portion of the epitaxial layer overlying the second well to a second formulation of silicon-germanium-carbon distinct from the first formulation.

Independent claims3

42 paragraphs in 4 sections, as filed

0001This application is a divisional of U.S. patent application Ser. No. 10/922,087 filed Aug. 19, 2004, and entitled, “CMOSFET With Hybrid-Strained Channels,” which is hereby incorporated by reference in its entirety.

BACKGROUND

0002Formation of a semiconductor transistor typically comprises a doped substrate featuring a source and a drain bounded by dielectric regions, a gate dielectric layer, and a gate. One method of increasing the performance of that composition is enhancement of carrier mobility by introduction of a strained channel beneath the gate and between the source and drain.

0003The conventional approach to creating this strained channel is the replacement of a silicon substrate with bulk silicon-germanium, which is graded so as to produce relaxed silicon-germanium at the wafer surface. The silicon-germanium is then covered (capped) with epitaxial silicon. The difference in lattice constants between the silicon cap and the underlying silicon-germanium produces tensile stress in the silicon, and thus more carrier mobility in the silicon cap. A disadvantage with this approach is that the substitution of silicon substrate with relaxed silicon-germanium is both expensive and time-consuming. A further disadvantage is that dislocations in the silicon-germanium lattice are difficult to control and can spread into the strained silicon layer, degrading that layer and hampering performance. The higher the level of defect control, the more expensive the process becomes.

0004Another approach is capping a doped silicon substrate with an epitaxial layer of strained silicon-germanium. As in the conventional approach, the difference in lattice constants between the silicon-germanium and the silicon produces stress in the capped layer. Since the layers are reversed from the conventional approach, the silicon is relaxed while the silicon-germanium is compressively stressed. The strain produces the same benefit of enhanced carrier mobility. Unlike the conventional approach, this process is not expensive since the growth of a thin layer of stressed silicon-germanium is cheaper and less time-consuming than the growth of a thick layer of relaxed silicon-germanium. A disadvantage is that this method only improves p-channel metal oxide semiconductor (PMOS) performance, but degrades n-channel metal oxide semiconductor (NMOS) performance. An alternative is the use of a thin silicon-carbon layer instead of a silicon-germanium layer. The difference in lattice constants for the silicon-carbon on silicon configuration puts tensile, rather than compressive, stress on the silicon-carbon cap. However, this method only improves NMOS performance, but degrades PMOS performance.

0005It is desired to provide strained channels that improve different types of channels and devices, such as complementary metal oxide semiconductor (CMOS) devices.

BRIEF DESCRIPTION OF THE DRAWINGS

0006Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increase or reduced for clarity of discussion.

0007<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of at least a portion of one embodiment of a microelectronic device in an intermediate stage of manufacture according to aspects of the present disclosure.

0008<figref idref="DRAWINGS">FIG. 2</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 1</figref> in a subsequent stage of manufacture.

0009<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 2</figref> in a subsequent stage of manufacture.

0010<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 1</figref> in a subsequent stage of manufacture.

0011<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 4</figref> in a subsequent stage of manufacture.

0012<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 3</figref> or <figref idref="DRAWINGS">FIG. 5</figref> in a subsequent stage of manufacture.

0013<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 6</figref> in a subsequent stage of manufacture.

0014<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional view of the device shown in <figref idref="DRAWINGS">FIG. 7</figref> in a subsequent stage of manufacture.

0015<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view of at least a portion of one embodiment of an integrated circuit according to aspects of the present disclosure.

DETAILED DESCRIPTION

0016The following disclosure provides many different embodiments or examples for implementing different features of various embodiments. Specific examples of components and arrangements are described below only to simplify the disclosure. These are merely examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numbers and/or letters in the various examples. Such repetition is for the purposes of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and/or configurations discussed herein. Moreover, the formation of a first feature proximate to a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact as well as embodiments in which additional features may be formed interposing the first and second features such that the first and second features may not be in direct contact.

0017Unless specified otherwise, layer addition may comprise chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical layer deposition, sputtering, spin-on-coating, and/or other additive processes. Unless specified otherwise, layer removal may comprise chemical mechanical polish (CMP), wet etch, dry etch, and/or other removal processes. Doping may comprise implantation, in situ growth, and/or other dopant addition processes.

0018<figref idref="DRAWINGS">FIG. 1</figref> illustrates a sectional view of at least a portion of one embodiment of a microelectronics device 100 in an intermediate stage of manufacture according to aspects of the present disclosure. In one embodiment, the device may be fabricated on substrate 101 having doped well regions 102a and 102b. The substrate 101 may comprise silicon, monocrystalline silicon, gallium-arsenide, and/or other materials. The differently doped well regions 102a and 102b may comprise any combination of substrate and one or more impurities in two different quantities in two different regions. In one embodiment, the differently doped well regions may comprise 102a being a p-type region, indicating doping with a species such as boron, and 102b being an n-type region, indicating doping with species such as arsenic and/or phosphorous. In another embodiment, the differently doped well regions may comprise 102a being a p+ region, indicating a high amount of doping with a species such as boron, and 102b being a p++ region, indicating a very high amount doping with a species such as boron. Formation of well regions is well known in the art, and one of ordinary skill may appreciate that certain combinations of different well regions are needed for certain devices.

0019In one embodiment, doped regions 102a and 102b may be separated by isolation structures 104. The isolation structures 104 may comprise a dielectric material such as silicon-oxide (SiO2), silicon-nitride (Si3N4), and/or other low-k dielectric or electrically insulating materials. Formation of the isolation structures 104 may comprise local oxidation of silicon (LOCOS), shallow trench isolation (STI), and/or other methods.

0020<figref idref="DRAWINGS">FIGS. 2 and 3</figref> illustrate one method for forming a strained channel that works with different types of doped regions. Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a first strained layer 206a by forming a hard mask 208b over one well 102b, while leaving the other well 102a uncovered. The hard mask 208b may comprise silicon-nitride, silicon-oxygen-nitride (SiON), and/or other deposition and/or implant resistive materials.

0021In one embodiment, the first strained layer 206a may comprise selective epitaxial growth (SEG) in areas where the substrate 101 is not covered by the hard mask 208b—which includes well 102a in the present example. The strained layer 206a can be formed using silane and/or disilane, germane, methane, and an etchant such as hydrochloric acid as reagents. After formation of the strained layer 206a, the hard mask 208b may be removed. If the embodiment contains isolation structures 104, the materials used for the hard mask 208b and the isolation structures 104 may be different to allow for selective removal and/or other processing at subsequent steps.

0022<figref idref="DRAWINGS">FIG. 3</figref> illustrates a subsequent step to <figref idref="DRAWINGS">FIG. 2</figref> in which a second hard mask 308a is formed over the first strained layer 206a. The second hard mask 308a may be similar in construction to the first hard mask 208b of <figref idref="DRAWINGS">FIG. 2</figref>. The second hard mask 308a permits formation of a second SEG strained layer 306b proximate to the second doped well 102b. In an embodiment where the second strained layer 306b is silicon-germanium-carbon, the layer may be formed using silane and/or disilane, germane, methane, and an etchant such as hydrochloric acid as reagents. After formation of the strained layer 306b, the hard mask 308a may be removed.

0023In some embodiments, the strained layers 206a and 306b may be tri-elemental, comprising silicon, germanium, and carbon in formulation, such as according to the following equation: Si1-x-yGexCy. (1) However, the fact that a tri-elemental layer substantially comprises three elements does not preclude composition of additional elements, be they impurities or desired species. The tri-elemental strained layers 206a and 306b may also comprise species added or removed by any subsequent processing, such as implant doping, to form a source and drain. Further, a tri-elemental layer may comprise substantially two elements such that it functions as a di-elemental layer, for example silicon-germanium-carbon with a only trace amount of carbon wherein y from equation (1) is nearly nil, leaving essentially Si1-xGex. This type of formulation allows for easier process modification to increase the relative amount of the trace third element, whereas use of a simple di-elemental layer might require process and tool redesign to achieve such an increase in the trace element. However, a di-elemental layer may be used when proper for the process and/or process tools.

0024In an embodiment where the strained tri-elemental layer 206a is silicon-germanium-carbon grown on the p-well 102a (in the present example), the germanium content may be about twenty to thirty mol percent. Applied to equation (1), x should be at least ten times y, such as: Si0.74Ge0.25C0.01. As y approaches nil, the composition is essentially Si1-xGex. In embodiments where x is greater than ten times y, the lattice constant of the strained silicon-germanium-carbon layer 206a is higher than the lattice constant of the underlying substrate 102a, producing compressive strain in the silicon-germanium-carbon layer 206a.

0025In an embodiment where the a strained tri-elemental layer 306b is silicon-germanium-carbon grown on a well 102b (in the present example), the carbon content may be about two to three mol percent. Applied to equation (1), x should be less than ten times y, such as: Si0.875Ge0.1C0.025. As x approaches nil, the composition is essentially Si1-yCy. In embodiments where x is less than ten times y, the lattice constant of the strained silicon-germanium-carbon layer 306b is lower than the lattice constant of the underlying n-type substrate 102b, producing tensile strain in the silicon-germanium-carbon layer 306b.

0026In order to be of distinct formulations, the tri-elemental strained layers 206a and 306b should have different lattice constants. In one embodiment, the distinct tri-elemental strained layer 206a may comprise silicon-germanium-carbon wherein carbon concentration is less than ten times germanium concentration and the distinct tri-elemental strained layer 306b being silicon-germanium-carbon wherein carbon concentration is greater than ten times germanium concentration. In another embodiment, the distinct tri-elemental strained layer 206a may comprise substantially silicon-germanium and the distinct tri-elemental strained layer 306b may comprise substantially silicon-carbon.

0027In some embodiments, the SEG strained tri-elemental layers 206a and 306b may be further processed to add and/or remove species with the hard masks 208b and 308a in place, with the hard masks 208b and 308a removed, or in combination. A process to add species may comprise implantation. Sacrificial layers such as silicon-oxide may be used to prevent surface damage caused by implantation. A process to remove species may comprise a leaching agent or layer.

0028<figref idref="DRAWINGS">FIGS. 4 and 5</figref> illustrate another method for forming a strained channel that works with different types of doped regions, such as is disclosed in <figref idref="DRAWINGS">FIG. 1</figref>. It is understood that the steps discussed above with <figref idref="DRAWINGS">FIGS. 2 and 3</figref> can be used on some devices while the steps discussed below with <figref idref="DRAWINGS">FIGS. 4 and 5</figref> can be used on other devices on the same wafer.

0029Referring to <figref idref="DRAWINGS">FIG. 4</figref>, a layer 406 may be formed over both the wells 102a and 102b. Formation of layer 406 may comprise SEG, non-selective epitaxial growth, and/or other means. In the present embodiment, the layer 406 includes the three elements silicon, germanium, and carbon.

0030After layer 406 has been formed, a hard mask 408b covers both well 102b and a portion 406b of layer 406 while leaving a portion 406a uncovered. The hard mask 408b may comprise silicon-nitride, silicon-oxygen-nitride, and/or other deposition and/or implant resistive materials. If the embodiment contains isolation structures 104, the materials used for the hard mask 408b and the isolation structures 104 may be different to allow for selective processing at subsequent steps.

0031Once the hard mask 408b is in place, subsequent processing can be performed to add species to and/or to remove species from layer 406a to produce the chemical formulation desired to achieve a certain lattice structure. For example, more or different materials can be implanted, thus changing layer 406a into something similar to tri-elemental strained layer 206a, discussed above. In an embodiment where the tri-elemental strained layer 206a is silicon-germanium-carbon, the implanted species may comprise germanium. Sacrificial layers such as silicon-oxide may also be used to prevent surface damage caused by implantation. In another embodiment, a process to remove species from the layer 406a may comprise a leaching agent or layer. After formation of the tri-elemental strained layer, now referred to as layer 506a (<figref idref="DRAWINGS">FIG. 5</figref>), the hard mask 408b may be removed.

0032Referring to <figref idref="DRAWINGS">FIG. 5</figref>, a hard mask 508a covers both well 102a and tri-elemental strained layer 506a while leaving the other well 102b and layer 406b uncovered. The hard mask 508a may comprise silicon-nitride, silicon-oxygen-nitride, and/or other deposition and/or implant resistive materials. If the embodiment contains isolation structures 104, the materials used for the hard mask 508a and the isolation structures 104 may be different to allow for selective processing at subsequent steps. Subsequent processing to add species to and/or to remove species from layer 406b may be used to produce the chemical formulation desired to achieve a certain lattice structure in the layer 406b, thus changing layer 406b into something similar to tri-elemental strained layer 306b, and distinct from tri-elemental strained layer 506a described in the preceding paragraph.

0033A process to add species may comprise implantation. In an embodiment where the tri-elemental strained layer is silicon-germanium-carbon, the implanted species may comprise carbon. Sacrificial layers such as silicon-oxide may be used to prevent surface damage caused by implantation. A process to remove species may comprise a leaching agent or layer. After formation of tri-elemental strained layer, the hard mask 508a may be removed. Although this embodiment illustrates treatment of layer 406a first, one of skill in the art will recognize that layer 406b may be treated first by covering layer 406a with hard mask 508a. Other embodiments may comprise alternating treatments wherein hard masks 408b and 508a are formed and removed more than once. Still other embodiments may comprise processes that affect both layers 406a and 406b or intermediaries.

0034<figref idref="DRAWINGS">FIG. 6</figref> illustrates one embodiment that may be formed using either the methods described with reference to <figref idref="DRAWINGS">FIGS. 2 and 3</figref> or with reference to <figref idref="DRAWINGS">FIGS. 4 and 5</figref>. A first tri-elemental strained layer 206a (similar to layer 506 in <figref idref="DRAWINGS">FIG. 5</figref>) of one formulation is formed over doped region 102a, and a second tri-elemental strained layer 306b of a formulation distinct from tri-elemental strained layer 206a is formed over differently doped region 102b.

0035<figref idref="DRAWINGS">FIG. 7</figref> illustrates subsequent processing in which the tri-elemental strained layers 206a and 306b may be capped with layer 710 and/or insulating layer 712. Capping layer 710 may comprise silicon. Insulating layer 712 may comprise silicon-oxide. In some embodiments, capping layer 710 may help to reduce stress between the tri-elemental strained layers 206a and 306b and subsequent insulating layer 712. In an embodiment where capping layer 710 is silicon and insulating layer 712 is silicon-oxide, capping layer 710 may serve as a silicon source for insulating layer 712. In some embodiments, capping layer 710 may prevent undesirable environmentally-induced oxidation of strained tri-elemental layers 206a and 306b. However, such oxidation may not occur in embodiments where the substrate never contacts an oxygenated atmosphere.

0036In a transistor embodiment, gate structures 714 may be formed on the insulating laye 712r. Formation of gate structures 714 is well-known in the art. Gate structure 714 materials may comprise doped or undoped silicon or polysilicon, and may be capped with a more conductive material such as tungsten, aluminum, copper, an alloy such as tungsten-silicide, or any other conductive or semiconductive material or combination of such materials. Representation in the drawing of gate structure 714 as a single layer does not preclude composition of multiple layers. In an embodiment where well region 102a is PMOS, well region 102b is NMOS, and there are gate structures 714 over both wells, a CMOS transistor is formed. In another embodiment, a mask may be used to form gate structures 714 proximate to only one well area, forming isolated transistors.

0037<figref idref="DRAWINGS">FIG. 8</figref> illustrates further processing in which insulating structures 812a/812b and spacers 816a/816b may be formed around gate structures 714. Formation of insulating structures 812a/812b and spacers 816a/816b is well-known in the art. Insulating structures 812a/812b may have a width substantially similar to the width of gate structures 714 as shown by structure 812a or substantially similar to the width of spacers 816b as shown by structure 812b. The spacers 816 may comprise one or more layers of silicon-oxide, silicon-nitride, silicon-oxygen-nitride, and/or other materials. The spacers 816a/816b may independently or collectively be employed as a mask during subsequent processing to remove at least portions of insulating layer 712 as shown by structure 812b.

0038In one embodiment, the spacers 816a/816b may act as a mask or pattern for implantation of dopants such as boron, phosphorous, arsenic, and/or other materials into substrate wells 102a and 102b, strained layers 206a and 306b, and capping layer 710 to create sources and drains 818 and channel region 820. In another embodiment, a photoresist mask may be used to implant dopants into only certain wells. Subsequent diffusion, annealing, and/or any other electrical activation processes may be employed to attain a desired doping profile. In some embodiments, the sources and drains 818 may not have similar geometric shapes or compositions. For example, the thicknesses of the sources and drains 818 relative to the sum of the layers 102a, 102b, 206a, 306b, and 710 may differ, or the widths of the sources and drains 818 and the width of the gate structure 714 may differ. In one embodiment, the sources and drains 818 may be implanted before spacer 816a formation but after formation of isolation structure 812a in order to produce a more narrow channel 820.

0039<figref idref="DRAWINGS">FIG. 9</figref> illustrates an integrated circuit 922 in which the device 100 described above may be implemented. For example, the circuit 922 includes a plurality of microelectronic devices 924, one or more of which may be substantially similar to the device 100 shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0040The integrated circuit 922 may also include interconnects 926 extending along and/or through one or more dielectric layers 928 to the devices 924. The interconnects 926 may comprise tungsten, aluminum, copper, and/or other materials. The interconnects 926 may further comprise a barrier metal layer between the bulk interconnect material and the dielectric layers 928. The barrier metal layer may comprise tantalum, titanium, titanium-nitride, tungsten, tungsten-silicide, tungsten-nitride, tantalum-silicon-nitride, and/or other suitable materials. The dielectric layers 928 may comprise silicon-oxide, carbon-doped silicon-oxide, fluorine-doped silicon-oxide, fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on-glass (SOG), and/or any other low-k material.

0041Thus, the present disclosure provides a method of manufacturing a microelectronic device including forming first and second tri-elemental strained layers of distinct formulations over differently doped substrate.

0042The foregoing has outlined features of several embodiments according to aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Contents4

Every citation, both ways

Citations
Document	Relation	Office	Cited during
US8476716B2	Cited by	United States of America	Applicant
US2010155855A1	Cited by	United States of America	Pre-grant
US8294222B2	Cited by	United States of America	Search report
US9419138B2	Cited by	United States of America	Applicant
US9768262B2	Cited by	United States of America	Applicant
US2002179946A1	Cites	United States of America	Applicant
US2004227169A1	Cites	United States of America	Applicant
US2005242398A1	Cites	United States of America	Applicant
US6482705B1	Cites	United States of America	Applicant
US6492216B1	Cites	United States of America	Applicant
US6621131B2	Cites	United States of America	Applicant
US6630714B2	Cites	United States of America	Applicant
US6703271B2	Cites	United States of America	Applicant
US6727550B2	Cites	United States of America	Applicant
US6844227B2	Cites	United States of America	Applicant
US6847098B1	Cites	United States of America	Applicant
US6943407B2	Cites	United States of America	Applicant
US6992025B2	Cites	United States of America	Applicant
US7015517B2	Cites	United States of America	Applicant
US20020179946A1	Cites	United States of America	Third party observation
US20040227169A1	Cites	United States of America	Third party observation
US20050242398A1	Cites	United States of America	Third party observation

8 members in 4 offices

This recordMember, by publication datePriority claim

Priority claims1

Priority claims
Document	Office	Kind	Date
92208704	United States of America	A	2004-08-19

Members8

Family members, oldest first
Document	Office	Kind
CN1738049A	China	A	2006-02-22
US2006038199A1	United States of America	A1	2006-02-23
TW200608570A	Taiwan Province of China	A	2006-03-01
SG120213A1	Singapore	A1	2006-03-28
TWI256731B	Taiwan Province of China	B	2006-06-11
US7145166B2	United States of America	B2	2006-12-05
US2007093046A1	United States of America	A1	2007-04-26
US7528044B2This record	United States of America	B2	2009-05-05

28 transactions on the USPTO file

Allowed after 1 non-final rejection.

Non-final rejections: 1
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2009-05-05	Recordation of Patent Grant MailedPGM/	PGM/
2009-05-05	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2009-04-15	Issue Notification MailedAllowedWPIR	WPIR
2009-03-30	Dispatch to FDCD1935	D1935
2009-03-30	Application Is Considered Ready for IssuePILS	PILS
2009-03-27	Issue Fee Payment VerifiedN084	N084
2009-03-27	Issue Fee Payment ReceivedIFEE	IFEE
2009-02-09	Correspondence Address ChangeC.ADB	C.ADB
2009-02-04	Response to Reasons for AllowanceREAS	REAS
2008-12-30	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2008-12-24	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2008-12-24	Case Docketed to Examiner in GAUDOCK	DOCK
2008-09-27	Date Forwarded to ExaminerFWDX	FWDX
2008-09-09	Response after Non-Final ActionA...	A...
2008-06-27	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2008-06-23	Non-Final RejectionNon-final rejectionCTNF	CTNF
2007-10-31	Case Docketed to Examiner in GAUDOCK	DOCK
2007-09-25	Case Docketed to Examiner in GAUDOCK	DOCK
2007-04-26	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2007-01-25	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2007-01-16	Application Is Now CompleteCOMP	COMP
2007-01-12	Application Dispatched from OIPEOIPE	OIPE
2007-01-09	Cleared by OIPE CSRL194	L194
2007-01-05	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2006-11-22	Information Disclosure Statement consideredIDSC	IDSC
2006-11-22	Electronic Information Disclosure StatementEIDS.	EIDS.
2006-11-22	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-11-22	Initial Exam Team nnIEXX	IEXX

4 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2020-09-30	Maintenance fee paymentMAFP	MAFP
2016-10-20	Fee paymentFPAY	FPAY
2012-09-28	Fee paymentFPAY	FPAY
2009-04-15	Information on status: patent grantGrantedPATENTED CASESTCF	STCF

CMOSFET with hybrid-strained channels

Summary by NHIP

Claim Score by NHIP

Abstract