Memory device with variable trim settings

CROSS-REFERENCE TO RELATED APPLICATIONS

0001Not applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

0002Not applicable

BACKGROUND OF THE INVENTION

0003The present invention relates generally to memory devices and, more particularly, to a memory device with variable trim settings.

0004Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.

0005One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in portable electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.

0006A typical flash memory includes a memory array having a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate. Within each block, cells may be further grouped by page. Each page is associated with a particular word line of the array.

0007NOR and NAND flash memory devices are two common types of flash memory devices, so called for the logical form of the basic memory cell configuration in which each is arranged. Typically, for NOR flash memory devices, the control gate of each memory cell of a row of the array is connected to a word line, and the drain region of each memory cell of a column of the array is connected to a bit line. The memory array for NOR flash memory devices is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current, depending upon their programmed states, from a connected source line to the connected column bit lines.

0008An array of memory cells for NAND flash memory devices is also arranged such that the control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line by its drain region. Instead, the memory cells of the array are arranged together in strings (often termed NAND strings), e.g., of 32 each, with the memory cells connected together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.

0009Memory devices usually include trim circuits that are programmed to output bit values used to provide a variety of options for algorithms that control the operations of the memory device. Such algorithm options may include timing, pulse counts, applied voltage levels, etc. The trim bit values are usually programmed once for a memory device and are rarely changed once the memory device has reached production. Moreover, the bit values are usually applied globally to an entire memory array, which can include thousands of memory blocks, especially for NAND devices. However, as memory array sizes increase, applying the bit values globally to an entire memory array may not be sufficient. Performance variations exist across the array due to factors such as critical dimension (CD) variation within the die and inside NAND strings. Hence, it is difficult to determine a single trim set that may be applied to the entire array.

0010This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

BRIEF SUMMARY OF THE INVENTION

0011The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

0012One aspect of the present invention is seen in a memory device including a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter.

0013Another aspect of the present invention is seen a method for operating a memory device. The method includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:

<figref idref="DRAWINGS">FIG. 1</figref> is a simplified block diagram of a memory device in accordance with one illustrative embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating the organization of a memory array in the device of <figref idref="DRAWINGS">FIG. 1</figref>; and

<figref idref="DRAWINGS">FIGS. 3-5</figref> are simplified flow diagrams of methods for programming the memory device of <figref idref="DRAWINGS">FIG. 1</figref>.

0018While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

0019One or more specific embodiments of the present invention will be described below. It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the present invention unless explicitly indicated as being “critical” or “essential.”

0020The present invention will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

0021Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to <figref idref="DRAWINGS">FIG. 1</figref>, the present invention shall be described in the context of an exemplary flash memory device <b>100</b> coupled to a processor <b>105</b>. The flash memory device <b>100</b> and the processor <b>105</b> may form part of an electronic system <b>110</b>. The flash memory device <b>100</b> has been simplified to focus on features of the memory that are helpful in understanding the present invention. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

0022The flash memory device <b>100</b> includes an array <b>115</b> of memory cells. The memory cells are non-volatile floating-gate memory cells and may employ a NAND or NOR topology. The memory array <b>115</b> is arranged in banks of rows and columns. An address buffer circuit <b>120</b> is provided to latch address signals provided on address input connections A<b>0</b>-Ax <b>125</b>. Address signals are received and decoded by a row decoder <b>130</b> and a column decoder <b>135</b> to access the memory array <b>115</b>. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array <b>115</b>. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

0023Bank address lines <b>140</b> are used to access the different banks of the memory array <b>115</b>. The number of banks may vary. For example, four memory banks may be provided. In such an embodiment, two bank address lines, BA<b>1</b> and BA<b>0</b>, are required to activate a selected one of the memory banks. For example, if the memory banks are designated as Bank<b>0</b> . . . Bank<b>3</b>, and memory bank <b>3</b> is desired to be activated, then the bank address lines are set to BA<b>1</b>=1 and BA<b>0</b>=1. If a memory embodiment has different quantities of memory banks, different quantities of bank select lines will be required.

0024The flash memory device <b>100</b> reads data in the memory array <b>115</b> by sensing voltage or current changes in the memory array columns using sense/latch circuitry <b>145</b>. In one embodiment, the sense/latch circuitry <b>145</b> is coupled to latch a row of data from the memory array <b>115</b>. Data input and output buffer circuitry <b>150</b> is included for bidirectional data communication over a plurality of data (DQ) connections <b>155</b> with the processor <b>105</b>. Write/erase circuitry <b>160</b> is provided to write data to the memory array <b>115</b> or to erase the data programmed therein.

0025A command control circuit <b>165</b> decodes signals provided on control connections <b>170</b> from the processor <b>105</b>. In one embodiment, the command control circuit <b>165</b> is implemented using a state machine that executes the functions of the memory array <b>115</b>, including data read, data write, and erase operations. The state machine may also be responsible for executing the functions required for either a virtual synchronous flash memory function or a synchronous flash memory function, depending on the control word.

0026The processor <b>105</b> generates signals on the address, data, and control lines to the memory device <b>100</b>. Alternate embodiments may use other controllers to generate these signals. Additionally, the memory device <b>100</b> may be coupled to something other than a controller or processor that generates the address, data, and control signals.

0027The command control circuit <b>165</b> in cooperation with the write/erase circuitry <b>160</b> employs variable trim parameters <b>175</b> for adjusting the parameters of the signals used for accessing, programming, or erasing the memory array <b>115</b> depending on the particular performance characteristics across the memory array <b>115</b>. For example, parameters such as program start voltage (Vpgm_start), program step voltage (Vpgm_step_up), program pulse width, inhibit pulse width, erase start voltage (Verarse_start), erase step voltage (Verase_step), erase pulse width, etc., may be varied. In the illustrated embodiment different trim settings may be applied to different subsets of the memory array <b>115</b>. For example, trim parameters <b>175</b> may be applied to a group of blocks, a single block, or pages within a block. The level to which trim parameters <b>175</b> are set depends on the particular characteristics of the memory array <b>115</b> and the expected performance variation across the array. Typically, the trim parameters are determined using a testing process performed during or after the fabrication of the memory device <b>100</b>.

0028In the illustrated embodiment, the memory array <b>115</b> is programmed using an incremental step pulse programming technique, where multiple short pulses are applied to the cells being programmed. After each pulse, the contents are verified to determine if the device is successfully programmed. If the verify step fails, the voltage of the pulse is increased, and the program/verify operation is repeated iteratively. The incremental pulse technique reduces the likelihood that the cells will be over-programmed (i.e., exposed to a higher than necessary voltage), which can reduce the reliability of the device and shorten its operating life. The trim parameters <b>175</b> specify a starting program voltage, a step size, and a pulse width for the incremental step pulse programming technique. An erase operation may also be performed using an incremental pulse technique, with additional trim parameters <b>175</b> being provided to specify the starting erase voltage, step size, and pulse width for the erase cycle.

0029Turning now to <figref idref="DRAWINGS">FIG. 2</figref>, a simplified diagram illustrating the organization of the memory array <b>115</b> is provided. The memory array <b>115</b> includes a plurality of blocks <b>200</b>. Each block <b>200</b> includes a plurality of pages <b>210</b>. Each page <b>210</b> includes a control region <b>220</b> and a data region <b>230</b>. The user data written to the memory array <b>115</b> is stored in the data region <b>230</b>. The control region <b>220</b> is reserved for user purposes, such as for storing error correction codes (ECC), but is not available for storing user data. For example, an exemplary memory array may have a control region <b>220</b> of 64 bytes and a data region <b>230</b> of 2048 bytes defined for each page. The capacity of the memory array <b>115</b> is determined by the size of the data region <b>230</b> across all the pages <b>210</b>, blocks <b>200</b>, and banks. In the illustrated embodiment, the trim parameters <b>175</b> for the memory array <b>115</b> are stored in the control region <b>220</b> for the associated page <b>210</b>. A portion of the control region <b>220</b> (e.g., 8 bytes) may be reserved for the trim parameters <b>175</b>.

0030The trim parameters <b>175</b> may also be defined for a larger grouping of cells in the memory array <b>115</b>, such as for a plurality of pages <b>210</b>, an entire block <b>200</b>, or a group <b>240</b> of blocks <b>200</b>. In such instances, the trim parameters <b>175</b> need not be stored in the control region <b>220</b> for each page <b>210</b>, but rather in a designated location within the trim grouping. For example, if the trim grouping corresponds to a block <b>200</b>, the trim parameters <b>175</b> may be stored in the control region <b>220</b> for the first page <b>210</b> in the block <b>200</b>. Similarly, if the trim grouping corresponds to a group <b>240</b> of blocks <b>200</b>, the trim parameters <b>175</b> may be stored in the control region <b>220</b> for the first page <b>210</b> in the first block <b>200</b> of the group <b>240</b>. Of course, the location of the trim parameters <b>175</b> may be varied depending on the particular implementation, as long as they are stored somewhere within the particular subset of the memory array <b>115</b> with which they are associated. If desired, the trim parameters <b>175</b> may be duplicated in other portions of the trim grouping. For example, the trim parameters <b>175</b> may be stored in every page <b>210</b> and/or in every block <b>200</b> of a trim grouping. The trim parameters <b>175</b> may include information specifying the size of the trim grouping (e.g., page, group of pages, block, or group of blocks).

0031Storing the trim parameters <b>175</b> within the subset of the memory array <b>115</b> with which it is associated is convenient in that no indexing of the trim parameters <b>175</b> to associate them with their associated subset is necessary. For example, if the trim parameters <b>175</b> were to be stored in an external buffer or other data structure, it would be necessary to link the trim parameters <b>175</b> with the associated trim grouping. Having the trim parameters <b>175</b> stored within the trim grouping makes such linking unnecessary. Also, due to the potentially large number of possible blocks <b>200</b> or pages <b>210</b> in a large memory array <b>115</b>, storing the trim parameters <b>175</b> externally would require significant storage resources. By storing the trim parameters <b>175</b> in the associated trim grouping, the trim parameters <b>175</b> may be read as cells within the trim grouping are programmed.

0032Turning now to <figref idref="DRAWINGS">FIGS. 3-5</figref>, simplified flow diagrams of methods for programming or erasing the memory array <b>115</b> in accordance with various embodiments of the present invention are provided. In the embodiments of <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, the memory device <b>100</b> is programmed without an initial block erase, while in the embodiments of <figref idref="DRAWINGS">FIG. 5</figref> the memory device <b>100</b> is programmed with an initial block erase. The method of <figref idref="DRAWINGS">FIG. 3</figref> may also be used for erasing portions of the memory array <b>115</b>. The particular programming technique employed may vary depending on the implementation and the nature of the electronic system <b>110</b>. For purposes of the following examples, it is assumed that the memory device <b>100</b> is programmed one page <b>210</b> at a time, and the trim parameters <b>175</b> are stored for each page <b>210</b> within the control region <b>220</b> of the page <b>210</b>.

0033As seen in <figref idref="DRAWINGS">FIG. 3</figref>, the programming or erasing of the memory array <b>115</b> begins in method block <b>300</b>. In method block <b>310</b>, the trim parameters are read from the control region <b>220</b> of the particular page <b>210</b> being programmed, and the command control circuit <b>166</b> and the write/erase circuitry <b>160</b> are configured to control the write/erase operations to the page <b>210</b> using the specified trim parameters <b>275</b> in method block <b>320</b>. The incremental pulse programming technique is performed by the iterative program/erase and verify stages of method blocks <b>330</b> and <b>340</b>, respectively. The trim parameters <b>175</b> specify the starting program/erase start voltage, the step increase for the iterative steps of the incremental technique, and the pulse width, for example. When the verify stage passes in method block <b>340</b>, the program/erase cycle finishes in method block <b>350</b>.

0034Turning now to <figref idref="DRAWINGS">FIG. 4</figref>, the program cycle begins in method block <b>400</b>, but note that the program trim parameters <b>175</b> are not read prior to the programming. In method block <b>410</b>, a first program step is completed. As the trim parameters <b>175</b> for the page <b>210</b> have not yet been determined, the command control circuit <b>166</b> and the write/erase circuitry <b>160</b> employ a predetermined default set of program parameters. Subsequently, an initial verify read is performed in method block <b>420</b>. During the verify read, the trim parameters <b>175</b> are read from the page <b>210</b>, and the command control circuit <b>166</b> and the write/erase circuitry <b>160</b> are configured using the trim parameters <b>175</b> in method block <b>430</b>. After the trim parameters <b>175</b> are set in method block <b>430</b>, the normal iterative steps of the incremental pulse programming technique are implemented in the program and verify steps of method blocks <b>440</b> and <b>450</b>. The method terminates in method block <b>460</b> following a successful verify in method block <b>450</b>. Of course, if the initial verify read passes in method block <b>420</b>, the method also terminates in method block <b>460</b>, however, this is unlikely due to the incremental pulse programming technique.

0035The default program parameters used in method block <b>410</b> may be selected based on the expected range of values typically for the memory array <b>115</b>, and are implementation specific. For the default parameters, a relatively low program voltage and average pulse width may be applied. For example, the trim parameters <b>175</b> may specify a program voltage of 16V with a step increase of 0.6V. The default parameter is set at a lower value than is expected for the trim parameters <b>175</b> to avoid over-programming the memory array <b>115</b>. In this example, a default program voltage of 15V may be used. Although the program voltage is less than what would have been used if the trim parameters <b>175</b> had been previously read (i.e., as in the method of <figref idref="DRAWINGS">FIG. 3</figref>), the impact on the programming is minimal, as it is used only in the first programming stage if the incremental pulse technique. Subsequent program pulses are completed using the specified trim parameters <b>175</b>. Generally, the initial programming voltage may be referred to as a weak program voltage, as it is less than the expected value for the actual program voltage.

0036Table 1 below illustrates the program pulses employed using the methods of <figref idref="DRAWINGS">FIGS. 3 and 4</figref> assuming a initial program voltage of 16V and a step increase of 0.6V specified in the trim parameters <b>175</b>. For purposes of illustration, it is assumed that the programming will be completed after 5 cycles of the incremental pulse technique. Of course, the actual number of pulses may vary in an actual implementation.

0037<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="center" /><thead><row><entry namest="1" nameend="1" rowsep="1">TABLE 1</entry></row></thead><tbody valign="top"><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>Incremental Pulse Programming</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="56pt" align="center" /><colspec colname="3" colwidth="98pt" align="center" /><tbody valign="top"><row><entry /><entry>Vpgm = 16 V</entry><entry>Initial Trim Read</entry><entry>Set Trim After Verify Read</entry></row><row><entry /><entry>Vstep = 0.6 V</entry><entry>(FIG. 3)</entry><entry>(FIG. 4)</entry></row><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="56pt" align="char" char="." /><colspec colname="3" colwidth="98pt" align="char" char="." /><tbody valign="top"><row><entry /><entry>Pulse 1</entry><entry>16</entry><entry>15</entry></row><row><entry /><entry /><entry /><entry>(Default)</entry></row><row><entry /><entry>Pulse 2</entry><entry>16.6</entry><entry>16.6</entry></row><row><entry /><entry>Pulse 3</entry><entry>17.2</entry><entry>17.2</entry></row><row><entry /><entry>Pulse 4</entry><entry>17.8</entry><entry>17.8</entry></row><row><entry /><entry>Pulse 5</entry><entry>18.4</entry><entry>18.4</entry></row><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0038The programming method of <figref idref="DRAWINGS">FIG. 4</figref> shortens the programming time for the memory array <b>115</b> as it is not necessary to perform the initial read of the trim parameters <b>175</b> prior to the programming. The trim parameters <b>175</b> are read without additional overhead during the first verify read.

0039Referring now to <figref idref="DRAWINGS">FIG. 5</figref>, a programming technique is illustrated that employs an initial block erase. In the example of <figref idref="DRAWINGS">FIG. 5</figref>, it is assumed for purposes of illustration only that all pages <b>210</b> of the block <b>200</b> have the same trim parameters <b>175</b>, and that the trim parameters <b>175</b> are stored in the control region <b>220</b> of the first page <b>210</b>. Of course, in an actual implementation, each page may have its own trim parameters <b>175</b> and the storage location may be varied as described above. The programming of the memory array <b>115</b> begins in method block <b>500</b>. In method block <b>510</b>, the trim parameters are read from the control region <b>220</b> of the first page <b>210</b> of the block <b>200</b> being programmed. The command control circuit <b>166</b> and the write/erase circuitry <b>160</b> are configured to control the write operations to the block <b>200</b> using the specified trim parameters <b>275</b> in method block <b>520</b>. A block erase of the block <b>200</b> is performed in method block <b>530</b>. The incremental pulse programming technique is performed by the iterative program and verify stages of method blocks <b>540</b> and <b>550</b>, respectively. The trim parameters <b>175</b> are restored to the control region <b>220</b> of the first page <b>210</b> during the programming in method block <b>540</b>. When the verify stage passes in method block <b>550</b>, the programming transitions to the next page via method block <b>560</b> and repeats the program and verify stages of method blocks <b>540</b> and <b>550</b> for the next page specified in method block <b>570</b>. After the last page is programmed in block <b>560</b>, the method finishes in method block <b>580</b>.

0040In some embodiments, the techniques of <figref idref="DRAWINGS">FIG. 3-5</figref> may be altered, depending on the particular implementation. For example, if the trim parameters <b>175</b> are stored in one location in a larger trim grouping, the trim parameters <b>175</b> need only be read once during the programming of the grouping. Subsequent programming may be completed using the extracted trim parameters <b>175</b>.

0041The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.