Load lookahead prefetch for microprocessors

CROSS REFERENCE TO RELATED APPLICATIONS

U.S. patent application entitled “Branch Lookahead Prefetch for Microprocessors”, having Ser. No. 11/016,200, filed on Dec. 17, 2004, and assigned to the assignee of the present invention.

U.S. patent application entitled “Using a Modified Value GPR to Enhance Lookahead Prefetch”, having Ser. No. 11/016,206, filed on Dec. 17, 2004, and assigned to the assignee of the present invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to instruction processing in a microprocessor. More particularly, the invention is a microprocessor that utilizes the time period associated with a stall condition in order to speculatively execute instructions and identify invalid data such that retrieval of valid data can be initiated.

2. Description of Related Art

There is a continual desire by computer users to maximize performance and a corresponding pressure on the computer industry to increase the computing power and efficiency of microprocessors. This is especially evident in the server computer field where entire businesses are dependent on their computer infrastructure to carry out and monitor day to day activities that affect revenue, profit and the like. Increased microprocessor performance will provide additional resources for computer users while providing a mechanism for computer manufacturers to distinguish themselves from the competition.

Over the years, state of the art microprocessors have evolved from fairly straight forward systems to extremely complex integrated circuits having many millions of transistors on a single silicon substrate. One of the many improvements made to microprocessors was the ability of microprocessors to execute more than one instruction per cycle. This type of microprocessor is typically referred to as being “superscalar”. A further performance enhancement was the ability of microprocessors to execute instructions “out of order”. This out of order operation allows instructions having no dependencies to bypass other instructions which were waiting for certain dependencies to be resolved. The IBM Power and PowerPC series of microprocessors are examples of superscalar systems that provide out of order processing of instructions. Microprocessors may support varying levels of out of order execution support, meaning that the ability to identify and execute instructions out of order may be limited.

One major motivation for limiting out of order execution support is the enormous amount of complexity that is required to identify which instructions can execute early, and to track and store the out of order results. Additional complexities arise when the instructions executed out of order are determined to be incorrect per the in order execution model, requiring their execution to not impact the architected state of the processor when an older instruction causes an exception. As processor speeds continue to increase, it becomes more attractive to eliminate some of the complexities associated with out of order execution. This will eliminate logic (and its corresponding chip area, or “real estate”) from the chip which is normally used to track out of order instructions, thereby allowing additional “real estate” to become available for use by other processing functions.

As known in the art, there are certain conditions that occur when instructions are executed by a microprocessor that will cause a stall to occur where instruction execution is limited or halted until that condition is resolved. One example is a cache miss which occurs when data required by an instruction is not available in a level one (L1) cache and the microprocessor is forced to wait until the data can be retrieved from a slower cache, or main memory. Obtaining data from main memory is a relatively slow operation, and when out of order execution is limited due to aforementioned complexities subsequent instructions cannot be fully executed until valid data is received from memory.

More particularly an older instruction that takes a long time to execute can create a stall that may prevent any younger, or subsequent instructions from executing until the time consuming instruction completes. For example, in the case of a load instruction that requires access to data not in the L1 cache (cache miss), a prolonged stall can occur while data is fetched from a slower cache, or main memory. Without facilities to support all out-of-order execution scenarios, it may not be possible to change instruction ordering such that forward progress through the instruction stream can be made while the missed data is retrieved.

Therefore, it can be seen that a need exists for a microprocessor with reduced or limited support for out of order execution that can make progress during stall conditions by identifying loads in the instruction stream and fetching the corresponding data.

SUMMARY OF THE INVENTION

In contrast to the prior art, the present invention defines a load lookahead prefetch mechanism that reduces the performance impact of a pipeline stall, and the frequency of cache miss stalls by allowing the instruction stream to be examined during an extended stall condition.

Broadly, the present invention allows the microprocessor to identify and speculatively execute future load instructions. When possible, the data for such future load instructions can be prefetched, such that it is either available in the L1 cache, or will be enroute to the processor, allowing the load to execute with a reduced latency when it is re-executed (i.e. non-speculatively executed) after the stall condition expires. The present invention performs this speculative execution without changing the architected state of the microprocessor.

When the machine detects an extended stall condition (for example a load that has an invalid address translation or misses the data cache), load lookahead prefetch is started and instructions that would normally have stalled begin to be speculatively executed. Results from speculative instruction execution are provided to younger dependent instructions in the speculative instruction stream when possible using available facilities.

In speculative execution mode, writeback (storing results in architected facilities) is disabled because of limitations in the ability of the microprocessor of the present invention to support out of order execution. That is, writeback for certain architected facilities cannot occur until the instruction causing the initial stali condition completes. Further, depending on the specific microprocessor implementation there may be limited facilities for storing speculative results and providing them to dependent instructions; therefore, it becomes necessary to track which results are unavailable or “dirty”, from the perspective of younger dependent instructions executing during the stall condition. Additionally, instructions may produce invalid, or “dirty”, results during speculative execution for various reasons (for example due to a cache miss, due to facilities not being supported or available during speculative execution, or due to “dirty” source operands i.e. the propagation of “dirty” results). It is desired to limit the occurrence of prefetches for loads with “dirty” source operands for any of these reasons because these prefetches will not perform valid work by loading data from an invalid address and may have a negative impact on performance by polluting the cache hierarchy with unneeded data.

The present invention uses a set of status bits in the execution units to dynamically keep track of the dependencies between instructions in the pipeline and transfer “dirty” indications to dependent instructions. A bit vector tracks the availability of valid results for executed instructions for which architected results are not available for use by subsequent instructions. Both sources of information are used to tell the load/store unit (LSU) whether or not the source operands (data to be used in the microprocessor operations) for a given load address calculation are valid. If the operands are valid, then a prefetch operation is started to retrieve the valid data from the cache ahead of time such that it can be available for the load instruction when it is subsequently non-speculatively executed. For example, this is possible in the case of a cache miss, since data for speculatively executed load instructions can be obtained from storage during the latency period caused when data is retrieved from memory for the instruction that missed the cache (i.e. caused the stall condition).

The present invention determines, by speculative execution of instructions during a stall condition, which load instructions are likely to have valid operands. The LSU then initiates a request for the data from that storage location during speculative operations such that the data is being retrieved during the stall condition and will likely be available when actual instruction execution resumes.

Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of an overall computer system that may include a microprocessor capable of implementing the load lookahead prefetch in accordance with the present invention;

<figref idref="DRAWINGS">FIG. 2</figref> represents the elements of a microprocessor which may implement the load lookahead prefetch mechanism of the present invention;

<figref idref="DRAWINGS">FIG. 3</figref> is a representation of the dirty bit vector as implemented by the present invention;

<figref idref="DRAWINGS">FIG. 4</figref> illustrates the dependency on load (DL) bits of the present invention;

<figref idref="DRAWINGS">FIG. 5</figref> is a representative microprocessor instruction of one preferred embodiment of the present invention showing the opcodes, source and destination register identification bits, dirty bit and DL bits;

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of the key load lookahead prefetch functions of the present invention;

<figref idref="DRAWINGS">FIG. 7</figref> is another more detailed block diagram that shows the checking and updating functions for the dirty bit vector in the instruction dispatch unit;

<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram that represents the tracking of the dirty bit and DL bits as they are maintained in the execution units;

<figref idref="DRAWINGS">FIG. 9</figref> is a logic diagram that illustrates the logical relationships between the dirty bit vector, execution unit dirty bit, DL bits and load reject signals of the tracking function of <figref idref="DRAWINGS">FIG. 6</figref>;

<figref idref="DRAWINGS">FIG. 10</figref> is a timing diagram showing a progression of load instructions through the pipeline in accordance with a preferred embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 11</figref> is a timing diagram that illustrates load and arithmetic/logical instructions in the pipeline of a microprocessor contemplated by a preferred embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 12</figref> is a flow chart showing the initiation of the load lookahead prefetch of the present invention; and

<figref idref="DRAWINGS">FIG. 13</figref> is another flow chart showing the instruction flow through a microprocessor operating in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a typical data processing system is shown which may be used in conjunction with the present invention. A central processing unit (CPU) <b>10</b> may include a PowerPC microprocessor, commercially available from the IBM Corporation or a Pentium class microprocessor, available from Intel Corporation interconnected to the various other system components by a system bus <b>12</b>. Read only memory (ROM) <b>16</b> is connected to CPU or microprocessor <b>10</b>, via bus <b>12</b> and includes the basic input/output system (BIOS) that controls the basic computer functions. Random access memory (RAM) <b>14</b>, I/O adapter <b>18</b> and communication adapter <b>34</b> are also connected to system bus <b>12</b>. RAM <b>14</b>, or main memory, along with a level 1 (L1) and level 2 and level 3 (L2 and L3) caches (if provided) will generally make up the memory hierarchy of the data processing system. Data can be loaded from the larger, slower main memory to the relatively smaller, faster cache memories in order to make it more readily available to the processor when needed. I/O adapter <b>18</b> may be a small computer system interface (SCSI) adapter that communicates with a disk storage device <b>20</b>. Communications adapter <b>34</b> may be a network card that interconnects bus <b>12</b> with an outside network. Adapter <b>34</b> may also include an I/O port that allows a connection to be made through a modem <b>40</b>, or the like to enable the data processing system to communicate with other such systems via the Internet, or other communications network (LAN, WAN). User input/output devices are also connected to system bus <b>12</b> via user interface adapter <b>22</b> and display adapter <b>36</b>. Keyboard <b>24</b>, track ball <b>32</b>, mouse <b>26</b> and speaker <b>28</b> are all interconnected to bus <b>12</b> via user interface adapter <b>22</b>. Display monitor <b>38</b> is connected to system bus <b>12</b> by display adapter <b>36</b>. In this manner, a user is capable of inputting to the system through keyboard <b>24</b>, trackball <b>32</b> or mouse <b>26</b> and receiving output from the system via speaker <b>28</b> and display <b>38</b>. Additionally, an operating system (OS) <b>39</b>, such as the AIX, Linux, Windows operating system, or the like is shown running on CPU <b>10</b> and used to coordinate the functions of the various components shown in <figref idref="DRAWINGS">FIG. 1</figref>.

Referring to <figref idref="DRAWINGS">FIG. 2</figref>, the basic components of a microprocessor in accordance with the present invention will now be described. Bus <b>12</b> connects microprocessor <b>10</b> to the other components of the data processing system, including RAM <b>14</b> (main memory). Memory <b>14</b> provides storage for data and instructions which are provided to, or received from, microprocessor <b>12</b> via bus interface unit (BIU) <b>112</b>. Data information is then stored in L1 data cache and memory management unit (MMU) <b>116</b>, while instructions are stored in instruction cache and MMU <b>114</b>. As known in the art, L1 data cache <b>116</b> and L1 instruction cache <b>114</b> provide smaller but higher speed storage for information being used by the microprocessor. It is desirable to load the L1 cache with the maximum data and instructions that are likely to be used by the microprocessor.

In accordance with the present invention, instructions are retrieved in order by sequential fetcher (IFU) <b>117</b> from L1 cache <b>114</b> and provided to instruction dispatch unit (IDU) <b>111</b>. Branch instructions are provided from fetcher <b>117</b> to IDU <b>111</b>, which in turn sends them to branch processing unit (BPU) <b>118</b>. Branch unit <b>118</b> executes branch instructions that control the flow of the instruction stream by branching, or jumping, to another basic block of instructions. Conditional branch instructions evaluate a condition stored in a condition register and branch to another non-sequential instruction when the condition is satisfied and continue sequential instruction processing when the condition is not satisfied. IFU <b>117</b> also includes branch prediction logic <b>113</b> that provides a prediction as to whether the branch will be taken or not, based on one or more hint bits, the history of previously executed branch instructions, or the like.

IDU <b>111</b> includes a <b>64</b> entry instruction buffer <b>121</b> which receives the fetched instructions from sequential fetcher <b>117</b>. Instructions are stored in buffer <b>121</b> while awaiting dispatch to the appropriate execution units. In a preferred embodiment of the present invention, a dirty bit vector <b>119</b> in IDU <b>111</b> includes 32 bits each one of which corresponds to each of the 32 architected general purpose registers in the microprocessor. It should be understood that a general purpose register having 32 entries is used merely as an example and should not be considered a limitation. Those skilled in the art will readily comprehend how general purpose registers (as well as other types of architected facilities such as floating point registers) of other sizes, e.g. 8, 16, 64, 128 and the like, are contemplated by the scope of the present invention. The bits in dirty bit vector <b>119</b> will indicate which results in the GPRs have valid, or invalid results. In a preferred embodiment a “0” will be set in the dirty bit vector for those registers having valid results and a “1” in the bit vector will indicate invalid results. Dirty bit vector <b>119</b> will be described in more detail below.

IDU <b>111</b> dispatches instructions to the various execution units, such as a fixed point, or integer unit, FXU <b>122</b> and floating point unit FPU <b>130</b>. Both FXU <b>122</b> and FPU <b>130</b> are arithmetic/logic units that perform various functions, such as ADD, SUBTRACT, MULTIPLY, DIVIDE. Basically, fixed point arithmetic differs from floating point arithmetic in that scientific notation is possible with floating point operations because the radix point is capable of being moved among the digits of the number. In contrast fixed point arithmetic implicitly sets the radix at a particular place. Fixed point and floating point arithmetic is well known to those skilled in the art and will not be discussed further herein.

Load store unit (LSU) <b>128</b> executes instructions that either load information (data and instructions) from memory to the microprocessor registers or store information from those registers into memory. GPRs <b>132</b> are associated with FXU <b>122</b> and floating point registers FPRs <b>136</b> are associated with the FPU <b>130</b>. These registers store the arithmetic and logical results from execution of the instructions by their respective execution units. It can be seen that IDU <b>111</b> is connected to all of the execution units and registers such that any type of instruction can be dispatched from the IDU. Further, the output of the execution units <b>122</b>, <b>128</b> and <b>130</b> are connected to the registers <b>132</b> and <b>136</b> such that the execution units can store results to the registers from executed instructions and then retrieve those results to be used in processing existing or future instructions. The elements shown in <figref idref="DRAWINGS">FIG. 2</figref> and described above can be considered to constitute the “core” of a microprocessor. With modem technology it is possible and even likely that many microprocessors will include multiple cores and thus have multiple execution units, such as LSUs, FXUs and FPUs.

Referring to <figref idref="DRAWINGS">FIG. 3</figref>, dirty bit vector <b>119</b> is shown with its relationship to general purpose registers <b>132</b>. Each of the 32 bits in vector <b>119</b> represent the values in the 32 general purpose registers, i.e. Bits <b>0</b>-<b>31</b> in vector <b>119</b> directly correspond to registers <b>0</b>-<b>31</b> in GPR <b>132</b>. For purposes of explanation and not limitation, vector <b>119</b> is described herein as being associated with GPR <b>132</b>. It should be understood that other preferred embodiments of the present invention are contemplated in which a dirty bit vector is associated with floating point registers <b>136</b>.

<figref idref="DRAWINGS">FIG. 4</figref> shows a set of bits which indicate the dependency of speculatively executing instructions relative to one another. These dependency on delayed validation bits can monitor various conditions such as the dependency by a current instruction on a prior instruction that moves data between registers within the microprocessor, or by an instruction that uses data written to a register by an I/O device. In the preferred embodiment the dependency on delayed validation bits will monitor the dependency of a current instruction on the data retrieved by a load instruction. These dependency on load (DL) bits are used to track the time between when a load instruction returns the result and when that result is determined to be valid. For purposes of simplifying the understanding the present invention, the dependency on load (DL) bits will be used as one example of the dependency on delayed validation bits. However, it should be noted that other preferred embodiments may have different, or additional dependency bits to track the distance between the validation of other sources of data (beyond load instructions) and the dependent instruction. The dependency on load example is used herein for the purposes of illustration only and not limitation. The DL bits are essentially a shift counter having a number of bit positions equal to the number of cycles between the time the load is returned and when its validity is subsequently determined. It will be apparent to those skilled in the art that various implementations of the present invention can be utilized wherein the validity may be determined, e.g. two (2) cycles after the result is returned (see timing diagram of <figref idref="DRAWINGS">FIG. 10</figref>) or three (3) cycles after the result is returned (<figref idref="DRAWINGS">FIG. 11</figref>). It will be understood that in the case where three (3) cycles are needed to determine validity, three bits will be needed to track the validity state, i.e. a first bit that is set when the result is returned, a second bit is set corresponding to the first cycle after return and a third bit that will indicate that the determination of validity is completed. In a preferred embodiment there may be two (2), or more, load store units. In this case there will need to be a set of DL bits for each L/S unit. In <figref idref="DRAWINGS">FIGS. 4 and 5</figref>, reference numerals <b>150</b>, <b>151</b> each represent three (3) DL bits that correspond to first and second LSUs, respectively. Further, the dirty bit vector that is associated with the result being processed by the load instruction will be tracked by the instruction. Field <b>152</b> of the instruction is a continuation of the dirty bit in vector <b>119</b> that is associated with an architected register. This dirty bit “D” in the instruction is also determined, not only by the value in bit vector <b>119</b>, but also by various other inputs. These include the DL bits, a load reject which is an indication of whether load data is valid, forwarded dirty bits from other instructions, and the like.

Further, with regard to <figref idref="DRAWINGS">FIG. 4</figref>, field <b>153</b> will be used in the case where multi-threading is implemented. That is, the processor will need to know which of the two (or more) threads is being executed in order to track the resources, i.e. context of each thread. This bit or an equivalent indicator will be present for all multithreaded implementation, regardless of whether the threads are capable of utilizing the load lookahead prefetch mechanism of the present invention. Finally, a field <b>157</b> includes a tag bit that tells the processor whether the instruction is being executed speculatively, i.e. “S”.

<figref idref="DRAWINGS">FIG. 5</figref> is an illustration of an instruction capable of being implemented by a microprocessor that operates in accordance with the present invention. Reference numeral <b>156</b> is an opcode that defines the type of operation being performed, such as an ADD, COMPARE, LOAD, or the like. RT <b>155</b> is the target register where the results of the operation are stored. Registers RA <b>154</b> and RB <b>158</b> are two source registers having the operands that are to be manipulated in accordance with the opcode of the instruction. Tag bit <b>157</b> is included to indicate whether the instruction is being speculatively executed and will not write its results back to the architected registers, or non-speculatively executed where write back is enabled. Dirty bit <b>152</b> and DL bits <b>150</b>, <b>151</b>, as well as speculative execution bit <b>153</b> have been described above with reference to <figref idref="DRAWINGS">FIG. 4</figref>.

Load lookahead prefetch in accordance with the present invention is started whenever a load (or other instruction that takes a lot of cycles to execute) causes an extended stall condition such that the out of order facilities, if any, provided by the processor can not support further progress through the instruction stream. Once active, it accomplishes three things: (1) allows the execution of instructions without changing the architected state of the machine; (2) determines which loads are eligible to be prefetched; and (3) speculatively prefetches data into the L1 cache. Once lookahead prefetch mode is activated, instructions that are not supported by the out of order execution mechanisms of the processor (if any), identified herein as “speculative instructions”, are not allowed to be written back, that is, speculative results are prevented from being written into the architected registers of the microprocessor. For the case of an in-order processor, all out of order instructions are considered speculative and will not write any architected facilities. If the architected registers were allowed to be updated, then actual execution rather than speculative execution of the instructions would occur. In a preferred embodiment, the present invention is implemented as an in-order microprocessor in which the results of speculatively executed instructions are not allowed to update the architected facilities. However, data processing systems which support all variations of out of order execution are contemplated by the scope of the present invention. In another aspect of the preferred embodiment, it is ensured that instructions are treated as speculative by sending a signal with each instruction dispatched under the load lookahead prefetch mechanism of the present invention, which indicates that the instruction should be treated as speculative. It should be understood that there are other methods contemplated by this invention for tracking speculative instructions.

Several techniques for processing the results of speculative instructions are possible. These include storing the speculative data to a separate set of registers (as described in co-pending patent application “Using a modified Value Register to Enhance Lookahead Prefetch Operations”, Ser. No. 11/016,206, having attorney docket number AUS9-2003-1068 and filed on Dec. 17, 2004, a small cache or, as in the presently described preferred embodiment, using the forwarding paths for data prior to, during, and after the stage at which writeback would have occurred (these paths being the same paths used in non-speculative execution) to forward the necessary bits of information to younger instructions, i.e. more recent instructions in the stream of instructions. As long as the instructions do not write results to the architected registers any of the aforementioned techniques will provide correct results.

In any case, determining which loads are eligible for prefetching requires that instruction dependencies and the validity of results be tracked. This functionality is split into two parts. Execution units are responsible for dynamically tracking dependencies related to instructions in the execution pipeline using a set of “Dirty” (D) and “Dependency on Load” (DL) bits. For the purpose of example and not limitation, invalid or unavailable results, particularly for those speculative instructions that are no longer in the pipeline, are tracked in this preferred embodiment by the IDU (other embodiments may track invalid or unavailable architectural facilities in the execution units, or with the architectural facility.

Load lookahead prefetch continues until the initial stall condition is resolved. In the case of a load causing a cache miss, this could be a signal indicating that the load data is now available. When this occurs, normal non-speculative execution will restart at the stalled instruction. Any information about speculative result validity tracked by load lookahead is cleared at this time.

<figref idref="DRAWINGS">FIG. 6</figref> is an overview of the present invention showing the various circuit elements used in a microprocessor utilizing load lookahead prefetch. Microprocessor instructions ready for dispatch are held in a latch <b>160</b>. These instructions were provided to instruction buffer <b>121</b> in IDU <b>111</b> and have been processed by instruction sequencing logic prior to be received in latch <b>160</b>. The instruction is then dispatched from latch <b>160</b> to its appropriate functional unit <b>168</b>, such as the LSU, FPU, FXU or the like and latched in by latch <b>169</b>. Source lookup logic <b>162</b> also receives the instruction via latch <b>166</b> and then determines if the source registers contain invalid data, and if so, a dirty bit value is provided to dirty bit latch <b>163</b>. As noted above, the dirty bit will be provided along with the instruction to the various pipeline stages encountered during instruction processing. Dirty bit logic <b>161</b> will be described in greater detail in accordance with <figref idref="DRAWINGS">FIG. 7</figref>.

The dirty bit tracking and dependence on load logic <b>165</b> then receives the dirty bit from latch <b>163</b> and stores it in latch <b>164</b>. Those skilled in the art will understand how bits of data and instructions are latched across logic boundaries in order to keep the various processing elements in synchronization with one another.

Tracking logic <b>167</b> is also shown as part of dirty bit tracking and DL logic <b>165</b>. Tracking logic <b>167</b> receives several inputs and outputs a dirty bit signal based on the state of the various inputs. The dirty bit from bit vector <b>119</b> is input to tracking logic <b>167</b> from IDU <b>111</b>, via latch <b>164</b> which represents one of possibly several latches used by the present invention to ensure correct timing and synchronization. A signal representing the reject status of a load instruction (i.e. whether the load data is valid) is also received by logic <b>167</b>. Further, the DL bits and dirty bit from the instructions in the functional unit <b>168</b> are also received by logic <b>167</b>, which then outputs a dirty bit signal on line <b>174</b> as determined by logic <b>167</b>. There are three (3) criteria which will cause the dirty bit on line <b>174</b> to be set: (1) source data marked as “dirty” is forwarded from another instruction in functional unit <b>168</b> (i.e. from mux <b>170</b>); (2) the IDU can determine the source operand is dirty from the associated bit in dirty bit vector <b>119</b> and data is read from the GPR; and (3) source data is read from a load that is later determined to be invalid (load reject) as received on input line <b>175</b> and the LSB of the DL bits is “1”. More particularly, when it is determined that the data is invalid a “reject” signal is input at the appropriate time via a bus <b>174</b> to logic <b>167</b> such that the dirty bit value is updated. Input lines <b>176</b>, <b>177</b> provide the dirty bit and DL bits from source multiplexer <b>170</b>. As noted above, the dirty bits and DL bits are forwarded with each instruction as it progresses through the pipeline. It can be seen that line <b>174</b> will provide these bits back to source mux <b>170</b> after each stage. As will be described in more detail below, the DL bits function as a shift counter with the number of bits being dependent on the cycles needed to validate the load data. The most significant bit (MSB) is initially set and then subsequently shifted as each pipeline stage is traversed. When the least significant bit (LSB) is set, then the determination of the validity of the load data is completed and it will be known whether a load reject has occurred. The operation and use of the DL bits will be described more fully below.

Functional unit <b>168</b> includes the pipeline stages commonly found in the vast majority of microprocessors, such as decode, execute (arithmetic and logic operations), writeback and the like. Source multiplexer <b>170</b> receives input from GPR <b>132</b>, from the latches <b>171</b>, <b>172</b> and <b>173</b> associated with each stage, and the dirty and DL bits from tracking logic <b>167</b> via line <b>174</b>. It should be noted that line <b>174</b> in <figref idref="DRAWINGS">FIG. 6</figref> represents multiple dirty bit signals, since tracking logic needs an output from each stage to that stage's own bypass multiplexer. The dirty and DL bits are then added to the instruction by source mux <b>170</b> as it enters the pipeline of functional unit <b>168</b>. This places the instruction in the format as shown in <figref idref="DRAWINGS">FIG. 5</figref>. By way of example but not limitation, latch <b>169</b> could be considered the decode and read stage, latches <b>171</b> and <b>172</b> execute stages and latch <b>173</b> the writeback stage.

<figref idref="DRAWINGS">FIG. 7</figref> shows the checking and updating functions associated with the dirty vector <b>119</b> in the instruction dispatch unit. More specifically, dirty bit vector <b>119</b> will be maintained to keep track of which results are no longer available for forwarding. The number of bits in dirty vector <b>119</b> is dependent on the number of architected registers present in the processor.

At dispatch time, every instruction will lookup all its source registers (R_Aand R_B) in dirty vector <b>119</b> to determine if any of these are to be considered invalid. Other preferred embodiments may lookup the dirty state of the register (or other architectural facility) vector at the time that the register is accessed. All of the bits in dirty bit vector <b>119</b> are initially set to “0” and these bits are set to “1” when the instructions pass the writeback stage. Source logic looks up the dirty bits in vector <b>119</b> for registers associated with the instructions being dispatched and a dirty bit is then forwarded to the functions units via latch <b>216</b>. The instruction dirty bit in the functional unit which is an indication that one or more data sources for an instruction are invalid, can be set in one of three (3) ways: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0052">Source data is read from a forwarding path and that data is already marked dirty (dirty bit from an instruction in the pipeline is forwarded)</li><li id="ul0002-0002" num="0053">The IDU indicates that a source operand is dirty based on a lookup in the dirty vector (IDU dirty bit vector <b>119</b>); or</li><li id="ul0002-0003" num="0054">Source data was read from a load that later determines the data is invalid and sends a reject signal (DL bits indicate LSB is “1” and load reject occurs).</li></ul></li></ul>

The dirty bit is forwarded along with results to any dependent instruction. If an instruction uses multiple sources, the dirty bits can simply be logically ORed together. That is, if an instruction is using R_Aand R_B, then the dirty bits for these two (2) registers are ORed together and if one bit is set then the data resulting for the execution of the instruction is considered invalid. The LSU will block cache access when it encounters a load with its dirty bit set.

As instructions pass the point where their results are no longer available to younger instructions, for example the writeback stage, which is the point where results calculated by the execution units are provided to the architected registers, target registers are marked in the IDU's dirty vector <b>119</b> to indicate which results are invalid. The timing is such that the first instruction which is dependent on the previous result, but cannot receive the value via a forwarding path will then be able to look up if the value is invalid in the dirty bit vector.

As shown in <figref idref="DRAWINGS">FIG. 7</figref>, instructions ready for dispatch are stored in latch <b>160</b> and then provided to another latch <b>211</b>, as well as to the execution units. Logic <b>213</b>, via decode <b>212</b>, also receives instructions from the writeback stage subsequent to latch <b>217</b> and prior to the instruction being provided to writeback latch <b>218</b>. Logic <b>213</b> determines if the instruction associated with the target register is considered invalid. This logic determines: (1) if the register is dirty based on whether load lookahead prefetch mode is active; (2) the instruction is currently considered valid; and (3) whether there are multiple threads in the processor and which thread is current, i.e. the dirty bit needs to be written to the dirty bit vector of the correct thread. If the three (3) previous considerations are true, the dirty bit for that instruction is set. The instructions are provided to source lookup logic <b>214</b> which examines the source registers and uses the dirty bit vector <b>119</b> to determine whether the data is valid. A logical “1” will be associated with the instruction being processed when the source data is invalid and a “0” will be associated with the instructions if then source data is valid. Of course, these bit values are merely exemplary and other patterns are contemplated by the scope of the present invention to indicate the validity of the instruction data. Logic <b>215</b> then validates the dirty bit by determining if lookahead mode is active, the instruction is valid and whether the correct thread is being utilized. The dirty bit is then provided to latch <b>216</b> to be subsequently supplied to the instruction in the execution unit. It can be seen that the instruction is initially provided to both the dirty bit logic and the execution units. Once the dirty bit logic determines the appropriate state of the bit, it is then supplied to the instruction as it is proceeding through the execution pipeline.

<figref idref="DRAWINGS">FIG. 8</figref> shows in greater detail the logic used in conjunction with the tracking of the dirty and DL bits. To improve performance, load/store units in one preferred embodiment return load results before having determined if those results are actually valid. If they are determined not to be valid, a “reject” signal is provided to indicate this invalid state. In this case a situation is created wherein a younger, dependent instruction may have already used the returned load result as source data before that data is determined to actually be valid.

Dependence on load (DL) bits are used within the execution units to indicate the occurrence of such a condition. The DL bits function as a shift counter that counts down the time, in microprocessor cycles, between when a load instruction returns a result from memory and when it can send a reject signal. That is the reject signal will be sent if the load data is determined invalid. In the case where the load is determined valid, then no reject signal is sent and processing is allowed to continue. The length of this time window, and accordingly the number of DL bits required is specific to the implementation of the LSU. In the case of microprocessors having multiple LSUs, a set of DL bits must be maintained for each LSU. The DL bits are set whenever an instruction receives forwarded data from another instruction in the pipeline. The number of sets of DL bits will correspond to the number of LSUs present in the microprocessor. In this manner the DL bits from a particular LSU will indicate that the validity of load data for that LSU. Once an instruction has passed the latest point, in terms of cycles after the load result is received, where it could be “rejected” the DL bits are no longer needed.

In accordance with the present invention the DL bits are set as follows: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0061">an instruction that uses the forwarded result of a load instruction as early as it is available will set the MSB of its DL bits;</li><li id="ul0004-0002" num="0062">an instruction that uses the forwarded result of a load instruction one cycle after it is available will set the second MSB of its DL bits;</li><li id="ul0004-0003" num="0063">an instruction that uses the forwarded result of a load instruction n cycles after it is available will set the nth MSB of its DL bits; and</li><li id="ul0004-0004" num="0064">an instruction that uses the forwarded result of a non-load instruction will copy that instruction's DL bits.</li></ul></li></ul>

The DL bits are then shifted every cycle. When a reject signal from an invalid load is encountered, the least significant DL bits of any dependent instruction will indicate that it depends on the rejected load. This instruction can then be marked, using the dirty bit, as having invalid source data. If the instruction receives data from a load that has already past the validation stage, then the instruction will get a dirty bit from the load at the time of the result bypass. Result data from a rejected load will be marked as dirty such that any dependent instruction that receives this data via a forwarding path will identify the data an dirty.

Returning to <figref idref="DRAWINGS">FIG. 8</figref>, the instruction flow through the various logic and latches associated with four (4) pipeline stages is shown. It should be noted that four stages are used merely as an example and any number of implementations having different stages are possible and contemplated by the scope of the present invention. In stage A a load instruction reads the data from the GPR or forwarding path and receives an indication of the status of the data (by forwarded dirty and DL bits). At this time it is unknown whether the data read from the GPR is valid or invalid. Also at stage A, logic <b>220</b> is used to copy the dirty bit associated with the instruction being executed from the output of a subsequent stage (stage B, C or D in this example). This dirty bit may have been received from latch <b>216</b> in the IDU (<figref idref="DRAWINGS">FIG. 7</figref>) and placed into latch <b>219</b> before being provided to dirty bit setting logic <b>228</b> in stage C. It should be noted that it takes a number of cycles for the dirty bit value to be supplied from the IDU to the execution units (other embodiments may not have such a delay as the dirty bit may be keep with the data in a register file, or elsewhere in the vicinity of the execution units). This is why the dirty bit is not provided until stage C. Additionally, conditions in the functional units (e.g. FXU) may cause the dirty bit to be set when the appropriate inputs are provided to logic <b>224</b> and <b>228</b>. These conditions include the LSB of the DL bits set to “1” coupled with a load reject signal, or a forwarded dirty bit from an older instructions. Referring back to stage A, the dirty bit from logic <b>220</b> is then placed in latch <b>222</b>. DL bit generation logic <b>221</b> receives the forwarded DL bits from a previous instruction and sets the bits in latch <b>223</b>.

In stage B, logic <b>224</b> receives the dirty bit from latch <b>222</b> and DL bits from latch <b>223</b> as well as a reject signal from line <b>33</b>. The least significant bit of the DL bits (variable A), from latch <b>223</b>, is then ANDed with the reject signal from line <b>33</b> (variable C). This result is then ORed with the dirty bit (variable B) to determine if the source registers associated with the instruction contain valid data. That is, the logical function (A AND C) OR B will determine whether the data is valid. As noted above, the DL bits function as a shift counter with the most significant bit originally set. The bit is then shifted until it reaches the LSB position at which time it is known whether the load data is valid. Logic <b>225</b> performs the shift counter function at stage B and right shifts the DL bits before sending them to latch <b>227</b> and forwarding the bits back to generation logic <b>221</b>. The result of the above AND/OR operation is then provided to latch <b>226</b>, as well as logic <b>220</b>.

Stage C performs the same essential functions as stage B. Latch <b>227</b> provides the DL bits to shifting logic <b>229</b> and dirty bit setting logic <b>228</b>. Logic <b>228</b> ANDs the least significant DL bit (variable A) from latch <b>227</b> with the load reject signal from line <b>233</b> (variable C). The dirty bit from latch <b>226</b> (variable B) is then ORed with the result from the AND operation between the DL bit and the load reject, and the result is provided to dirty bit latch <b>230</b> and dirty bit copy logic <b>220</b>. The resulting DL bits output from logic <b>229</b> are provided to latch <b>231</b> and also forwarded back to stage A and input to logic <b>221</b>.

This processing continues until the writeback stage D is encountered. As noted earlier, load lookahead speculative execution cannot be allowed to update the architected registers and the dirty bits from latch <b>232</b> are provided to a mechanism that bypasses the system GPRs via a forwarding path mechanism as shown in <figref idref="DRAWINGS">FIG. 8</figref>.

<figref idref="DRAWINGS">FIG. 9</figref> illustrates in more detail the logic implemented by the “set dirty bit” logic <b>224</b> and <b>228</b> of <figref idref="DRAWINGS">FIG. 8</figref>. In one preferred embodiment two load/store units (L/S <b>0</b> and L/S <b>1</b>) are present such that two (2) sets of DL bits will be provided, one for each load store unit. More particularly, the DL bits from a prior instruction are shown by reference numerals <b>300</b> and <b>301</b>. It can be seen that the LSB positions from DL fields <b>300</b> and <b>301</b> respectively are coupled to AND gates <b>306</b> and <b>307</b>, respectively. These AND gates also receive inputs indicating whether the load operations from L/S <b>0</b> and L/S <b>1</b> are rejected, i.e. the load data is invalid. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, if the DL LSB is set to “1” and the loads are rejected (set=“1”), then a “1” output is provided to OR gate <b>308</b>. This is true for both L/S <b>0</b> and L/S <b>1</b>, i.e. when the loads are rejected for either load/store unit and the load data is not valid, then a “1” is provided from AND gates <b>306</b> and <b>307</b> to OR gate <b>308</b>.

Further, a dirty bit from vector <b>119</b> corresponding to the register addresses from the instruction being executed is read and input to AND gates <b>309</b> and <b>310</b>. For example, when an instruction uses registers R_Aand R_B, the associated dirty bit from vector <b>119</b> is used as an input to AND gates <b>309</b>, <b>310</b>. It is also determined whether the registers R_Aand R_Bare read from the register file (e.g. GPR for integer operations). It should be noted that the present invention contemplates any type of register file and a GPR is used herein only for purposes of explanation. If the registers used by the instructions are read from the register file, e.g. GPR, then a “1” is input along with the corresponding dirty bit value into AND gates <b>309</b> and <b>310</b>, respectively. It can be seen that when the operand is read from the register (e.g. R_A) and the dirty bit corresponding to R_Ais set, then a logical “1” output is provided from AND gate <b>309</b> to OR gate <b>308</b>. Similarly, when R_Bis read from the GPR and its corresponding dirty bit from vector <b>119</b> in IDU <b>111</b> is set, then a logical “1” will also be provided to OR gate <b>308</b> from AND gate <b>310</b>.

The outputs from AND gates <b>306</b>, <b>307</b>, <b>309</b>, <b>310</b>, along with the dirty bit forwarded with result data, such as a source operand from any previous instruction are then ORed together and if any one of these inputs is true (e.g. set equal to “b <b>1</b>”), then the dirty bit <b>305</b> is set and forwarded to a younger instruction in the pipeline. If none of the inputs to OR gate <b>308</b> are true, then the dirty bit is not forwarded and the DL bit in fields <b>303</b> and <b>304</b> are shifted to the right, since it would not have been in the least significant bit position. In this manner, the present invention can track the status of the dirty bit for instructions proceeding through the pipeline stages of the microprocessor.

Referring to <figref idref="DRAWINGS">FIG. 10</figref>, a timing diagram is shown that tracks a series of load instructions through the microprocessor pipeline. At time zero the first load instruction L₁is in the dispatch unit. Four cycles later load L₂is in dispatch with load L₃being in dispatch at cycle five. As known in the art, these load instructions will continue through the various pipeline stages, such as decode, execute and write back. In one preferred embodiment eight (8) stages are included in the microprocessor pipeline, however other microprocessors with different numbers of pipeline stages are also contemplated by the scope of the present invention. At cycle <b>1</b> (stage D<b>1</b>) of <figref idref="DRAWINGS">FIG. 10</figref>, the load instruction reads it source data, i.e. the instruction reads its source operands during the first processor cycle. For the purpose of example and not limitation the following load instructions will be used to assist in the description of <figref idref="DRAWINGS">FIG. 10</figref>. <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0074">L₁Load R₁, R₂, R₃</li><li id="ul0005-0002" num="0075">L₂Load R₄, R₁, R₅</li><li id="ul0005-0003" num="0076">L₃Load R₆, R₁, R₇<br /> For this type of load instruction, the values in the second and third registers are manipulated (usually through an ADD instruction) to calculate the address in memory where the value to be accessed is currently stored. The first register is where the value retrieved from memory is to be placed. Using L₁as an example, the values in registers R₂, R₃are added to obtain an address which is then used to access a memory location. The value in that memory location is then retrieved and stored in register R₁. </li></ul>

Returning to <figref idref="DRAWINGS">FIG. 10</figref>, load instruction L₁proceeds through the pipeline until it reaches cycle <b>5</b> at which point the data retrieved from the local cache is available. If either R₂or R₃are dirty, then L₁will forward a dirty indication in cycle <b>5</b> to L₂with the data and in cycle <b>6</b> to L₃since the data is known to be invalid. If R₂and R₃are not dirty then it is unknown at cycle <b>5</b> whether the data is valid or invalid. Also, at cycle <b>5</b>, the DL bit shift counter is initialized for instruction L₂since it is reading in the results from L₁. In this embodiment two (2) cycles are needed to determine the validity of data in R₁, thus two (2) corresponding DL bits are needed in accordance with the embodiment of the present invention shown in <figref idref="DRAWINGS">FIG. 9</figref>. Therefore, the DL bits are set to (10) at cycle <b>6</b>. When load instruction L₁reaches stage/cycle <b>7</b>, the validity of the data is known and the DL bits of instruction L₂become (01). At this point, if the load has not been rejected the data in register R₁is known to be valid (<figref idref="DRAWINGS">FIG. 9</figref>). In the case where the data in R₁is valid, then the results of the calculation of the address for load instruction L₂are correct. However, when the data in R₁is invalid due to a cache miss, then L₁will initiate a prefetch request if its own address calculation data was valid (R₂and R₃are not dirty). Also, when R₁is invalid the output of OR gate <b>308</b> (<figref idref="DRAWINGS">FIG. 9</figref>) will be dirty, and the prefetch operation of the present invention will be blocked for instructions L₂or L₃. More particularly, when the dirty bit is set, there is no reason to continue with the prefetching of invalid data for L₂or L₃. Further, when the data is invalid, or dirty, the bit <b>305</b> (<figref idref="DRAWINGS">FIG. 9</figref>) forwarded to younger instructions in the pipeline is set indicating that the load data cannot be used. Similarly, the validity of data values retrieved by load instructions L₂and L₃will be determined at cycles <b>11</b>, <b>12</b>, respectively, so that, at this point, the data is available for use by subsequent instructions when valid, or can be reloaded if it is invalid.

Referring to <figref idref="DRAWINGS">FIG. 11</figref>, another timing diagram is shown that includes both load instructions and arithmetic/logical instructions. Again, for the purposes of explanation and not limitation, ADD instructions are used as the arithmetic instructions. In this example the instructions used for the description are: <ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0079">L₁LOAD R₁, R₂, R₃</li><li id="ul0006-0002" num="0080">A₁ADD R₂, R₁, R₄</li><li id="ul0006-0003" num="0081">A₂ADD R₅, R₁, R₆</li><li id="ul0006-0004" num="0082">L₂LOAD R₃, R₂, R₇<br /> At stage P<b>1</b> the load instruction L₁reads the values R₂, R₃from the GPRs and manipulates these values to find the address of the data to be loaded into register R₁. Add instruction A₁is dispatched two (2) cycles after load instruction L1 and it will read the result from the load instruction of cycle four (<b>4</b>), however, at this point it is unknown whether the load data is valid. It can be seen that ADD instruction A₁is dependent on load instruction L1, since the ADD uses the value from the load instruction (i.e. data that will be loaded to register R₁when writeback occurs) L1 as an operand. The data is then read from load instruction L1 at cycle four (<b>4</b>) and the DL bits for cycle five (<b>5</b>) are set to 100. It should be noted that in the implementation of <figref idref="DRAWINGS">FIG. 11</figref>, it will take three (3) cycles (as opposed to 2 cycles in the embodiment of <figref idref="DRAWINGS">FIG. 10</figref>) to determine if the load will be rejected. Therefore, three DL bit positions are required for the implementation of <figref idref="DRAWINGS">FIG. 11</figref> (100, 010, 001), while only two DL bit positions are needed for the implementation of <figref idref="DRAWINGS">FIG. 10</figref> (10, 01). Returning to the timing diagram of <figref idref="DRAWINGS">FIG. 11</figref>, at cycle five (<b>5</b>) the ADD instruction A₂will receive the data from the load instruction, if it is valid, but as previously noted it is not known at this time whether the data is valid, or invalid. When the LSB of the DL bits is not set, then the validity of the data is unknown. Next, at cycle six, (<b>6</b>) the DL bits are shifted to 010, for ADD instructions A₁and A₂. At cycle seven (<b>7</b>) the DL bits are then shifted to where the LSB is now “1”, i.e. 001, and at this time it is known whether the data is valid or not. The data was provided to both ADD instructions A₁and A₂, and used as an operand for both of these instructions. The DL bits are combined with the load reject signal (data valid) as shown in <figref idref="DRAWINGS">FIG. 9</figref> to set the dirty bit for instructions A₁and A₂. Load instruction L₂is using the value calculated by ADD instruction A₁as one of its memory address determining operands. During cycle <b>6</b>, load instruction L₂copies the DL bits from ADD instruction A₁, shifts the bit to the right and then writes “001” in cycle <b>7</b>. It can be seen from this example that the dependency existing between load instruction L₁, ADD instruction A₁and Load instruction L₂is maintained by the DL bits in accordance with the present invention. When instruction L₁is determined to be invalid during cycle <b>7</b>, the DL bits of instruction L₂, which are “001”, cause L₂to be marked as dirty. If the source data is in fact dirty, then the load operation in blocked. That is, if load L₁is invalid (load reject) L₂will not attempt to read the cache and the load data for L₂will not be prefetched because the address for the location where the data is stored was computed based upon the invalid data from load L₁. In the case where data retrieved from memory is not valid it will be reloaded during the stall condition in order to have the data in the L1 cache when the stall is resolved to aid in the operation of the microprocessor. </li></ul>

<figref idref="DRAWINGS">FIG. 12</figref> is a flow chart showing when the load lookahead prefetch mechanism of the present invention is entered and exited for a preferred embodiment in which a load cache miss is the extended stall condition for which speculative execution is initiated. At step <b>1</b> the process is started and step <b>2</b> determines if the instruction is a LOAD instruction. If not, then the process proceeds to step <b>3</b> and a determination of whether the next instruction is a LOAD occurs by looping back to step <b>2</b>. However, if at step <b>2</b> it is determined that the instruction is a LOAD, then step <b>4</b> determines whether a load reject has occurred such that a stall condition exists in the in-order microprocessor, such as a cache miss, address translation table miss, or the like. If there is no stall condition, then the process loops back to step <b>3</b> and the microprocessor continues actual (non-speculative) instruction execution. If, at step <b>4</b> it is determined that a stall condition exists, then the load lookahead prefetch method is initiated at step <b>5</b>. It is then determined by step <b>6</b> if the data to be loaded is ready and if not, step <b>7</b> will cause the dirty bit vector to be updated for any instructions passing the write back stage. More particularly, all instructions (e.g. LOAD, ADD, etc.) will write to the dirty bit vector to indicate that results were not written to the GPR. That is, there is no write back allowed to the architected registers in the lookahead mode of the present invention. At the same time, any instruction, e.g. arithmetic/logical operation, which seeks to use the data in a particular register will read the dirty bit vector to determine if the data is valid and can be used. It should be noted that all instructions will write dirty bits and read dirty bits by receiving (reading) forwarded dirty bits from older instructions, or forwarding (writing) dirty bits to younger instructions. After step <b>7</b> the process loops back to step <b>6</b> until the data to be loaded is ready. If, at step <b>6</b> the load data is ready then the load lookahead method is exited at step <b>8</b> and all dirty bits are cleared at step <b>9</b>. The load operation is then restarted at step <b>10</b> to reload the data that was initially rejected at step <b>4</b>. In this manner, the present invention will maximize the data available in the L1 cache such that the likelihood of another rejected load operation (cache miss) for the desired data is minimized.

<figref idref="DRAWINGS">FIG. 13</figref> will now describe the process steps for the load lookahead prefetch mechanism which is started at step <b>5</b> of <figref idref="DRAWINGS">FIG. 12</figref> for one preferred embodiment of the present invention. At step <b>1</b> of <figref idref="DRAWINGS">FIG. 13</figref>, the instruction is dispatched and the dirty vector is checked, in step <b>2</b>, against the registers that are being called for at the data or operand sources for the instruction. A determination as to whether the dirty bits are set (indicating invalid data) is made at step <b>3</b>. If the data is not dirty, the process continues to writeback at step <b>20</b>. However if the data is invalid, or dirty, then the dirty bits are forwarded with the instruction to the appropriate execution unit e.g. fixed point unit, floating point unit, or the like, for inclusion in the instruction (step <b>4</b>). For example, with an ADD instruction the target register (R_t) would be the register which will receive the result of the addition of the values from the source registers and the dirty bit will be forwarded to this instruction from a prior instruction that used the same target register. Subsequent to step <b>4</b>, the method proceeds to writeback (step <b>20</b>) where it is determined if instruction processing has reached the writeback stage. If so, then the target register is marked at step <b>21</b> as either valid (remains “0”) or invalid (set to “1”). If the instruction has not yet reached the writeback stage, then the process loops back to step <b>20</b> and remains until the writeback stage is reached. As noted above, the results of speculatively executed instructions cannot be written back to the microprocessor's architected registers.

Also subsequent to step <b>1</b>, it is determined at step <b>5</b> (<figref idref="DRAWINGS">FIG. 13</figref>) whether the data is forwarded from a prior instruction or read from the general purpose register. With reference to <figref idref="DRAWINGS">FIG. 10</figref>, this occurs at cycle <b>5</b> where the data is available. If the data is provided from a forwarding path, then the DL bits are set at step <b>6</b>, i.e. the DL bits are initialized to e.g. 100 (when 3 cycles are required to determine the validity of load data). At step <b>7</b> it is then determined if the source registers are dirty (a dirty bit was forwarded). If so, then the dirty bits for these instructions are set at step <b>8</b>, i.e. the dirty bits are forwarded to younger instructions. If the source registers are not dirty, then the method proceeds to step <b>11</b>. Subsequent to <b>8</b> the process also continues to step <b>11</b>.

The method of <figref idref="DRAWINGS">FIG. 13</figref> continues to step <b>9</b> if the source data is provided from the GPR, rather than being forwarded (step <b>5</b>). Step <b>9</b> determines if the instruction dispatch unit has indicated dirty data. If so, then step <b>10</b> sets the dirty bit. Subsequent to setting the dirty bit at step <b>10</b> or if the data from the IDU is not determined to be dirty at step <b>9</b>, then step <b>11</b> determines if the load reject signal has been received (indicating that the data loaded from cache is invalid). If so, then step <b>12</b> determines if the LSB of the DL bits is set and if so, the dirty bit is set (step <b>13</b>). When the LSB of the DL bits is set then the dependency between the instructions in the pipeline is known. The dirty bit can be sent when the data reject signal for a corresponding load instruction is also known. However, the process continues to step <b>14</b> when either the load reject signal has not been received (step <b>11</b>), or the lowest DL bit is not set (step <b>12</b>) or subsequent to setting the dirty bit in step <b>13</b>.

At step <b>14</b>, the process checks to see whether the instruction is a load instruction, and if so the present invention then determines, at step <b>15</b>, if the dirty bit is set. When it is determined by step <b>15</b> that the dirty bit is set, then step <b>16</b> blocks access to the cache. Subsequent to step <b>16</b> or if it is determined by step <b>14</b> that the instruction is not a load instruction or the dirty bit is not set (step <b>15</b>), the process of the present invention continues to step <b>17</b> where it is determined whether the point in time where a load reject could occur is past (e.g. cycle <b>7</b> of <figref idref="DRAWINGS">FIG. 9</figref>). If the process is past the point where validity is determined, then the DL bits are dropped, i.e. ignored, at step <b>18</b>, because there is no need to track the progress of the instruction relative to the validity of its target or source registers. Finally, if the rejection point is not past, as determined at step <b>17</b>, then the DL bits are shifted at step <b>19</b> and the process loops back to step <b>11</b> where it is determined if a load reject has been received.

Although certain preferred embodiments have been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claims.