Connection of a memory component to an electronic device via a connection bus utilizing multiple interface protocols

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application claims priority under 35 USC §119 to Finnish Patent Application No. 20035072 filed on May 22, 2003.

BACKGROUND OF THE INVENTION

0002The present invention relates to a method for connecting a memory component to an electronic device by a connection bus. The invention also relates to a system comprising an electronic device, a memory component connectable to the electronic device, and a connection bus for connecting the memory component to the electronic device. Further, the invention relates to an electronic device with a connection bus for connecting a memory component to the electronic device. Moreover, the invention relates to a connection bus to be used in an electronic device, for connecting a memory component to the electronic device.

0003In a number of electronic devices of prior art, in which e.g. a memory is used for data storage, the memory is implemented as an internal integrated memory. The electronic device is thus provided with a memory bus to which the memory is connected. The structure of the memory bus depends, inter alia, on the types of the memories connected to the memory bus. The memories to be connected to such a memory bus must thus be similar with respect to their way of connection. Consequently, the arrangement is fixed and dependent on the technology.

0004Electronic devices are known, to which it is possible to connect various peripheral devices, such as cards (interface cards, expansion cards), by which it is possible to change the facilities of the electronic device. For example, such a card can be used to provide a memory expansion for an electronic device, such as a computer, a wireless communication device, a personal digital assistant, etc. The electronic device is thus equipped with a peripheral device connection, such as a card connection, in which the peripheral device is placed. The peripheral device connection comprises a connection bus, through which data can be transferred between the electronic device and the interface card by using an interface protocol. Via the peripheral device connection, it is also possible to supply the card with the necessary operating voltages. The connection bus typically comprises a control bus, an address bus and/or a data bus. The control bus is used for the transmission of control information between the electronic device and the card. The address bus is used for the transmission of addresses to the card. The data bus, in turn, is intended for the transmission of information between the electronic device and the card. However, arrangements have been developed, in which one or several of said buses are combined at least partly. For example, some of the address data can be transmitted via the data bus. An example of such a card is the memory card complying with the MultiMediaCard™ specifications.

0005A problem in the systems of prior art is, for example, the fact that the same protocol is not necessarily used in all interface cards, wherein the electronic device should, in each case, be capable of determining the bus connection protocol supported by the interface card connected to the electronic device. For example, in bus arrangements of the NOR and NAND types, a technology-dependent protocol is used, wherein an interface card driver complying with this protocol must be implemented in the electronic device. Bus arrangements complying with different technologies cannot be mixed with each other, wherein a separate bus is required for each technology. However, a relatively massive bus connection protocol is used in implementations which are aimed at eliminating the dependency of the bus connection on the technology, that is, in which the internal implementation of the interface card is not manifested on the connection bus. This requires that a processor is used on the interface card to perform the functions required by the protocol.

SUMMARY OF THE INVENTION

0006It is an aim of the present invention to provide an improved bus connection which supports more than one interface protocol. The invention is based on the idea that the bus connection comprises means for implementing message transmission according to two or more protocols. To put it more precisely, the bus connection according to the present invention is primarily characterized in that at least a first interface protocol and a second interface protocol are available on the connection bus, wherein the memory component is recognized, the recognition is used to determine if said first interface protocol or said second interface protocol is available in the memory component, wherein the recognition is used to select one of the protocols available in the memory component, for use on the connection bus. The system according to the present invention is primarily characterized in that at least a first interface protocol and a second interface protocol are available on the connection bus, wherein the system comprises means for recognizing the memory component, determining means for using the recognition to determine the protocols available in the memory component, and selecting means for selecting one of the protocols available in the memory component to be used on the connection bus, on the basis of the recognition. The electronic device according to the present invention is primarily characterized in that at least a first interface protocol and a second interface protocol are available on the connection bus, wherein the electronic device comprises means for recognizing the memory component, determining means for using the recognition to determine the protocols available in the memory component, and selecting means for selecting one of the protocols available in the memory component to be used on the connection bus, on the basis of the recognition. The memory component according to the present invention is primarily characterized in that at least a first interface protocol and a second interface protocol are available on the connection bus, wherein the electronic device comprises means for recognizing the memory component, determining means for using the recognition to determine the protocols available in the memory component, and selecting means for selecting one of the protocols available in the memory component to be used on the connection bus, on the basis of the recognition.

0007Considerable advantages are achieved by the present invention. With the arrangement according to the invention, different internal or external memory components can be used in the same bus connection so that the technology implemented in the memory component does not need to be known by the electronic device, or so that the technology implemented in the memory component is taken into account in the electronic device, in the control of the bus and in data transmission between the electronic device and the memory component. The technology-dependent implementation has the advantage that no processor will be needed in the memory component, but a simpler control logic will be sufficient, which, inter alia, reduces the power consumption of the memory component and may also reduce the surface area required by the memory component. The technology-independent alternative, in turn, has e.g. the advantage that there is no need to implement a driver required by a given technology in the electronic device. The control of the bus and the data transmission are thus implemented by a protocol of a higher level. The invention has the significant advantage that the electronic device does not require different types of buses for different types of memory components, but the memory components of different types can be connected to the same bus. If necessary, this bus can be doubled or multiplied, wherein more memory components than one can be simultaneously connected to the bus. Also in this case, the bus connection is substantially similar.

0008Consequently, the arrangement of the invention combines the implementations of a conventional integrated technology-dependent memory system and a detachable technology-independent memory system in such a way that each implementation can be used on the same physical bus by the same method of initial recognition. This arrangement provides cost savings in the memory component when a technology-dependent driver is used. Furthermore, a technology-independent arrangement can also be used if it is not known in advance which technology is used in the detachable memory to be inserted later in the electronic device.

DESCRIPTION OF THE DRAWINGS

0009In the following, the invention will be described in more detail with reference to the appended drawings, in which

0010<figref idref="DRAWINGS">FIG. 1</figref> shows an electronic device and a memory component according to a first advantageous embodiment of the invention in a reduced block diagram;

0011<figref idref="DRAWINGS">FIGS. 2</figref><i>a </i>and <b>2</b><i>b </i>show a doubled bus connection between an electronic device and a memory component, implemented in two different ways; and

0012<figref idref="DRAWINGS">FIGS. 3</figref><i>a </i>and <b>3</b><i>b </i>illustrate signalling between an electronic device and a memory component by means of memory components of different types.

DETAILED DESCRIPTION OF THE INVENTION

0013In the following description of an advantageous embodiment of the invention, the electronic device will be exemplified with a wireless terminal <b>1</b>, but it should be evident that the invention is not limited to be used in such terminals only. Furthermore, a memory card is used as an example of the memory component. However, the invention is not limited to memory cards only. The terminal <b>1</b> comprises a processor <b>2</b>, a memory <b>3</b>, which may also comprise several different memory blocks, such as a read only memory (ROM) and a random access memory (RAM). Furthermore, a part of the memory can be a non-volatile memory, such as an EEPROM memory, in a way known as such. Also, the terminal preferably comprises a display <b>4</b>, a keypad <b>5</b>, and audio means, such as an earpiece and/or a speaker <b>6</b> and a microphone <b>7</b>. Preferably, the terminal <b>1</b> also comprises communication means, such as a transmitter <b>9</b> and a receiver <b>8</b>, for data transmission between the terminal <b>1</b> and a communication network <b>10</b>. These communication means <b>8</b>, <b>9</b> are preferably intended for wireless communication, wherein the communication network <b>10</b> comprises a wireless communication network, such as a mobile communication network, a wireless local area network, or the like. The terminal also comprises a memory component connection <b>11</b> for connecting one or more memory components <b>12</b> to the terminal <b>1</b>.

0014The memory component connection <b>11</b> preferably comprises a memory component driver <b>13</b> for controlling the functions necessary for using the memory component <b>12</b> connected to the memory component connection. Furthermore, the memory component connection is provided with a necessary connection bus, which preferably comprises a control bus <b>14</b><i>b </i>and a data bus <b>14</b><i>a</i>. The control bus <b>14</b><i>b </i>is used, for example, for the transfer of commands and responses between the memory component <b>12</b> and the terminal <b>1</b>. The data bus <b>14</b><i>a </i>is intended for data transmission between the memory component <b>12</b> and the terminal <b>1</b>. If more memory components than one can be simultaneously connected to the memory component connection <b>11</b>, the memory component connection <b>11</b> is provided with several connectors (not shown), to which the buses <b>14</b><i>a</i>, <b>14</b><i>b </i>are coupled. In addition, the bus connection may comprise an internal bus and/or an external bus, as shown in <figref idref="DRAWINGS">FIGS. 2</figref><i>a </i>and <b>2</b><i>b. </i>

0015The memory component driver <b>13</b> is not necessarily needed in all applications, wherein the processor <b>2</b> is responsible for the control of the connection bus.

0016In various applications, the memory component <b>12</b> to be connected to the terminal <b>1</b> may be very different, and the present invention is not limited to any specific memory component. Some non-restrictive examples to be mentioned of such memory components <b>12</b> include memory cards, such as a memory card complying with the specifications of a MultiMediaCard, or a memory card complying with the specifications of an SD Memory Card, communication cards, such as cards comprising mobile communication functions, etc. When various memory component types are used, the memory component connection <b>11</b> in the terminal may vary, but a person skilled in the art will be able to apply the invention in also other types of memory components and memory connections, on the basis of the following example applications. In the system according to an advantageous embodiment of the invention, shown in <figref idref="DRAWINGS">FIG. 1</figref>, the memory component is a memory card complying with the SD Memory Card specifications, and the data transfer between the memory component <b>12</b> and the memory component driver <b>13</b> of the terminal <b>1</b> is implemented in serial format according to the MultiMediaCard specifications. In this case, the control bus <b>14</b><i>b </i>and the data bus <b>14</b><i>a </i>of the memory component connection <b>11</b> are serial in format. Furthermore, the memory component connection typically comprises one or more ground lines <b>14</b><i>c </i>(Gnd) set in 0 potential, and one or more operating voltage lines <b>14</b><i>d </i>(Vcc). The control bus <b>14</b><i>b </i>preferably comprises a command line CMD, a clock line CLK, and a chip select line CS. Pull-up resistances R are preferably coupled to the lines of the data bus <b>14</b><i>a</i>, of which only one resistance is shown in <figref idref="DRAWINGS">FIG. 1</figref> for clarity.

0017<figref idref="DRAWINGS">FIG. 1</figref> also shows the internal structure of one such memory component <b>12</b> in a simplified block diagram. The memory component <b>12</b> comprises a bus connection block <b>15</b>, via which the buses <b>14</b><i>a</i>, <b>14</b><i>b </i>are connected to the memory component <b>12</b>. The memory component may also comprise a controller <b>16</b> for controlling the functions of the memory component <b>12</b>. On the other hand, the invention also makes it possible to use such memory components which do not have a separate processor, in connection with the bus connection. The operation of these different types of memory components in the bus connection will be discussed in more detail below in this description. Preferably, the memory component <b>12</b> also comprises internal registers <b>17</b> for storing some data. Since the memory component <b>12</b> used here as an example is a memory card, the memory component <b>12</b> is also provided with a memory <b>18</b> which can be a read only memory and/or a random access memory. The memory <b>18</b> may comprise one or more memory types, such as a dynamic memory (DRAM), a static memory (SRAM), or a non-volatile memory (e.g. EEPROM, Flash). The memory <b>18</b> may also be implemented wholly or partly as a magnetic and/or optic memory, of which non-restrictive examples include a fixed disk, a CD-ROM, and a digital versatile disk. Furthermore, the memory component <b>12</b> may preferably comprise a clock circuit <b>19</b> for generating clock signals required in the operation of the different functional blocks of the memory component <b>12</b> in a way known as such.

0018In the following, the operation of the method according to a preferred embodiment of the invention will be described with reference to the signalling charts of <figref idref="DRAWINGS">FIGS. 3</figref><i>a </i>and <b>3</b><i>b</i>. In this context, it is assumed that two protocols have been defined, of which the first one is a protocol of a lower level, i.e., it only comprises a limited number of commands. The second protocol is a protocol of a higher level, comprising a more versatile set of commands than the first protocol. Furthermore, it is assumed that all the memory components <b>12</b> which use the interface bus recognize, from the commands of the first protocol, at least the commands relating to initialization. On the other hand, also an initialization protocol can be used for the initialization, wherein its commands must thus be recognized by the memory components <b>12</b>. <figref idref="DRAWINGS">FIG. 3</figref><i>a </i>shows signalling in a situation in which the memory component <b>12</b> does not support the second protocol. <figref idref="DRAWINGS">FIG. 3</figref><i>b</i>, in turn, shows an example of a signalling chart between the terminal <b>1</b> and the memory component <b>12</b> when the second protocol is available in the memory component <b>12</b>.

0019In the terminal <b>1</b>, the steps <b>301</b> to initialize the bus connection are started, whereby the bus connection is started to operate with said first protocol (or initialization protocol, if one has been defined). In the protocol used for initialization, some functions are defined, by means of which commands can be sent to the memory component and responses can be received from the memory component. The initialization steps can be taken, for example, by program commands implemented in the memory component driver <b>13</b> or in the processor <b>2</b>. If necessary, the memory component <b>12</b> can also be used to take initialization steps <b>302</b> to start the operation of the memory component e.g. with respect to the bus connection. So that the communication between the memory component and the terminal would be implemented by using the correct protocol, the type or other data of the memory component <b>12</b> must first be recognized, to determine the protocol supported by the memory component <b>12</b>. The type of the memory component <b>12</b> can be recognized, for example, by setting, in the first protocol, a command which the memory component <b>12</b> must recognize, irrespective of the protocol level supported by the memory component. Thus, this command is transmitted <b>303</b> from the terminal <b>1</b> via the control bus <b>14</b><i>b </i>of the bus connection to the memory component <b>12</b>. When in working condition, the memory component <b>12</b> interprets <b>304</b> the received command and transmits <b>305</b>, either on the control bus <b>14</b><i>b </i>or on the data bus <b>14</b><i>a</i>, a response, on the basis of which the protocol supported by the memory component can be determined. However, it is possible that the memory component is recognized so that the memory component <b>12</b> sets one or more detecting lines (not shown) in a state which is detected by the processor <b>2</b> of the terminal or the memory component driver <b>13</b>, to determine the type of the memory component.

0020After the protocol supported by the memory component <b>12</b> has been determined <b>306</b>, the operation can be continued according to this protocol. If said second protocol is available in the memory component <b>12</b>, the memory component <b>12</b> thus normally has a separate controller <b>16</b> to receive and interpret the commands, to send responses and to take the steps complying with the commands in the memory component <b>12</b>, such as to store data in the memory <b>18</b> and to read data from the memory <b>18</b>. In this case, the terminal <b>1</b> does not need to have any information about the technology used in the memory component <b>12</b>, because the second protocol is substantially a technology-independent protocol. This makes it possible to use several different types of memory components <b>12</b> in connection with the terminal <b>1</b>. Moreover, the terminal <b>1</b> does not require any memory-component-specific driver software, or the like. Consequently, the connection format is one that hides the technology. Furthermore, the functions included in the second protocol may be more versatile than the functions of the first protocol.

0021In a situation in which the memory component <b>12</b> does not support the second protocol, the steps complying with the first protocol are taken after the initialization. In this case, if necessary, the terminal <b>1</b> determines the technology used in the memory component <b>12</b>, for a more detailed determination of the signalling to be used in the bus connection. In a way known as such, the technology may be, for example, NAND or NOR technology, wherein the bus protocol is adapted to comply with the function of the NAND protocol or the NOR protocol. Consequently, the connection format is dependent on the technology. On the basis of the type of the memory component <b>12</b>, a driver program corresponding to the type is downloaded <b>307</b>, for example from a memory, to the software memory (not shown) of the processor <b>2</b> or the memory component driver <b>13</b>. After this, the running of this driver program is started. The steps required for using the bus complying with the type are implemented in the driver program. In this arrangement, the memory component <b>12</b> does not need to comprise a controller of its own, but the interpretation of the commands and the processing of the functions corresponding to them can be preferably implemented as relatively simple logic functions in the memory component <b>12</b>. To start data transmission, e.g. a given special command is transmitted <b>308</b> to the memory component <b>12</b>, for example a switch command (#<b>6</b>) presented in the MMCA protocol specifications. This command sets the communication between the memory component <b>12</b> and the terminal <b>1</b> to be implemented by commands <b>309</b> complying with the memory component and/or the application. In the transmission of these commands, certain messages complying with the first protocol are used, from which the memory component <b>12</b> is capable of decrypting the transmitted command.

0022If necessary, also more memory components than one can be simultaneously connected to the bus connection according to the invention, as shown in <figref idref="DRAWINGS">FIGS. 2</figref><i>a </i>and <b>2</b><i>b</i>. Furthermore, the memory components can be of different types; that is, both the first and the second protocol can be used simultaneously on the connection bus. For the sake of clarity, <figref idref="DRAWINGS">FIGS. 2</figref><i>a </i>and <b>2</b><i>b </i>do not show all the functional blocks of the terminal <b>1</b> but primarily the blocks which are essential in illustrating the principle of doubling the bus connection.

0023In the electronic device according to an advantageous embodiment of the invention, shown in <figref idref="DRAWINGS">FIG. 2</figref><i>a</i>, the doubling is implemented by dividing the bus connection in two parts. Thus the control bus <b>14</b><i>b </i>and the data bus <b>14</b><i>a </i>are branched into two (or more) parallel buses. It is thus possible to connect one memory component <b>12</b> to each branch. In the example of <figref idref="DRAWINGS">FIG. 2</figref><i>a</i>, the control and data buses of one branch are intended for connecting external memory components <b>12</b><i>a</i>, and the control and data buses of the other branch are intended for connecting an internal memory component <b>12</b><i>b. </i>

0024In the embodiment of <figref idref="DRAWINGS">FIG. 2</figref><i>b</i>, the doubling is implemented in an application specific integrated circuit (ASIC) <b>20</b> comprising a memory component driver. In this alternative, the signals are divided to two (or more) different bus connections within the circuit. Also in this example of <figref idref="DRAWINGS">FIG. 2</figref><i>b</i>, one bus connection is intended for an external memory component <b>12</b><i>a </i>and the other bus connection for an internal memory component <b>12</b><i>b. </i>

0025In the embodiments of <figref idref="DRAWINGS">FIGS. 2</figref><i>a </i>and <b>2</b><i>b</i>, it has been explained as an example that the application specific integrated circuit <b>20</b> also comprises a processor <b>2</b> (CPU) and a memory component driver <b>13</b>. However, it will be evident that they can also be separate circuits.

0026Using the bus connection according to the invention, it is possible to provide a flexible method for using various memory components <b>12</b> in connection with a terminal <b>1</b>. For example, the internal memory component <b>12</b><i>b </i>may be a mass storage, such as a fixed disk, a FLASH memory, or the like. Thus, the driver program(s) required for controlling the mass storage with the first protocol are preferably installed in the terminal <b>1</b> at the manufacturing stage, wherein e.g. circuit board area is saved in the terminal <b>1</b>. The external memory component may also be a memory component, which can be used e.g. to load new applications into the terminal, to increase the memory capacity of the terminal <b>1</b>, etc. In spite of the different types of memories, the same bus connection can be used.

0027The driver programs required by the memory components <b>12</b> using the first protocol are preferably stored in the terminal <b>1</b> at the stage of manufacture of the terminal, wherein the memory component types to be supported are selected at the manufacturing stage. On the other hand, in some cases it is possible to update the application software of the terminal <b>1</b>, including the driver programs, later on e.g. via the communication means <b>8</b>, <b>9</b> or via the memory component connection <b>11</b>, wherein the number of memory component types to be supported can be increased.

0028In the above description of the invention, the term memory component <b>12</b>, <b>12</b><i>a</i>, <b>12</b><i>b </i>refers to such functional units which can be connected to the terminal by the connection bus <b>14</b>. However, it will be obvious that the mechanical implementation of the memory component <b>12</b>, <b>12</b><i>a</i>, <b>12</b><i>b </i>can be detachable or integrated.

0029The present invention is not limited solely to the above-presented embodiments, but it can be modified within the scope of the appended claims.