US7424397B2

General purpose performance counter

Summary by NHIP

General Purpose Performance Counter

The general purpose performance counter connects to a debug data bus and uses an AND/OR circuit to control a counter and a compare circuit. The AND/OR circuit activates an increment signal when operating in OR mode if one or more selected bits are set, or in AND mode if all selected bits are set.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

US7424397B2, drawing sheet 1 — Sheet 1 of 4

Term

Term ended

Expired 14 April 2026, 0.4 years ago.

32 claims: 3 independent, 29 dependent

1
Broadest claimClaim Score 55, average(NHIP)A general purpose performance counter (“GPPC”) connected to a bus carrying debug data, the GPPC comprising:an AND/OR circuit connected to receive an events signal that comprises the debug data;a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a current count value;and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a designated relationship to a compare value;wherein, when the AND/OR circuit is operating in OR mode, the AND/OR circuit activates the increment signal responsive to one or more selected bits of the events signal being set and when the AND/OR circuit is operating in AND mode, the AND/OR circuit activates the increment signal when all of the selected bits of the events signal are set.
15
A general purpose performance counter (“GFFC”) connected to a bus carrying debug data, the GPPC comprising:an AND/OR circuit connected to receive an events signal that comprises a match/threshold signal and the debug data;a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated while the counter circuit is enabled, causes the counter circuit to increment a count value;and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a designated relationship to a compare value, wherein when the AND/OR circuit is in AND mode, the AND/OR circuit activates the increment signal if all of one or more selected bits of the events signal are set and when the AND/OR circuit is in OR mode, the AND/OR circuit activates the increment signal if at least one of the selected bits of the events signal is set.
25
A method of implementing a general purpose performance counter (“GPPC”) connected to a bus carrying debug data, the method comprising:providing an AND/OR circuit connected to receive an events signal that comprises the debug data;providing a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count;and providing a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a designated relationship to a compare value;and in a first mode, activating the increment signal by the AND/OR circuit responsive to one or more selected bits of the events signal being set and in a second mode, activating the increment signal by the AND/OR circuit responsive to all of the one or more selected bits of the events signal being set.

Independent claims3

36 paragraphs in 5 sections, as filed

PRIORITY UNDER 35 U.S.C. §119(e) & 37 C.F.R. §1.78

This nonprovisional application claims priority based upon the following prior United States provisional patent application entitled: “General Purpose Counters for Performance, Debug and Coverage,” Application No.: 60/469,180, filed May 9, 2003, in the name(s) of Richard W. Adkisson and Tyler J. Johnson, which is hereby incorporated by reference.

This application is related to U.S. patent application Ser. No. 10/635,371, filed Aug. 6, 2003, entitled COVERAGE CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 20004/0237004; U.S. patent application Ser. No. 10/635,372 filed Aug. 6, 2003, entitled COVERAGE DECODER CIRCUIT FOR PERFORMANCE COUNTER, Now U.S. Pat. No. 7,275,191; U.S. patent application Ser. No. 10/635,103, filed Aug. 6, 2003, entitled DATA SELECTION CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 2004/0236994; U.S. patent application Ser. No. 10/635,079, filed Aug. 6, 2003, entitled ZEROING CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 20004/0236992; U.S. patent application Ser. No. 10/635,373, filed Aug. 6, 2003, entitled MATCH CIRCUIT FOR PERFORMANCE COUNTER, now U.S. Pat. No. 7,331,003; U.S. patent application Ser. No. 10/635,369, filed Aug. 6, 2003, entitled INCREMENT?DECREMENT CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 2004/0237003, all of which are hereby incorporated by reference in their entirety.

BACKGROUND

Increasing demand for computer system scalability (i.e., consistent price and performance and higher processor counts) combined with increases in performance of individual components continues to drive systems manufacturers to optimize core system architectures. One such systems manufacturer has introduced a server system that meets these demands for scalability with a family of application specific integrated circuits (“ASICs”) that provide scalability to tens or hundreds of processors, while maintaining a high degree of performance, reliability, and efficiency. The key ASIC in this system architecture is a cell controller (“CC”), which is a processor-I/O-memory interconnect and is responsible for communications and data transfers, cache coherency, and for providing an interface to other hierarchies of the memory subsystem.

In general, the CC comprises several major functional units, including one or more processor interfaces, memory units, I/O controllers, and external crossbar interfaces all interconnected via a central data path (“CDP”). Internal signals from these units are collected on a performance monitor bus (“PMB”). One or more specialized performance counters, or performance monitors, are connected to the PMB and are useful in collecting data from the PMB for use in debugging and assessing the performance of the system of which the CC is a part. Currently, each of the performance counters is capable of collecting data from only one preselected portion of the PMB, such that the combination of all of the performance counters together can collect all of the data on the PMB. While this arrangement is useful in some situations, there are many situations in which it would be advantageous for more than one of the performance counters to access data from the same portion of the PMB. Additionally, it would be advantageous to be able to use the performance counters in the area of determining test coverage. These applications are not supported by the state-of-the-art performance counters.

SUMMARY

In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC comprises an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating general purpose data collection in a logic design;

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a general purpose performance counter according to one embodiment;

<figref idref="DRAWINGS">FIG. 3</figref> is a more detailed block diagram of the general purpose performance counter of <figref idref="DRAWINGS">FIG. 2</figref>; and

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a method in which signals are mapped from an observabilty bus to a performance counter in accordance with one embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale.

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of general purpose data collection in a logic design. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the state space 100 of a logic design under consideration is driven to data collection and selection logic 102. The logic 102 drives a D-bit data collection, or observability, bus 104 carrying a D-bit debug_bus signal to a plurality of performance counters 106(1)-106(M). Details of one embodiment of the logic 102 and bus 104 are provided in U.S. patent application Ser. No. 10/402,092; filed Mar. 28, 2003, entitled A BUS INTERFACE MODULE; and U.S. patent application Ser. No. 10/402,034; filed Mar. 28, 2003, entitled AN INTEGRATED CIRCUIT, each of which is hereby incorporated by reference in its entirety.

In one embodiment, D is equal to 80, M is equal to 12, and performance counters 106(1)-106(M-1) are general purpose performance counters, while the remaining performance counter 106(M) increments on every clock cycle. As will be illustrated below, the general purpose performance counters are “general purpose” in that each of them is capable of accessing any bit of the 80-bits on the bus 104; moreover, all of them may access the same block of bits and do the same or different performance calculations thereon.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a general purpose performance counter 200, which is identical in all respects to each of the performance counters 106(1)-106(M-1) (<figref idref="DRAWINGS">FIG. 1</figref>), in accordance with one embodiment. As will be described in greater detail below, the performance counter 200 can be used to perform general purpose operations to extract performance, debug, or coverage information with respect to any system under test (SUT) such as, for instance, the system state space 100 shown in <figref idref="DRAWINGS">FIG. 1</figref>. The performance counter 200 includes an AND/OR circuit 201, a match/threshold circuit 202, an sm_sel circuit 204, an szero circuit 206, and a counter circuit 208.

In general, the AND/OR circuit 201 enables access to all of the bits of the debug_bus signal coming into the performance counter 200 via the observability bus 104. In one embodiment, as illustrated in <figref idref="DRAWINGS">FIGS. 2 and 3</figref>, debug_bus is an 80-bit signal. When the AND/OR circuit 201 is operating in AND mode, the circuit activates an “inc” signal to the counter circuit 208 if all of the bits of the debug_bus signal plus two bits that are appended thereto, as will be described in greater detail below, that are of interest (as indicated by the value of an 80-bit “mask” plus two bits that are appended thereto) are set. When the AND/OR circuit 201 is operating in OR mode, the circuit activates the inc signal to the counter circuit 208 if any one or more of the bits of the debug_bus signal plus the two additional bits that are of interest (as indicated by the value the mask plus the two additional bits) are set.

When the match/threshold circuit 202 is operating in “match” mode, a match portion 300 (<figref idref="DRAWINGS">FIG. 3</figref>) of the circuit activates a match_thresh_event signal to the AND/OR circuit 201 when an N-bit portion of the debug_bus signal selected as described in greater detail below with reference to the sm_sel circuit 204 and the szero circuit 206 matches an N-bit threshold for all bits selected by a match mask (“mmask”). In particular, for all bits of the selected N-bit debug bus signal portion that are “don't cares”, the corresponding bit of mmask will be set to 0; conversely, for all bits of the selected N-bit debug bus signal portion that are not “don't cares”, the corresponding bit of mmask will be set to 1. The match_thresh_event signal is one of the two bits appended to the debug_bus signal. In the illustrated embodiment, N is equal to 16.

When the match/threshold circuit 202 is operating in “threshold” mode, a threshold portion 302 (<figref idref="DRAWINGS">FIG. 3</figref>) of the circuit 202 activates the match_thresh_event signal to the AND/OR circuit 201 when an S-bit portion of the debug_bus signal selected and zeroed as described in greater detail below with reference to the sm_sel circuit 204 and the szero circuit 206 is equal to or greater than the threshold. In the illustrated embodiment, S is equal to N/2, or 8.

Additional details regarding operation of the match/threshold circuit 202 are provided in U.S. patent application Ser. No. 10/635,373, filed Aug. 6, 2003, entitled MATCH CIRCUIT FOR PERFORMANCE COUNTER, now U.S. Pat. No. 7,331,003.

The sm_sel circuit 204 selects an N-bit portion of the debug_bus signal aligned on a selected 10-bit block boundary into both the match portion 300 and the threshold portion 302 (<figref idref="DRAWINGS">FIG. 3</figref>) of the match/threshold circuit 202 and to a sum input of the counter circuit 208. As previously stated, in the illustrated embodiment, N is equal to 16. The szero circuit 206 zeroes out none or all but one of S bits aligned on a selected 10-bit block boundary into the threshold portion 302 of the match/threshold circuit 202 and the sum input of the counter circuit 208. In the illustrated embodiment, S is equal to eight. The selected 10-bit block boundary is identified by the value of a three-bit control signal sm_sel input to the sm_sel circuit 204.

Additional details regarding the operation of the sm_sel circuit 204 and the szero circuit 206 are provided in U.S. patent application Ser. No. 10/635,103, filed Aug. 6, 2003, entitled DATA SELECTION CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 2004/0236994 and U.S. patent application Ser. No. 10/635,079, filed Aug. 6, 2003, entitled ZEROING CIRCUIT FOR PERFORMANCE COUNTER, U.S. Pub. No. 2004/0236992.

In one embodiment, each general purpose performance counter, such as the performance counter 200, is 48 bits plus overflow. The performance counter 200 is general purpose in that it looks at all D bits of the debug_bus signal for an event mask plus two extra events, eight separate selections of 16 bits for the match compare operation and eight separate selections of eight bits for the threshold compare and the accumulate operations. The eight bits for the threshold compare and the accumulate operations are the bottom eight bits of the 16 bits selected for the match compare operation. Those 16 bits are aligned to 10 slot boundaries as shown in an exemplary mapping arrangement illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

In <figref idref="DRAWINGS">FIG. 4</figref>, an events signal 400 comprises the debug_bus signal, designated in <figref idref="DRAWINGS">FIG. 4</figref> by reference numeral 401, the match_threshold_event signal, designated by reference numeral 402 and a logic 1 bit, designated by reference numeral 404. The debug_bus signal 401 comprises bits [79:0] of the events signal 400; the match_threshold_event signal 402 comprises bit [80] of the events signal, and the logic 1 bit 404 comprises bit [81] of the events signal.

As best illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, the events signal 400 (i.e., the debug_bus signal with the match_threshold_event signal and the logic 1 appended thereto) are input to a first logic stage 304 of the AND/OR circuit 201 for purposes that will be described in greater detail below.

Referring again to <figref idref="DRAWINGS">FIG. 4</figref>, a composite mask signal 410 comprises an 80-bit mask signal, designated by a reference numeral 412, a match_threshold_event mask (“TM”) bit, designated by reference numeral 414, and an accumulate bit (“acc”), designated by reference numeral 416. The mask signal 412 comprises bits [79:0] of the composite mask signal 410; the TM bit 414 comprises bit [80] of the composite mask signal, and the acc bit 416 comprises bit [81] of the composite mask signal. As best illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, each bit of the composite mask 410 (i.e., the mask signal with the TM and acc bits appended thereto) is input to the first logic stage 304 of the AND/OR circuit 201 for purposes that will be described in greater detail below.

Continuing to refer to <figref idref="DRAWINGS">FIG. 4</figref>, eight 10-bit-block-aligned 16-bit match selections are respectively designated by reference numerals 420(0)-420(7). In particular, the selection 420(0) comprises bits [0:15]; the selection 420(1) comprises bits [10:25]; the selection 420(2) comprises bits [20:35]; the selection 420(3) comprises bits [30:45]; the selection 420(4) comprises bits [40:55]; the selection 420(5) comprises bits [50:65]; the selection 420(6) comprises bits [60:75]; and the selection 420(7) comprises bits [70:5] (bits above 79 wrap back to zero.

Referring again to <figref idref="DRAWINGS">FIG. 3</figref>, the first logic stage 304 comprises an AND portion, represented by an AND gate 304a, for bit-wise ANDing the events signal 400 with the composite mask signal 410, and an OR portion, represented by an OR gate 304b, for bit-wise ORing the inverse of the composite mask signal 410 with the events signal 400. It will be recognized that, although represented in <figref idref="DRAWINGS">FIG. 3</figref> as a single two-input AND gate 304a, the AND portion of the first logic stage 304 actually comprises 82 two-input AND gates. Similarly, the OR portion of the first logic stage 304 comprises 82 two-input OR gates identical to the OR gate 304b.

The outputs of the AND portion of the first logic stage 304 are input to an 82-input OR gate 306, the output of which is input to one input of a two-input MUX 308 as an “or_result”. Similarly, the outputs of the OR portion of the first logic stage 304 are input to an 82-input AND gate 310, the output of which is input to the other input of the MUX 308 as an “and_result”. A control signal (“and/or#”) from a control status register (CSR) (not shown) controls whether the AND/OR circuit 201 functions in AND mode, in which case the and_result is output from the MUX 308 as the inc signal, or in OR mode, in which case the or_result is output from the MUX as the inc signal.

As a result, when the AND/OR circuit 201 is operating in the AND mode, the inc signal comprises the and_result signal and will be activated when all of the bits of the events signal 400 that are of interest as specified by the composite mask 410 are set. When the AND/OR circuit 201 is operating in OR mode, the inc signal comprises the or_result signal and will be activated when any one of the bits of the events signal 400 that are of interest as specified by the composite mask 410 is set.

The acc bit 416 of the composite mask 410 is CSR-settable. Setting the TM bit 414 in the composite mask 410 designates the match_thresh_event signal in the events signal as a bit of interest; not setting the TM bit in the composite mask will cause the value of the match_thresh_event signal in the events signal 400, and hence the result of any match or threshold operation performed by the match/threshold circuit 202, to be ignored.

Continuing to refer to <figref idref="DRAWINGS">FIG. 3</figref>, the operation of an embodiment of the counter circuit 208 will be described in greater detail. The counter circuit 208 is an X bit counter that can hold, increment by one, add S bits, clear, or load a value into a count value register 312. Other processing may also occur in order to read the value of the register 312. In the embodiment illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, X is equal to 48. Counter circuit 208 operation is enabled by setting a counter enable signal B, which comprises one input of a two-input AND gate 314. The other input of the AND gate 314 is connected to receive the inc signal from the AND/OR circuit 201. Accordingly, when the counter circuit 208 is enabled and the inc signal is activated, a logic one is output from the AND gate 314. In any other case, the output of the AND gate 314 will be a logic zero. The output of the AND gate 314 is replicated by an 8× replicator 316 and the resulting 8-bit signal is bit-wise ANDed with an 8-bit signal output from a MUX circuit 318. The inputs to the MUX circuit 318 are the sum[7:0] signal output from the szero circuit 206 and an 8-bit signal the value of which is [00000001]. The sum[7:0] signal will be output from the MUX circuit 318 when the acc signal is activated; otherwise, the [00000001] signal will be output from the MUX circuit.

An AND circuit, represented by an AND gate 320, bit-wise ANDs the signals output from the replicator 316 and from the MUX circuit 318. The resulting 8-bit signal is input to a register 322. An adder 324 adds the 8-bit signal stored in the register 322 to the 48-bit sum stored in the count value register 312. The new sum output from the adder 324 is input to a MUX circuit 326. Two other sets of inputs to the MUX circuit 326 are connected to a logic zero and a csr_write_value, respectively. When a csr_write enable signal to the MUX circuit 326 is activated, the value of csr_write_value is output from the MUX circuit 326 and written to the count value register 312. In this manner, a value can be loaded into the count value register 312. Similarly, when the clear_counter signal is asserted, 48 zero bits are output from the MUX circuit 326 to the count value register 312, thereby clearing the register.

If neither the csr_write signal nor the clear_counter signal is asserted and the acc signal is asserted, the output of the adder 324 is written to the count value register 312, thereby effectively adding S bits (i.e., the value of the sum[7:0] signal) to the previous value of the count value register 312. Not enabling the counter circuit 208 results in the count value register 312 being held at its current value. Finally, to increment the value of the count value register 312 by one, the counter circuit 208 must be enabled, the inc signal must be asserted, and the acc signal must not be asserted.

As described in detail above, <figref idref="DRAWINGS">FIG. 4</figref> illustrates that the entire data collection bus 104 (<figref idref="DRAWINGS">FIG. 1</figref>) is available for all of the performance counters, each being represented by the performance counter 200, making them general purpose. All D bits of the debug_bus signal can be used by the AND/OR circuit 201. N bits aligned on block boundaries can be selected by the sm_sel circuit 206, enabling full coverage of the observabilty bus 104.

As previously mentioned, prior art performance counter designs were not general purpose, in that they have limited range and are designed solely for performance calculations and debug of a system design. The embodiments described herein are general purpose, in that the AND/OR circuit can perform calculations on the entire range of the data collection bus 104. The embodiments also incorporate the concept of coverage. In particular, by observing specific states in a logic design, the designer can determine how much of the state space thereof is being covered by the test vectors of a test suite. The designer can thereby gauge whether more tests need to be run and what needs to be added to fully test the entire design.

An implementation of the invention described herein thus provides a general purpose performance counter. The embodiments shown and described have been characterized as being illustrative only; it should therefore be readily understood that various changes and modifications could be made therein without departing from the scope of the present invention as set forth in the following claims. For example, while the embodiments are described with reference to an ASIC, it will be appreciated that the embodiments may be implemented in other types of ICs, such as custom chipsets, Field Programmable Gate Arrays (“FPGAs”), programmable logic devices (“PLDs”), generic array logic (“GAL”) modules, and the like. Furthermore, while the embodiments shown are implemented using CSRs, it will be appreciated that control signals may also be applied in a variety of other manners, including, for example, directly or may be applied via scan registers or Model Specific Registers (“MSRs”). Additionally, although specific bit field sizes have been illustrated with reference to the embodiments described, e.g., 16-bit threshold for patten matching (where the bottom 8 bits are used for the threshold), 80-bit mask signal, 3-bit sm_sel, et cetera, various other implementations can also be had.

Accordingly, all such modifications, extensions, variations, amendments, additions, deletions, combinations, and the like are deemed to be within the ambit of the present invention whose scope is defined solely by the claims set forth hereinbelow.

Contents5

Every citation, both waysCites: the store holds 19 of 20

Citations
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29 members in 7 offices

This recordMember, by publication datePriority claim

Priority claims6

Priority claims
Document	Office	Kind	Date
46918003	United States of America	P	2003-05-09
46918003	United States of America	P	2003-05-09
63508303	United States of America	A	2003-08-06
60469180	–	–	–
US20030469180P	–	–	–
US20030635083	–	–	–

Members29

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Document	Office	Kind
GB0409007D0	United Kingdom	D0	2004-05-26
ITRM20040391A1	Italy	A1	2004-11-03
GB2401447A	United Kingdom	A	2004-11-10
US2004225930A1	United States of America	A1	2004-11-11
US2004236992A1	United States of America	A1	2004-11-25
US2004236993A1	United States of America	A1	2004-11-25
US2004236994A1	United States of America	A1	2004-11-25
US2004236995A1	United States of America	A1	2004-11-25
US2004236996A1	United States of America	A1	2004-11-25
US2004237003A1	United States of America	A1	2004-11-25
US2004237004A1	United States of America	A1	2004-11-25
TW200428206A	Taiwan Province of China	A	2004-12-16
DE102004003867A1	Germany	A1	2004-12-30
US2005039084A1	United States of America	A1	2005-02-17
ES2231042A1	Spain	A1	2005-05-01
TWI241480B	Taiwan Province of China	B	2005-10-11
GB2401447B	United Kingdom	B	2006-01-04
SG121075A1	Singapore	A1	2006-04-26
DE102004003867B4	Germany	B4	2006-05-24
ES2231042B2	Spain	B2	2006-08-16
US7275191B2	United States of America	B2	2007-09-25
US7331003B2	United States of America	B2	2008-02-12
US7404112B2	United States of America	B2	2008-07-22
US7415643B2	United States of America	B2	2008-08-19
US7424397B2This record	United States of America	B2	2008-09-09
US7430696B2	United States of America	B2	2008-09-30
US7432742B2	United States of America	B2	2008-10-07
US7475301B2	United States of America	B2	2009-01-06
US7475302B2	United States of America	B2	2009-01-06

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2007-10-09	Response after Non-Final ActionA...	A...
2007-10-09	Request for Extension of Time - GrantedXT/G	XT/G
2007-06-27	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2007-06-25	Non-Final RejectionNon-final rejectionCTNF	CTNF
2007-06-06	Case Docketed to Examiner in GAUDOCK	DOCK
2007-06-01	Case Docketed to Examiner in GAUDOCK	DOCK
2007-05-14	Transfer Inquiry to GAUTI1050	TI1050
2007-04-16	Transfer Inquiry to GAUTI1050	TI1050
2007-03-06	Transfer Inquiry to GAUTI1050	TI1050
2007-02-05	Transfer Inquiry to GAUTI1050	TI1050
2007-01-18	Case Docketed to Examiner in GAUDOCK	DOCK
2007-01-16	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2007-01-16	Case Docketed to Examiner in GAUDOCK	DOCK
2005-11-10	Miscellaneous Incoming LetterLET.	LET.
2005-02-22	Information Disclosure Statement consideredIDSC	IDSC
2005-02-22	Information Disclosure Statement (IDS) FiledM844	M844
2005-02-22	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2004-12-06	Information Disclosure Statement consideredIDSC	IDSC
2004-12-06	Reference capture on IDSRCAP	RCAP
2004-12-06	Information Disclosure Statement (IDS) FiledM844	M844
2004-12-06	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2004-10-07	Correspondence Address ChangeC.ADB	C.ADB
2003-11-03	Application Is Now CompleteCOMP	COMP
2003-11-03	Pre-Exam Office Action WithdrawnW/OA	W/OA
2003-11-03	Application Is Now CompleteCOMP	COMP
2003-11-01	Application Return from OIPEWROIPE	WROIPE
2003-11-01	Application Return TO OIPEROIPE	ROIPE
2003-11-01	Application Dispatched from OIPEOIPE	OIPE
2003-10-24	Cleared by OIPE CSRL194	L194
2003-09-21	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2003-08-06	Information Disclosure Statement consideredIDSC	IDSC
2003-08-06	Reference capture on IDSRCAP	RCAP
2003-08-06	Information Disclosure Statement (IDS) FiledM844	M844
2003-08-06	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2003-08-06	Initial Exam Team nnIEXX	IEXX

9 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2016-11-01	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2016-10-10	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2016-10-07	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2016-09-09	Lapse for failure to pay maintenance feesLapsedLAPS	LAPS
2016-04-22	Maintenance fee reminder mailedREMI	REMI
2015-11-09	AssignmentAS	AS
2011-09-23	Fee paymentFPAY	FPAY
2008-12-23	Certificate of correctionCC	CC
2003-09-30	AssignmentAS	AS

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Summary by NHIP

Claim Score by NHIP

Abstract