Current sensing bi-directional switch and plasma display driver circuit
Summary by NHIP
Bi-directional switch with current sensor
The bi-directional switch includes two semiconductor devices in series with a current sensor, controlled by a driver circuit. The driver turns both devices off when sensor current drops to near zero or when a control input changes state.
Claim Score by NHIP
Abstract
A bi-directional switch comprising first and second semiconductor switching devices, a current sensor connected in series with the switching devices, thereby forming a series circuit, a driver circuit controlling the on/off operation of the first and second switching devices such that the first and second switching devices are substantially simultaneously turned on and off, the driver circuit turning the first and second switching devices on in response to a control input and turning the first and second switching devices off when current in the current sensor substantially drops to near a zero current. A discharge sustain driver circuit employing the bi-directional switches for a plasma display panel (PDP) is also described.

Term
Term ended
Expired 2 May 2026, 0.4 years ago.
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8 claims: 2 independent, 6 dependent
- 1A bi-directional switch comprising:first and second semiconductor switching devices;a current sensor connected in series with the switching devices, thereby forming a series circuit;a driver circuit controlling the on/off operation of the first and second switching devices such that the first and second switching devices are substantially simultaneously turned on and off, the driver circuit turning the first and second switching devices on in response to a control input and turning the first and second switching devices off when current in the current sensor substantially drops to near a zero current.
- 5Broadest claimClaim Score 81, broad(NHIP)A bi-directional switch comprising:at least one semiconductor switching device;a current sensor connected in series with the switching device, thereby forming a series circuit;a driver circuit controlling the on/off operation of the at least one switching device the driver circuit turning the switching device on in response to a control input and turning the switching device off when current in the current sensor substantially drops to near a zero current.
Independent claims2
39 paragraphs in 5 sections, as filed
CROSS REFERENCE TO RELATED APPLICATION
0001The present application claim the benefit and priority of U.S. Provisional Patent application Ser. No. 60/475,180 filed May 30, 2003 entitled “CURRENT SENSING BI-DIRECTIONAL SWITCH FOR PDP APPLICATIONS”, the entire disclosure of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
0002The present invention relates to switching circuits, and more particularly, to a current sensing bi-directional switching circuit and even more particularly, to a current sensing bi-directional switching circuit for plasma display applications. The present invention relates to a current sensing bi-directional switch and a sustain driver circuit for plasma display devices using the bidirectional switch.
0003Plasma display devices are gaining popularity because they are flat screen display devices. Currently, plasma display panel (PDP) devices are used for many display applications including television monitors and receivers and computer monitors. In a plasma display device of the AC type, an AC voltage, typically of approximately 180 volts, is provided to the display device. When the display device discharges it can only do so for a limited period of time. In order to sustain the discharge, an AC signal can be provided to the PDP device to sustain the discharge. A PDP device is essentially capacitive, so it is necessary to quickly provide the alternating current voltage to the PDP to sustain the discharge. Accordingly, the PDP must be charged and discharged repeatedly with the AC signal which reverses the voltage across the PDP at a periodic rate.
0004Currently, typical PDP sustain drivers utilize at least two capacitors to store a charge developed across the PDP from the B plus voltage and a number of transistor switches and diodes as well as at least two inductors to periodically reverse the charge across the PDP.
0005Typically, such PDP sustain drivers incorporate a full bridge driver, two inductors and two additional switching circuits connected to charge storage capacitors to store the charge and allow it to be reversed.
0006With reference to <figref idref="DRAWINGS">FIG. 1</figref>, a typical prior art PDP sustain driver is shown. The PDP device, being primarily capacitive, is indicated by the capacitor Cp. The capacitor Cp is connected to the outputs of a full bridge driver <b>10</b> comprising transistors Q<b>3</b>, Q<b>4</b>, Q<b>7</b> and Q<b>8</b>. The full bridge driver is connected between the B plus source, typically 170 to 180 volts DC and ground. The full bridge driver outputs, which are connected across the PDP device indicated by Cp, are also connected through inductors L<b>1</b> and L<b>2</b> to respective charge storage circuits <b>12</b> and <b>14</b>. Once charge storage circuit <b>12</b> comprises transistors Q<b>1</b> and Q<b>2</b>, diodes D<b>1</b> and D<b>2</b> and the charge storage capacitor C<b>1</b>. The other charge storage circuit <b>14</b> comprises transistors Q<b>5</b> and Q<b>6</b>, diodes D<b>3</b> and D<b>4</b> and the charge storage capacitor C<b>2</b>. In addition, diodes D<b>5</b>, D<b>6</b>, D<b>7</b> and D<b>8</b> are also needed. The circuit shown in <figref idref="DRAWINGS">FIG. 1</figref> thus comprises eight transistors, eight diodes, two inductors and two charge storage capacitors.
0007In the circuit of <figref idref="DRAWINGS">FIG. 1</figref>, the AC plasma display panel (ACPDP) employs the full bridge driver <b>10</b> to alternately impose a positive and a negative voltage on the panel (Cp) and sustain the image for a predetermined length of time. Since the PDP is a capacitive load, high peak currents are forced to flow in the switches comprising the full bridge, which can results in excessive losses, thereby reducing system efficiency. To reduce such losses and peak currents, the PDP sustain circuit as shown in <figref idref="DRAWINGS">FIG. 1</figref> uses charge storage and recovery circuitry to reduce the peak currents.
0008With reference to <figref idref="DRAWINGS">FIG. 1</figref>, the cycle operates as follows: Initially, the panel Cp is charged in the positive direction as shown in <figref idref="DRAWINGS">FIG. 1</figref> from the bus voltage source. Transistors Q<b>2</b> an Q<b>8</b> are initially turned on. The charge from Cp is transferred to capacitor C<b>1</b> through inductor L<b>1</b>, diode D<b>2</b>, transistor Q<b>2</b> and transistor Q<b>8</b>. Q<b>2</b> and Q<b>8</b> are then turned off. Q<b>5</b> and Q<b>4</b> are then turned on. With these transistors turned on the PDP indicated by Cp will now charge in the reverse direction from the charge stored on capacitor C<b>2</b> via transistor Q<b>5</b>, diode D<b>3</b> inductor L<b>2</b> and transistor Q<b>4</b>. Cp is now charged in the reverse direction and Q<b>5</b> is turned off. Transistor Q<b>7</b> is then turned on and capacitor Cp is charged to the full bus voltage through transistor Q<b>7</b> as well as transistor Q<b>4</b> which is still turned on. Q<b>7</b> is then turned off after a predetermined time and the PDP Cp is now fully charged in the reverse direction. Transistor Q<b>6</b> is then turned on while transistor Q<b>4</b> is still on. The charge on Cp is transferred to capacitor C<b>2</b> via L<b>2</b>, D<b>4</b>, Q<b>6</b> and Q<b>4</b>.
0009Transistors Q<b>1</b> and Q<b>8</b> are then turned on. The charge present on C<b>1</b> is then transferred to Cp thereby again charging the panel in the opposite direction. The charge on capacitor C<b>1</b> is transferred to Cp via transistor Q<b>1</b>, diode D<b>1</b>, inductor L<b>1</b> and transistor Q<b>8</b>. At this point transistor Q<b>4</b> is off. Transistor Q<b>1</b> is now turned off and Q<b>3</b> is turned on while Q<b>8</b> remains on, thereby fully charging the plasma display panel capacitance to the full bus voltage in the initial direction. Q<b>3</b> is then turned off after a predetermined time and the cycle repeats again so that Q<b>2</b> and Q<b>8</b> are turned on transferring the charge to capacitor C<b>1</b> as previously described.
0010Components Q<b>1</b>, Q<b>2</b>, D<b>1</b> and D<b>2</b> serve as the bidirectional switch which transfers charge from Cp to C<b>1</b> and back to Cp. Similarly, components Q<b>5</b>, Q<b>6</b>, D<b>3</b> and D<b>4</b> serve to transfer the charge between Cp and C<b>2</b>. These transistors are driven by half bridge drivers for example IR-2110 or IR-2113 half bridge drivers. The inductors L<b>1</b> and L<b>2</b> are required to ensure that most of the charge is transferred. In the absence of these inductors, only half of the charge will be transferred in either direction. Transferring most of the charge is highly desirable since a low voltage differential between Cp and the bus voltage will results in lower peak currents flowing through the full bridge switches, reducing losses. The timing for the transfer is also critical. It has to be a sufficient length such that the current in the inductor is near zero, as this ensures that maximum charge is transferred in either direction. <figref idref="DRAWINGS">FIGS. 2 and 3</figref> show a simulation of major components in the prior art bidirectional switch. As apparent, the voltage across C<b>1</b> is at its maximum i.e., most of the charge has been transferred, when the voltage across Cp is minimum and the current in the inductor L<b>1</b> is zero. Component and timing variations will inevitably cause a residual current to be present in the inductor at the end of the transfer period. The diodes D<b>5</b>, D<b>6</b>, D<b>7</b> and D<b>8</b> are included to dissipate this residual current but generate additional losses.
0011The circuit shown in <figref idref="DRAWINGS">FIG. 1</figref> is complex and requires a significant number of components, as described, eight transistors, eight diodes, two storage capacitors and two inductors. The circuit is complex, expensive and suffers from unnecessary switching losses as a result of the large number of components.
0012It is desirable to provide a simpler, less expensive circuit that uses fewer components and suffers from fewer losses.
0013It is also desirable to provide an improved bi-directional switch which can be used in a PDP sustain driver circuit as well as in other applications.
SUMMARY OF THE INVENTION
0014It is an object of the present invention to provide an improved bi-directional switch and, in particular, a current sensing bi-directional switch.
0015It is yet still a further object of the present invention to provide an improved sustain driver for plasma display devices.
0016The above and other objects of the present invention are achieved by a bi-directional switch comprising: first and second semiconductor switching devices, a current sensor connected in series with the switching devices, thereby forming a series circuit, a driver circuit controlling the on/off operation of the first and second switching devices such that the first and second switching devices are substantially simultaneously turned on and off, the driver circuit turning the first and second switching devices on in response to a control input and turning the first and second switching devices off when current in the current sensor substantially drops to near a zero current.
0017The objects of the present invention are also achieved by a bi-directional switch comprising: at least one semiconductor switching device, a current sensor connected in series with the switching device, thereby forming a series circuit, a driver circuit controlling the on/off operation of the at least one switching device the driver circuit turning the switching device on in response to a control input and turning the switching device off when current in the current sensor substantially drops to near a zero current.
0018Further, the objects of the invention are also achieved by a discharge sustain driver circuit for a plasma display device, the driver circuit comprising: a first transistor switching circuit for switching a DC bus voltage across the plasma display device, a storage capacitance, at least one inductor; and first and second bi-directional switching circuits coupled in series and being coupled to the first switching circuit to transfer charge from the plasma display device through the at least one inductor to the storage capacitance, and back to the plasma display device; and a controller for the bi-directional switching circuits to control the bi-directional switching circuits so as to receive the charge on the storage capacitance and return the charge in an opposite charge direction to the plasma display device.
0019The objects of the invention are also achieved wherein the bi-directional switching circuits each include a current sensor and each turn off when current through the switching circuit is approximately zero.
0020The objects of the invention are furthermore achieved by a method of operating a discharge sustain driver circuit for a plasma display device, the driver circuit comprising a first transistor switching circuit for switching a DC bus voltage across the plasma display device, a storage capacitance, at least one inductor; and first and second bi-directional switching circuits coupled in series and being coupled to the first switching circuit to transfer charge from the plasma display device through the at least one inductance to the storage capacitor, and back to the plasma display device, and a controller for the bi-directional switching circuits to control the bi-directional switching circuits so as to receive the charge on the storage capacitance and return the charge in an opposite charge direction to the plasma display device; and wherein the first switching comprises a full bridge switching circuit, the full bridge switching circuit comprising first and second series connected transistors connected across the DC bus and third and fourth series connected transistors connected across the DC bus; wherein the first and third transistors are high side connected and the second and fourth are low side connected; the plasma display device being connected across a common connection of the first and second transistors and a common connection of the third and fourth transistors, and wherein the first and second bi-directional switches are coupled in series together, and wherein the storage capacitance and the at least one inductor are coupled in a series circuit across the second bi-directional switch, the method comprising: turning on the first and fourth transistors to substantially charge the display device to the bus voltage; turning off the first and fourth transistors when the display device has changed to substantially the bus voltage; turning on the first bi-directional switch to transfer the charge on the display device to the storage capacitance; turning off the first bi-directional switch when the current through the switch is substantially zero; turning on the second bi-directional switch to reverse the charge across the storage capacitance; turning off the second bi-directional switch when the current therethrough is substantially zero; turning on the first bi-directional switch to transfer the reverse charge on the storage capacitance to the display device; turning on the second and third transistors to fully charge the display device to substantially the bus voltage in the reverse direction; turning off the second and third transistors when the display device has charged to substantially the bus voltage; turning on the first bi-directional switch to transfer the reverse charge on the display device to the storage capacitance; turning off the first bi-directional switch when the current through the switch is substantially zero; turning on the second bidirectional switch to again reverse the charge across the storage capacitance; turning off the second bi-directional switch when the current therethrough is substantially zero; turning on the first bi-directional switch to transfer the charge on the storage capacitance to the display device; and repeating the above steps as long as desired to sustain a discharge in the display device.
0021Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWING(S)
0022The invention will now be described in greater detail in the following detailed description with reference to the drawings in which:
0023<figref idref="DRAWINGS">FIG. 1</figref> shows a prior art PDP sustain driver circuit;
0024<figref idref="DRAWINGS">FIG. 2</figref> shows a circuit used in simulating charge transfer from the PDP to a charge storage capacitor for the circuit of <figref idref="DRAWINGS">FIG. 1</figref>;
0025<figref idref="DRAWINGS">FIG. 3</figref> shows simulation results of transferring the charge from the PDP to the storage capacitor including the voltage across the storage capacitor, the voltage across the PDP Cp, current in the inductor L<b>1</b> and starting pulse;
0026<figref idref="DRAWINGS">FIG. 4A</figref> shows the current sensing bi-directional switch according to the present invention;
0027<figref idref="DRAWINGS">FIG. 4B</figref> shows waveforms for the circuit of <figref idref="DRAWINGS">FIG. 4A</figref>;
0028<figref idref="DRAWINGS">FIG. 5</figref> shows block diagram for the bi-directional switch driver for the circuit of <figref idref="DRAWINGS">FIG. 4A</figref>;
0029<figref idref="DRAWINGS">FIG. 6</figref> shows a PDP sustain circuit of the present invention using the bi-directional switches of the present invention; and
0030<figref idref="DRAWINGS">FIG. 7</figref> shows a variation of the circuit of <figref idref="DRAWINGS">FIG. 6</figref> using only one inductor.
DETAILED DESCRIPTION OF THE INVENTION
0031With reference again to the drawings, <figref idref="DRAWINGS">FIG. 4A</figref> shows the current sensing bi-directional switch according to the present invention. In the embodiment shown, the bi-directional switch <b>20</b> employs two common source, N channel MISFITS <b>22</b> and a driver IC <b>30</b>. Both N channel FETs are turned on and off simultaneously so the gates are commonly connected to the driver <b>30</b> output HO. The switch is activated externally through an ON pulse on the controller IN terminal. A series resistor RS of approximately 10 milli ohms is used to sense the current in the switch. The switch is turned off automatically when the current approaches zero, indicating a complete transfer of charge from one input/output (<b>110</b>) to the other. The block diagram for the switch controller is shown in <figref idref="DRAWINGS">FIG. 5</figref>. <figref idref="DRAWINGS">FIG. 4B</figref> shows waveforms at the input IN, at the current sense input CS and at the output HO with respect to VS, the source voltage. The terminals of the controller <b>30</b> include VCC which is the input logic supply voltage, IN which is the logic input for the high side gate driver, COM which is the low side logic supply return, CHG which is a bootstrap capacitor charging input, VB which is the high side floating supply, HO which is the high side output, CS which is the high side current sense input and VS which is the high side floating supply return.
0032With reference to <figref idref="DRAWINGS">FIG. 5</figref>, the controller block diagram utilizes mostly conventional circuitry including MISFITS, Schmidtt triggers, pulse generators, dv/dt filters, an RS latch, level shifters, comparators and amplifiers, and will not be described in detail herein. When an input is received as shown in <figref idref="DRAWINGS">FIG. 4A</figref> on the input IN, the output HO will go high after a delay td (on). An exemplary wave form is shown in <figref idref="DRAWINGS">FIG. 4B</figref> for the current sense input CS, which is proportional to the current in resistor RS. When the current sense returns to zero, after a delay td(off), the output HO goes low turning off the MISFITS <b>22</b>. The output HO automatically shuts down at the next current zero crossing through the sense resistor in series with the MISFITS. The output HO can also be turned off by a logic zero at the IN terminal. This is shown in <figref idref="DRAWINGS">FIG. 4B</figref> at <b>25</b>. With an input IN is received which goes to zero before the current sense input goes to zero, the HO output will go to zero as shown at <b>27</b>. Otherwise, the output HO will go to zero at the next current zero crossing, as shown in <figref idref="DRAWINGS">FIG. 4B</figref> at <b>29</b>.
0033Turning again to <figref idref="DRAWINGS">FIG. 4A</figref>, since the current can flow in both directions in the switch, a level shift function circuit <b>35</b> is employed in the current sensing circuitry as shown in <figref idref="DRAWINGS">FIG. 5</figref> to assist in detecting the zero crossing in both directions. This arrangement of the bidirectional switches in results in that the diodes D<b>1</b>, D<b>2</b>, D<b>3</b> and D<b>4</b> in series with the MOSFETs Q<b>1</b>, Q<b>2</b>, Q<b>3</b> and Q<b>4</b> in the circuit of <figref idref="DRAWINGS">FIG. 1</figref> are not necessary. In addition, diodes D<b>5</b>, D<b>6</b>, D<b>7</b> and D<b>8</b> are also not necessary since the residual current in the inductors L<b>1</b> and L<b>2</b> are low under all component/input pulse width variations. The only requirement is that the input pulse width be wider than that required to fully transfer the charge. Thus, the input pulse IN should be longer than the pulse width at the input CS, the zero crossing of which indicates when the charge has been fully transferred. See <figref idref="DRAWINGS">FIG. 4B</figref>, and in particular, see that IN from <b>31</b> to <b>33</b> is longer in time than pulse CS. Further, increased system efficiency is provided by the circuit of <figref idref="DRAWINGS">FIG. 4A</figref> due to the complete transfer of charge from the panel to the storage capacitor and back.
0034<figref idref="DRAWINGS">FIG. 6</figref> shows a PDP sustain driver circuit utilizing the bi-directional switches according to the present invention. As shown, the sustain driver circuit employs a full bridge comprising transistors Q<b>1</b>, Q<b>2</b>, Q<b>3</b> and Q<b>4</b> and a single storage capacitor Cs, along with two bi-directional switches identified as BDS<b>1</b> and BDS<b>2</b> together with inductors L<b>1</b> and L<b>2</b>. The circuit eliminates the diodes D<b>1</b>-D<b>8</b> as well as one of the storage capacitors. In another embodiment described with reference to <figref idref="DRAWINGS">FIG. 7</figref>, only a single inductor is necessary.
0035With reference to <figref idref="DRAWINGS">FIG. 6</figref>, the operation of the circuit is as follows: initially, transistors Q<b>3</b> and Q<b>4</b> are turned on. This causes the display Cp panel to charge up through transistors Q<b>3</b> and Q<b>4</b> to the full bus voltage. Q<b>3</b> and Q<b>4</b> are then turned off. Bi-directional switch BDS<b>1</b> is then turned on and charge is transferred from the display Cp to the storage capacitor Cs via BDS<b>1</b> and inductor L<b>1</b>. BDS<b>1</b> turns off automatically in accordance with <figref idref="DRAWINGS">FIG. 4B</figref> at the current zero crossing when the charge transferred to Cs is complete. BDS<b>2</b> is then turned on and the charge in Cs flows through BDS<b>2</b> into inductor L<b>2</b>. When the current in L<b>2</b> and thus in BDS<b>2</b> is zero, the charge cross the resonant circuit comprising Cs and L<b>2</b> is reversed and BDS<b>2</b> goes off. BDS<b>1</b> is then turned on and the oppositely charged capacitor Cs now transfers its charge through BDS<b>1</b> and L<b>1</b> to Cp which is connected directly across the series circuit comprising BDS<b>1</b>, Cs and L<b>1</b>. Q<b>1</b> and Q<b>2</b> are then turned on and the reverse voltage across Cp further charges Cp to the full bus voltage. Q<b>1</b> and Q<b>2</b> are then turned off and BDS<b>1</b> and BDS<b>2</b> are again used to transfer the charge stored in Cp to Cs and reverse it. Hence, the oppositely charged voltage on Cp is transferred to Cs by turning on BDS<b>1</b> which goes off once the charge has been fully transferred. BDS<b>2</b> is then turned on to again reverse the charge on Cs. BDS<b>2</b> goes off once the charge has been reversed and the charge is now provided across Cp again in the opposite direction. Then the cycle repeats, that is, Q<b>3</b> and Q<b>4</b> are turned on to charge Cp fully to the full bus voltage and the switches BDS<b>1</b> and BDS<b>2</b> are used to transfer the charge and reverse it.
0036The circuit according to <figref idref="DRAWINGS">FIG. 6</figref> uses nine less components (the diodes D<b>1</b> to D<b>8</b> of <figref idref="DRAWINGS">FIG. 1</figref> and one of the storage capacitors are eliminated than the original circuit of <figref idref="DRAWINGS">FIG. 1</figref>.) Furthermore, the switch losses are reduced since efficient charge transfer between Cp and Cs reduces current in the full bridge.
0037<figref idref="DRAWINGS">FIG. 7</figref> describes an alternative circuit using only a single inductor L<b>1</b>. Similarly to the circuit of <figref idref="DRAWINGS">FIG. 6</figref>, Q<b>3</b> and Q<b>4</b> first charge Cp to the full bus voltage, and are then turned off. BDS<b>1</b> is then turned on to charge Cs. When the charge on Cp is transferred to Cs, BDS<b>1</b> turns off. BDS<b>2</b> is then turned on and the charge on Cs is reversed through L<b>1</b> and then BDS<b>2</b> turns off. BDS<b>1</b> is then turned on and the charge is transferred from the reversely charged Cs to Cp, thereby charging Cp oppositely. Q<b>1</b> and Q<b>2</b> are then turned on to fully charge Cp to the full bus voltage in the reverse direction. Then Q<b>1</b> and Q<b>2</b> are turned off and BDS<b>1</b> is turned on to charge Cs. Once Cs has been fully charged in the opposite direction, BDS<b>1</b> turns off and BDS<b>2</b> is turned on, thus reversing the charge again across Cs. BDS<b>2</b> then turns off and BDS<b>1</b> is turned on to charge Cp again in the original direction and the cycle repeats.
0038There has thus been described a current sensing bi-directional switch and an efficient sustain driver circuit for a plasma display device.
0039Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention should be limited not by the specific disclosure -herein, but only by the appended claims.
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| Application Return TO OIPEROIPE | ROIPE | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Additional Application Filing FeesADDFLFEE | ADDFLFEE | |
| Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW | CORRDRW | |
| Corrected PaperCPAP | CPAP | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Initial Exam Team nnIEXX | IEXX |
8 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS | LAPS | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS |
Numbers
- Publication
- 07403200
- Publication, DOCDB
- 7403200
- Publication, EPODOC
- US7403200
- Application
- 10853980
- Application, DOCDB
- 85398004
- Application, EPODOC
- US20040853980
Titles
- English
- Current sensing bi-directional switch and plasma display driver circuit
Patent term adjustment
- A delay
- +708 daysthe office missed an examination deadline
- Applicant delay
- −1 day
- Net adjustment
- 707 days
Classification
- CPC, 2
- G09G3/2965
- G09G3/296
- IPC, 4
- G09G5 00
- G09G3 28
- G05F1 00
- G09G3 288
- USPC, 9
- 345211000
- 323277000
- 323282000
- 327108000
- 327387000
- 345060000
- 345061000
- 345068000
- 345069000