Amplification circuit and control method of amplification circuit

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-098582 filed on Mar. 30, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

0002The present invention relates to an amplification circuit using a minute signal as an input for connecting a lowpass filter and a control method thereof.

0003As an example of an amplification circuit for amplifying minute signals, an amplification circuit, which connects to a sensor outputting detection signals in response to changes in physical value, is given. As for the sensor, a pressure sensor, an acceleration sensor, an angular velocity (gyro) sensor and the like are given.

0004In the signals inputted to the amplification circuit, noises such as 1/f noise are included along with the detection signals outputted from the sensor. Due to the influence of these noises, in the output of the amplification circuit, an error is generated with respect to the amplification output of the original detection signal. Therefore, in order to inhibit such noises, generally, a lowpass filter is connected to the amplification circuit. However, when the lowpass filter is connected, the response performance of the input/output decreases in the amplification circuit.

0005On the other hand, in the amplification circuit, in some cases, an amplification characteristic generated due to changes in temperature, power supply voltage or changes due to lapse of time are compensated.

0006An amplification circuit disclosed in Japanese unexamined patent publication No. H11 (1999)-88071 includes an offset voltage variable device for changing the offset voltage of the operational amplifier, a comparator means for comparing the output voltage of the operational amplifier with a predetermined reference voltage, and a control means that outputs an offset voltage control value and, based on the result of the comparator means, stores a control value in which output voltage of the operational amplifier and the reference voltage agree with each other. As disclosed in Japanese unexamined patent publication No. H11 (1999)-88071, the amplification circuit repeats amplification operation while changing the value of DAC as an offset voltage variable means; thus, the control value of the offset voltage is detected to carry out the compensation.

SUMMARY OF THE INVENTION

0007However, in the case where the above technique is applied to an amplification circuit connected with a lowpass filter as its object, amplification operation with poor response performance is repeated. As a result, the time required for the compensation increases resulting in a considerable problem.

0008Also, in the amplification circuit connected with a lowpass filter, there occurs another problem such that pre-charge time of the lowpass filter at turning on the power supply increases.

0009The present invention has been proposed to solve at least one of the above problems of the background art. An object of the present invention is to provide an amplification circuit connected with a lowpass filter, which reduces the time required for compensating the amplification characteristic and for starting up at turning on the power supply, and a control method thereof.

0010In order to achieve the above object, according to a first aspect, there is provided an amplification circuit, which operates in either one of operation modes of an ordinary operation mode for performing ordinary amplification operation and a special operation mode, comprising an amplifying section that amplifies an input signal and generates an output signal, a lowpass filter connected to the amplifying section for cutting off a frequency band at the side higher than a cut-off frequency to inhibit error in the output signal due to noises, and a lowpass filter setting section that sets the cut-off frequency, wherein the cut-off frequency is, in the case of the ordinary operation mode, set to an ordinary cut-off frequency in which error in the output signal does not exceed an output allowable error as an allowable error, and in the case of the special operation mode, set to the side higher than the ordinary cut-off frequency.

0011Also, according to the first aspect, there is provided a control method of an amplification circuit, which operates in either one of operation modes of an ordinary operation mode for performing ordinary amplification operation and a special operation mode, comprising the steps of amplifying an input signal and generating an output signal, cutting off a frequency band at the side higher than a cut-off frequency using a lowpass filter, thereby to inhibit error in the output signal due to noises, and setting the cut-off frequency, wherein the cut-off frequency is, in the case of the ordinary operation mode, set to an ordinary cut-off frequency in which error in the output signal does not exceed an output allowable error as an allowable error, and in the case of the special operation mode, set to the side higher than the ordinary cut-off frequency.

0012In the amplification circuit according to the present invention, the lowpass filter is connected to the amplifying section to cut off the frequency band at the side higher than the cut-off frequency; thereby an error in output signals due to noises is inhibited. In addition, the lowpass filter has such characteristics; i.e., the lower the cut-off frequency is, the larger the effect to inhibit the error in the output signals due to noises is obtained, while the worse the response performance at inputting/outputting is. In the present invention, focusing attention on the above fact, when operating in a special operation mode having a large output allowable error, the cut-off frequency is set to the side higher than the ordinary cut-off frequency. Accordingly, in this case, since the response performance of the lowpass filter is increased, the process in the special operation mode can be carried out swiftly.

0013The lowpass filter may be a passive filter well known in the art, which is configured of a resistance element and a capacitive element, or an active filter well known in the art, in which an operational amplifier is employed.

0014The special operation mode may include any modes which operate other than ordinary operation. For example, in particular, an amplification characteristic compensation mode in which the amplification characteristic of the amplifying section is detected and compensated, or lowpass filter initialization mode, in which the lowpass filter is pre-charged at turning on the power supply, are given.

0015In the amplification characteristic compensation mode, when detecting an amplification characteristic, the allowable error in the output may be smaller than the output allowable error in the ordinary operation mode. In such a case, by setting the cut-off frequency to the side higher than the ordinary cut-off frequency, the response performance of the lowpass filter can be increased to perform the process swiftly.

0016In the lowpass filter initialization mode, since only the capacitive element constituting the lowpass filter is pre-charged, the output signal is not referred to. Therefore, irrespective of the output allowable error, the cut-off frequency can be set to the side higher than the ordinary cut-off frequency.

0017The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating the principle of the present invention;

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a circuit of an embodiment of the invention;

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of a circuit showing a concrete example of an amplifying section;

<figref idref="DRAWINGS">FIG. 4</figref> is a circuit diagram showing a concrete example of a resistance value adjusting section;

<figref idref="DRAWINGS">FIG. 5</figref> is a circuit diagram showing a concrete example of the resistance value adjusting section;

<figref idref="DRAWINGS">FIG. 6</figref> is a circuit diagram showing a concrete example of a minute voltage generating section;

<figref idref="DRAWINGS">FIG. 7</figref> is a circuit diagram showing a concrete example of a window comparator;

<figref idref="DRAWINGS">FIG. 8</figref> is a waveform diagram showing the operation of an amplification characteristic compensation mode;

<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram showing a modification of a compensation storage section;

<figref idref="DRAWINGS">FIG. 10</figref> is a waveform diagram showing the operation of a failure detection mode; and

<figref idref="DRAWINGS">FIG. 11</figref> is a waveform diagram showing the operation of a lowpass filter initialization mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0029Embodiments of an amplification circuit and a control method of the amplification circuit in accordance with the present invention will be described in detail with reference to <figref idref="DRAWINGS">FIGS. 1 to 11</figref>.

0030<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating the principle of an amplification circuit <b>1</b> in accordance with the present invention. The amplification circuit <b>1</b> operates in any one of ordinary operation mode MDN for performing a predetermined amplification operation and special operation mode MDT.

0031The amplification circuit <b>1</b> includes an amplifying section <b>2</b> for amplifying input signals VI, a lowpass filter <b>3</b> connected to the amplifying section <b>2</b> for cutting off a frequency band at the side higher than a cut-off frequency fc, and a lowpass filter setting section <b>4</b> for switching the cut-off frequency fc of the lowpass filter <b>3</b> in accordance with the operation mode MD.

0032When an input signal VI is inputted to the amplifying section <b>2</b>, an amplified amplification signal VZ is outputted to the lowpass filter <b>3</b>. Further, with respect to the amplification signal VZ, the lowpass filter <b>3</b> cuts off the frequency band at the side higher than the cut-off frequency fc to remove noises, which are included in the amplification signal VZ causing an error in output signals VO.

0033It is understood that a large part of noises, which causes an error in the output signal VO, is the 1/f noise. The 1/f noise has such a characteristic that the lower frequency side generates the larger output level. That is, in the lowpass filter <b>3</b>, when the cut-off frequency fc is set to the lower level, the larger effect to remove the 1/f noise is obtained. Contrary to this, the input/output response performance decreases.

0034The cut-off frequency fc is set in accordance with the operation mode MD in the lowpass filter setting section <b>4</b>. In the case of the ordinary operation mode MDN for performing ordinary amplification operation, the cut-off frequency fc is set to an ordinary cut-off frequency fcn not exceeding an output allowable error EA in which an error EO in the output signal VO is allowable.

0035On the other hand, in the case of the special operation mode MDT, the cut-off frequency fc is set to the side higher than that of the ordinary operation mode MDN. In the lowpass filter <b>3</b>, the higher cut-off frequency fc requires the shorter response time for inputting/outputting. Accordingly, in this case, the input/output response time of the lowpass filter <b>3</b> can be reduced shorter than that in the case of the ordinary operation mode MDN; and accordingly, the input/output response time in the amplification circuit <b>1</b> can be reduced.

First Embodiment

0036Next, <figref idref="DRAWINGS">FIG. 2</figref> shows an amplification circuit <b>10</b> based on the principle diagram in <figref idref="DRAWINGS">FIG. 1</figref>.

0037The amplification circuit <b>10</b> is equipped with an amplifying section <b>20</b> that performs differential amplification of a pair of differential input signals V<b>1</b> and V<b>2</b>, a lowpass filter <b>30</b> connected to the amplifying section <b>20</b>, which cuts off a frequency band of the side higher than the cut-off frequency fc, and a lowpass filter setting section <b>40</b> that sets the cut-off frequency fc of the lowpass filter <b>30</b>.

0038The lowpass filter <b>30</b> includes two resistance elements RL<b>1</b> and RL<b>2</b> connected to each other in parallel and a capacitive element CL. The amplification signal VZ inputted to one end of the resistance element RL<b>1</b> is outputted to the output signal VO via the resistance elements RL<b>1</b> and RL<b>2</b>. Also, one end of the capacitive element CL is connected to the output signal VO side of the resistance element RL<b>2</b>, and the other end thereof is connected to the ground. Accordingly, the lowpass filter <b>30</b> performs charge and discharge of the capacitive element CL via the resistance elements RL<b>1</b> and RL<b>2</b>; thus, the lowpass filter <b>30</b> functions as a lowpass filter. The cut-off frequency fc of the lowpass filter <b>30</b> depends on a time constant, which is determined by the resistance elements RL<b>1</b> and RL<b>2</b> and the capacitive element CL.

0039The lowpass filter setting section <b>40</b> comprises two switches SW<b>1</b> and SW<b>2</b> connected to the both ends of each of the resistance elements RL<b>1</b> and RL<b>2</b> of the lowpass filter <b>30</b>. ON/OFF operation of the switches SW<b>1</b> and SW<b>2</b> is controlled, respectively, by the control signal CRL<b>1</b> and CRL<b>2</b> from a controlling section <b>80</b>. For example, when the control signal CRL<b>1</b> is set to the high level, the switch SW<b>1</b> turns ON; contrarily, when the control signal CRL<b>1</b> is set to the low level, the switch SW<b>1</b> turns OFF. Likewise, this control is carried out on the control signal CRL<b>2</b> and the switch SW<b>2</b>. By setting these control signals CRL<b>1</b> and CRL<b>2</b>, the cut-off frequency fc of the lowpass filter <b>30</b> can be changed. For example, when the control signal CRL<b>1</b> is set to the high level (switch SW<b>1</b>=ON) and the control signal CRL<b>2</b> is set to the low level (switch SW<b>2</b>=OFF), the resistance value of the time constant in the lowpass filter <b>30</b> is the resistance value of the resistance element RL<b>2</b> only. Therefore, since the resistance value is small, in accordance with this, the cut-off frequency fc of the lowpass filter <b>30</b> changes to the higher band side.

0040When the control signal CRL<b>1</b> is low level and the CRL<b>2</b> is low level, the cut-off frequency fc of the lowpass filter <b>30</b> is set to the ordinary cut-off frequency fcn. When the control signal CRL<b>1</b> is high level and CRL<b>2</b> is low level, the cut-off frequency fc of the lowpass filter <b>30</b> is set to a first cut-off frequency fc<b>1</b>. And when the control signal CRL<b>1</b> is low level and CRL<b>2</b> is high level, the cut-off frequency fc of the lowpass filter <b>30</b> is set to a second cut-off frequency fc<b>2</b>. When both of the control signal CRL<b>1</b> and the control signal CRL<b>2</b> are set to high level, a state in which the resistance elements are short-circuited is obtained and the response time is the shortest.

0041Next, <figref idref="DRAWINGS">FIG. 3</figref> shows a concrete example of the amplifying section <b>20</b>.

0042The example is a differential amplification circuit of which a sensor comprises a Wheatstone bridge, which amplifies the differential voltage of the bridge as the sensor output. The amplifying section <b>20</b> includes three operational amplifiers OP<b>1</b> to OP<b>3</b>, which are well known in the art, resistance adjusting sections <b>21</b> and <b>22</b> that carry out the gain compensation of the operational amplifiers OP<b>1</b> and OP<b>2</b>, a minute voltage generation section <b>23</b> that carries out offset compensation of the operational amplifier OP<b>3</b>, and resistance elements R<b>2</b> and R<b>3</b>.

0043In the above, the minute voltage generation section <b>23</b> is configured using the same circuit as that of a reference signal generating section <b>60</b> (refer to <figref idref="DRAWINGS">FIG. 6</figref>), which will be described later.

0044The operational amplifiers OP<b>1</b> and OP<b>2</b> constitute a negative feedback differential amplification circuit along with negative feedback resistances including the resistance adjusting sections <b>21</b> and <b>22</b>, each of which changes at the same resistance value, and the resistance element R<b>2</b>. When the differential input signals V<b>1</b> and V<b>2</b> are inputted, a voltage expressed with the following formula is outputted to the amplification signal VZ. <br />Gain <i>G</i>=(<i>RX/R</i>2*2)+1, output signal <i>VO=VOF</i>+(<i>V</i>1<i>−V</i>2)*<i>G</i>

0045Accordingly, by adjusting the resistance value RX in the resistance adjusting sections <b>21</b> and <b>22</b>, the gain G can be set; and by compensating the offset voltage VOF in the minute voltage generation section <b>23</b>, the offset of the amplification signal VZ can be set appropriately.

0046The resistance adjusting sections <b>21</b> and <b>22</b> are circuits of which the resistance value can be variably set using a gain compensation value CZ<b>1</b>. In particular, the resistance adjusting sections <b>21</b> and <b>22</b> are configured using a circuit shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0047The circuit is equipped with n-steps of resistance elements RX<b>1</b> to RXn, which are connected to each other in series, and switches SWX<b>1</b> to SWXn. Each of the switches SWX<b>1</b> to SWXn short-circuits the both ends of each of the resistance elements RX<b>1</b> to RXn. ON/OFF operation of the switches SWX<b>1</b> to SWXn is controlled by the gain compensation value CZ<b>1</b>. When a switch is controlled to turn ON, the resistance value between the both ends of the corresponding resistance element results in 0. The (resultant) resistance value RX between the terminals RA and RB is the integrated value of the resistance values between the both ends of the respective resistance elements RX<b>1</b> to RXn. Accordingly, the resistance value RX between the terminals RA and RB changes in accordance with the combination of the ON/OFF control of the gain compensation value CZ<b>1</b>. That is, the resistance value RX between the terminals RA and RB can be variably set using the gain compensation value CZ<b>1</b>.

0048Or, a circuit shown in <figref idref="DRAWINGS">FIG. 5</figref> may be employed for the resistance adjusting sections <b>21</b> and <b>22</b>. The circuit is configured as described below. That is, plural sets of resistance elements RX<b>1</b> to RXn and switches SWX<b>1</b> to SWXn are connected to each other in parallel; and each of the sets is configured of a pair of a resistance element and a switch being connected to each other in series. Also, ON/OFF operation of the switches SWX<b>1</b> to SWXn is controlled with the gain compensation value CZ<b>1</b>. When a switch is controlled to turn OFF, an infinite large resistance value is obtained between the both ends of a set of the corresponding resistance element and switch. The (resultant) resistance value RX between the terminals RA and RB results in a parallel resistance value obtained by plural sets of the resistance element and switch, which are connected to each other in parallel. Accordingly, the resistance value RX can be changed in accordance with the combination of the ON/OFF control of the gain compensation value CZ<b>1</b>. That is, same as the circuit shown in <figref idref="DRAWINGS">FIG. 4</figref>, the resistance value RX between the terminals RA and RB can be variably set using the gain compensation value CZ<b>1</b>.

0049Referring to <figref idref="DRAWINGS">FIG. 2</figref> again, the amplification circuit <b>10</b> is equipped with a window comparator <b>51</b>, which decides whether the output signal VO is within a target voltage allowable error range VMW, which is set with the upper limit voltage value VC<b>1</b> and the lower limit voltage value VC<b>2</b>, and a target voltage generating section <b>52</b>, which generates the upper limit voltage value VC<b>1</b> and the lower limit voltage value VC<b>2</b>.

0050<figref idref="DRAWINGS">FIG. 7</figref> shows a particular circuit of the window comparator <b>51</b>. The window comparator <b>51</b> is equipped with two operational amplifiers <b>51</b>A and <b>51</b>B, a NOR gate <b>51</b>C and an AND gate <b>51</b>D. The operational amplifier <b>51</b>A compares the output signal VO and the upper limit voltage value VC<b>1</b>, and when the output signal VO< the upper limit voltage value VC<b>1</b>, outputs the low level. Also, the operational amplifier <b>51</b>B compares the output signal VO and the lower limit voltage value VC<b>2</b>, and when the output signal VO> the lower limit voltage value VC<b>2</b>, outputs the low level. Also, the NOR gate <b>51</b>C which inputs the outputs of the operational amplifiers <b>51</b>A and <b>51</b>B, and when the both inputs are the low level, outputs the high level. The AND gate <b>51</b>D which inputs the outputs of the NOR gate <b>51</b>C and the comparison instruction signal COMPT, when the both inputs are the high level, outputs the high level. Accordingly, when the upper limit voltage value VC<b>1</b>> the output signal VO> the lower limit voltage value VC<b>2</b>, and when the comparison instruction signal COMPT is the high level, a comparison result comparison signal COMPO results in the high level.

0051Next, <figref idref="DRAWINGS">FIG. 6</figref> shows a particular circuit of the target voltage generating section <b>52</b>. Between the power supply voltage Vd and the ground GND, resistance elements RY<b>1</b> to RYn−1 having n−1 steps are connected to each other in series, and from each of the connection nodes, intermediate taps TY<b>1</b> to TYn are extended. Further, to each of the intermediate taps, one end of a pair of switches is connected, and to the other end of the respective switches, buffers BUFA and BUFB are connected. For example, to an intermediate tap TY<b>1</b>, one end of the switches SWY<b>1</b>A and SWY<b>1</b>B is connected. Furthermore, to the other end of the switch SWY<b>1</b>A, the buffer BUFA is connected, and to the other end of the switch SWY<b>1</b>B, the buffer BUFB is connected.

0052Further, as for the switches SWY<b>1</b>A to SWYnA, among the switches SWY<b>1</b>A to SWYnA, only one switch is controlled to turn ON, and the rest thereof are controlled to turn OFF. Being controlled as described above, the potential of the intermediate tap, which is connected to the switch controlled to turn ON, is outputted as the reference potential VA via the buffer BUFA. For example, when the switch SWY<b>3</b>A is controlled to turn ON, the potential of the intermediate tap TY<b>3</b> is outputted as the reference potential VA.

0053On the other hand, since the switches SWY<b>1</b>B to SWYnB are also controlled in the same manner, the potential thereof is outputted as the reference potential VB of the intermediate tap connected to the switch controlled to turn ON.

0054Referring to <figref idref="DRAWINGS">FIG. 2</figref> again, the amplification circuit <b>10</b> is equipped with the reference signal generating section <b>60</b> that generates a pair of differential reference signals VE<b>1</b> and VE<b>2</b>, and an input selecting section <b>70</b> comprises two input selectors well known in the art. The reference signal generating section <b>60</b> is configured of the same circuit as that of the target voltage generating section <b>52</b> (refer to <figref idref="DRAWINGS">FIG. 7</figref>). Also, the input selecting section <b>70</b> selects either one of the pair of differential input signals VI<b>1</b> and VI<b>2</b> and the pair of differential reference signals VE<b>1</b> and VE<b>2</b> depending on a select signal generated in accordance with the operation mode MD, and outputs the signals.

0055The amplification circuit <b>10</b> is further equipped with a controlling section <b>80</b>. The controlling section <b>80</b> is equipped with a sequencer <b>81</b> well known in the art, which performs computing, comparison and sequence processing based on a program, a first timer <b>82</b>, which performs timer operation at intervals of first standby time TW<b>1</b>, a second timer <b>83</b>, which performs timer operation at intervals of second standby time TW<b>2</b>, and a compensation value storage <b>85</b> including a clocking section <b>86</b> and a nonvolatile memory <b>87</b>.

0056In accordance with the processing, the sequencer <b>81</b> outputs the gain compensation value CZ<b>1</b>, an offset compensation signal CZ<b>2</b>, control signals CRL<b>1</b> and CRL<b>2</b>, a reference signal control signal CE<b>1</b>, a select signal CI, a target voltage control signal CE<b>2</b> and the comparison instruction signal COMPT.

0057Next, the operation of the amplification circuit <b>10</b> in accordance with the first embodiment will be described.

0058The amplification circuit <b>10</b> operates in the following modes; i.e., ordinary operation mode MDN in which a predetermined amplification operation is carried out; amplification characteristic compensation mode MDH in which the amplification characteristic of the amplifying section <b>20</b> is compensated; failure detection mode MDF in which failures of the amplification circuit <b>10</b> are simply detected; and lowpass filter initialization mode MDL in which, at turning on the power supply, the capacitive element CL in the lowpass filter <b>30</b> is pre-charged. The state of the respective sections in each operation mode will be described below.

0059When the amplification circuit <b>10</b> operates in the ordinary operation mode MDN, the differential input signals VI<b>1</b> and VI<b>2</b> are selectively inputted to the differential input signals V<b>1</b> and V<b>2</b>. In the lowpass filter setting section <b>40</b>, both of the switches SW<b>1</b> and SW<b>2</b> are controlled to turn OFF. Accordingly, in the lowpass filter <b>30</b>, an ordinary cut-off frequency fcn depending on the time constant RL<b>1</b>+RL<b>2</b> and CL is set. As described above, the error EO in the output signal VO of lowpass filter <b>30</b>, in which the ordinary cut-off frequency fcn is set, is inhibited within an output allowable error EA.

0060On the other hand, when the amplification circuit <b>10</b> operates in the amplification characteristic compensation mode MDH, differential reference signals VE<b>1</b> and VE<b>2</b> are inputted to the differential input signals V<b>1</b> and V<b>2</b>. Also, in the lowpass filter setting section <b>40</b>, the controlling section <b>80</b> controls so that either one of the switches SWI or SW<b>2</b> turns OFF. Accordingly, in the lowpass filter <b>30</b>, the cut-off frequency fc<b>1</b> or fc<b>2</b>, which depends on the time constants RL<b>1</b> and CL or RL<b>2</b> and CL, is set. Since the resistance value is smaller than that in the case of the ordinary operation mode MDN, these cut-off frequencies fc<b>2</b> and fc<b>3</b> are at the side higher than the ordinary cut-off frequency fcn. Also, the response time of input/output in the lowpass filter <b>30</b> is reduced. In addition, a target voltage VM with respect to the differential reference signals VE<b>1</b> and VE<b>2</b> is derived based on the relationship with the amplification characteristic, and the target voltage control signal CE<b>2</b> corresponding to the target voltage is outputted from the sequencer <b>81</b>. The target voltage generating section <b>52</b> outputs the upper limit voltage value VC<b>1</b> and the lower limit voltage value VC<b>2</b> corresponding to the target voltage control signal CE<b>2</b> to the window comparator <b>51</b>.

0061In this embodiment, the differential reference signals VE<b>1</b> and VE<b>2</b> serve as the reference signals; and the sequencer <b>81</b>, the window comparator <b>51</b> and the target voltage generating section <b>52</b> serve as the controlling section.

0062Next, a description will be given as to a concrete example in which, in the amplification characteristic compensation mode MDH, the offset voltage VOF is compensated in the amplifying section <b>20</b>.

0063In the case where a characteristic fluctuation is generated in the amplifying section <b>20</b> caused by the changes in temperature and/or power supply voltage or caused by changes due to lapse of time, when the differential input signals V<b>1</b> and V<b>2</b> are inputted, a differential voltage VOFF is generated between the uniquely decided target voltage VM and the actually outputted voltage of the output signal VO. Therefore, by setting the differential voltage VOFF to the offset voltage VOF, the differential voltage VOFF can be eliminated.

0064As for the method to compensate the offset voltage VOF, the offset voltage VOF is gradually changed while comparing the target voltage VM with the output signal VO. And at the point when the target voltage VM and the output signal VO finally agree with each other, the offset voltage VOF is set. At first, the width to be changed for the offset voltage VOF is preferably set widely, and the width is reduced as the target voltage VM and the output signal VO come closer to each other. Thus, it is preferred that the agreement between the target voltage VM and the output signal VO can be detected quickly. In this example of the operation, the case, in which the offset voltage VOF is compensated using the method as described above, will be described.

0065<figref idref="DRAWINGS">FIG. 8</figref> is a waveform diagram illustrating the operation to compensate the offset voltage VOF using the above-described method.

0066In <figref idref="DRAWINGS">FIG. 8</figref>, cycles T<b>0</b> to T<b>7</b> are shown as the steps of the operation. In cycle TO and cycle T<b>7</b>, the amplification circuit <b>10</b> operates in the ordinary operation mode MDN; and in the cycles T<b>1</b> to T<b>6</b>, operates in the amplification characteristic compensation mode MDH.

0067First of all, when shifting from cycle T<b>0</b> to cycle T<b>1</b>, the control signal CRL<b>1</b> is set to the high level; the control signal CRL<b>2</b> is set to the low level; the target voltage allowable error range VMW indicated by the upper limit voltage value VC<b>1</b> and the lower limit voltage value VC<b>2</b> is set to the first voltage width VW<b>1</b>; and the standby time from the point when the offset voltage VOF is output to the point when the comparison instruction signal COMPT is outputted is set to the first standby time TW<b>1</b>, respectively.

0068In cycle T<b>1</b>, the offset voltage VOF is set to voltage V<b>10</b>. After the first standby time TW<b>1</b> generated by the first timer <b>82</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is within the range of the first voltage width VW<b>1</b>. Since the output signal VO is out of the range of the first voltage width VW<b>1</b>, the low level is outputted to the comparison signal COMPO.

0069In cycle T<b>2</b>, the offset voltage VOF is set to voltage V<b>20</b>. After the first standby time TW<b>1</b> generated by the first timer <b>82</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is within the range of the first voltage width VW<b>1</b>. Since the output signal VO is out of the range of the first voltage width VW<b>1</b>, the low level is outputted to the comparison signal COMPO.

0070In cycle T<b>3</b>, the offset voltage VOF is set to voltage V<b>30</b>. After the first standby time TW<b>1</b> generated by the first timer <b>82</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is with in the range of the first voltage width VW<b>1</b>. Since the output signal VO is within the range of the first voltage width VW<b>1</b>, the high level is outputted to the comparison signal COMPO.

0071In cycle T<b>4</b>, the offset voltage VOF is set to voltage V<b>40</b>. After the first standby time TW<b>1</b> generated by the first timer <b>82</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is within the range of the first voltage width VW<b>1</b>. Since the output signal VO is out of the range of the first voltage width VW<b>1</b>, the low level is outputted to the comparison signal COMPO.

0072Since the comparison signal COMPO is the high level in cycle T<b>3</b>, and in cycle T<b>4</b>, changes to the low level, it is determined that the offset voltage VOF closest to the target voltage VM is the voltage V<b>30</b>. In the next cycle (cycle T<b>5</b>), the control signal CRL<b>2</b> is set to the low level; the target voltage allowable error range VMW is set to the second voltage width VW<b>2</b>; and the standby time from the point when the offset voltage VOF is outputted to the point when the comparison instruction signal COMPT is outputted is set to the second standby time TW<b>2</b>, respectively.

0073In cycle T<b>5</b>, the offset voltage VOF is set to voltage V<b>30</b>. After the second standby time TW<b>2</b> generated by the second timer <b>83</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is within the range of the second voltage width VW<b>2</b>. Since the output signal VO is within the range of the second voltage width VW<b>2</b>, the high level is outputted to the comparison signal COMPO.

0074In cycle T<b>6</b>, the offset voltage VOF is set to voltage V<b>31</b>. After the second standby time TW<b>2</b> generated by the second timer <b>83</b> has passed, the comparison instruction signal COMPT is set to the high level, and at the same time, it is determined whether the output signal VO is within the range of the second voltage width VW<b>2</b>. Since the output signal VO is out of a range of the second voltage width VW<b>2</b>, the low level is outputted to the comparison signal COMPO.

0075Since the comparison signal COMPO is at the high level in cycle T<b>5</b>, and changes to the low level in cycle T<b>6</b>, it is determined that the offset voltage VOF closest to the target voltage VM is the voltage V<b>30</b>, and the amplification characteristic compensation mode MDH is terminated. And at the same time, the voltage V<b>30</b> is set to the offset voltage VOF. That is, from cycle T<b>7</b> onward, the operation mode MD shifts to the ordinary operation mode MDN.

0076As for the actual voltages of the voltages V<b>10</b> to V<b>40</b> and V<b>31</b> shown in the example of operation, the voltage V<b>10</b> is set to 0 mV; the voltage V<b>20</b> is set to 20 mV; the voltage V<b>30</b> is set to 40 mV; the voltage V<b>31</b> is set to 50 mV; and the voltage V<b>40</b> is set to 60 mV. As for the actual voltage of the first voltage width VW<b>1</b> and the second voltage width VW<b>2</b>, which indicate the voltage width of the target voltage allowable error range VMW with respect to the target voltage VM, the first voltage width VW<b>1</b> is set to 20 mV; and the second voltage width VW<b>2</b> is set to 10 mV. That is, the variation width of the offset voltage VOF agrees with the target voltage allowable error range VMW. For example, the variation width (voltage V<b>20</b>-voltage V<b>10</b>) of the offset voltage VOF when shifting from cycle T<b>1</b> to cycle T<b>2</b> is 20 mV; and at this time, the target voltage allowable error range VMW is the first voltage width VW<b>1</b>; i.e., 20 mV. Therefore, it is possible to reliably judge whether the output signal VO agrees with the target voltage allowable error range VMW with respect to the target voltage VM.

0077In the example of operation, with respect to the case where each cut-off frequency fc is set, the noise amount included in the output signal VO and the response time of the lowpass filter <b>30</b> has been previously measured and comprehended. When the ordinary cut-off frequency fcn is set (CRL<b>1</b>=low level, CRL<b>2</b>=low level), the noise amount included in the output signal VO is 2 mVpp, and the response time is 100 ms; when the second cut-off frequency fc<b>2</b> is set (CRL<b>1</b>=high level, CRL<b>2</b>=low level), the noise amount included in the output signal VO is 10 mVpp, and the response time is 20 ms; and when the cut-of frequency fc<b>1</b> is set (CRL<b>1</b>, CRL<b>2</b>=high level), the noise amount included in the output signal VO is 20 mVpp, and the response time is 10 ms.

0078Next, the relationship between the target voltage allowable error range VMW and the cut-off frequency fc, which are set in each cycle, will be described.

0079In cycle T<b>1</b> to T<b>4</b>, to the target voltage allowable error range VMW, the first voltage width VW<b>1</b> (20 mV) is set, and to the cut-off frequency fc, the first cut-off frequency fc<b>1</b> (noise amount=20 mVpp) is set. In cycle T<b>5</b> to T<b>6</b>, to the target voltage allowable error range VMW, the second voltage width VW<b>2</b> (10 mV) is set, and to the cut-off frequency fc, the second cut-off frequency fc<b>2</b> (noise amount=10 mVpp) is set. That is, in any cycle, the cut-off frequency fc in which the noise amount equal to the target voltage allowable error range VMW or less is decided. Since being adapted as described above, the comparison judgment of the output signal VO and target voltage VM is carried out reliably.

0080Then, the processing time of the amplification characteristic compensation mode MDH will be described. The processing time is obtained based on the standby time TW (period of time from the point when the offset voltage VOF is inputted to the point when the comparison instruction signal COMPT is outputted), which is set in each cycle.

0081In cycle T<b>1</b> to T<b>4</b>, each standby time TW is the first standby time TW<b>1</b>; i.e., 10 ms. Accordingly, the total standby time TW in cycles T<b>1</b> to T<b>4</b> is 40 ms. In cycle T<b>5</b> to T<b>6</b>, each standby time TW is the second standby time TW<b>2</b>; i.e., 20 ms. Accordingly, the total standby time TW in cycle T<b>5</b> to T<b>6</b> is 40 ms; and the inclusive sum of the standby time TW in cycles T<b>1</b> to T<b>6</b> is 80 ms.

0082When the present invention is not applied, the standby time TW is always 100 ms, which is the standby time corresponding to the ordinary cut-off frequency fcn. Therefore, the inclusive sum of the standby time TW in cycles T<b>1</b> to T<b>6</b> is 600 ms.

0083In the amplification circuit <b>10</b> to which the present invention is applied, the processing time of the amplification characteristic compensation mode MDH is reduced to about ⅛ of that in the case to which the present invention is not applied.

0084In this embodiment, to describe simply, an example in which the number of operation steps is reduced is given. However, in the actual instruments, since a fine offset compensation is made in a wider dynamic range, the compensation is carried out in a larger number of operation steps. When the present invention is applied to an actual instrument, a further larger effect of time reduction will be obtained.

0085In the conventional amplification circuits, the calibration to compensate the amplification characteristic was indispensable before operation. Therefore, the amplification circuit could not be used immediately after turning on the power.

0086Contrarily, in the present invention, even when only a small period of time is allowed for idling the instrument, calibration can be carried out. For example, by arbitrarily carrying out the calibration during the operation of the instrument, the calibration before the operation can be omitted. And further, the amplification circuit can always be maintained in a state of a high accuracy being well compensated.

0087On the other hand, Japanese Published Unexamined Patent Application No. H11-88071 discloses the following technique. That is, compensation values of the amplification characteristic in each application conditions, which are previously obtained using a considerably large period of time, are stored in a storage such as nonvolatile memory, and a compensation value in accordance with the application conditions of the amplification circuit is taken out and the amplification circuit is adjusted in accordance with the compensation value. By employing the technique disclosed in the Japanese Published Unexamined Patent Application No. H11-88071, the calibration prior to the operation can be omitted.

0088Contrarily, when the present invention is employed, and by arbitrarily carrying out the calibration during the operation of the instrument in the same manner as described above, the calibration prior to the operation can be omitted without being equipped with a storage such as nonvolatile memory nor previously obtaining the compensation values of the amplification characteristic in each application condition.

0089In this embodiment, the following example has been described. That is, the differential reference signals VE<b>1</b> and VE<b>2</b>, which are generated by the reference signal generating section <b>60</b>, are inputted to the amplifying section <b>20</b> to operate. However, an unshown sensor may be set to the standard status, and sensor reference signals, which are generated at that time, may be used as the input. As for the sensor reference signal, for example, a 0-point output signal, which is outputted when the sensor is set to the 0-point, is available.

0090Next, a description will be given as to the features of the amplification characteristic compensation value ZD such as offset voltage VOF obtained by setting the amplification characteristic. And further, means with which the invention solves the problems will be described.

0091As described above, in the amplification circuit disclosed in the Japanese Published Unexamined Patent Application No. H11-88071, the following technique has been proposed. That is, the compensation value of the amplification characteristic is previously obtained and stored in the storage. And when the power is turned on again to start up, the amplification characteristic is set using the stored compensation value of the amplification characteristic, thereby the time required for compensating the amplification characteristic is reduced or omitted.

0092However, for converting a physical value such as pressure, acceleration and angular velocity into an electrical signal, in many cases, a sensor connected to an amplification circuit is provided with a moving part. Accordingly, a change tends to occur as time passes due to the influence of wear, metal fatigue and the like. Such change due to lapse of time appears as an error with respect to the amplification output of an original detection signal. Accordingly, there resides a problem in the amplification circuit disclosed in the Japanese Published Unexamined Patent Application No. H11-88071 such that error, in the case where changes due to lapse of time occur to the connected sensor, cannot be eliminated.

0093In order to solve the above problems it is preferred that the amplification circuit according to claim <b>2</b>, which further includes an event counting section that counts the events occurring continuously in time series and outputs and holds the event count value, and a characteristic value storing section constituted of a nonvolatile storage that, in the measurement of the amplification characteristic, assuming that a value corresponding to the measurement result is an amplification characteristic value, and assuming that the event count value for obtaining the amplification characteristic value is the event count value during compensation, stores the amplification characteristic value and the event count value during compensation, wherein before measurement of the amplification characteristic, it is judged whether the difference value between the event count value during compensation stored in the characteristic value storing section and the event count value outputted from the event counting section exceed a predetermined value, when the difference value exceeds the predetermined value, the amplification characteristic value is obtained, and the obtained amplification characteristic value and the event count value at obtaining are stored in the characteristic value storing section, when the difference value does not exceed the predetermined value, the amplification circuit is compensated in accordance with the amplification characteristic value stored in the characteristic value storing section.

0094In the amplification circuit according to the present invention, before compensating the amplification characteristic, the event count value during compensation stored in the characteristic value storing section is compared with the present event count value. When the difference exceeds a predetermined value, the amplification characteristic value is obtained again, and a new amplification characteristic value is stored in the storage along with the event count value during compensation as the event count value at that time. On the other hand, when the difference does not exceed the predetermined value, the amplification characteristic value stored in the characteristic value storing section is used as the compensation value of the amplification circuit.

0095For example, it is preferred to set a predetermined value equivalent to a period that changes in a sensor due to lapse of time are expected. At a point of time when changes in the sensor due to lapse of time are expected to occur, since the amplification characteristic value is obtained again, the error caused by the changes in the sensor due to lapse of time can be eliminated.

0096As for the event, which occurs continuously in time series, for example, in particular, a clock generated with a certain frequency is given. The intervals between the events may not always be regular intervals. For example, a clock, which is generated only when the power supply of the amplification circuit is turned on, or a signal representing the turn on of the power supply for the amplification circuit.

0097As for the event counting section, a calendar clock using a clock generated with a certain frequency as the input, or power-on counter using a signal representing the power-on of the amplification circuit as the input are available.

0098The nonvolatile storage is a storage in which the contents therein are maintained even when the power supply of the amplification circuit is cut off. For example, a flash memory or volatile memory connected with a battery backup are given.

0099In the amplification circuit <b>10</b> according to the first embodiment, in order to eliminate the error caused by the changes in the sensor due to lapse of time, the amplification characteristic compensation value ZD such as offset voltage VOF obtained by setting the amplification characteristic can be stored in the compensation value storage <b>85</b>. The compensation value storage <b>85</b> is equipped with the clocking section <b>86</b> having a backup function and clocking day and time, and the nonvolatile memory <b>87</b> for storing the amplification characteristic compensation value ZD along with a clock value KD generated by the clocking section <b>86</b>. The clock value KD includes clock information (day and time) when the amplification characteristic compensation value ZD is stored. When carrying out the amplification characteristic compensation, the sequencer <b>81</b> reads out the clock value KD along with the amplification characteristic compensation value ZD. At the same time, the present clock information is read out from the clocking section <b>86</b> to obtain the difference between the previously read out clock value KD and the present clock information. As a result, when a predetermined day and time has not been passed, the amplification characteristic is compensated using the amplification characteristic compensation value ZD; and if not so, a new amplification characteristic compensation value is obtained.

0100Owing to this, when the predetermined day and time has been passed from the previous detection of the amplification characteristic, the amplification characteristic compensation value can be obtained. This enables the amplification characteristic generated from the changes due to lapse of time to be compensated.

0101In this embodiment, the clocking section <b>86</b> is equivalent to the event counting section, the clock value KD is equivalent to event count value, the nonvolatile memory <b>87</b> is equivalent to characteristic value storing section, and the amplification characteristic compensation value ZD is equivalent to the amplification characteristic value.

0102In order to eliminate the influence of the changes due to lapse of time as described above, not only the compensation of the amplification characteristic of the amplifying section, but the compensation of the amplification characteristic including the sensor is necessary. In the amplification circuit <b>10</b> according to the first embodiment, the reference signal generating section <b>60</b> gives the reference to the amplifying section <b>20</b>. In the case of the compensation of the amplification characteristic including the sensor, in place of generating the reference signal, the amplification circuit <b>10</b> serves as the circuit that sets the sensor physically to the reference state. As for the circuit for setting the sensor physically to the reference state, an unshown positioning circuit of the sensor movable section using an electrostatic force, which is well known in the art, is available.

0103Also, in order to eliminate the error caused by the changes in the sensor due to lapse of time, in place of the compensation value storage <b>85</b> according to the first embodiment, a compensation value storage <b>85</b>A shown in <figref idref="DRAWINGS">FIG. 9(A)</figref> may be used. The compensation value storage <b>85</b>A is equipped with a clock generator <b>88</b>A in place of the clocking section <b>86</b>, and a counter <b>86</b>A that counts the clock generated by the clock generator <b>88</b>A and has a backup function. In the nonvolatile memory <b>87</b>, along with the previously detected amplification characteristic compensation value ZD, count value CD outputted simultaneously by the counter <b>86</b>A is stored. When carrying out the compensation of the amplification characteristic, the sequencer <b>81</b> reads out the count value CD along with the amplification characteristic compensation value ZD. At the same time, the present count value is read out from the counter <b>86</b>A and is compared with the previously read out clock value KD. As a result, when the predetermined count number has not been exceeded, the amplification characteristic is compensated using the amplification characteristic compensation value ZD. If not so, a new amplification characteristic compensation value ZD is obtained.

0104Owing to this, when a predetermined count number has been exceeded from the previously obtained amplification characteristic compensation value ZD, by obtaining the amplification characteristic compensation value ZD, the error caused by the changes in the sensor due to the lapse of time can be eliminated.

0105In this embodiment, the clock generator <b>88</b>A and counter <b>86</b>A are equivalent to the event counting section, the count value CD is equivalent to the event count value, the nonvolatile memory <b>87</b> is equivalent to the characteristic value storing section, and the amplification characteristic compensation value ZD is equivalent to the amplification characteristic value.

0106Likewise, in place of the compensation value storage <b>85</b> according to the first embodiment, a compensation value storage <b>85</b>B shown in <figref idref="DRAWINGS">FIG. 9(B)</figref> may be used. The compensation value storage <b>85</b>B is equipped with a power-on detecting section <b>88</b>B in place of the clocking section <b>86</b>, and a counter <b>86</b>B that counts the pulse generated by the power-on detecting section <b>88</b>B and has a backup function. In the nonvolatile memory <b>87</b>, along with the previously detected amplification characteristic compensation value ZD, count value CD outputted simultaneously by the counter <b>86</b>B is stored. When carrying out the compensation of the amplification characteristic, the sequencer <b>81</b> reads out the count value CD along with the amplification characteristic compensation value ZD. At the same time, the present count value is read out from the counter <b>86</b>B and is compared with the previously read out clock value KD. As a result, when the predetermined count number has not been exceeded, the amplification characteristic is compensated using the amplification characteristic compensation value ZD. If not so, a new amplification characteristic compensation value is obtained.

0107In this embodiment, the power-on detecting section <b>88</b>B and counter <b>86</b>B are equivalent to the event counting section, the count value CD is equivalent to the event count value, the nonvolatile memory <b>87</b> is equivalent to the characteristic value storing section, and the amplification characteristic compensation value ZD is equivalent to the amplification characteristic value.

0108Owing to this, when a predetermined number of the turn-on of the power has been exceeded from the previously obtained amplification characteristic compensation value, by obtaining the amplification characteristic compensation value, the error caused by the changes in the sensor due to lapse of time can be eliminated.

0109Returning to the description of the operation mode MD, in the case where the amplification circuit <b>10</b> operates in the failure detection mode MDF, failure detection reference signals VF<b>1</b> and VF<b>2</b> for failure detection are inputted to the differential input signals V<b>1</b> and V<b>2</b>. These failure detection reference signals VF<b>1</b> and VF<b>2</b> are voltages for detecting whether the amplification circuit <b>10</b> operates normally, by setting the controlling section <b>80</b>, the signals are outputted from the reference signal generating section <b>60</b>.

0110With respect to the differential reference signals VE<b>1</b> and VE<b>2</b>, a failure detection target voltage VFM is derived based on the relationship with the amplification characteristic, and in accordance with this, the target voltage control signal CE<b>2</b> is outputted from the sequencer <b>81</b>. In the target voltage generating section <b>52</b>, the upper limit voltage value VC<b>1</b> and the lower limit voltage value VC<b>2</b> corresponding to the target voltage control signal CE<b>2</b> are outputted to the window comparator <b>51</b>. After the failure detection reference signals VF<b>1</b> and VF<b>2</b> for failure detection are applied, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level to increase the response speed of the lowpass filter <b>30</b>; thus, the comparison judgment between the output signal VO and the failure detection target voltage VFM is carried out swiftly.

0111In this embodiment, the failure detection reference signals VF<b>1</b> and VF<b>2</b> are equivalent to the reference signals, the sequencer <b>81</b>, the window comparator <b>51</b> and the target voltage generating section <b>52</b> are equivalent to the controlling section.

0112Referring to <figref idref="DRAWINGS">FIG. 10</figref>, the operation of the failure detection mode MDF will be described below.

0113<figref idref="DRAWINGS">FIG. 10</figref> shows cycles T<b>10</b> to T<b>14</b> as the steps of the operation. In cycle T<b>10</b> and cycle T<b>14</b>, the amplification circuit <b>10</b> operates in the ordinary operation mode MDN; and in cycle T<b>11</b> to T<b>13</b>, operates in the failure detection mode MDF.

0114First of all, when shifting from cycle T<b>10</b> to cycle T<b>11</b>, the failure detection reference signals VF<b>1</b> and VF<b>2</b> are inputted to the differential input signals V<b>1</b> and V<b>2</b>, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level, and the target voltage allowable error range VMW is set to the failure detection voltage width VWF, respectively.

0115In cycle T<b>11</b>, since both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level, when there is no abnormality in the operation of the amplification circuit <b>10</b>, the output signal VO changes swiftly toward the failure detection target voltage VFM.

0116In cycle T<b>12</b>, in order to compare the output signal VO with the failure detection target voltage VFM with a high accuracy, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the low level. Also, the comparison instruction signal COMPT is set to the high level, and it is determined whether the output signal VO is within the range of the failure detection voltage width VWF. Since the output signal VO is within a range of the failure detection voltage width VWF, the high level is outputted to the comparison signal COMPO.

0117When the output signal VO is out of the range of the failure detection voltage width VWF, the low level is outputted to the comparison signal COMPO. Receiving this, the controlling section <b>80</b> emits a failure notification signal.

0118In cycle T<b>13</b>, the differential input signals VI<b>1</b> and VI<b>2</b> from the sensor are inputted to the differential input signals V<b>1</b> and V<b>2</b>, and both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level. Owing to this, the output signal VO changes swiftly toward the original level (cycle T<b>10</b>).

0119In cycle T<b>14</b>, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the low level. Owing to this, the amplification circuit <b>10</b> shifts to the ordinary operation mode MDN.

0120Thus, in the failure detection mode MDF also, by setting the cut-off frequency fc to the side higher than the ordinary cut-off frequency fcn, the amplification circuit <b>10</b> can perform the failure detection swiftly.

0121In this embodiment, an example in which the operation is carried out by inputting the failure detection reference signals VF<b>1</b> and VF<b>2</b>, which are generated by the reference signal generating section <b>60</b>, to the amplifying section <b>20</b> has been shown. However, an unshown sensor may be set to the standard status, and sensor reference signals, which are generated at that time, may be used as the input.

0122Returning to the description of the operation mode MD again, when the amplification circuit <b>10</b> operates in the lowpass filter initialization mode MDL, initialization voltages VL<b>1</b> and VL<b>2</b> for pre-charging the capacitive element CL of the lowpass filter <b>30</b> are inputted to the differential input signals V<b>1</b> and V<b>2</b>. The initialization voltages VL<b>1</b> and VL<b>2</b> are inputted to the amplifying section <b>20</b>, and by the outputted amplification signal VZ, the capacitive element CL is pre-charged. At the pre-charging, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level to increase the response speed of the lowpass filter <b>30</b> to carry out the pre-charge swiftly. The comparison judgment between the output signal VO and the initialization target voltage VLM is carried out within a lowpass filter initialization allowable error range VWL, and in accordance with the judgment result, the mode shifts to the ordinary operation mode MDN.

0123Referring to <figref idref="DRAWINGS">FIG. 11</figref>, the operation of the lowpass filter initialization mode MDL will be described below.

0124<figref idref="DRAWINGS">FIG. 11</figref> shows cycles T<b>20</b> to T<b>23</b> as the steps of the operation. Cycle T<b>20</b> is the state before the power supply is turned on. Cycle T<b>23</b> is a state of the ordinary operation mode MDN. In cycle T<b>21</b> to T<b>22</b>, the amplification circuit <b>10</b> operates in the lowpass filter initialization mode MDL.

0125First of all, in cycle T<b>21</b>, when detecting the turn-on of the power supply, both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level, and the initialization voltages VL<b>1</b> and VL<b>2</b> are inputted to the differential input signals V<b>1</b> and V<b>2</b>. Also, the lowpass filter initialization allowable error range VWL is set to the target voltage allowable error range VMW, and the comparison instruction signal COMPT is set to the high level.

0126Since both of the control signals CRL<b>1</b> and CRL<b>2</b> are set to the high level, the output signal VO changes swiftly toward the initialization target voltage VLM.

0127As a means for detecting the turn-on of the power supply, an unshown power-on reset circuit, which is well known in the art, is given. From such a means, the information is transmitted to the controlling section <b>80</b>.

0128In cycle T<b>22</b>, when the output signal VO has reached within the range of the lowpass filter initialization allowable error range VWL, the comparison signal COMPO changes to the high level. When the lowpass filter initialization has completed, from the next cycle (cycle T<b>23</b>), the mode shifts to the ordinary operation mode MDN.

0129As described above, in the lowpass filter initialization mode MDL, since the amplification circuit <b>10</b> sets the cut-off frequency fc of the lowpass filter <b>30</b> to the side higher than the ordinary cut-off frequency fcn, the lowpass filter can be initialized swiftly.

0130In this example of the operation, by the comparison judgment between the output signal VO and the initialization target voltage VLM, the operation to shift to the ordinary operation mode MDN has been described.

0131As for the means to shift from the lowpass filter initialization mode MDL to the ordinary operation mode MDN, the following means may be employed. That is, using a signal outputted from the means for detecting the turn-on of the power supply as the trigger, after a predetermined waiting period, the circuit is switched to the operation mode MD. By employing such a circuit, the window comparator <b>51</b> and the target voltage generating section <b>52</b> become unnecessary. Accordingly, the circuit can be configured simply.

0132The present invention is not limited to the above-described embodiments. It is a matter of course that various improvements and modifications are possible without departing from the scope of the present invention.

0133For example, to describe special operation mode, the amplification characteristic compensation mode, the failure detection mode and the lowpass filter initialization mode have been described. However, the three modes are not always necessary, but in accordance with an embodiment, only one mode may be selected.

0134Also, in the example of the operation of the amplification characteristic according to the embodiments, the offset compensation has been described. In the same manner as the above-described offset compensation, the resistance value of the feedback resistance may be adjusted to carry out the gain compensation. The present invention may be applied to the case where such gain compensation is carried out, or the case where the gain compensation and the offset compensation are carried out simultaneously.

0135Further, in the embodiments, the amplification circuit configured such that the operational amplifier is used in the amplifying section has been described. The present invention is not limited to the above; but may be applied to the case where a bipolar transistor, an FET element and the like are used to configure and the same function is obtained.

0136By applying the present invention, in the amplification circuit connected with a lowpass filter, the time required for compensating the amplification characteristic and for pre-charging the lowpass filter at turning on the power supply can be reduced.