Programmable logic module and upgrade method thereof

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a logic module, and more particularly, to a programmable logic module and upgrade method thereof.

2. Description of the Related Art

Programmable logic devices such as FPGAs have wide applicability due to their flexibility and reprogrammability. An FPGA typically includes an array of configurable logic blocks (CLBs) connected across a configurable routing structure for implementing desired logic functions and circuit design. Thus, the FPGA occupies a larger area on the wafer surface. FPGAs also include a number of configuration memory cells coupled to the CLBs to specify the function to be performed by each CLB, and a number of configuration memory cells coupled to the configurable routing structure to specify the connectivity between CLBs.

FPGAs are most commonly used within systems including a microprocessor and a memory unit. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, an available FPGA <b>120</b> receives a configuration bitstream from memory device <b>100</b> upon receipt of a program signal from microprocessor <b>110</b>, to erase previous configuration data and receive new configuration data from memory device <b>100</b>. Thus, the FPGA <b>120</b> can implement new logic functions and circuit designs according to new configuration data.

<figref idref="DRAWINGS">FIG. 2</figref> shows a conventional FPGA module. The FPGA module has a circuit board with a FPGA <b>18</b>, a downloading unit <b>12</b>, and a memory device <b>16</b> disposed thereon. The memory device <b>16</b> is plugged into a socket <b>14</b> on the circuit board <b>10</b>. The configuration data stored in the memory device <b>16</b> is written into the FPGA by the downloading unit <b>12</b>. When FPGA gate count is increased and the desired functions and circuits are more complex, a memory device with a larger storage capacity is required. The conventional memory device <b>16</b>, however, is formed within a dual-in-line package (DIP), the maximum storage capacity of which is only 8 Mb. Thus, DIP memory <b>16</b> in the conventional FPGA module limits the upgrade capacity of the FPGA <b>18</b>.

<figref idref="DRAWINGS">FIG. 3</figref> shows another conventional FPGA module. This FPGA module has a circuit board <b>30</b> with an FPGA <b>38</b> disposed thereon, a downloading unit <b>32</b>, and a plurality of memory devices <b>36</b>. The memory devices <b>36</b> are plugged into the circuit board <b>30</b> through the corresponding sockets <b>34</b>. Configuration data stored in the serial memory devices <b>36</b> is written into the FPGA <b>38</b> by the downloading unit <b>32</b>. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the circuit board <b>30</b> has eight memory sockets <b>34</b> to receive the memory devices <b>36</b>. Typically, serial memory devices have slow write speed, and are expensive. Additional, when FPGA gate count is increased and the desired functions and circuits are more complex, a memory device with a larger storage capacity is required. A new circuit board with more sockets is necessary when the eight serial memory devices cannot sufficient to store the desired configuration data. Thus, the FPGA <b>38</b> of the conventional FPGA module has limited the upgrade capacity.

Further, the FPGAs <b>18</b> and <b>38</b> shown in <figref idref="DRAWINGS">FIGS. 2 and 3</figref> both have a plurality of I/O terminals and power terminals, each of the I/O terminals and power terminals is connected to a corresponding pin (<b>20</b> or <b>40</b>) on the circuit board <b>10</b> and <b>30</b>. Insertion force between the pins (<b>20</b> and <b>40</b>) of the FPGA and the corresponding connector (not shown), however, increases with increased pin count. Thus, it is inconvenient to insert or remove the FPGA from the connector.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to enable upgrade of an FPGA to increase the storage capacity of the memory device in the programmable logic module.

Another object of the present invention is to decrease insertion force between the pins of the programmable logic module and the corresponding connector.

According to the above mentioned object, the present invention provides a programmable logic module capable of enabling upgrade of an FPGA to increase the storage capacity of the memory device.

In the programmable logic module, a first printed circuit board has a socket and a downloading unit. A field programmable gate array (FPGA) is disposed on the first printed circuit board. A nonvolatile memory stores program codes for the field programmable gate array. The nonvolatile memory is soldered on a second printed circuit board with a plurality of pins corresponding to the socket, and the second printed circuit board is plugged into the socket on the first printed circuit board. The nonvolatile memory downloads program codes thereof to the field programmable gate array by the downloading unit.

According to the above mentioned object, the present invention also provides a programmable logic module capable of decreasing the insertion force between the pins and the corresponding connector.

In the programmable logic module, a first printed circuit board has a power pin region and a plurality of I/O pin regions. The power pin region is separated from the I/O pin regions, and each power pin region and I/O pin region has a plurality of pins. A field programmable gate array is disposed on the first printed circuit board. The field programmable gate array has a plurality of power terminals and I/O terminals. A nonvolatile memory stores program codes for the field programmable gate array. Each I/O terminal of the field programmable gate array is electrically connected to a corresponding pin in the I/O pin region. All power terminals of the field programmable gate array are electrically connected to pins in the power pin region. The pins in the power pin region and the I/O pin region are connected to external circuits through different connectors.

According to the above mentioned object, the present invention also provides a method of upgrading a programmable logic module.

In this method, the second printed circuit board with nonvolatile memory is removed from the socket on the first printed circuit board. Next, the second printed circuit board with the nonvolatile memory is disposed on a writer to write a new program into the nonvolatile memory. The second printed circuit board with nonvolatile memory is then plugged back into the socket. Finally, the new program stored in the nonvolatile memory is downloaded to the field programmable gate array by the downloading unit.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of a conventional FPGA module;

<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing another conventional FPGA module;

<figref idref="DRAWINGS">FIG. 3</figref> is a diagram showing another conventional FPGA module; and

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram of the programmable logic module according to the prestent invention.

DETAILED DESCRIPTION OF THE INVENTION

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram of the programmable logic module according to the present invention. In the programmable logic module <b>200</b>, a first printed circuit board <b>50</b> has a downloading unit <b>52</b>, and a socket <b>54</b>. The downloading unit <b>52</b> is electrically connected to the first printed circuit board <b>50</b>. The first printed circuit board <b>50</b> has a power pin region <b>64</b> and a plurality of I/O pin regions <b>62</b>. The power pin region <b>64</b> is isolated from the I/O pin regions <b>62</b> each of the power pin region <b>64</b> and the I/O pin regions <b>62</b> has a plurality of pins.

A field programmable gate array (FPGA) <b>58</b> is disposed on the first printed circuit board <b>50</b>. For example, the FPGA <b>58</b> includes an array of configurable logic blocks (not shown) programmably interconnected to one another across a configurable routing structure for implementing desired logic functions and circuit design. FPGAs <b>58</b> also include a number of configuration memory cells coupled to the configurable logic blocks (CLBs) to specify the function to be performed by each CLB, and a number of configuration memory cells coupled to the configurable routing structure to specify the connectivity between CLBs.

Further, FPGA <b>58</b> also has a plurality of power terminals and I/O terminals. In this case, each I/O terminal of the FPGA <b>58</b> is electrically connected to a corresponding pin in the I/O pin region <b>62</b>. All power terminals of the FPGA <b>58</b> are electrically connected to the pins in the power pin region <b>64</b>. Each power pin region <b>64</b> and the I/O pin region <b>62</b> are coupled to external circuits by different connectors. Typically, conventional FPGA modules do not separate the power pins from the I/O pins, such that one connector connects an I/O pin region with power pins and I/O pins. Thus, the required insertion force between this region and connector is great. Further, the number of power terminals includes 30 percent of all FPGA terminals. In the present invention, pin count in the I/O pin region is reduced because all power terminals are electrically connected to the pins in the power pin region <b>64</b>. Thus, the required insertion force between each I/O pin region <b>62</b> and the corresponding connector is reduced.

A nonvolatile memory <b>60</b> storing program codes for programming the FPGA <b>58</b>, is soldered on a second printed circuit board <b>56</b>. The second printed circuit board <b>56</b> has a plurality of pins corresponding to the socket <b>54</b>, such that the second printed circuit board can be plugged into the socket <b>54</b>. In this case, the nonvolatile memory <b>60</b> can be a 128 Mb flash memory module soldered on the second printed circuit board <b>56</b> by surface mounted technology. The I/O terminals and power terminals are electrically connected to the corresponding pins of the second printed circuit board <b>56</b>.

Further, to facilitate the surface mounted technology, the nonvolatile memory <b>60</b> can be packaged in a chip on board (COB) package, a small outline J-lead package, a quad flat package (QFP), plastic quad flat package (FQGP), a thin quad flat package (LQFP), a quad flat J-lead package, ball grid array (BGA) package or a fine pitch BGA package.

The program codes stored in the nonvolatile memory <b>60</b> are downloaded into FPGA <b>58</b> by a downloading unit <b>52</b>, enabling FPGA <b>58</b> to implement desired functions according to the program codes downloaded from nonvolatile memory <b>60</b>.

In this case, the nonvolatile memory <b>60</b> can be a 128 Mb flash memory module soldered on the second printed circuit board <b>56</b> by surface mounted technology. The capacity of the memory <b>60</b> is sufficient for program codes even when FPGA gate count increases and the desired functions are more complex. The present invention replaces only the nonvolatile memory <b>60</b> on the second printed circuit board <b>60</b> with a new memory module with larger storage capacity. Therefore, the present invention does not limit the upgrade potential of the FPGA <b>58</b>, and does not require new layout for the entire programmable logic module <b>200</b>.

Moreover, in the present invention, the number of pins in the I/O pin regions is reduced as all power terminals are electrically connected to the pins in the power pin region. Thus, the required insertion force between each I/O pin region and the corresponding connector is reduced, thereby increasing convenience when inserting or removing the FPGA <b>58</b>.

The present invention also provides an upgrade method for a programmable logic module. The programmable logic module is shown in <figref idref="DRAWINGS">FIG. 4</figref>. In the upgrade method, the second printed circuit board <b>56</b> with the nonvolatile memory <b>60</b> is removed from the socket <b>54</b> on the first printed circuit board <b>50</b>. Next, the second printed circuit board <b>60</b> with the nonvolatile memory <b>56</b> is disposed on a writer (not shown), for writing new program codes into the nonvolatile memory <b>60</b>. The second printed circuit board <b>56</b> is then inserted into the socket <b>54</b> on the first printed circuit board <b>50</b>. Thus, new program codes are stored in the nonvolatile memory <b>60</b>. Finally, the new program codes are downloaded to the FPGA <b>58</b> by the downloading unit <b>52</b>, enabling the FPGA <b>58</b> to implement new functions according to the new program codes downloaded from the nonvolatile memory <b>60</b>.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.