Fabrication method of polycrystalline silicon TFT

0001This application claims the benefit of Korean Patent Application No. 35577/2003, filed on Jun. 3, 2003, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a fabrication method of a thin film transistor, and more particularly, to a fabrication method of a thin film transistor using polycrystalline silicon.

00042. Description of the Related Art

0005Generally, a thin film transistor (hereinafter referred to as “TFT”) includes a semiconductor active layer as one element thereof, which is of amorphous silicon or polycrystalline silicon.

0006The amorphous silicon may be deposited at a low temperature to form a thin film and is usually used in a switching device of a liquid crystal panel with a glass substrate having a low melting point.

0007When an amorphous silicon semiconductor layer containing hydrogen is used as a switching device and the semiconductor layer is exposed to light, a photocurrent is generated due to photoelectric conversion. Accordingly, current is generated in an off state. This fatally affects the operation of the switching device.

0008Even if the semiconductor layer is not exposed to light, many defects, such as dangling bonds that are a typical non-periodic lattice characteristic of amorphous silicon are generated and electrons do not flow naturally. As a result the performance of the device degrades. Accordingly, when forming a semiconductor layer using amorphous silicon, the electrical characteristics and reliability of the liquid crystal panel driving device deteriorate, and it is difficult to make the area of the display device large.

0009On the other hand, when polycrystalline silicon is used to form a semiconductor layer, the surface of the semiconductor layer has fewer defects. The operation speed of the TFT formed of polycrystalline silicon is about 100-200 times faster than that of the TFT formed of amorphous silicon.

0010Referring to <figref idref="DRAWINGS">FIGS. 1A through 1F</figref>, the process to fabricate a polycrystalline silicon TFT will be described. <figref idref="DRAWINGS">FIGS. 1A through 1F</figref> illustrate a method of fabricating a polycrystalline silicon TFT according to related art.

0011First, as shown in <figref idref="DRAWINGS">FIG. 1A</figref>, a buffer layer <b>102</b> is formed on a substrate <b>101</b>. Here, the buffer layer <b>102</b> may be formed of one of insulating materials such as silicon oxide (SiO₂), silicon nitride (SiN_x), aluminum oxide (Al₂O₃) and the like. The buffer layer <b>102</b> provides a buffer between the substrate and the semiconductor layer to be formed later and prevents the substrate and the semiconductor layer from twisting because of nonuniform contact between the substrate and the semiconductor layer.

0012After that, an amorphous silicon layer <b>103</b> containing hydrogen is deposited on the buffer layer <b>102</b>. The amorphous silicon layer <b>103</b> deposited on the buffer layer <b>102</b> is crystallized to form a semiconductor layer formed of polycrystalline silicon.

0013In general, to form the polycrystalline silicon layer, pure amorphous silicon is deposited with a thickness of about 500 Å and crystallized. A plasma chemical vapor deposition (CVD) or a low pressure CVD (LPCVD) may be used as a method to deposit an amorphous silicon layer.

0014There are a number of polycrystalline silicon forming methods using amorphous silicon, some of which are described below.

0015First, an amorphous silicon layer may be annealed at high temperature for a long time in a solid phase crystallization (SPC) method to form the polycrystalline silicon layer.

0016Second, metal may be deposited on the amorphous silicon in a metal induced crystallization (MIC) method to form the polycrystalline silicon layer, so that a large glass substrate may be used.

0017Third, polycrystalline silicon may be grown using a laser in laser annealing on the substrate on which an amorphous silicon layer is deposited.

0018The method of fabricating the TFT by using polycrystalline silicon layer will be described successively as follows. Referring to <figref idref="DRAWINGS">FIG. 1B</figref>, the crystallized polycrystalline layer is patterned to form a semiconductor layer <b>103</b><i>a </i>and inorganic insulating film such as silicon nitride (SiN_x) or silicon oxide (SiO_x) may be deposited on an entire surface including the semiconductor layer <b>103</b><i>a </i>to form a first insulating film <b>104</b>.

0019Then, as shown in <figref idref="DRAWINGS">FIG. 1C</figref>, a conductive material such as aluminum (Al) or Al alloy is deposited over the first insulating film <b>104</b> and patterned using photolithography to form a gate electrode <b>105</b> on a predetermined portion on the semiconductor layer <b>103</b><i>a. </i>

0020Ions are implanted into the semiconductor layer <b>103</b><i>a </i>by using the gate electrode <b>105</b> as a mask to form a source/drain region. The semiconductor layer <b>103</b><i>a </i>is masked by the gate electrode <b>105</b>, and the area of the semiconductor layer <b>103</b><i>a </i>into which ions are not implanted into becomes channel region.

0021As shown in <figref idref="DRAWINGS">FIG. 1D</figref>, after implanting ions, an inorganic insulating film is deposited on an entire surface including the gate electrode <b>105</b> to form a second insulating film <b>106</b>. The second insulating film <b>106</b> and the first insulating film <b>104</b> are selectively removed to form a contact hole through which a predetermined portion of the source/drain region is exposed.

0022Then, as shown in <figref idref="DRAWINGS">FIG. 1E</figref>, conductive material such as Al or Al alloy is deposited on the second insulating film <b>106</b> through the contact hole and patterned in photolithography to form a source electrode <b>107</b> and a drain electrode <b>108</b> connected to the source/drain regions through the contact hole.

0023Finally, as shown in <figref idref="DRAWINGS">FIG. 1F</figref>, a passivation film <b>109</b> is deposited on the source electrode <b>107</b> and the drain electrode <b>108</b>. A contact hole is formed in a region of the drain electrode <b>108</b> on the passivation film <b>109</b> and a pixel electrode <b>110</b> is formed to connect the pixel electrode <b>110</b> to the drain electrode <b>108</b>.

0024Meanwhile, the electrical characteristic of the polycrystalline silicon TFT is affected greatly by grain morphology. In other words, the electric field effect mobility of the polycrystalline silicon TFT is increased as the size of the grains is increased.

0025<figref idref="DRAWINGS">FIG. 2</figref> illustrates the size of grains according to the thickness of the general crystallized polycrystalline silicon layer. <figref idref="DRAWINGS">FIG. 3</figref> illustrates characteristics of the TFT according to the thickness of the general polycrystalline silicon layer.

0026As shown in <figref idref="DRAWINGS">FIG. 2</figref>, it is well known that the amorphous silicon that is thinly formed at a thickness of 300-500 Å and crystallized has a small grain size, while the amorphous silicon that is thickly formed at a thickness of 1000-2000 Å and crystallized has a large grain size. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the mobility of the TFT is increased as the thickness of the polycrystalline silicon layer is increased. It is thought that the increase of the mobility is because the factors which hinder electrons from moving due to the increase of the size of the grains and the reduction of the defects in the grains are decreased.

0027In the method where the amorphous silicon is thickly formed at the thickness of 1000-2000 Å and the size of the crystallized grains is increased to improve the device characteristics, other problems arise.

0028For instance, as shown in <figref idref="DRAWINGS">FIG. 3</figref>, off current I_offincreases as the polycrystalline silicon layer gets thicker. When the polycrystalline silicon layer is thick, the generation-recombination region increases and leakage current increases.

0029In addition, when the polycrystalline silicon layer is thick, the gate metal line can be easily disconnected due to a high aspect ratio of the semiconductor layer (in the case of coplanar structure).

SUMMARY OF THE INVENTION

0030Accordingly, the present invention is directed to a fabrication method of a polycrystalline silicon TFT that substantially obviates one or more problems due to limitations and disadvantages of the related art.

0031An advantage of the present invention to provide a fabrication method of a polycrystalline silicon TFT in which the grain morphology of the polycrystalline silicon layer is improved to thereby improve the device characteristics.

0032Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned from practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

0033To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.

0034It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

0035The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

0036In the drawings:

0037<figref idref="DRAWINGS">FIG. 1A through 1F</figref> illustrate a TFT fabricated according to a method of fabricating a polycrystalline silicon TFT according to related art;

0038<figref idref="DRAWINGS">FIG. 2</figref> illustrates a general the size of grains according to the thickness of a crystallized polycrystalline silicon layer;

0039<figref idref="DRAWINGS">FIG. 3</figref> illustrates a general the characteristic of the TFT according to the thickness of a polycrystalline silicon layer.

0040<figref idref="DRAWINGS">FIGS. 4A through 4E</figref> illustrate a TFT fabricated according to a method of fabricating a polycrystalline silicon TFT according to the present invention;

0041<figref idref="DRAWINGS">FIG. 5</figref> illustrates a general chemical mechanical polishing process schematically; and

0042<figref idref="DRAWINGS">FIG. 6</figref> illustrates a general chemical mechanical polishing equipment schematically.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

0043Reference will now be made in detail to embodiments of the present invention, an example of which is illustrated in the accompanying drawings.

0044<figref idref="DRAWINGS">FIGS. 4A through 4E</figref> illustrate a TFT that is fabricated according to a method of fabricating a polycrystalline silicon TFT according to the present invention.

0045First, as shown in <figref idref="DRAWINGS">FIG. 4A</figref>, a buffer layer <b>402</b> is formed on a substrate <b>401</b>. In general, the buffer layer <b>402</b> may be made of an insulating material such as a silicon oxide (SiO₂) film, a silicon nitride (SiN_x) film or an aluminum oxide (Al₂O₃) film. The buffer layer <b>402</b> provides a buffer between the substrate <b>401</b> and a semiconductor layer to be formed later and avoids twisting caused by nonuniform contact between the substrate <b>401</b> and the semiconductor layer.

0046As shown in <figref idref="DRAWINGS">FIG. 4B</figref>, the intrinsic amorphous silicon layer <b>403</b> is deposited on the formed buffer layer <b>402</b> with thickness of about 700-10000 Å. The amorphous silicon layer <b>403</b> may be deposited by plasma chemical vapor deposition or LPCVD low pressure.

0047The amorphous silicon layer <b>403</b> is dehydrogenated by annealing. If not dehydrogenated, a surface of the crystalline thin film gets very tough so that the electrical characteristic degrades.

0048Subsequently, as shown in <figref idref="DRAWINGS">FIG. 4C</figref>, the deposited amorphous silicon <b>403</b> is crystallized to become a polycrystalline silicon layer <b>403</b><i>a</i>. A crystallization process using a laser may be used.

0049More particularly described, the crystallization process using the laser may be exemplified by an excimer laser annealing process using high power pulse laser or a sequential lateral solidification process.

0050In the excimer laser annealing process, strong energy pulses of short wavelength (for example, λ=0.3 μm) are projected to melt a thick silicon layer so that crystallization may be performed rapidly, and the thick silicon layer is crystallized uniformly to improve the mobility of a device.

0051Particularly, the short wavelength of the excimer may locally and finely anneal an object in short time, and a lower silicon layer is not thermally damaged because the energy concentration of a laser light is used.

0052The size of grains of polycrystalline silicon layer fabricated using excimer laser crystallization can be finely determined by varying the thickness of an amorphous silicon film, the density of ultraviolet irradiation caused by a laser, and the temperature of the lower substrate.

0053Then, a sequential lateral solidification process is performed using the fact that silicon grains grow on the boundary surface between liquid silicon and solid silicon perpendicular to the boundary surface. In the sequential lateral solidification process, the amount of laser energy and the irradiation range of the laser beam are properly adjusted, and silicon grains laterally grow a predetermined length so that an amorphous silicon thin film is crystallized.

0054Next, as shown in <figref idref="DRAWINGS">FIG. 4D</figref>, the crystallized polycrystalline silicon layer <b>403</b><i>a </i>of thickness of about 700-10000 Å is etched to have thickness of about 100-600 Å.

0055When etching the crystallized polycrystalline silicon layer, the crystallized polycrystalline silicon layer is etched with respect to channel resistance according to thickness of the polycrystalline silicon layer so that the polycrystalline silicon layer is thicker than thickness needed to implement the on-current drive of the thin film transistor.

0056In addition, when etching the crystallized polycrystalline silicon layer, the crystallized polycrystalline silicon layer is etched with according to a process margin within which the polycrystalline silicon layer is etched in a subsequent contact hole formation process for contacting a source/drain electrode, and so that the polycrystalline silicon layer is thicker than a predetermined thickness.

0057The crystallized polycrystalline silicon layer may be thinly etched using a chemical mechanical polishing (CMP) process or an etch-back process. Methods, other than etching may also be used to reduce the thickness of the polycrystalline silicon layer according to the present invention.

0058The chemical mechanical polishing process is a combination process in which a mechanical polishing process and a chemical polishing process are combined. In the chemical mechanical polishing process, the mechanical performance and the chemical performance act simultaneously.

0059<figref idref="DRAWINGS">FIG. 5</figref> illustrates a general chemical mechanical polishing process schematically. <figref idref="DRAWINGS">FIG. 6</figref> illustrates general chemical mechanical polishing equipment schematically. As shown in <figref idref="DRAWINGS">FIGS. 5 and 6</figref>, the substrate <b>502</b> is polished by a pad <b>504</b> and slurry <b>506</b>. Here, in general, the polishing table <b>520</b> with the pad <b>504</b> rotates. The head <b>510</b> rotates and vibrates simultaneously and applies a predetermined pressure to the substrate <b>502</b>.

0060The substrate <b>502</b> is installed on the head <b>510</b> using surface tension or vacuum. The surface of the substrate <b>502</b> and the pad <b>504</b> are placed in contact with each other, and the weight of the head <b>510</b> applies pressure. Here, the slurry <b>506</b> flows into the fine gap of the contacted surface. The polishing particles of the slurry <b>506</b> and the surface projections <b>508</b> of the pad <b>504</b> polish objects mechanically. The chemical component of the slurry <b>506</b> polishes the objects chemically.

0061In the chemical mechanical polishing process, the pad <b>504</b> is in contact with an upper portion of a projection on the substrate <b>502</b>. Due to the applied pressure between the pad <b>504</b> and the substrate <b>502</b>, the pressure is concentrated on this portion so that a comparatively higher surface removing speed is achieved. As the process proceeds, the projections are reduced. The entire surface of the substrate <b>502</b> is polished uniformly.

0062As described above, the crystallized polycrystalline silicon layer may be polished with the desired thickness using the chemical mechanical polishing process.

0063In addition, the crystallized polycrystalline silicon layer may be polished with the desired thickness using an etch-back process. The etch-back process is a method of etching without a mask. When forming a sidewall in a semiconductor process, it may be etched without any mask, and it may be etched without any mask so as to planarize after deposition process. All these are called an etch-back process.

0064Next, the step of curing the polycrystalline silicon layer <b>403</b><i>a </i>etched to a predetermined thickness is performed so as to cure the injured region of the surface of the polycrystalline silicon layer <b>403</b><i>a</i>. Either an annealing process using a furnace or an annealing process using a laser may be used as a curing process. Also a rapid thermal annealing (RTA) may be used as the curing process.

0065When the polycrystalline silicon layer <b>403</b><i>a </i>is etched using the chemical mechanical polishing process, it is usually annealed at about 400-500° C. When polycrystalline silicon layer <b>403</b><i>a </i>is etched using an etch-back process, the annealing using the laser or the rapid thermal annealing usually is performed.

0066Through the processes, the injured silicon on the etched polycrystalline silicon layer <b>403</b><i>a </i>is cured along a good quality crystal formed on a lower portion of the polycrystalline silicon layer <b>403</b><i>a. </i>

0067As shown in <figref idref="DRAWINGS">FIG. 4E</figref>, the cured polycrystalline silicon layer <b>403</b><i>a </i>is patterned to form the semiconductor layer <b>403</b><i>b. </i>

0068More particularly described, the crystallized polycrystalline silicon layer <b>403</b><i>a </i>is patterned to form a semiconductor layer <b>403</b><i>b</i>. An inorganic insulating film such as silicon nitride (SiN_x) or silicon oxide (SiO_x) may be deposited on the entire surface including the semiconductor layer <b>403</b><i>b </i>to form a first insulating film <b>404</b>.

0069Then, the conductive material such as aluminum (Al) or Al alloy is deposited on the entire surface including the first insulating film <b>404</b> and patterned by a photolithography process to form a gate electrode <b>405</b> on a predetermined portion on the semiconductor layer <b>403</b><i>b. </i>

0070An impurity is implanted into the semiconductor layer <b>403</b><i>b </i>by using the gate electrode <b>405</b> as a mask to form source/drain regions. Here, the semiconductor layer which is masked by the gate electrode <b>405</b> and wherein ions are not implanted becomes a channel region.

0071After ions are implanted, an inorganic insulating film is deposited on the entire surface including the gate electrode <b>405</b> to form a second insulating film <b>406</b>. The second insulating film <b>406</b> and the first insulating film <b>404</b> are selectively removed so that a contact holes is formed through which a predetermined portion of the source/drain region is exposed.

0072Then, the conductive material such as aluminum (Al) or Al alloy is deposited on the second insulating film <b>406</b> through the contact holes and patterned by the photolithography process to form a source electrode <b>407</b> and drain electrode <b>408</b> connected to source/drain regions through the contact hole.

0073Finally, after a passivation film <b>409</b> is deposited on the formed source electrode <b>407</b> and the drain electrode <b>408</b>, a pixel electrode <b>410</b> is formed on the passivation film <b>409</b>.

0074Accordingly, the semiconductor layer <b>403</b><i>b </i>formed by the above-mentioned method has grains which are large and thin so that electrical characteristics are improved.

0075In other words, as described above, according to the polycrystalline silicon TFT fabrication method of the present invention, the amorphous silicon layer is deposited thickly and crystallized to enlarge the size of its grains so that the characteristic of the device is improved.

0076In addition, according to the polycrystalline silicon TFT fabrication method of the present invention, a polycrystalline silicon layer is formed and etched to be thin so that the leakage current is prevented from increasing which is caused when polycrystalline silicon layer is thick. The polycrystalline silicon layer is formed to be thin so that the gate metal line is short despite a high aspect ratio.

0077It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.