Field-effect transistor

BACKGROUND OF THE INVENTION

0001(1) Field of the Invention

0002The present invention relates to a field-effect transistor, and in particular, to a process of manufacturing the field-effect transistor that operates with stability, which allows the transistor to be miniaturized.

0003(2) Description of the Related Art

0004As a field-effect transistor (hereinafter to be referred to as “FET”), a gallium arsenide field-effect transistor (hereinafter to be referred to as “GaAs FET”) as disclosed in Japanese Laid-Open Patent Application No. 6-163604 can be taken as an example. <figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of a structure of the GaAs FET described in the patent literature as mentioned above.

0005In the GaAs FET, a mesa <b>141</b> having a channel layer (i.e. active layer) is formed on a semi-insulating substrate <b>140</b>, while a gate electrode <b>142</b>, a source electrode <b>143</b> and a drain electrode <b>144</b> are formed on the mesa <b>141</b>.

0006<figref idref="DRAWINGS">FIG. 2</figref> is a top view of the GaAs FET having the structure as described above.

0007The GaAs FET is a multi-finger FET in which plural unit FETs are electrically connected in parallel. Such GaAs FET has a wiring layout in which the finger portions of the respective source electrode <b>143</b> and drain electrode <b>144</b> are positioned opposite each other so as to interdigitate, and the finger portions of the comb-shaped gate electrode <b>142</b> are formed between the source electrode <b>143</b> and the drain electrode <b>144</b>.

0008In the GaAs FET having the wiring layout as shown in <figref idref="DRAWINGS">FIG. 6</figref>, it is necessary to reserve a space outside the transistor for forming a common portion (a part A indicated by a dotted line in <figref idref="DRAWINGS">FIG. 2</figref>) that is a base part of the finger portions of the gate electrode <b>142</b>. Therefore, it is difficult to reduce the chip size of such GaAs FET.

0009The respective structures shown in <figref idref="DRAWINGS">FIGS. 3A</figref>, <b>3</b>B, <b>3</b>C and <b>3</b>D are some examples (see reference to Japanese Laid-Open Patent Application No. 2005-72671) of the conventional GaAs FET that solves the above problem. <figref idref="DRAWINGS">FIG. 3A</figref> is an outer view of the GaAs FET and <figref idref="DRAWINGS">FIG. 3B</figref> is a top view of the GaAs FET, while <figref idref="DRAWINGS">FIG. 3C</figref> is a cross-sectional view of the GaAs FET at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 3A</figref> and <figref idref="DRAWINGS">FIG. 3D</figref> is a cross-sectional view of the GaAs FET at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 3A</figref>.

0010In such GaAs FET, a GaAs epitaxial layer <b>132</b>, a GaAs layer <b>133</b> that is to become an operating layer, a AlGaAs layer <b>134</b> that is to become a carrier supplying layer, and an n-type GaAs layer <b>135</b> that is to become a contact layer with low resistance are sequentially stacked on a substrate <b>131</b> that is made of semi-insulating GaAs. Here, the source electrode <b>123</b> and the drain electrode <b>124</b> are formed on the n-type GaAs layer <b>135</b> while the gate electrode <b>122</b> is formed on the AlGaAs layer <b>134</b>. The mesa <b>121</b> is made up of the GaAs epitaxial layer <b>132</b>, the GaAs layer <b>133</b>, the AlGaAs layer <b>134</b> and the n-type GaAs layer <b>135</b>.

0011The GaAs FET has a wiring layout in which finger portions <b>123</b><i>a </i>and <b>124</b><i>a </i>of the respective comb-shaped source electrode <b>123</b> and drain electrode <b>124</b> are positioned opposite each other so as to interdigitate and the gate electrode <b>122</b> is formed in meandering-shape between the drain electrode <b>123</b> and the drain electrode <b>124</b>.

0012Here, the finger portions <b>123</b><i>a </i>and <b>124</b><i>a </i>of the respective source electrode <b>123</b> and drain electrode <b>124</b>, and a straight portion <b>122</b><i>a </i>of the gate electrode <b>122</b> are formed on the mesa <b>121</b>. The common portions <b>123</b><i>b </i>and <b>124</b><i>b </i>of the finger portions <b>123</b><i>a </i>and <b>124</b><i>a </i>of the respective source electrode <b>123</b> and drain electrode <b>124</b>, and a corner portion <b>122</b><i>b </i>of the gate electrode <b>122</b> are formed on the substrate <b>131</b>.

0013The GaAs FET having the structure as described above has a wiring layout in which the meandering gate electrode <b>122</b> is formed between the source electrode <b>123</b> and the drain electrode <b>124</b>. Therefore, it is possible to eliminate the common portions of the gate electrode <b>122</b>, so that the GaAs FET that allows the reduction of the chip size can be realized.

0014According to the GaAs FET having the above structure, the corner portion <b>122</b><i>b </i>of the gate electrode <b>122</b> is not formed on the mesa <b>121</b> that includes a channel layer. Thus, it is possible to prevent the part located below the corner portion <b>122</b><i>b </i>of the gate electrode <b>122</b>, that is, the part that does not operate as a stable FET, from operating as a FET. As a result, it is possible to realize the GaAs FET that can operate, as a whole, with stability, so as to obtain desired characteristics.

SUMMARY OF THE INVENTION

0015According to the conventional GaAs FET, since the finger portions <b>123</b><i>a </i>and <b>124</b><i>a </i>of the source electrode <b>123</b> and the drain electrode <b>124</b> are formed on the GaAs layer <b>135</b> of the mesa <b>121</b>, a metallic-metallic bond is formed between the finger portions <b>123</b><i>a </i>and <b>124</b><i>a</i>, and the semiconductor layer, so that an ohmic junction is formed. Since the common portions <b>123</b><i>b </i>and <b>124</b><i>b </i>of the source electrode <b>123</b> and the drain electrode <b>124</b> are formed on the substrate <b>131</b>, a metallic-semiconductor junction is formed between the common portions <b>123</b><i>b </i>and <b>124</b><i>b</i>, and the semiconductor layer, so that a Schottky junction is formed. With the Schottky junction formed between the source electrode <b>123</b> and the semiconductor layer, in the case where a potential difference is generated between the drain and the source, the electrons move from the source side to the drain side. As a result, a leakage current flows (i.e. side gate effect). The conventional GaAs FET, therefore, degrades field-effect transistor characteristics. More precisely, the electrons that have moved to the drain side prevent a depletion layer from being enlarged, which causes degradation of various high-frequency characteristics such as insertion loss, isolation and the like. In order to reduce such side gate effect, it is necessary to maintain a certain distance between drain and source. This prevents the miniaturization of the transistor.

0016The present invention is conceived in view of the above problem, and an object of the present invention is to provide a small field-effect transistor that can reduce degradation of the field-effect transistor characteristics.

0017In order to achieve the above object, the field-effect transistor according to the present invention includes: a substrate; a mesa which is formed on the substrate and includes a channel layer; and a source electrode, a drain electrode and a gate electrode which are formed on the mesa, the source and drain electrodes respectively being formed in comb-shape, and the gate electrode being formed in meandering-shape; wherein, on the mesa, a top-surface pattern in which respective finger portions of the source electrode and the drain electrode are positioned opposite each other so as to interdigitate, and the gate electrode is formed between the source electrode and the drain electrode is formed, common portions, each being a base part of the finger portions of the source and drain electrodes, are formed on the mesa, and in the gate electrode, a part located below a straight portion which is parallel to the finger portions is electrically separated from a part located below a corner portion that connects the neighboring straight portions. The part located below the corner portion of the gate electrode in said mesa may not function as a transistor. A trench may be formed in the mesa, cutting across the channel layer, and the corner portion of the gate electrode may be formed in the trench. A high-resistance region may be formed in the mesa, cutting across the channel layer, and the corner portion of the gate electrode may be formed on the high-resistance region.

0018Thus, the gate electrode is to be formed in meandering shape, which enables reduction of the size of chip. Both of the finger portions and the common portions of the source electrode and the drain electrode are formed on the mesa, so that it is possible to eliminate the side gate effects and reduce the degradation of field-effect transistor characteristics. The elimination of the side gate effects simultaneously encourages the shortening the drain-source distance and thereby realizes the miniaturization of the GaAs FET. That is to say that it is possible to realize a small field-effect transistor that can reduce the degradation of field-effect transistor characteristics.

0019It is also possible to stabilize the operation of the field-effect transistor since the lower part of the straight portion of the gate electrode is separated from the lower part of the corner portion of the gate electrode due to the trench or high-resistance region so that the transistor located in the corner portion of the gate electrode stops its operation.

0020The mesa may have a layer structure in which a buffer layer, the channel layer, a carrier supplying layer, a Schottky layer and a contact layer are sequentially stacked, the trench may be formed by etching which is performed on the contact layer so that the buffer layer is exposed, the finger portions and the common portions of the respective source and drain electrodes may be formed on the contact layer, and the corner portion of the gate electrode may be formed on the buffer layer which is exposed as a result of the formation of the trench. The mesa may have a layer structure in which the buffer layer, the channel layer, the carrier supplying layer, the Schottky layer and the contact layer are sequentially stacked, the high-resistance region may be formed, reaching the buffer layer, by implantation of impurities onto the contact layer, the common portions and the finger portions of the source and drain electrodes may be formed on the contact layer, and the corner portion of the gate electrode may be formed on the high-resistance region which is partly formed in the contact layer.

0021Thus, it is possible to realize a small HEMT that can reduce the degradation of field-effect transistor characteristics. It is also possible to realize an HEMT that can operate with stability.

0022The finger portions and the common portions of the source and drain electrodes may be formed so that the surface of the finger portions flush with the surface of the common portions.

0023Thus, it is possible to realize a field-effect transistor that requires low cost due to the simple manufacturing of the transistor.

0024A top surface of the substrate may be at a (100) basal plane, and an angle θ formed between a direction of the straight portion of the gate electrode and a direction <0-1-1> of the substrate may be 45 degrees.

0025Thus, it is possible to prevent the variation in threshold voltages of the field-effect transistor due to piezo effect, and thereby to stabilize the field-effect transistor characteristics.

0026As described above, the field-effect transistor according to the present invention, it is possible to reduce the chip size. The degradation of the field-effect transistor characteristics due to the side gate effect caused in the source electrode or drain electrode can be reduced. Namely, it is possible to realize a small field-effect transistor that can reduce the degradation of the field-effect transistor characteristics. Moreover, instability of the operation due to the difference in the direction in which the gate electrode is placed can be overcome, so that it is possible to stabilize the field-effect transistor characteristics.

Further Information about Technical Background to this Invention

0027The disclosure of Japanese Patent Application No. 2004-221568 filed on Jul. 29, 2004, including specification, drawings and claims is incorporated herein by reference in its entirety.

BRIEF DESCRIPTION OF THE DRAWINGS

0028These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the invention. In the Drawings:

0029<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of the GaAs FET described in Japanese Laid-Open Patent Application No. 6-163604;

0030<figref idref="DRAWINGS">FIG. 2</figref> is a top view of the conventional GaAs FET;

0031<figref idref="DRAWINGS">FIG. 3A</figref> is an outer view of the conventional GaAs FET;

0032<figref idref="DRAWINGS">FIG. 3B</figref> is a top view of the conventional GaAs FET;

0033<figref idref="DRAWINGS">FIG. 3C</figref> is a cross-sectional view, at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 3A</figref>, of the conventional GaAs FET;

0034<figref idref="DRAWINGS">FIG. 3D</figref> is a cross-sectional view, at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 3A</figref>, of the conventional GaAs FET;

0035<figref idref="DRAWINGS">FIG. 4A</figref> is an outer view of a GaAs FET according to a first embodiment of the present invention;

0036<figref idref="DRAWINGS">FIG. 4B</figref> is a top view of the GaAs FET according to the first embodiment;

0037<figref idref="DRAWINGS">FIG. 4C</figref> is a cross-sectional view, at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 4A</figref>, of the GaAs FET according to the first embodiment;

0038<figref idref="DRAWINGS">FIG. 4D</figref> is a cross-sectional view, at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 4A</figref>, of the GaAs FET according to the first embodiment;

0039<figref idref="DRAWINGS">FIGS. 5(</figref><i>a</i>) through <b>5</b>(<i>e</i>) are cross-sectional views of the GaAs FET according to the first embodiment for describing a manufacturing method of the GaAs FET according to the first embodiment;

0040<figref idref="DRAWINGS">FIG. 6A</figref> is an outer view of the GaAs FET according to a second embodiment of the present invention;

0041<figref idref="DRAWINGS">FIG. 6B</figref> is a top view of the GaAs FET according to the second embodiment;

0042<figref idref="DRAWINGS">FIG. 6C</figref> is a cross-sectional view, at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 6A</figref>, of the GaAs according to the second embodiment;

0043<figref idref="DRAWINGS">FIG. 6D</figref> is a cross-sectional view, at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 6A</figref>, of the GaAs FET according to the second embodiment; and

0044<figref idref="DRAWINGS">FIGS. 7(</figref><i>a</i>) through <b>7</b>(<i>e</i>) are cross-sectional views of the GaAs FET according to the second embodiment for describing the manufacturing method of the GaAs FET.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

0045The following describes the GaAs FET according to the embodiments of the present invention, with reference to the diagrams.

First Embodiment

0046<figref idref="DRAWINGS">FIG. 4A</figref> shows an outer view of the GaAs FET according to the present embodiment and <figref idref="DRAWINGS">FIG. 4B</figref> shows a top view of the GaAs FET, while <figref idref="DRAWINGS">FIG. 4C</figref> shows a cross-sectional view of the GaAs FET, at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 4A</figref>, and <figref idref="DRAWINGS">FIG. 4D</figref> shows a cross-sectional view of the GaAs FET at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 4A</figref>.

0047The GaAs FET is comprised of a substrate <b>31</b> made of semi-insulating GaAs, and an epitaxial layer <b>30</b> formed by mesa separation due to an element separation region after a semiconductor layer is grown by crystal growth on the substrate <b>31</b>. The epitaxial layer <b>30</b> includes the following layers which are sequentially stacked: a buffer layer <b>332</b> which has a thickness of 1 μm and is made of undoped GaAs, for alleviating lattice mismatch between the epitaxial layer <b>30</b> and the substrate <b>31</b>,; a buffer layer <b>33</b> made of undoped AlGaAs; a channel layer <b>34</b> which is made of undoped In_0.2Ga_0.8As with a thickness of 20 nm, and in which carriers run; a spacer layer <b>35</b> made of undoped AlGaAs with a thickness of 5 nm; a carrier supplying layer <b>36</b> made of AlGaAs resulted from planar doping performed only on one atomic layer of Si being an n-type impurity ion; a Schottky layer <b>37</b> made of undoped AlGaAs with a thickness of 30 nm; a contact layer <b>38</b> made of n⁺-type GaAs with a thickness of 100 nm. Here, the source electrode <b>13</b> and the drain electrode <b>14</b> are formed on the contact layer <b>38</b>. In the area between the source electrode <b>13</b> and the drain electrode <b>14</b>, etching is performed on the contact layer <b>38</b> so that the surface of the Schottky layer <b>37</b> is exposed as a surface of the epitaxial layer <b>30</b>, the gate electrode <b>12</b> is formed on the Schottky layer <b>37</b> that is thus exposed.

0048The GaAs FET is a multi-finger FET in which plural unit FETs are connected electrically and in parallel, and has a layout in which the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>of the comb-shaped source electrode <b>13</b> and drain electrode <b>14</b> are placed opposite each other so as to interdigitate, and one gate electrode <b>12</b> is formed in meandering shape between the source electrode <b>13</b> and the drain electrode <b>14</b>. That is to say that the GaAs FET has a layout in which each finger portion <b>13</b><i>a </i>of the source electrode <b>13</b> and each finger portion <b>14</b><i>a </i>of the drain electrode <b>14</b> are placed one after the other, and the finger portions <b>13</b><i>a </i>of the source electrode <b>13</b> are connected to the common portion <b>13</b><i>b </i>that is a base part of the finger portions <b>13</b><i>a</i>, while the finger portions <b>14</b><i>a </i>of the drain electrode <b>14</b> are connected to the common portion <b>14</b><i>b </i>that is a base part of the finger portions <b>14</b><i>a. </i>

0049The followings are formed on the mesa <b>11</b>: the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>as well as the common portions <b>13</b><i>b </i>and <b>14</b><i>b </i>of the respective source electrode <b>13</b> and drain electrode <b>14</b>; the straight portion <b>12</b><i>a </i>of the gate electrode <b>12</b> that is almost in parallel to the finger portion <b>13</b><i>a</i>; and the corner portion <b>12</b><i>b </i>which connects the neighboring straight portions <b>12</b><i>a. </i>

0050The mesa <b>11</b> is formed by the buffer layers <b>32</b> and <b>33</b>, the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b>. Since the direction of the gate electrode <b>12</b> is different between the corner portion <b>12</b><i>b </i>and the straight portion <b>12</b><i>a</i>, variation in threshold voltages of the field-effect transistor is generated due to piezo effect, which causes instability of the FET characteristics. Therefore, in the part located below the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> in the mesa <b>11</b>, a gate electrode separation trench <b>15</b> is formed by etching so that it reaches the buffer layer <b>33</b> across the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b>. The part located below the corner portion <b>12</b><i>b </i>is electrically separated from the part located below the straight portion <b>12</b><i>a</i>, and therefore, does not function as a transistor. The top surface of the substrate <b>31</b> is at a (100) basal plane, and a direction of the straight portion <b>12</b><i>a </i>of the gate electrode <b>12</b> (direction A in <figref idref="DRAWINGS">FIG. 4A</figref>) is adjusted to make every angle θ formed between the direction of the straight portion <b>12</b><i>a </i>of the gate electrode and the direction <0-1-1> of the substrate to be 45 degrees.

0051The following describes the method of manufacturing the GaAs FET having the structure as described above, with reference to the diagrams.

0052<figref idref="DRAWINGS">FIGS. 5(</figref><i>a</i>) through <b>5</b>(<i>e</i>) are cross-sectional views of the GaAs FET.

0053Firstly, the epitaxial layer <b>30</b> is formed on the substrate <b>31</b> by sequentially growing, with the use of an MOCVD method or an MBE method, the buffer layers <b>32</b> and <b>33</b>, the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b> (see <figref idref="DRAWINGS">FIG. 5(</figref><i>a</i>)).

0054Then, a predetermined place is protected by forming a pattern using a photo resist <b>51</b>. Wet etching using, for example, a solution of phosphoric acid, oxygenerated water and water, is performed on the epitaxial layer <b>30</b> so that predetermined areas of the contact layer <b>38</b>, the Schottky layer <b>37</b>, the carrier supplying layer <b>36</b>, the spacer layer <b>35</b>, the channel layer <b>34</b>, and the buffer layer <b>33</b> are removed and an element separation region and a gate electrode separation trench <b>15</b> are formed (see <figref idref="DRAWINGS">FIG. 5(</figref><i>b</i>)).

0055After the removal of the photo resist <b>51</b>, a pattern is formed using another photoresist, an ohmic metal made of metal composed of Ni, Au and Ge is vapor-deposited all over the surface of the epitaxial layer <b>30</b>, and by lifting it off, the drain electrode <b>14</b> and the source electrode <b>13</b> are formed (see <figref idref="DRAWINGS">FIG. 5(</figref><i>c</i>)).

0056After the formation of the photo resist <b>52</b>, an opening is formed by performing recess etching onto a predetermined area of the contact layer <b>38</b> between the source electrode <b>13</b> and the drain electrode <b>14</b> (see <figref idref="DRAWINGS">FIG. 5(</figref><i>d</i>)). Note that dry etching that uses a mixed gas made of SiCl₄, SF₆, and N₂is also effective in removing the contact layer <b>38</b> selectively and in different direction with respect to the Schottky layer <b>37</b>, so that it is possible to form a tiny opening in the pattern based on this method.

0057Lastly, a gate metal made of a metal, for instance, of Ti, Pt and Au is vapor-deposited all over the epitaxial layer <b>30</b>, and by lifting it off, the gate electrode <b>12</b> is formed on the Schottky layer <b>37</b> whose opening is exposed, and the buffer layer <b>33</b> where the gate electrode separation trench <b>15</b> is exposed (see <figref idref="DRAWINGS">FIG. 5(</figref><i>e</i>)).

0058As described above, according to the GaAs FET of the present embodiment, the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>as well as the common portions <b>13</b><i>b </i>and <b>14</b><i>b </i>of the source electrode <b>13</b> and the drain electrode <b>14</b> are both formed on the mesa <b>11</b>, and an ohmic junction is formed between the GaAs FET and the semiconductor layer. Therefore, the side gate effects can be eliminated, and degradation of the field-effect transistor characteristics can be reduced. The elimination of the side gate effects can simultaneously reduce the drain-source distance, and thereby, it is possible to miniaturize the GaAs FET.

0059According to the GaAs FET of the present embodiment, the part located below the straight portion <b>12</b><i>a </i>of the gate electrode <b>12</b> is separated from the part located below the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b>, so that the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> does not function as a gate of the transistor. That is to say, the operation of the transistor that is placed in the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> is stopped. Therefore, it is possible to allow the field-effect transistor to operate with stability.

Second Embodiment

0060<figref idref="DRAWINGS">FIG. 6A</figref> shows an outer view of the GaAs FET of the present embodiment and <figref idref="DRAWINGS">FIG. 6B</figref> shows a top view of the GaAs FET, while <figref idref="DRAWINGS">FIG. 6C</figref> shows a cross-sectional view of the GaAs FET at the line b-b′ shown in <figref idref="DRAWINGS">FIG. 6A</figref> and <figref idref="DRAWINGS">FIG. 6D</figref> shows a cross-sectional view of the GaAs FET at the line a-a′ shown in <figref idref="DRAWINGS">FIG. 6A</figref>.

0061The GaAs FET is comprised of a substrate <b>31</b> and an epitaxial layer <b>30</b>. The epitaxial layer <b>30</b> is structured by sequentially stacking the buffer layers <b>32</b> and <b>33</b>, the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b>. Here, the source electrode <b>13</b> and the drain electrode <b>14</b> are formed on the contact layer <b>38</b>. In the area between the source electrode <b>13</b> and the drain electrode <b>14</b>, etching is performed on the contact layer <b>38</b> so that the surface of the Schottky layer <b>37</b> is exposed as a surface of the epitaxial layer <b>30</b>, and the gate electrode <b>12</b> is formed on the Schottky layer <b>37</b> thus exposed.

0062The GaAs FET is a multi-finger FET in which plural unit FETs are connected electrically and in parallel, and has a layout in which the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>of the comb-shaped source electrode <b>13</b> and drain electrode <b>14</b> are placed opposite each other so that the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>interdigitate, and one gate electrode <b>12</b> is formed in meandering shape between the source electrode <b>13</b> and the drain electrode <b>14</b>.

0063The followings are formed on the mesa <b>11</b>: the finger portions <b>13</b><i>a </i>and <b>14</b><i>a </i>as well as the common portions <b>13</b><i>b </i>and <b>14</b><i>b </i>of the respective source electrode <b>13</b> and drain electrode <b>14</b>; and the straight portion <b>12</b><i>a </i>of the gate electrode <b>12</b> that is almost in parallel to the finger portion <b>13</b><i>a</i>; and the corner portion <b>12</b><i>b </i>which connects the neighboring straight portions <b>12</b><i>a. </i>

0064The mesa <b>11</b> has a layer structure in which the buffer layers <b>32</b> and <b>33</b>, the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b> are sequentially stacked. Here, in the part located below the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> in the mesa <b>11</b>, a high-resistance region <b>16</b>, which cuts across the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b> and reaches the buffer layer <b>33</b>, is formed. The part located below the corner portion <b>12</b><i>b </i>is electrically separated from the part located below the straight portion <b>12</b><i>a</i>, and therefore, does not function as a transistor. The high-resistance region <b>16</b> is formed by performing ion implantation onto the epitaxial layer <b>30</b> with impurities such as oxygen (O), boron (B) and helium (He) and destroying crystallizability of the epitaxial layer <b>30</b> so as to make the epitaxial layer <b>30</b> partly high-resistant.

0065The following describes the method of manufacturing the GaAs FET that has the structure as described above, with reference to the diagrams.

0066<figref idref="DRAWINGS">FIGS. 7(</figref><i>a</i>) through <b>7</b>(<i>e</i>) are cross-sectional views of the GaAs FET.

0067The epitaxial layer <b>30</b> is formed on the substrate <b>31</b> by sequentially growing, by epitaxial growth with the use of an MOCVD method or an MBE method, the buffers <b>32</b> and <b>33</b>, the channel layer <b>34</b>, the spacer layer <b>35</b>, the carrier supplying layer <b>36</b>, the Schottky layer <b>37</b> and the contact layer <b>38</b> (see <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>)).

0068Wet etching using, for example, a solution of phosphoric acid, oxygenerated water and water, is performed on the epitaxial layer <b>30</b> so that an element separation region is formed. After that, a predetermined place is protected by forming a pattern by a photo resist <b>53</b>, and then, a high-resistance region <b>16</b> is formed, reaching the buffer layer <b>33</b> located lower than the channel layer <b>34</b>, by ion implanting, e.g, with boron, a predetermined area of the contact layer <b>38</b>, Schottky layer <b>37</b>, the carrier supplying layer <b>36</b>, the spacer layer <b>35</b>, the channel layer <b>34</b> and the buffer layer <b>33</b> (see <figref idref="DRAWINGS">FIG. 7(</figref><i>b</i>)).

0069Then, after the removal of the photoresist <b>53</b>, a pattern is formed using another photoresist, an ohmic metal made of metal composed of Ni, Au and Ge is vapor-deposited all over the surface of the epitaxial layer <b>30</b>, and by lifting it off, the drain electrode <b>14</b> and the source electrode <b>13</b> are formed (see <figref idref="DRAWINGS">FIG. 7(</figref><i>c</i>)).

0070After the formation of the photo resist <b>54</b>, an opening is formed by performing recess etching onto a predetermined area of the contact layer <b>38</b> between the source electrode <b>13</b> and the drain electrode <b>14</b> (see <figref idref="DRAWINGS">FIG. 7(</figref><i>d</i>)). Note that dry etching that uses a mixed gas made of SiCl₄, SF₆, and N₂is also effective in removing the contact layer <b>38</b> selectively and in different direction with respect to the Schottky layer <b>37</b>, it is possible to form a tiny opening in the pattern based on this method.

0071Lastly, a gate metal made of a metal, for instance, of Ti, Pt and Au is vapor-deposited all over the epitaxial layer <b>30</b>, and by lifting it off, the gate electrode <b>12</b> is formed on the high-resistance region <b>16</b> that is partly formed in the contact layer <b>38</b> (see <figref idref="DRAWINGS">FIG. 7(</figref><i>e</i>)).

0072As described above, the GaAs FET of the present embodiment, as is the case of the GaAs FET described in the first embodiment, can reduce the degradation of the field-effect transistor characteristics, and also, miniaturize the GaAs FET transistor.

0073According to the GaAs FET of the present embodiment, the straight portion <b>12</b><i>a </i>of the gate electrode <b>12</b> is separated from the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> by a high-resistance region <b>16</b> so that the corner portion <b>12</b><i>b </i>does not function as a transistor. That is to say, the operation of the transistor that is placed in the corner portion <b>12</b><i>b </i>of the gate electrode <b>12</b> is stopped. Therefore, it is possible to allow the field-effect transistor to operate with stability.

0074As described above, the FET according to the present invention is described based on the embodiments. The present invention, however is not limited to these embodiments. Variation of each embodiment that is conceivable by a skilled person within the scope of the present invention shall be included in the present invention.

0075For example, the FET according to the present invention may be a double-hetero FET.

INDUSTRIAL APPLICABILITY

0076The present invention is suitable for use as a FET, and especially as an RF amplifier, an oscillator, an electric amplifier or the like that uses the FET.