Method for forming metal silicide regions in an integrated circuit

FIELD OF THE INVENTION

0001The present invention relates to the field of semiconductor devices and device manufacturing, and more particularly, to the formation of low leakage self-aligned silicide (“salicide”) regions.

BACKGROUND OF THE INVENTION

0002After forming the individual device regions in a semiconductor substrate, the regions must be connected together to form an operative device that performs the desired circuit functions. This connection process is referred to as metallization and is performed using a number of different photolithographic and deposition techniques. The overall effectiveness of the metal interconnect system is governed by the resistivity, thickness, length and the total contact resistance of all the metal-region interconnects. The contact resistance at a metal-to-region interface is influenced by the materials employed, the substrate doping and the contact dimensions. The smaller the contact size, the higher the contact resistance. In modern semiconductor circuits the contact region is the dominant factor in the metal interconnect system performance.

0003One technique for forming a low contact resistance device employs a silicide layer on the device doped regions, such as the source/drain regions and polysilicon gate of a metal-oxide-semiconductor field effect transistor (MOSFET). This practice has become increasingly important for very high density devices where the feature size, and thus the contact area, is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity and the contact resistance of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop layer during subsequent processing steps.

0004A common technique employed in semiconductor manufacturing to form the suicide contact is self-aligned silicide (“salicide”) processing. Salicide processing involves the deposition of a metal that forms intermetallic bonds with the silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), tungsten (W), molybdenum (Mo) and nickel (Ni). Generally, refractory metals are used to form the silicide. These metals form low resistivity phases with silicon, such as TiSi₂, CoSi₂and NiSi.

0005To form the silicide, the metal is deposited with a uniform thickness across the entire semiconductor wafer, by for example, using a physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, direct current magnetron sputtering system. The deposition is performed after gate etch and source/drain junction formation. The deposited metal blankets the polysilicon gate electrode, the oxide spacers between the gate and the source/drain regions, and the oxide isolation regions between devices. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in <figref idref="DRAWINGS">FIG. 1</figref>.

0006As shown in <figref idref="DRAWINGS">FIG. 1</figref>, a n-type MOSFET <b>8</b> is formed within a silicon substrate <b>10</b>, comprising a p-type well <b>11</b>, lightly doped (n−) source/drain regions <b>12</b>/<b>14</b>, source/drain regions (n+) <b>16</b>/<b>18</b>, and a polysilicon gate <b>20</b> formed over a gate oxide <b>22</b>. Oxide spacers <b>24</b> are formed on the sides of the polysilicon (n+ type) gate electrode <b>20</b>. A refractory metal layer <b>30</b>, comprising cobalt, for example, is blanket deposited over the source/drain regions <b>16</b>/<b>18</b>, the polysilicon gate <b>20</b> and the spacers <b>24</b>. The metal layer <b>30</b> also blankets silicon dioxide isolation regions <b>32</b> that isolate adjacent devices.

0007A first rapid thermal anneal (RTA) is then performed at a temperature of between about 450° to 700° C. for a short period in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the top surface <b>33</b> of the metal <b>30</b>, while the metal reacts with the underlying silicon, forming a metal silicide. Hence, the reaction of the metal with the silicon forms a silicide region <b>40</b> within the gate <b>20</b> and silicide regions <b>41</b> within the source/drain regions <b>16</b>/<b>18</b>, as depicted in <figref idref="DRAWINGS">FIG. 2</figref>. Typically, about one-third of the underlying silicon is consumed during the formation of the metal silicide.

0008After the first rapid thermal anneal step, any unreacted metal is stripped away by a wet etch process that is selective to the metal silicide. The resultant structure is illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. The substrate <b>10</b> is subjected to a second, higher temperature rapid thermal anneal step, for example above 700° C., to change the stochiometry of the metal silicide, forming a lower resistance metal silicide by converting the higher resistivity metal silicide to a lower resistivity phase. For example, when the metal is cobalt, the higher resistivity phase is Co₂Si and the lowest resistivity phase is CoSi₂.

0009As described above, when the polysilicon and doped source/drain regions are both exposed to the metal, the silicide forms simultaneously over both regions. Thus, this method is described as a “salicide” process since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.

0010One of the concerns associated with cobalt silicide technologies is junction leakage, which occurs when cobalt silicide is formed such that it extends nearly to the bottom of the source/drain region <b>16</b>/<b>18</b>. The distance between the cobalt silicide layer <b>41</b> and the bottom of the source/drain region <b>16</b>/<b>18</b> is identified by a reference character <b>50</b> in <figref idref="DRAWINGS">FIG. 3</figref>. A cause of this problem is high silicon consumption during the silicide formation process. One solution for overcoming this problem is to make the doped source/drain regions <b>16</b>/<b>18</b> deeper. However, this is counter to the preferred extremely shallow source and drain regions that support device scaling. Also, the deeper device regions negatively impact device performance.

0011Leakage also occurs due to incomplete removal of the unreacted metal from the spacers <b>24</b> and the oxide isolation regions <b>32</b>. As a result, gate-to-substrate and region-to-region leakage currents flow through the unreacted metal. Also, prolonged anneal cycles, used to ensure reaction between the metal and the underlying silicon, can result in the formation of metal silicide ribbons on the surface of the silicon dioxide regions <b>32</b>, again creating a path for the flow of leakage currents.

0012It is known that the sheet resistance of the silicide layer <b>40</b>/<b>41</b> is an inverse function of the layer thickness. It is also known that the degree of roughness at the interface between the silicide layer <b>40</b>/<b>41</b> and the underlying silicon device region, such as the source/drain regions <b>16</b>/<b>18</b>, influences current leakage. To achieve a preferred sheet resistance, a thicker silicide layer may be required. However, if the silicide layer <b>41</b> is made too thick, the distance <b>50</b> decreases, thereby increasing the likelihood of leakage current flow between the source/drain regions <b>16</b>/<b>18</b> and the p-type well <b>11</b>. Further, increased roughness of the interface also increases leakage current. It is therefore advantageous to form a silicide layer with reduced surface roughness.

0013According to the prior art, a capping layer, for example a titanium layer, is formed over the cobalt layer before the first RTA step, to reduce the aforementioned surface roughness.

BRIEF SUMMARY OF THE INVENTION

0014According to the teachings of the present invention, both a titanium and a titanium nitride layer are formed over the metal layer before the substrate is processed through a RTA step.

0015A metal layer, such as cobalt, is deposited over the substrate surface, including over the gate and source/drain junctions. A titanium layer is formed over the metal layer and a titanium nitride layer is formed over the titanium layer. During the subsequent anneal step, the titanium nitride layer reduces the roughness of the silicide-silicon region interface. The titanium layer provides a gettering action for oxide that may be on the surface of the silicon region to reduce the formation of impurities in the silicide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

0016The present invention can be more easily understood and the further advantages and uses thereof more readily apparent, when considered in view of the following detailed description when read in conjunction with the following figures, wherein:

0017<figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b> and <b>3</b> are cross-sectional views of a semiconductor substrate during various prior art silicide processing steps; and

0018<figref idref="DRAWINGS">FIGS. 4 and 5</figref> are cross-sectional views of a semiconductor substrate during various processing steps in accordance with certain embodiments of the present invention.

0019In accordance with common practice, the various described features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Reference characters denote like elements throughout the figures and text.

DETAILED DESCRIPTION OF THE INVENTION

0020According to the teachings of the present invention, a capping layer over the metal layer comprises a relatively thin layer of titanium (for example on the order of a few Angstroms thick) and a relatively thicker layer of titanium nitride. Both material capping layers are formed before the substrate <b>10</b> undergoes the first RTA process.

0021The metal layer <b>30</b> is first deposited with a substantially uniform thickness over an upper surface <b>60</b> of the substrate <b>10</b>. See <figref idref="DRAWINGS">FIG. 4</figref>. Exemplary processes for forming the metal layer <b>30</b> include physical vapor deposition (PVD) from an ultra-pure metal sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, direct current magnetron sputtering system. The deposition is performed after both the gate and the source/drain regions have been formed. The deposited metal blankets the polysilicon gate electrode <b>20</b>, the oxide spacers <b>24</b>, the source/drain regions <b>16</b>/<b>18</b>, and the oxide isolation regions <b>32</b>.

0022A titanium layer <b>62</b> (or a layer comprised of another gettering material) is formed over the metal layer <b>30</b>. In one exemplary process, the substrate <b>10</b> enters a second chamber of the deposition tool, after which titanium is introduced to form the titanium layer <b>62</b>. Advantageously, both the titanium and the metal material are typically available within the same deposition tool, thus the substrate <b>10</b> is not exposed to ambient air between the formation of the metal layer <b>30</b> and formation of the titanium layer <b>62</b>. Finally, nitrogen is introduced into the chamber to form the titanium nitride layer <b>64</b>.

0023The substrate is then subjected to a first RTA process, conventionally carried out in a nitrogen ambient vacuum. As the metal layer is forming a silicide in the underlying silicon, the titanium atoms, which are smaller than the metal atoms, diffuse through the metal layer to the surface of the silicon, where they getter silicon dioxide that may be present on the silicon surface.

0024It is known that higher quality suicide regions are formed when the silicon surface is pristine, i.e., having minimal amount of silicon dioxide formed thereon. Since silicon dioxide forms rapidly in a standard atmosphere at room temperature, during the various wafer processing steps the silicon surface can become contaminated with silicon dioxide. For example, prior to the metal deposition the substrate is cleaned. After the cleaning step, the substrate is transported to a deposition tool. During transportation the substrate is subjected to the ambient atmosphere. Since the vacuum has been “broken,” conditions are favorable for the formation of silicon dioxide on the substrate surface. Most fabrication processes employ “close coupling” steps in the process to limit silicon dioxide formation, but close coupling requires an organized and efficient fabrication process and is not always achievable in an operational fabrication facility. Thus the use of gettering titanium is advantageous to remove the silicon dioxide from the silicon surface as the silicide is being formed. Formation of a relatively thin titanium layer also prevents the titanium from substantially competing with the metal for the silicon atoms, thus limiting the amount of titanium silicide that is formed.

0025During the first RTA process, the titanium nitride <b>64</b> interacts with the metal silicide to produce a smoother surface at the interface between the metal silicide layer <b>41</b> and the source/drain regions <b>16</b>/<b>18</b>, (referred to by reference character <b>70</b> in <figref idref="DRAWINGS">FIG. 5</figref>) and the silicide layer <b>40</b> and the gate electrode <b>20</b> (referred to by reference character <b>72</b> in <figref idref="DRAWINGS">FIG. 5</figref>). This is due, at least in part, to a more uniform grain boundary growth promoted by the titanium nitride at the interface between the metal silicide and the underlying silicon or polysilicon region.

0026The substrate is then subjected to a wet cleaning process to remove the titanium nitride layer <b>64</b>, the titanium layer <b>62</b> and the unreacted metal overlying the silicon dioxide spacers <b>24</b> and the silicon dioxide isolation regions <b>32</b>. The final form of the substrate is illustrated in <figref idref="DRAWINGS">FIG. 5</figref>.

0027An architecture and process have been described as useful for forming a metal silicide layer in a semiconductor substrate. While specific applications and examples of the invention have been illustrated and discussed, the principals disclosed herein provide a basis for practicing the invention in a variety of ways and in a variety of circuit structures. Numerous variations are possible within the scope of the invention. The invention is limited only by the claims that follow.