LMS-based adaptive pre-distortion for enhanced power amplifier efficiency

RELATED APPLICATIONS

0001This application is a Continuation application of U.S. patent application Ser. No. 10/704,439, filed Nov. 7, 2003. The contents are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

0002This invention relates generally to communication systems and, more particularly, to pre-distortion circuitry for use with power amplifiers.

BACKGROUND

0003Many types of communication systems use a power amplifier as part of the front end of a transmitter for transmitting RF signals. In some systems, a low noise amplifier (LNA) at the front end of a receiver may be used for receiving RF signals. However, a power amplifier has non-linear distorting characteristics that can cause distortion of the information signal being amplified. The non-linear distorting characteristics of the power amplifier can impact the instantaneous amplitude and phase of the signal significantly. Furthermore, non-linearity within the RF components can introduce distortion in the signal and reduced SNR or poorer performance at the receiver. In wireless systems, non-linearity in the power amplifier at transmission can introduce intermodulation distortion which can result in spectral emissions in the adjacent channels. Typically, tight specifications in terms of spectral masks are provided by Standards Committees and/or Government bodies, which put a maximum limit to such spurious, out-of-band emissions for compliant transceivers. Therefore, it is desirable to provide a linear signal out of the power amplifier.

0004One type of method to linearize the power amplifier output signal is to “pre-correct” the signal being input to the amplifier, also known as pre-distortion. There are many known techniques are used to pre-correct an information signal in order to linearize the output of the amplifier. One of these techniques involves amplitude correction which produces a linear piece-wise pre-correction function which is correlated to the non-linear characteristics of the amplifier. The result is a piece-wise correction curve which approximates the ideal correction. The correction is then added to the information signal.

0005Pre-distortion has been almost exclusively in the baseband domain. The typical approach has been to apply a pre-distortion function at digital baseband. A relatively recent but commonly used approach has been to store the pre-distortion function as a look-up table which stores the gain and phase values as a function of the input signal envelope. The input signal is compared with the feedback signal from the power amplifier and certain metrics, such as ratio of in-band to out-of-band emission power and/or their correlation are used to adaptively map the look-up table with respect to the envelope of the input signal. Thus, the data path is simply a complex multiplication at digital baseband; the adapt-path (or feedback path) consists of a look-up table indexed by the input signal envelope and the adaptation metric is the ratio of in-band to out-of-band emission or the correlation between the feedback and the input signals. These operations are carried out at digital baseband.

0006However, increasing the linearity of the power amplifiers can reduce the power efficiency of the amplifiers, make them more voluminous, require more cooling equipment, and substantially increase the cost and form-factor of the transceivers. To improve the linearity of the transmission without resorting to a higher end and more expensive power amplifier, one method that has been carried out in the prior art is to perform pre-distortion on the transmitted signal before the signal is input into the power amplifier such that the pre-distortion equalizes in some sense the non-linear post-distortion of the amplifier. The pre-distortion may be carried out within an integrated circuit; however, a significant challenge has always been to be able to adaptively obtain the pre-distortion transfer function so as to be optimal in some metric. It is also desirable to have a tracking mechanism with the pre-distortion so that different temperature and aging effects are also compensated for.

0007Accordingly, it would be desirable to have systems and methods for performing pre-distortion in power amplifiers that overcome the disadvantages of the prior art as discussed.

SUMMARY

0008According to one aspect of the present invention, adaptive pre-distortion is performed using a least-mean square (LMS) method to adaptively obtain an optimal pre-distortion transfer function in the mean square error sense. In one embodiment, a LMS-based adaptive pre-distortion circuit coupled between an input signal to be transmitted and a non-linear power amplifier compares the input signal to a feedback signal from the power amplifier. The circuit adaptively reduces the least-mean square error between the two signals using both linear and non-linear filters and various feedback signals within the circuit. The result is an approximately linear output from the power amplifier. This technique can be used with single and multi-carrier transceivers, as well as with either a power amplifier (at the transmitter) or low noise amplifier (LNA) (at the receiver). The adaptive pre-distortion can be performed in the baseband domain or purely in the RF domain, using analog continuous-time or discrete-time signal processing.

0009According to one embodiment, an LMS-based adaptive pre-distortion (LAPD) circuit receives an input signal to be transmitted, such as from a baseband processor and RF circuitry, and a feedback signal from a power amplifier. The LAPD circuit adaptively minimizes a metric, such as an error signal, formed by the difference between the two signals. The LAPD circuit receives the input signal through an adaptive AGC circuit. The LAPD circuit further includes a feedforward filter, an adaptive coefficient generator, a slicer, timing control circuit, and slicer output time-align circuit. An error timing align circuit within the adaptive coefficient generator may be used to time align the input signal from the adaptive AGC circuit with the error signal e(t) or equalize delays between the input signal and the error signal. The error timing align circuit may receive as an input signal a feedback tap coefficient vector c or the error signal e(t). The timing control circuit time aligns or equalizes the delays between the input signal and the feedback signal from the power amplifier to compute an error signal, which is the time difference between the two signals. This error signal is iteratively reduced until a desired signal is obtained. The output signal is then input to the non-linear power amplifier, which amplifies the signal for transmission, resulting in a linearized output signal.

0010The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

0011<figref idref="DRAWINGS">FIG. 1</figref> shows a block diagram of a portion of a single-carrier transceiver with adaptive pre-distortion according to one aspect of the present invention;

0012<figref idref="DRAWINGS">FIG. 2</figref> shows a block diagram of a pre-distortion circuit for use in the transceiver of <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment;

0013<figref idref="DRAWINGS">FIG. 3A</figref> shows a more detailed block diagram of the pre-distortion circuit of <figref idref="DRAWINGS">FIG. 2</figref> according to one embodiment;

0014<figref idref="DRAWINGS">FIG. 3B</figref> shows one embodiment of the pre-distortion circuit of <figref idref="DRAWINGS">FIG. 3A</figref> with a more detailed feedforward filter and adaptive coefficient generator;

0015<figref idref="DRAWINGS">FIG. 4</figref> shows one embodiment of a feedforward filter in <figref idref="DRAWINGS">FIG. 3A</figref>;

0016<figref idref="DRAWINGS">FIG. 5</figref> shows one embodiment of an adaptive coefficient generator of <figref idref="DRAWINGS">FIG. 3A</figref>;

0017<figref idref="DRAWINGS">FIG. 5A</figref> shows one embodiment of a controllable delay in <figref idref="DRAWINGS">FIG. 5</figref>;

0018<figref idref="DRAWINGS">FIG. 5B</figref> shows one embodiment of an interpolation control circuit of <figref idref="DRAWINGS">FIG. 5A</figref>;

0019<figref idref="DRAWINGS">FIG. 5C</figref> shows one embodiment of an interpolation delay circuit of <figref idref="DRAWINGS">FIG. 5A</figref>;

0020<figref idref="DRAWINGS">FIG. 6</figref> shows one embodiment of a low pass filter block suitable for use in the system of <figref idref="DRAWINGS">FIG. 5</figref>;

0021<figref idref="DRAWINGS">FIG. 7</figref> shows one embodiment of a slicer input time align circuit for use in the system of <figref idref="DRAWINGS">FIG. 3A</figref>;

0022<figref idref="DRAWINGS">FIG. 7A</figref> shows one embodiment of an interpolating mixer circuit of <figref idref="DRAWINGS">FIG. 7</figref>;

0023<figref idref="DRAWINGS">FIG. 7B</figref> shows one embodiment of a phase detector circuit of <figref idref="DRAWINGS">FIG. 7</figref>;

0024<figref idref="DRAWINGS">FIG. 8</figref> shows one embodiment of a slicer output time align circuit for use in the system of <figref idref="DRAWINGS">FIG. 3A</figref>;

0025<figref idref="DRAWINGS">FIG. 8A</figref> shows one embodiment of a coefficient generator circuit of <figref idref="DRAWINGS">FIG. 8</figref>;

0026<figref idref="DRAWINGS">FIG. 8B</figref> shows one embodiment of a timing interpolation parameter signal generator circuit of <figref idref="DRAWINGS">FIG. 8</figref>;

0027<figref idref="DRAWINGS">FIG. 9</figref> shows a block diagram of a multi-carrier transceiver with adaptive pre-distortion according to one embodiment; and

0028<figref idref="DRAWINGS">FIG. 10</figref> show a block diagram of a multi-carrier pre-distortion circuit of <figref idref="DRAWINGS">FIG. 9</figref> according to one embodiment.

0029Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

0030<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a portion of an RF communication system <b>100</b> for transmitting RF signals. System <b>100</b> includes a baseband processor <b>102</b> as part of a single carrier transceiver that generates signals in baseband to be transmitted. These signals are input to one or more RF circuits <b>104</b> that translate the signals to the RF domain. A least-mean square (LMS) based adaptive pre-distortion (LAPD) circuit <b>106</b> processes the desired signal (x<b>1</b>) to be transmitted from RF circuits <b>104</b> and feedback signals (x<b>2</b>) from a single carrier power amplifier <b>108</b> to generate a pre-distorted signal to power amplifier <b>108</b>. LAPD circuit <b>106</b> adaptively pre-distorts the input signal such that after traveling through power amplifier circuit <b>108</b>, the signal is linear. Note that with conventional systems, LAPD circuit <b>106</b> is replace by a look-up table that compares the two input signals and assigns specific values to the signal for pre-distortion.

0031System <b>100</b> further includes a power coupler <b>110</b> that receives the output signal from power amplifier <b>108</b> and splits a portion of the input RF signal into the feedback path and passes the rest of the signal through to the antenna for transmission. The output signal from power coupler <b>110</b> is received by an amplitude control or controllable gain circuit <b>112</b>, which then scales the signal so that the signal input into LAPD circuit <b>106</b> is within an admissible range for operation of the LAPD circuit. Controllable gain circuit <b>112</b> feeds the signal back to LAPD circuit <b>106</b> for comparing with the desired signal to be transmitted. Power coupler <b>110</b>, after receiving the signal from power amplifier circuit <b>108</b>, sends the signal to an antenna <b>114</b> for transmission. After adaptive pre-distortion by LAPD circuit <b>106</b>, the signal from power amplifier circuit <b>108</b> is essentially linear.

0032<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of LAPD circuit <b>106</b> according to one embodiment of the invention. LAPD circuit <b>106</b> includes an adder <b>200</b> that calculates the difference between the input signal (x<b>1</b>) from RF circuits <b>104</b> and the feedback signal (x<b>2</b>) from power amplifier circuit <b>108</b>. Signal x<b>2</b> will sometimes be referred to as the feedback signal from power amplifier <b>108</b>. However, it is recognized that feedback signal x<b>2</b> may actually pass from power amplifier <b>108</b> through power coupler <b>110</b> and amplitude control circuit <b>112</b>. Thus, a feedback signal from the power amplifier or a low noise amplifier (or other non-linear element) can be any signal that passes through one or more circuit elements before entering LAPD circuit <b>106</b> and does not require a direct signal from the power amplifier to the LAPD circuit. The output signal e(t) of adder <b>200</b> (i.e., the difference or error signal) is input to an LAPD adaptpath circuit <b>202</b>, which provides adaptive tap coefficients or vector <u style="single">c</u> from the error signal e(t) and the input signal x<b>1</b>. Note that as used herein, adaptpath indicates circuitry that adaptively changes a signal. The tap coefficients <u style="single">c</u>, along with input signal x<b>1</b>, are then input to an LAPD datapath circuit <b>204</b>, which generates an pre-distorted signal z(t). LAPD datapath circuit <b>204</b> pre-distorts the signal based on a set of configuration parameters (or tap weights) which are controlled by LAPD adaptpath circuit <b>202</b> based on minimizing a certain metric, such as mean squared amplitude of the input signal into the LAPD and the amplitude control circuit output. The signal is then filtered through a bandpass filter <b>206</b> for transmission to the power amplifier. In one embodiment, bandpass filter <b>206</b> is part of LAPD circuit <b>106</b>, while in another embodiment, bandpass filter <b>206</b> is external to LAPD circuit <b>106</b>.

0033<figref idref="DRAWINGS">FIG. 3A</figref> is a more detailed block diagram of LAPD circuit <b>106</b> of <figref idref="DRAWINGS">FIGS. 1 and 2</figref> according to one embodiment. LAPD circuit <b>106</b> includes an adaptive automatic gain control (AGC) circuit <b>300</b> within LAPD adaptpath circuit <b>202</b>, which provides the necessary gain for small signals. Thus, after a signal is output from AGC circuit <b>300</b>, the signal is within a suitable range that allows the signal to be properly used throughout the rest of the circuit. Adaptive AGCs are known and any such suitable one can be used with the present invention to adaptively provide the proper gain. LAPD circuit <b>106</b> also includes a feedforward filter <b>302</b>, an adaptive coefficient generator <b>304</b>, an output signal slicer <b>306</b>, a timing control or time-align circuit <b>308</b>, and a slicer output time-align circuit <b>310</b>. Within LAPD circuit <b>106</b> is LAPD adaptpath circuit <b>202</b>, which includes adaptive coefficient generator <b>304</b>, an adder <b>318</b>, and an integrator, such as a low pass filter block <b>316</b>, and LAPD datapath circuit <b>204</b>, which includes adaptive AGC circuit <b>300</b>, feedforward filter <b>302</b>, timing control circuit <b>308</b>, output signal slicer <b>306</b>, slicer output time-align circuit <b>310</b>, an adder <b>312</b>, and a multiplier <b>314</b>.

0034Input signal x<b>1</b> is received by adaptive AGC circuit <b>300</b>. Feedforward filter <b>302</b> receives the output signal x<b>1</b>′ from adaptive AGC circuit <b>300</b> and tap coefficients from adaptive coefficient generator <b>304</b> and generates a pre-distorted signal, which is input to adder <b>312</b>. The other input to adder <b>312</b> is the product <b>314</b> of the output of low pass filter block <b>316</b>, and slicer output time-align circuit <b>310</b>.

0035The feedback signal (from product <b>314</b>) into adder <b>312</b> provides an iterative correction to an error signal e(t) for use by adaptive coefficient generator <b>304</b> to generate adaptive tap coefficients. The error signal, processing through adder <b>318</b>, is the difference between the output of timing control circuit <b>308</b> and input signal x<b>2</b> (the feedback signal from the power amplifier). As time passes, the error signal converges until a sufficiently small error signal is obtained through adaptively changing the tap coefficients.

0036<figref idref="DRAWINGS">FIG. 3B</figref> is a more detailed block diagram of LAPD circuit <b>106</b> according to one embodiment, in which adaptive coefficient generator <b>304</b> and feedforward filter <b>302</b> are shown in greater detail. Details will be discussed further below.

0037<figref idref="DRAWINGS">FIG. 4</figref> shows one embodiment of a feedforward filter suitable for use as feedforward filter <b>302</b> of <figref idref="DRAWINGS">FIG. 3A</figref>. The feedforward filter includes a series of signal delay elements <b>402</b>-<b>1</b> to <b>402</b>-N. Each delay element <b>402</b> delays the incoming signal by a fixed amount τ, e.g., x<b>1</b>′ (t−τ), x<b>1</b>′ (t−2τ), . . . x<b>1</b>′ (t−Nτ). The delay τ is typically selected to be less than a symbol period, and in one embodiment, is based on the symbol period T_sand the number of feedforward taps N as follows:

0038<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><mi>τ</mi><mo>=</mo><mfrac><msub><mi>T</mi><mi>s</mi></msub><mrow><mi>N</mi><mo>-</mo><mn>1</mn></mrow></mfrac></mrow></math></maths><img file="US7239203B2_D0001.tif" /><br /> The input data signal x<b>1</b>′ (t) and each successive delayed signal from delay elements <b>402</b>-<b>1</b> to <b>402</b>-N are multiplied by multipliers <b>404</b>-<b>1</b> to <b>404</b>-N with its respective adaptive coefficient signals from adaptive coefficient generator <b>304</b>. The product signals are then summed by an adder circuit <b>406</b> to form the pre-distorted signal.

0039<figref idref="DRAWINGS">FIG. 5</figref> shows one embodiment of an adaptive coefficient generator for use as adaptive coefficient generator <b>304</b> of <figref idref="DRAWINGS">FIG. 3A</figref>. The generator includes a controllable delay <b>500</b>, which receives input data signal x<b>1</b>′ (t) and the error signal e(t), and introduces a fixed delay into the signal. One type of controllable delay suitable for the present invention is an error timing control (ETC) and precursor/postcursor control (PPC) circuit, such as described in commonly-owned U.S. patent application Ser. No. 10/290,993, filed Nov. 8, 2002, entitled “Adaptive Signal Equalizer with Adaptive Error Timing and Precursor/Postcursor Configuration Control”, which is incorporated herein by reference in its entirety. The controllable delay in the present invention is used to align the error signal e(t) with the input signal x<b>1</b>′ (t). In one embodiment, the ETC/PPC circuit of the above referenced application is used to adaptively set the delay by using the error signal e(t) as a control input signal.

0040<figref idref="DRAWINGS">FIG. 5A</figref> shows one embodiment of controllable delay <b>500</b>. Controllable delay <b>500</b> includes an interpolation control stage <b>552</b> and an interpolation delay stage <b>554</b>. Interpolation control <b>552</b> processes the error signal coefficients to produce a set of delay interpolation control signals for interpolation stage <b>554</b>. In response to these delay interpolation control signals, interpolation delay stage <b>554</b> processes its input signal x<b>1</b>′ (t) to produce the corresponding delayed signal for processing by delay elements <b>502</b>.

0041<figref idref="DRAWINGS">FIG. 5B</figref> shows one embodiment of interpolation controller <b>552</b>. Interpolation controller <b>552</b> includes a set of signal multipliers <b>556</b>-<b>1</b> to <b>556</b>-N, a signal combining circuit <b>558</b>, a signal integration circuit (e.g., a low pass filter) <b>560</b>, and a signal complement circuit <b>562</b>, interconnected substantially as shown. Each of the error signal coefficient signals e₁to e_Nis multiplied in a respective multiplier <b>556</b>-<b>1</b> to <b>556</b>-N with a corresponding weighted or scaled signal K₁to K_N. In one embodiment, K₁, to K_N/2are equal to +1, while K_(N/2)+1to K_Nare equal to −1. The resulting product signals are summed in signal combiner <b>558</b>. The sum signal is integrated by signal integrator <b>560</b> to produce the primary delay interpolation control signal representing the timing control ratio parameter r. This delay interpolation control signal is also complemented by signal complement circuit <b>562</b> to provide the complement delay interpolation control signal. Signal complement circuit <b>562</b> processes the delay interpolation control signal by subtracting it from a normalized value (e.g., unity) to produce the complement signal. The uncomplemented and complemented signals are then processed by interpolation delay <b>554</b>.

0042<figref idref="DRAWINGS">FIG. 5C</figref> shows one embodiment of interpolation delay <b>554</b>. Interpolation delay <b>554</b> includes three signal delay elements <b>572</b>-<b>1</b>, <b>572</b>-<b>2</b>, and <b>572</b>-<b>3</b>. The incoming signal, i.e., the input signal x<b>1</b>′ (t), and the corresponding successively time-delayed versions are multiplied in signal multipliers <b>574</b>-<b>1</b>, <b>574</b>-<b>2</b>, <b>574</b>-<b>3</b>, and <b>574</b>-<b>4</b> with corresponding interpolation control signals. The resulting product signals are summed in a signal combiner <b>576</b> to produce the delayed version of the incoming signal.

0043Referring to <figref idref="DRAWINGS">FIG. 5</figref>, the aligned output signal of controllable delay <b>500</b> is processed through a series of delay elements <b>502</b>-<b>1</b> through <b>502</b>-N. Delay elements <b>502</b> introduce a delay of τ′ to its input signal. In one embodiment, τ′ is greater than the delay τ of delay elements <b>402</b> of <figref idref="DRAWINGS">FIG. 4</figref>, although it may also be suitable for τ′ to be approximately equal to τ in other embodiments. Having τ′>τ results in a generally more robust system. The delayed signals (by multiples of τ′) are input to respective low pass filter blocks <b>504</b>-<b>1</b> to <b>504</b>-N, along with the error signal e(t) from adder <b>318</b> of <figref idref="DRAWINGS">FIG. 3A</figref>. Low pass filter blocks <b>504</b> multiply each delayed signal with a corresponding error signal and integrate the result to generate individual tap coefficient signals for use by multipliers <b>404</b>-<b>1</b> to <b>404</b>-N of <figref idref="DRAWINGS">FIG. 4</figref>. <figref idref="DRAWINGS">FIG. 6</figref> shows one embodiment of low pass filter block <b>504</b>, which includes a multiplier circuit <b>600</b> and an integrator circuit, such as a low pass filter <b>602</b>.

0044In one embodiment, low pass filters <b>602</b> are analog (or continuous-time) first-order low-pass filters having a transfer function

0045<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mrow><mrow><mi>H</mi><mo>⁡</mo><mrow><mo>(</mo><mi>s</mi><mo>)</mo></mrow></mrow><mo>=</mo><mfrac><mi>G</mi><mrow><mn>1</mn><mo>+</mo><mrow><mi>s</mi><mo>·</mo><msub><mi>T</mi><mi>l</mi></msub></mrow></mrow></mfrac></mrow></math></maths><img file="US7239203B2_D0002.tif" /><br /> where G is the gain of the low pass filter and T₁is the leakage time constant. The filter parameters gain G and time constant T₁can be chosen to meet system and component requirements. For example, the time constant T₁is selected as a non-zero positive number for more robust performance with a fractionally-spaced feedforward filter at the front-end. The gain G should be large enough so that the mismatch of the tap coefficient with the least-mean square value at convergence is sufficiently small. Further, T₁>0 and G need to be moderate enough to minimize the effects of “tap coefficient drift”. Another factor in selecting gain G and time constant T₁is to achieve a convergence time that is sufficiently small for the system.

0046Selecting values for G and T₁depend on system requirements and include factors such as the maximum steady state mismatch of signals, time variability of the channel, amount of noise within the channel, and parasitic effects of the circuit. In one embodiment, the gain G may be set to 10 to 50 which will result in small mismatch and possibly stable operation. The time constant T₁is typically set to about 10,000 to 100,000 symbol times, in one embodiment. For very fast varying channels, T₁is much smaller. T₁is larger for channels having less temporal variations and more noise. Higher order low pass filters are also suitable for use with the present invention.

0047Referring back to <figref idref="DRAWINGS">FIG. 3A</figref>, similarly, low pass filter block <b>316</b> receives error signal e(t) from adder <b>318</b> and the output of slicer output time-align circuit <b>310</b>. These two signals are then multiplied and integrated by low pass filter block <b>316</b>.

0048<figref idref="DRAWINGS">FIG. 7</figref> shows one embodiment of a timing control circuit for use as timing control circuit <b>308</b> of <figref idref="DRAWINGS">FIG. 3A</figref>. The circuit includes a controllable delay, which receives the input data signal x<b>1</b>(t) and introduces a delay Δ into the signal. One type of controllable delay suitable for the present invention is an adaptive least mean square-based timing interpolation (ALTI) circuit, such as described in commonly-owned U.S. patent application Ser. No. 10/321,893, filed Dec. 17, 2002, entitled “Adaptive Signal Latency Control for Communications Systems Signals”, which is incorporated herein by reference in its entirety.

0049The controllable delay in the present invention is used to time align the input signal x<b>1</b> with the feedback signal x<b>2</b> from the power amplifier. As used herein, time align can also be described as equalizing the delays between two signals. In one embodiment, the ALTI circuit of the above referenced application is used to adaptively set the delay to align the signals by using the feedback signal x<b>2</b>(t) from the power amplifier. The ALTI block may be used to time-align the input signal to compute the distortion error signal which is the difference between the power amplifier output signal and the input signal, i.e., the time-align circuit <b>308</b> delays its output signal to compensate for delays introduced by processing of the input signal by the circuit.

0050<figref idref="DRAWINGS">FIG. 7</figref> shows one embodiment of timing control circuit <b>308</b>, which includes an interpolating mixer <b>702</b>, a phase detector <b>704</b>, and a signal integrator <b>706</b>, interconnected substantially as shown. The feedback signal x<b>2</b>(t) is compared in signal phase by phase detector <b>704</b> with the delayed signal from interpolating mixer <b>702</b>. The resulting detection signal is integrated by signal integrator <b>706</b> (e.g., a low pass filter) to produce an interpolation control signal r(t) for interpolating mixer <b>702</b>.

0051<figref idref="DRAWINGS">FIG. 7A</figref> shows one embodiment of interpolating mixer <b>702</b>, which is implemented as a tapped delay line with correlated tap coefficients. The input signal x<b>1</b> (t) is delayed by a signal delay element <b>712</b> which is a fractional delay element introducing a delay which is less than one data symbol period in duration. The resulting fractionally delayed signal and the original input signal x<b>1</b> (t) are mixed (e.g., multiplied) in respective signal mixers <b>714</b>-<b>1</b>, <b>714</b>-<b>2</b> with respective interpolation control signals representing timing interpolation parameters. The first timing interpolation parameter signal is the feedback signal from signal integrator <b>706</b> (<figref idref="DRAWINGS">FIG. 7</figref>). This signal is also complemented by a signal complement circuit <b>718</b> in which the input signal is subtracted from a normalized value (e.g., unity) to produce the second timing interpolation parameter signal. The resultant mixed signals are combined (e.g., summed) in a signal combining circuit <b>716</b> to produce the delayed signal x<b>1</b> (t−Δ).

0052<figref idref="DRAWINGS">FIG. 7B</figref> shows one embodiment of phase detector <b>704</b> of <figref idref="DRAWINGS">FIG. 7</figref>, which can be implemented using a fractional delay element <b>722</b>, a signal combining circuit <b>724</b>, and a signal mixer <b>726</b>, interconnected substantially as shown. The delayed signal x<b>1</b> (t−Δ) is further delayed by fractional delay element <b>722</b>, after which it is combined with delayed signal x<b>1</b> (t−Δ) in signal combiner <b>724</b> such that the further delayed signal is subtracted from the input delayed signal x<b>1</b> (t−Δ). The resulting combined signal is mixed (e.g., multiplied) in signal mixer <b>726</b> with the feedback signal x<b>2</b> (t) (and a gain constant G_r, if desired) to produce the phase detection signal for signal integrator <b>706</b> (<figref idref="DRAWINGS">FIG. 7A</figref>).

0053<figref idref="DRAWINGS">FIG. 8</figref> shows one embodiment of a slicer output time-align circuit for use as slicer output time-align circuit <b>310</b> of <figref idref="DRAWINGS">FIG. 3A</figref>. The circuit includes a controllable delay, which receives the data signal y(t) from slicer <b>306</b> of <figref idref="DRAWINGS">FIG. 3A</figref> and introduces a delay into the signal. One type of circuit suitable for the present invention is a fat tap adaptation (FTA) circuit, such as described in commonly-owned U.S. patent application Ser. No. 10/322,024, filed Dec. 17, 2002, entitled “Adaptive Coefficient Signal Generator for Adaptive Signal Equalizers with Fractionally-Spaced Feedback”, which is incorporated herein by reference in its entirety.

0054The controllable delay in the present invention is used to time align the decision feedback signal, which is the signal from slicer <b>306</b>, to be a symbol period delay with respect to the slicer input signal from which it is cancelled. A method of obtaining this delay in an adaptive manner is by using the FTA block, as described in the above-referenced application, which uses the tap coefficients or error signal e(t) as a control input signal.

0055<figref idref="DRAWINGS">FIG. 8</figref> shows one embodiment of slicer output time-align circuit <b>310</b>, which includes multiplier circuits <b>802</b>-<b>1</b>, <b>802</b>-<b>2</b> and control signal generator circuitry implemented as a coefficient signal generator <b>804</b> and a timing interpolation parameter signal generator <b>806</b>, all interconnected as substantially shown. The adjacent time-delayed feedback signals, the output signal y(t) of slicer <b>306</b> (<figref idref="DRAWINGS">FIG. 3A</figref>) and the signal y(t−δ) delayed by a symbol period δ, are multiplied in their respective multiplier circuits <b>802</b>-<b>1</b>, <b>802</b>-<b>2</b> with the error signal e(t). The resulting product signals e(t)y(t) and e(t)y(t−δ) are processed by signal generator circuits <b>804</b>, <b>806</b>. Coefficient signal generator circuit <b>804</b> provides an adaptation control signal d(t) to timing interpolation parameter signal generator circuit <b>806</b>, which in return, provides two other adaptation control signals r(t) and 1−r(t) back to coefficient signal generator <b>804</b>. As a result of processing these input signals e(t)y(t), e(t)y(t−δ), r(t), and 1−r(t), coefficient signal generator <b>804</b> provides the adaptive coefficient signals d(t)r(t) and d(t)[1−r(t)], where signal element d(t) is the weighting factor and signal element r(t) is the factor indicative of the degree of correlation between the adjacent time-delayed feedback signals y(t) and y(t−δ).

0056<figref idref="DRAWINGS">FIG. 8A</figref> shows one embodiment of coefficient signal generator <b>804</b>. Initial product signals y(t) and y(t−δ) are further multiplied in multiplier circuits <b>812</b>-<b>1</b>, <b>812</b>-<b>2</b> with the adaptation control signals r(t) and 1−r(t), respectively, from timing interpolation parameter signal generator <b>806</b>. An additional constant signal μ_ccan also be multiplied as part of the product operations or implemented as a constant scaling factor within the multiplier circuits <b>812</b>-<b>1</b>, <b>812</b>-<b>2</b>.

0057The resulting product signals are summed in a signal summing circuit <b>814</b>. The resulting sum signal is integrated in an integration circuit <b>816</b> (e.g., a low pass filter) to produce the first adaptation control signal d(t). This adaptation control signal d(t), in addition to being provided to timing interpolation parameter signal generator <b>806</b>, is multiplied within multiplier circuits <b>818</b>-<b>1</b>, <b>818</b>-<b>2</b> with the other adaptation control signals r(t) and 1−r(t), respectively, provided by timing interpolation parameter signal generator <b>806</b>. The product signals resulting from these multiplication operations are the adaptive coefficient signals d(t)r(t) and d(t)[1−r(t)].

0058<figref idref="DRAWINGS">FIG. 8B</figref> shows one embodiment of timing interpolation parameter signal generator <b>806</b>. The initial product signals e(t)y(t) and e(t)y(t−δ) are differentially summed in a signal summing circuit <b>822</b>, where the second product signal e(t)y(t−δ) is subtracted from the first product signal e(t)y(t). The resulting difference signal is multiplied in a multiplier circuit <b>824</b> with the adaptation control signal d(t) provided by coefficient signal generator <b>804</b>. As with the multiplier circuits <b>812</b>-<b>1</b>, <b>812</b>-<b>2</b> of coefficient signal generator <b>604</b>, an additional constant signal μ_rcan also be used in this multiplication operation or implemented as a constant scaling factor within multiplier circuit <b>824</b> operation.

0059The resulting product signal is integrated by a signal integration circuit <b>826</b> (e.g., a low pass filter) to produce one of the adaptation control signals r(t) used by coefficient signal generator <b>804</b>. This adaptation control signal r(t) is further processed by a signal complement circuit <b>828</b>, in which the input signal r(t) is subtracted from a reference signal having a normalized value, with the resulting difference signal <b>1</b>−r(t) serving as the other adaptation control signal used by coefficient signal generator <b>804</b>. For example, if the value of the incoming signal r(t) were considered to have a normalized signal value range bounded by the values of zero and one, signal complement circuit <b>828</b> subtracts the incoming signal r(t) from the value of one to produce the output signal <b>1</b>−r(t).

0060The above described embodiment utilizes an adaptive pre-distortion circuit with feedback circuitry and both linear and non-linear elements. By selecting the appropriate parameters for the low pass filters, the convergence of the least mean square value can be controlled to prevent coefficient drift of the adaptive tap coefficients. The continuous time iterative process results in the ability to adaptively change the tap coefficients for error minimization and provide a linear signal out of a non-linear power amplifier.

0061While the above description is for a single-carrier transceiver, the present invention can also be used with multi-carrier transceivers. <figref idref="DRAWINGS">FIG. 9</figref> shows a block diagram of a transceiver <b>900</b>, in which multi-carrier adaptive pre-distortion is performed by a multi-carrier LAPD circuit <b>910</b>. In this example, there are two carriers. Transceiver <b>900</b> includes two baseband processors <b>102</b>-<b>1</b> and <b>102</b>-<b>2</b>, each followed by two RF circuits <b>104</b>-<b>1</b> and <b>104</b>-<b>2</b>, LAPD circuit <b>910</b> that receives the outputs x<b>11</b> and x<b>12</b> from RF circuits <b>104</b>-<b>1</b> and <b>104</b>-<b>2</b>, respectively, and a feedback signal x<b>2</b> from a multi-carrier power amplifier <b>912</b> via power coupler <b>110</b>. Amplitude control circuit <b>112</b> (not shown) may be coupled between power coupler <b>110</b> and LAPD circuit <b>910</b> in some embodiments. A linearized signal out of power amplifier <b>912</b> can be transmitted through antenna <b>114</b>.

0062<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram of multi-carrier LAPD circuit <b>910</b> of <figref idref="DRAWINGS">FIG. 9</figref>, according to one embodiment. LAPD circuit <b>910</b> includes two “branches”, one for each signal at a different carrier. The input signal x<b>11</b> from the first carrier is utilized by a first branch, which includes LAPD adaptpath circuit <b>202</b>-<b>1</b> and LAPD datapath circuit <b>204</b>-<b>1</b>, such as described above with respect to a single carrier LAPD circuit. The input signal x<b>12</b> from the second carrier is utilized by a second branch, which includes LAPD adaptpath circuit <b>202</b>-<b>2</b> and LAPD datapath circuit <b>204</b>-<b>2</b>, again as described above with respect to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> according to one embodiment. The error signal e(t) is input to LAPD adaptpath circuits <b>202</b>-<b>1</b> and <b>202</b>-<b>2</b> for adaptive processing, as described above. However, a difference with the single-carrier LAPD circuit is that the error signal for multi-carrier LAPD <b>160</b> is the difference between power amplifier feedback signal x<b>2</b> and all the different input signals (x<b>11</b> and x<b>12</b> in this example), instead of just a single carrier input signal x<b>1</b>. This difference or error signal is determined by an arithmetic circuit <b>1002</b>, such as a multi-input adder.

0063After adaptively generating a pre-distortion signal for each carrier, the output signals from LAPD datapath <b>204</b>-<b>1</b> and from LAPD datapath <b>204</b>-<b>2</b> are passed through bandpass filters <b>206</b>-<b>1</b> and <b>206</b>-<b>2</b>, respectively. As with the single-carrier embodiment, bandpass filters <b>206</b> may be internal to or external of multi-carrier LAPD circuit <b>910</b>. The output signals from bandpass filters <b>206</b>-<b>1</b> and <b>206</b>-<b>2</b> are then summed by an adder <b>1004</b> to generate a pre-distorted signal z for power amplifier <b>912</b>. Due to adaptively pre-distorting input signals according to the present invention, the output of a non-linear power amplifier can be made linear with a wider range of factors, as well as at lower cost and size.

0064In some applications and systems, the power amplifier and/or other RF components may introduce inter-symbol interference (ISI) in addition to non-linearity. To compensate for both ISI and non-linearity effects jointly, the present invention can be modified, in part, by using a larger number of taps N′ such that N′*τ>T_s.

0065The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. For example, although the multi-carrier mode is shown with two carriers, the invention can also be used with a multi-carrier transceiver having more than two carriers by modifying the above descriptions accordingly. Further, the above description has focused on continuous-time, RF domain signal processing; however, the present invention can be extended or modified for use with discrete-time signal processing architectures as well. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.