Method and apparatus for protection from over-erasing nonvolatile memory cells

BACKGROUND OF THE INVENTION

00011. Field

0002This technology relates generally to semiconductor devices, and more specifically to nonvolatile memories with program and erase operations.

00032. Description of Related Art

0004Both <figref idref="DRAWINGS">FIGS. 1A and 1B</figref> show a charge-trapping memory cell with a substrate <b>170</b>, first current-carrying terminal <b>150</b>, second current-carrying terminal <b>160</b>, bottom oxide <b>140</b>, charge-trapping structure <b>130</b>, top oxide <b>120</b>, and gate <b>110</b>. <figref idref="DRAWINGS">FIGS. 1A and 1B</figref> show a charge-trapping memory cell undergoing the establishment of a high threshold state in different parts of the charge-trapping structure. Representative top oxides include silicon dioxide and silicon oxynitride having a thickness of about 50 to 100 Angstroms, or other similar high dielectric constant materials including, for example Al2O3. Representative bottom oxides include silicon dioxide and silicon oxynitride having a thickness of about 30 to 100 Angstroms, or other similar high dielectric constant materials. Representative charge-trapping structures include silicon nitride having a thickness of about 30 to 90 Angstroms, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others. The charge-trapping structure may be a discontinuous set of pockets or particles of charge-trapping material, or a continuous layer as shown in the drawing.

0005In <figref idref="DRAWINGS">FIG. 1A</figref>, the right part of the charge-trapping structure <b>130</b> undergoes a program operation to establish a low threshold state. The voltage of the gate <b>110</b> is −5 V. The voltage of the drain <b>160</b> is 5 V. The voltage of the source <b>150</b> is 0 V. The voltage of the substrate <b>170</b> is 0V. Consequently, the right part of the charge-trapping structure <b>130</b> has trapped charge <b>133</b>. In <figref idref="DRAWINGS">FIG. 1B</figref>, the left part of the charge-trapping structure <b>130</b> undergoes a program operation to establish a low threshold state. The voltage of the gate <b>110</b> is −5 V. The voltage of the drain <b>160</b> is 0 V. The voltage of the source <b>150</b> is 5 V. The voltage of the substrate <b>170</b> is 0 V. Consequently, the left part of the charge-trapping structure <b>130</b> has trapped charge <b>133</b>.

0006In <figref idref="DRAWINGS">FIG. 2A</figref>, the nonvolatile memory cell undergoes an erase operation. The voltage of the gate <b>210</b> is −8 V. The voltage of the drain <b>260</b> is 10 V. The voltage of the source <b>250</b> is 10 V. The voltage of the substrate <b>270</b> is 10 V. Consequently, the electrons move from the gate <b>210</b> to the charge trapping structure <b>230</b> and from the charge trapping structure <b>230</b> towards the substrate <b>270</b>. In <figref idref="DRAWINGS">FIG. 2B</figref>, the nonvolatile memory cell undergoes an erase operation with reversed voltage polarities. The voltage of the gate <b>210</b> is 10 V. The voltage of the drain <b>260</b> is −8 V. The voltage of the source <b>250</b> is −8 V. The voltage of the substrate <b>270</b> is −8 V. Consequently, the electrons move to the gate <b>210</b> from the charge trapping structure <b>230</b> and to the charge trapping structure <b>230</b> from the substrate <b>270</b>. The erase operation may also be carried out with a floating voltage at the drain <b>260</b> and/or the source <b>250</b>.

0007<figref idref="DRAWINGS">FIG. 3</figref> shows an example process flow of erasing a nonvolatile memory cell. In <b>310</b>, a command to erase the nonvolatile memory cell is received. In <b>320</b>, in response to the erase command, a biasing arrangement for erasing the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In <b>330</b>, an erase verify test is performed to confirm that a sufficient amount of erasing has been performed. If the erase verify test fails, then the biasing arrangement for erasing the nonvolatile memory cell is applied again. If the erase verify test passes, then the erase process is successful and done <b>340</b>.

0008<figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B, and <b>4</b>C show graphs of the relative distribution of the number of nonvolatile memory cells at various threshold voltages corresponding to the programmed state and erased state. <figref idref="DRAWINGS">FIG. 4A</figref> shows, prior to an erase operation, some nonvolatile memory cells having threshold voltages in the range of 3.5 V to 4 V corresponding to the programmed state <b>410</b>, and some nonvolatile memory cells having threshold voltages in the range of 5 V to 6 V corresponding to the erased state <b>420</b>. <figref idref="DRAWINGS">FIG. 4B</figref> shows an erase operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state <b>410</b> and on the nonvolatile memory cells having threshold voltages corresponding to the erased state <b>420</b>. As a result, the distribution of the nonvolatile memory cells originally in the programmed state <b>410</b> shifts to the erased state <b>415</b>. Similarly, the distribution of the nonvolatile memory cells originally in the erased state <b>420</b> shifts to the erased state <b>425</b>. <figref idref="DRAWINGS">FIG. 4C</figref> shows the actual distribution of threshold voltages of the nonvolatile memory cells in the erased state after the erase operation, which is the sum of distribution <b>415</b> and distribution <b>425</b>, or distribution <b>430</b> in the range of 5 V to 7 V. Because the erase operation shifted not only the threshold voltages of the nonvolatile memory cells in the programmed state <b>410</b>, but also the threshold voltages of the nonvolatile memory cells in the erased state <b>420</b>, the result of the program-and-erase cycle is an undesirable wide distribution <b>430</b> of threshold voltages of nonvolatile memory cells in the erased state.

0009Therefore, it would be desirable to perform an erase operation on a nonvolatile memory cell while reducing the tendency of the distribution of threshold voltages of nonvolatile memory cells in the erased state to drift.

SUMMARY OF THE INVENTION

0010One embodiment is a charge-trapping integrated circuit comprising an array of charge-trapping memory cells and logic coupled to the array. Each charge-trapping memory cell has a charge trapping structure associated with a threshold voltage and a programmed state and an erased state. The value of the threshold voltage determines whether the memory cell is in the programmed state or the erased state. The logic is responsive to a command to erase charge trapping memory cells, by performing several actions. The logic applies a bias arrangement to program charge trapping memory cells whose threshold voltage is outside the programmed state. Then, the logic applies another bias arrangement to establish the erased state in the charge trapping memory cells.

0011In some embodiments, the charge trapping structure of each charge trapping memory cell takes advantage of the localized charge trapping nature of the charge trapping structure (unlike the uniform charge storage of a floating gate) by associating different charge trapping parts of the charge trapping part structure with a threshold voltage and a programmed state and an erased state. In one embodiment, the logic identifies nonvolatile memory cells of the plurality of charge trapping memory cells having a threshold voltage outside the programmed state, and the programming bias arrangement programs any charge trapping part having a threshold voltage outside the programmed state, and the erasing bias arrangement establishes the erased state in the charge trapping parts. In another embodiment, the programming bias arrangement programs all the charge trapping parts of all the charge trapping memory cells, and the erasing bias arrangement establishes the erased state in all the charge trapping parts of all the charge trapping memory cells

0012In some embodiments, each charge trapping part is associated with not just one erased state and one programmed state, but multiple programmed states. The multiple programmed states include a most programmed state and other, less programmed, states. In one embodiment, the programming bias arrangement programs any charge trapping part having a threshold voltage in either the erased state or any of the less programmed states. In another embodiment, the programming bias arrangement programs all charge trapping parts of all charge trapping memory cells.

0013In some embodiments, the programming bias arrangement adds holes to the charge trapping structure, and the erasing bias arrangement adds electrons to the charge trapping structure of the plurality of charge trapping memory cells. The holes can be added by band-to-band hot hole conduction. The electrons can be added by tunneling electrons. In other embodiments, the programming bias arrangement adds electrons to the charge trapping structure, and the erasing bias arrangement adds holes to the charge trapping structure.

0014Various embodiments of erasing nonvolatile memory cells successfully resist a drift in the threshold voltage of nonvolatile memory cells that are repeatedly erased in response to multiple erase commands. For example, after 100 program and erase cycles, the threshold voltage in the erased state of charge trapping memory cells changes by no more than a magnitude of about 0.7 V.

0015Other aspects of the technology include embodiments directed to a method for performing erasing as described, and a method for manufacturing a nonvolatile memory integrated circuit as described.

BRIEF DESCRIPTION OF THE DRAWINGS

0016<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> show a charge-trapping memory cell undergoing programming of different parts of the charge-trapping structure.

0017<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> show a charge-trapping memory cell undergoing erasing of different parts of the charge-trapping structure.

0018<figref idref="DRAWINGS">FIG. 3</figref> shows an example process flow of erasing a charge-trapping memory cell without preprogramming.

0019<figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B, and <b>4</b>C show graphs of the relative distribution of the number of charge-trapping memory cells at various threshold voltages corresponding to the programmed state and erased state, during an erase operation without preprogramming.

0020<figref idref="DRAWINGS">FIG. 5</figref> shows an example process flow of erasing a charge-trapping memory cell with preprogramming.

0021<figref idref="DRAWINGS">FIGS. 6A</figref>, <b>6</b>B, and <b>6</b>C show graphs of the relative distribution of the number of charge-trapping memory cells at various threshold voltages corresponding to the programmed state and erased state, during an erase operation with preprogramming.

0022<figref idref="DRAWINGS">FIG. 7</figref> shows a graph of threshold voltage of a charge-trapping memory cell versus program and erase cycle # for repeated erase operations without preprogramming.

0023<figref idref="DRAWINGS">FIG. 8</figref> shows a graph of threshold voltage of a charge-trapping memory cell versus program and erase cycle # for repeated erase operations with preprogramming.

0024<figref idref="DRAWINGS">FIG. 9</figref> shows an example of a biasing arrangement for preprogramming an array of charge-trapping memory cells.

0025<figref idref="DRAWINGS">FIG. 10</figref> is a schematic of threshold voltage, indicating two threshold states.

0026<figref idref="DRAWINGS">FIG. 11A</figref> is a schematic of two-level state operation.

0027<figref idref="DRAWINGS">FIGS. 11B</figref>, <b>11</b>C, and <b>11</b>D are schematics of multi-level threshold states for multi-level cell operation.

0028<figref idref="DRAWINGS">FIG. 12</figref> is a schematic of an integrated circuit embodiment.

DETAILED DESCRIPTION

0029<figref idref="DRAWINGS">FIG. 5</figref> shows an example process flow of erasing a nonvolatile memory cell according an embodiment. In <b>510</b>, a command to erase the nonvolatile memory cell is received. In <b>520</b>, in response to the erase command, biasing arrangement for programming the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In one embodiment, the biasing arrangement for programming is applied to an entire sector, regardless of which cells in the sector are in the programmed state and which cells are in the erased state. This has the advantage of simplicity, such as decreasing any overhead involved in communication of data about which cells are in the erased state. In another embodiment, the biasing arrangement for programming is applied only to cells which are in the erased state. This avoids the slight shift in the distribution of threshold voltages of nonvolatile memory cells which are already in the programmed state. In <b>530</b>, after applying the biasing arrangement for programming in response to the erase command, the biasing arrangement for erasing the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In <b>540</b>, an erase verify test is performed to confirm that a sufficient amount of erasing has been performed. If the erase verify test fails, then the biasing arrangement for erasing the nonvolatile memory cell is applied again. If the erase verify test passes, then the erase process is successful and done <b>540</b>.

0030In another embodiment, nonvolatile memory cells having a threshold voltage outside the programmed state are identified. For example, during regular operation, a memory keeping track of the particular state—programmed or erased—is accessed to identify the nonvolatile memory cells having a threshold voltage outside the programmed state. In another example, a read procedure is performed to identify nonvolatile memory cells in the erased state, and/or nonvolatile memory cells nominally in the programmed state but, due to nonideal behavior, have a threshold voltage outside the programmed state. An advantage of identifying nonvolatile memory cells having a threshold voltage outside the programmed state, is that during the erase procedure, rather than programming all the nonvolatile memory cells, some subset of the nonvolatile memory cells may be programmed in order to avoid programming already programmed cells.

0031<figref idref="DRAWINGS">FIGS. 6A</figref>, <b>6</b>B, and <b>6</b>C show graphs of the relative distribution of the number of nonvolatile memory cells at various threshold voltages corresponding to the programmed state and erased state. <figref idref="DRAWINGS">FIG. 6A</figref> shows, prior to an erase operation, some nonvolatile memory cells having threshold voltages in the range of 3.5 V to 4 V corresponding to the programmed state <b>610</b>, and some nonvolatile memory cells having threshold voltages in the range of 5 V to 6 V corresponding to the erased state <b>620</b>. <figref idref="DRAWINGS">FIG. 6B</figref> shows a program operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state <b>610</b> and on the nonvolatile memory cells having threshold voltages corresponding to the erased state <b>620</b>. As a result, the distribution of the nonvolatile memory cells originally in the programmed state <b>610</b> shifts slightly to the programmed state <b>615</b>. Similarly, the distribution of the nonvolatile memory cells originally in the erased state <b>620</b> shifts to the programmed state <b>625</b>. <figref idref="DRAWINGS">FIG. 6C</figref> shows an erase operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state <b>615</b> and on the nonvolatile memory cells having threshold voltages corresponding to the programmed state <b>625</b>. The distribution of the threshold voltages of nonvolatile memory cells in the erased state after the erase operation is the distribution <b>630</b> in the range of 5 V to 6 V, which represents the sum of the threshold voltage distributions of cells in the erased state, from both distribution <b>615</b> and <b>625</b> after erasing. Because of the prior program operation which shifted the threshold voltages of cells in the erased state to the programmed state, the erase operation did not excessively shift the threshold voltage distribution of nonvolatile memory cells in the erased state.

0032<figref idref="DRAWINGS">FIG. 7</figref> shows a graph of threshold voltage versus program and erase cycle # for a nonvolatile memory cell with two distinct parts in the charge trapping structure, each capable of holding data independently of the other part. Both bits are repeatedly erased, emulating the situation where both bits of the nonvolatile memory cell are in the erased state, and are not pre-programmed in response to an erase command. Because preprogramming is not performed in response to the erase command, the threshold voltage of bit<b>1</b><b>710</b> drifts upward from about 4 V to nearly 6 V after 100 cycles. The threshold voltage of bit<b>2</b><b>720</b> also drifts upward from about 4.5 V to nearly 6 V after 100 cycles.

0033<figref idref="DRAWINGS">FIG. 8</figref> also shows a graph of threshold voltage versus program and erase cycle # for a nonvolatile memory cell with two distinct parts in the charge trapping structure, each capable of holding data independently of the other part. Both bits are repeatedly erased, emulating the situation where both bits of the nonvolatile memory cell are in the erased state, but first pre-programmed prior to erasing, in response to an erase command. Because preprogramming is performed in response to the erase command, the threshold voltage of bit<b>1</b><b>810</b> drifts upward much less, from about 4 V to slightly over 4 V after 100 cycles. The threshold voltage of bit<b>2</b><b>820</b> also drifts upward much less, from about 4 V to about 4.5 V after 100 cycles.

0034<figref idref="DRAWINGS">FIG. 9</figref> shows an example of a biasing arrangement for preprogramming an array of nonvolatile memory cells. The nonvolatile memory cells are interconnected in a virtual ground array arrangement. The voltages of bit line BL<b>1</b>, V_BL1<b>910</b>; bit line BL<b>3</b>, V_BL3<b>930</b>; and bit line BL<b>5</b>, V_BL5<b>950</b>; are 0 V. The voltages of bit line BL<b>2</b>, V_BL2<b>920</b>; and bit line BL<b>4</b>, V_BL4<b>940</b>; are 5 V. The voltages of word line WL<b>1</b>, V_WL1<b>901</b>; and word line WL<b>2</b>, V_WL2<b>902</b>; are 0 V. The voltages of word line WL<b>3</b>, V_WL3<b>903</b>; word line WL<b>4</b>, V_WL4<b>904</b>; and word line WL<b>5</b>, V_WL5<b>905</b>; are −8 V. By selectively applying voltages to word lines, preprogramming is limited to nonvolatile memory cells in sector <b>960</b>. By selectively applying voltages to bit lines, preprogramming is limited to the parts of the charge trapping structures indicated by the dashed areas <b>970</b>. By switching the voltages applied to the bit lines, the remaining parts of the charge trapping structures of nonvolatile memory cells in the sector <b>960</b> can be preprogrammed.

0035<figref idref="DRAWINGS">FIG. 10</figref> is a schematic of threshold voltage, indicating two threshold states. High threshold state <b>1010</b> is defined by a range of threshold voltages having a minimum threshold voltage of <b>1015</b>. Low threshold state <b>1020</b> is defined by a range of threshold voltages having a maximum threshold voltage of <b>1025</b>.

0036In one embodiment, the charge trapping structure has distinct parts which are each associated independently with a threshold state. In another embodiment, a low threshold state <b>1020</b> is stored in a charge-trapping memory cell by establishing the low threshold state <b>1020</b> in different parts of the charge-trapping structure. The high threshold state <b>1010</b> is stored in the charge-trapping memory cell by raising the threshold voltage of one part of the charge-trapping structure into the high threshold state <b>1010</b> and raising the threshold voltage of another part of the charge-trapping structure into the high threshold state <b>1010</b>.

0037<figref idref="DRAWINGS">FIGS. 11A</figref>, <b>11</b>B, <b>11</b>C, and <b>11</b>D are threshold state schematics corresponding to 1 bit, 2 bits, 3 bits, and 4 bits, respectively. <figref idref="DRAWINGS">FIG. 11A</figref> shows a schematic for two-level threshold state operation. There are two states, the 1 state <b>1</b> f<b>01</b> and the 0 state <b>1102</b>. <figref idref="DRAWINGS">FIG. 11B</figref> shows a schematic for four-level threshold state operation. There are 4 states, the 11 state <b>1111</b>, the 10 state <b>1112</b>, the 01 state <b>1111</b>, and the 00 state <b>1114</b>. <figref idref="DRAWINGS">FIG. 11C</figref> shows a schematic for 8-level threshold state operation. There are 8 states, of which 4 states are shown, the 111 state <b>1121</b>, the 110 state <b>1122</b>, the 001 state <b>1123</b>, and the 000 state <b>1124</b>. <figref idref="DRAWINGS">FIG. 11D</figref> shows a schematic for 16-level threshold state operation. There are 16 states, of which 4 states are shown, the 1111 state <b>1131</b>, the 1110 state <b>1132</b>, the 0001 state <b>1133</b>, and the 0000 state <b>1134</b>.

0038<figref idref="DRAWINGS">FIG. 12</figref> is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit <b>1250</b> includes a memory array <b>1200</b> implemented using localized charge-trapping memory cells on a semiconductor substrate. A row decoder <b>1201</b> is coupled to a plurality of word lines <b>1202</b> arranged along rows in the memory array <b>1200</b>. A column decoder <b>1203</b> is coupled to a plurality of bit lines <b>1204</b> arranged along columns in the memory array <b>1200</b>. Addresses are supplied on bus <b>1205</b> to column decoder <b>1203</b> and row decoder <b>1201</b>. Sense amplifiers and data-in structures in block <b>1206</b> are coupled to the column decoder <b>1203</b> via data bus <b>1207</b>. Data is supplied via the data-in line <b>1211</b> from input/output ports on the integrated circuit <b>1250</b>, or from other data sources internal or external to the integrated circuit <b>1250</b>, to the data-in structures in block <b>1206</b>. Data is supplied via the data-out line <b>1212</b> from the sense amplifiers in block <b>1206</b> to input/output ports on the integrated circuit <b>1250</b>, or to other data destinations internal or external to the integrated circuit <b>1250</b>. A biasing arrangement state machine <b>1209</b> controls the application of biasing arrangement supply voltages <b>1208</b>, such as for the erase verify and program verify voltages, and performing preprogramming in response to a command to erase sectors of the charge-trapping structure of a memory cell.

0039While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. What is claimed is: