Method and apparatus for reducing strapping devices

0001This application is a Divisional of co-pending application Ser. No. 09/934,574, filed on Aug. 23, 2001, now U.S. Pat. No. 6,845,444 and for which priority is claimed under 35 U.S.C. § 120; the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

0002The present invention relates generally to the initial configuration of computer systems and, in particular, to a method and apparatus for reducing strapping devices used by computer systems.

BACKGROUND OF THE INVENTION

0003A computer system typically includes a number of integrated circuit devices, or computer chipsets, that may be operated in more than one configuration. The computer is designed to use the chipsets in only one particular configuration and thus the chipsets must be “initialized” or “set up” whenever a user turns the computer on or resets the computer. The computer chipsets also have some operating parameters which must be set before the first central processing unit (CPU) cycle issues, and thus these parameters cannot be set by normal CPU configuration cycles. Such a chip is usually initialized by providing certain electrical signals to the chip when the computer is turned on or reset. The circuitry used to generate these signals is frequently referred to as the “strapping device”. Jumpers and dual inline package (DIP) switches are two examples of strapping devices which set the strapping options for the computer. Several pins of the chip must thus be assigned to receive the configuration signals generated by the strapping devices as soon as power is provided.

0004However, the computer motherboard assembly employed by these strapping devices is costly and space consuming. Moreover, an integrated circuit chip cannot spare too many dedicated pins for receiving the configuration signals generated by the strapping devices. Accordingly, certain pins of the chip may be used to perform one function during the startup process, while serving another function during normal operation. In other words, these pins are multiplexed. Data pins of a chip are usually this type of multiplexed pin. For a computer system adopting double data rate (DDR) technology, there are some problems if the DDR data pins are connected to the strapping devices, since the DDR data pins must be kept at a stable voltage during bus idle. As well, data pins conforming to the Peripheral Component Interconnect (PCI) specification cannot be used to receive the strapping signals, since the PCI bus is a shared bus and there will be contention if more than one PCI device uses the same data pin to receive the strapping signal. Hence, the static nature of currently available strapping devices makes their use unappealing in such implementations.

0005For the reasons mentioned previously, a firmware configuration scheme is provided to initialize the operating parameters of a computer system, unencumbered by the limitations associated with the prior art.

SUMMARY OF THE INVENTION

0006It is one object of the present invention to provide a method and apparatus for reducing strapping devices used in computer systems.

0007It is another object of the present invention to provide a method and apparatus for efficiently initializing computer configuration that should be set before the CPU reset signal is deasserted.

0008The present invention is a method and apparatus for reducing strapping devices in a computer system having at least one configurable device. Briefly, the method comprises the following steps. First, a configuration value stored in non-volatile memory is provided to reduce the strapping devices. During power-up and reset states of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. Repeating the fetching step until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Following that, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, thereby the at least one configurable device is configured completely.

0009The present invention is embodied in an apparatus comprising a low-speed peripheral bus, a non-volatile memory, and a bridge logic. The non-volatile memory and the bridge logic are separately coupled to the low-speed peripheral bus. The non-volatile memory has a reserve space to store a configuration value for the at least one configurable device. The bridge logic still comprises a latch and a multiplexer. The latch, in response to a configuration enable signal, asserts the configuration value to configure the at least one configurable device. The multiplexer has an output port coupled to the latch. The multiplexer asserts the configuration value stored in the non-volatile memory on the output port during power-up and reset states of the computer system, and asserts run-time programmable configuration information on the output port during other operational states, based on the state of a strapping ready signal.

0010Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

0011The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

0012<figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram illustrating an exemplary computer system incorporating the teachings of the present invention;

0013<figref idref="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating an alternative computer system;

0014<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating a preferred embodiment in accordance with the present invention;

0015<figref idref="DRAWINGS">FIG. 3</figref> is a flow chart illustrating an example of the method steps for initializing configuration; and

0016<figref idref="DRAWINGS">FIG. 4</figref> is a timing chart of signals relative to an initialization cycle in the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

0017As illustrated in <figref idref="DRAWINGS">FIG. 1A</figref>, exemplary computer system <b>100</b> is shown comprising a computer motherboard <b>150</b> including a processor <b>101</b>, a random access memory (RAM) <b>103</b>, and a clock source <b>123</b>, each of which is coupled to a system bus <b>105</b> as shown. A second bridge logic <b>107</b> is also coupled to system bus <b>105</b> for coupling system bus <b>105</b> to one or more, typically input/output (I/O), buses. In one embodiment, this bus is a high-speed peripheral bus <b>115</b>, e.g. Peripheral Component Interconnect (PCI) bus <b>115</b>. That is to say, the second bridge logic <b>107</b> is a system-to-PCI bus bridge (a.k.a., north bridge). As depicted, system-to-PCI bus bridge <b>107</b> couples system bus <b>105</b> to PCI bus <b>115</b>. A hard disk <b>111</b> is coupled with PCI bus <b>115</b> for storing information and instruction for processor <b>101</b>. I/O devices <b>113</b> are also coupled to PCI bus <b>115</b> which input and output data and control information to and from processor <b>101</b>. I/O devices <b>113</b> may include, for example, a display device and a network adapter device.

0018With continued reference to <figref idref="DRAWINGS">FIG. 1A</figref>, PCI bus <b>115</b> is also coupled to a low-speed peripheral bus <b>121</b> via a first bridge logic <b>109</b>. In one embodiment, for example, a low-speed peripheral bus <b>121</b> is an Industry Standard Architecture (ISA) bus <b>121</b> and the first bridge logic <b>109</b> is a PCI-to-ISA bridge (a.k.a., south bridge). The bus clocks of PCI bus <b>115</b> and ISA bus <b>121</b> are also provided by clock source <b>123</b>. A non-volatile memory <b>119</b> is coupled to ISA bus <b>121</b> for storing static information and instruction for processor <b>101</b>. In one embodiment, non-volatile memory <b>119</b> is a flash memory, or an electrically erasable programmable read only memory (EEPROM). I/O devices <b>117</b> may also be coupled to ISA bus <b>121</b> which input and output data and control information to and from processor <b>101</b>. <figref idref="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating an alternative computer system <b>100</b>′. It should be noted that the second bridge logic <b>107</b> is directly coupled to the first bridge logic <b>109</b> via a point-to-point bus <b>125</b>. Further, a third bridge logic <b>127</b>, within the first bridge logic <b>109</b>, is provided to form an interface between the high-speed peripheral bus <b>115</b> and the low-speed peripheral bus <b>121</b>.

0019The basic idea of the firmware configuration scheme, in accordance with the present invention, is that the computer chipsets including the first and second bridge logic <b>107</b>˜<b>109</b> read desired configuration value from non-volatile memory <b>119</b> and latch the value into configuration registers before the chipsets deasserting processor reset. <figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating an expanded view of the first bridge logic <b>109</b>. The first bridge logic, i.e. south bridge <b>109</b>, is comprised of a multiplexer <b>201</b> and a latch <b>203</b>. As illustrated, the outputs of non-volatile memory <b>119</b> are coupled to one input port <b>211</b> of multiplexer <b>201</b> via ISA bus <b>121</b>. The other input port <b>209</b> of multiplexer <b>201</b> receives run-time programmable configuration information (not shown). As depicted, the output port <b>219</b> of multiplexer <b>201</b> is coupled to latch <b>203</b>, and the outputs of latch <b>203</b> are transported to the second bridge logic, i.e. north bridge <b>107</b>, via PCI bus <b>115</b>. A strapping ready signal, STRP_RDY <b>213</b>, controls the output of multiplexer <b>201</b>. When STRP_RDY <b>213</b> is deasserted (i.e., during power-up and reset states of exemplary computer system <b>100</b>), multiplexer <b>201</b> will select the configuration value from non-volatile memory <b>119</b> to drive on output port <b>219</b>. Alternatively, when STRP_RDY <b>213</b> is asserted (i.e., during other operational states of exemplary computer system <b>100</b>), multiplexer <b>201</b> will select the run-time programmable configuration information to drive on output port <b>219</b>. Latch <b>203</b> is controlled by a configuration enable signal, CONF_ENA <b>215</b>, output from a combinational logic circuit <b>221</b> consisting of a logic NOT gate <b>205</b> and a logic NAND gate <b>207</b>. As depicted, STRP_RDY <b>213</b> is directly coupled to one input of the logic NAND gate <b>207</b>. A run-time programmable configuration write signal, CONF_WR <b>217</b>, is coupled to the other input of the logic NAND gate <b>207</b> by way of logic NOT gate <b>205</b>. CONF_ENA <b>215</b> is asserted except when STRP_RDY <b>213</b> is asserted and CONF_WR <b>217</b> is deasserted. In other words, whatever input is resident on the input port of latch <b>203</b> during STRP_RDY <b>213</b> is deasserted, or during STRP_RDY <b>213</b> and CONF_WR <b>217</b> are both asserted, will be asserted on PCI bus <b>115</b>.

0020Having generally described the hardware elements of the present invention in <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the operation of the present invention will be further described with reference to <figref idref="DRAWINGS">FIGS. 3 and 4</figref>. The first step of the firmware configuration scheme is to reserve a 64-bit memory space within a basic input/output system (BIOS) area. The reserved space is defined as the non-volatile memory <b>119</b> hexadecimal address ranging from FFFFFFD0˜FFFFFFD7. The most significant bit (MSB) of the configuration value is programmed to a logic “0”, thereby an initialization strapping status of the computer system is indicated. Then, the configuration value is stored into the 64-bit reserved memory space in the non-volatile memory. As computer system <b>100</b> is turned on or reset (step <b>301</b>), a processor reset signal CPURST# (where # denotes an active low trigger), and a bus reset signal PCIRST# of PCI bus <b>115</b>, must be asserted (step <b>303</b>). In step <b>305</b>, after a short period of time, PCIRST# is deasserted as shown in <figref idref="DRAWINGS">FIG. 4</figref>. When system clock SYSCLK of system bus <b>105</b> and PCI clock PCICLK of PCI bus <b>115</b> are stable, i.e., reaching their working voltages and frequencies, an internal signal FWT_RD in south bridge <b>109</b> is asserted. While FWT_RD asserted, a read transaction is initiated to keep fetching data from hexadecimal address FFFFFFD0 until all of the 64-bit configuration value has been successfully read (step <b>307</b>). If in step <b>309</b> it is determined that the MSB of fetched value is a logic “1”, the read transaction must be repeated until the MSB of fetched value becomes a logic “0”. If the MSB of fetched configuration value is a logic “0”, the internal signal FWT_RD will be deasserted. In step <b>311</b>, STRP_RDY is asserted and the configuration value is latched on the output port of latch <b>203</b>. In step <b>313</b>, the latched configuration value is transport to north bridge <b>107</b>. In step <b>315</b>, while the latched configuration value is received and latched into configuration registers (not shown) by north bridge <b>107</b>, an internal signal NB_STRP_RDY in north bridge <b>107</b> is asserted. Finally, CPU reset control logic (not shown) in north bridge <b>107</b> is activated and CPURST# is deasserted after configurable devices, including processor and chipsets, are set completely (step <b>317</b>).

0021Thus, a preferred embodiment for a method and apparatus for reducing strapping devices has been disclosed. It will be apparent that the invention is not limited thereto, and that many modifications and additions may be made within the scope of the invention. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.