Display apparatus and drive method therefor

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to a display apparatus equipped with optical elements, pixel by pixel, which perform an optical operation according to a current value, particularly, optical elements which emit light with a brightness according to the current value, and a drive method for the display apparatus.

00032. Description of the Related Art

0004In general, there are two types of display apparatuses: a passive driving type and an active matrix driving type which has switching transistors provided pixel by pixel. In a liquid crystal display of the active matrix driving type, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, a liquid crystal element <b>501</b> having a liquid crystal which also serves as a capacitor, and a transistor <b>502</b> which serves as a switching element are provided for each pixel. In the active matrix driving type, when a data driver applies a voltage for controlling the transmittivity of the liquid crystal to a signal line <b>504</b> while a scan line <b>503</b> is selected in a select period as a pulse signal is input to the scan line <b>503</b> by a scan driver, a voltage is applied to the liquid crystal element <b>501</b> via the transistor <b>502</b>. In the liquid crystal element <b>501</b>, liquid crystal molecules are aligned in the direction according to the applied voltage to adequately change the transmittivity of light which passes the liquid crystal element <b>501</b>. Even if the transistor <b>502</b> is turned off in a non-select period following the select period, however, the liquid crystal element <b>501</b> serves as a capacitor to hold charges according to the invention the voltage value in the allowable range until the next select period, the alignment direction of the liquid crystal molecules is maintained over that period. As apparent from the above, the liquid crystal display is a voltage-controlled type display apparatus in which a voltage is newly written in the select period in such a way that the light transmittivity becomes that of the liquid crystal element <b>501</b> and which provides arbitrary gradation expression according to the voltage value.

0005Unlike the liquid crystal display, a display apparatus that uses an organic EL (Electroluminescence) element which is a self light-emitting element requires no backlight and is optimal for ensuring a flatter display and is free of the restriction on the angle of visibility that the liquid crystal display has. In this respect, this organic EL type display apparatus is promising as the next generation of the display apparatus and its practical usage is greatly expected.

0006From the view points of high luminance or brightness, high contrast and high definition, it is particularly desirable that the organic EL display, like the liquid crystal display, should be of the active matrix driving type. While a passive driving organic EL display requires that the current flowing in the select period should be increased, an active matrix driving type is provided, for each pixel, with an element for holding the voltage applied across both ends of an organic EL element in order to allow the organic EL element to keep emitting light with a predetermined brightness for light emission even in a non-select period, thus ensuring continuous flow of the current even in the non-select period. Therefore, the value of the current that flows in the organic EL element per unit time in the select period and non-select period could be small. Because the organic EL element has a very small capacitance as a capacitor, however, the organic EL element, when merely provided in the pixel circuit as shown in <figref idref="DRAWINGS">FIG. 11</figref> in place of the liquid crystal element <b>501</b>, cannot keep emitting light until the non-select period.

0007As one example of solutions to this shortcoming, as shown in <figref idref="DRAWINGS">FIG. 12</figref>, an active matrix driving type organic EL display is provided, for each pixel, with an organic EL element <b>601</b> which emits light with a brightness proportional to the value of the current flowing inside, a transistor <b>602</b> which serves as a switching element and a transistor <b>605</b> which allows the drive current according to the gate voltage applied by the transistor <b>602</b> to flow in the organic EL element <b>601</b>. In this display, when a signal voltage for letting the drive current having a predetermined current value flow to the transistor <b>605</b> is applied to a signal line <b>604</b> by the data driver while a pixel connected to a scan line <b>603</b> is selected as a pulse signal is input to the scan line <b>603</b> in the select period by the scan driver, the voltage is applied to the gate electrode of the transistor <b>605</b> and brightness data is written in the gate electrode of the transistor <b>605</b>. This sets the transistor <b>605</b> on so that the drive current with the gradation according to the invention the value of the voltage applied to the gate electrode flows into the organic EL element <b>601</b> via the transistor <b>605</b> from a power supply and the organic EL element <b>601</b> emits light with the brightness according to the current value. In the non-select period following the select period, even when the transistor <b>602</b> is turned off, charges according to the gate-source voltage of the transistor <b>5605</b> are kept stored by the parasitic capacitor or the like between the gate and source of the transistor <b>605</b>, thus keeping supplying the drive current to the organic EL element <b>601</b>. In short, the drive current is specifically controlled by the value of the gate voltage of the transistor which is output in the select period so that the organic EL element <b>601</b> is allowed to emit light with a predetermined gradation brightnesses.

0008Generally, as the channel resistance of a transistor depends on the ambient temperature or varies over a long usage, the gate threshold voltage changes with time or varies. Even if the value of the current flowing in the organic EL element <b>601</b> is changed by changing the voltage to be applied to the gate electrode of the transistor <b>605</b>, i.e., even if the brightness of the organic EL element <b>601</b> is changed changing the voltage to be applied to the gate electrode of the transistor <b>605</b>, therefore, it is difficult to specifically write the value of the current flowing in the organic EL element <b>601</b> with the gate voltage of the transistor <b>605</b>.

0009In this respect, a study has been made on a scheme for controlling the brightness based on the current value, not based on the level of the voltage to be applied to the transistor. That is, a current-writing system to directly supply the value of the current flowing in an organic EL element to a signal line, not a voltage-writing system which supplies the level of the gate voltage to a signal line, is adapted to the active matrix driving for an organic EL display.

0010In the current-writing display, the value of the current that flows per unit time should be made smaller. In case where the current-writing system is adapted to an active matrix driving organic EL display, therefore, an organic EL display provided with a transistor which reduces the value of the current flowing into the organic EL element with respect to the output current from the driver as shown in <figref idref="DRAWINGS">FIG. 13</figref> has been proposed. For each pixel, the organic EL display in <figref idref="DRAWINGS">FIG. 13</figref> is provided with an organic EL element <b>701</b>, an N type MOS transistor <b>702</b> and a P type MOS transistor <b>707</b> which serve as switching elements, a P type MOS transistor <b>706</b> which converts the value of a write current to a gate voltage, a capacitor <b>709</b> which holds charges according to the gate voltage of the transistor <b>706</b> and a P type MOS transistor <b>705</b> which lets a drive current with the gradation according to the held charges flow into the organic EL element <b>701</b>.

0011In this display, as the write current is allowed to flow in a signal line <b>704</b> by the data driver while the transistors <b>707</b> and <b>702</b> are selected by signals output onto a first scan line <b>708</b> and a second scan line <b>703</b>, a voltage is produced between the gate and source of the transistor <b>706</b> and the current according to the channel characteristic of the transistor <b>705</b> and the channel characteristic of the transistor <b>706</b> flows into the transistor <b>705</b> and the organic EL element <b>701</b>.

0012The organic EL display in <figref idref="DRAWINGS">FIG. 13</figref> should have however been provided with a current mirror circuit comprised of the transistors <b>705</b> and <b>706</b> for each pixel, and the increase in the number of pixels made the production yield of displays lower due to defects in the transistors <b>705</b> and <b>706</b>. When the transistors <b>705</b> and <b>706</b> and the organic EL element <b>701</b> are laid out two-dimensionally, the ratio of the area of the non-luminous area, such as a transistor, of the pixel to the area of the luminous area increases, so that a burden is put on the organic EL element <b>701</b> to ensure bright display. To supply the current to an element, such as an organic EL element, which emits light on a minute current, in particular, the transistor <b>706</b> should have been designed larger with respect to the transistor <b>705</b>, resulting in a considerable increase in the ratio of the non-luminous area to the luminous area. There had occurred an additional problem such that the probability of occurrence of an in-plane variation in the current characteristics of the transistors <b>705</b> and <b>706</b> which serve as a current mirror circuit would become higher in proportional to an increase in the number of pixels. Further, while the transistor <b>702</b> is an N channel transistor, the other transistors <b>705</b> to <b>707</b> are P channel transistors. This necessitates that different channel types of transistors should be fabricated, thus lowering the throughput.

0013One advantage of the invention lies in that the display can emit light on a current with the adequate current value and the ratio of the luminous area to the non-luminous area is high, and another advantage lies in that the display has a structure which is easy to manufacture.

SUMMARY OF THE INVENTION

0014To overcome the aforementioned problems, a display apparatus according to one aspect of the invention comprises:

0015a plurality of pixels respectively laid out at intersections of plural scan lines and plural signal lines in a display area and each having an optical element which performs an optical operation based on a current value of a drive current flowing therethrough and a pixel circuit which supplies the drive current to the optical element; and

0016a current control driver which is arranged in an other area than the display area, is connected to each of the signal lines and reduces a current value of a gradation signal by a predetermined current reduction ratio to supply the drive current to the optical element.

0017As the current control driver is laid outside the display area in the invention, it is unnecessary to arrange a current control element within a pixel, thus making it possible to increase the ratio of the luminous portion to the non-luminous portion.

0018When an organic EL element which should emit light on an extremely minute current is used as an optical element, for example, the current value should be made very small and a change in current value originated from a gradation difference should be made very small in order to provide the organic EL element with the luminous gradation. According to the invention, by way of contrast, the provision of the current control driver can efficiently convert the gradation current to a current with a minute current value.

0019The apparent brightness of a pixel is expressed by the ratio of the area of an optical element in the pixel whose brightness is modulated and the product of the brightness of the pixel per unit time and the brightness sustain period of the pixel. In case where the optical element appears to display with a predetermined brightness, if the brightness sustain period of the pixel is short, the brightness of the pixel per unit time should be increased, whereas if the brightness sustain period of the pixel is long, the brightness of the pixel per unit time should be decreased. In a passive driving, voltage-controlled type organic EL display apparatus, such as a conventional simple matrix type, for example, the greater the number of pixels gets, the higher the ratio of the non-select period to the select period (i.e., the luminous period) becomes, so that the luminous brightness per unit time should be increased. In case where the display apparatus is an active driving type, however, the greater the number of pixels gets, the higher the ratio of the non-select period (luminous period) to the select period becomes. Contrary to the passive driving display apparatus, therefore, the active driving display apparatus should make the value of the current flowing into the optical element per unit time very small. The invention is particularly effective in such a case because it can supply a sufficiently minute current which meets the requirements on such a high-definition active display apparatus. Further, as the current control driver is laid outside the display area according to the invention, the ratio of the area of the optical element where the brightness of a pixel is modulated is high. It is therefore possible to restrain the deterioration of the optical element by suppressing the current density of the current flowing in the optical element per unit area to a low level, thus ensuring a longer life of the display apparatus. The invention is particularly effective when the optical element is an organic EL element in which case as the current density gets higher, the luminous life becomes considerably shorter.

0020A display apparatus according to another aspect of the invention comprises:

0021a plurality of signal lines;

0022a plurality of pixels each having an optical element which performs an optical operation based on a value of a drive current flowing therethrough and connected to one ends of the plurality of signal lines; and

0023a current control driver which is connected to other ends of the plurality of signal lines and reduces a current value of a gradation signal by a predetermined current reduction ratio and lets a write current flow in the signal lines.

0024In the display apparatus according to the second aspect of the invention, plural pixels are provided on one end side of a plurality of signal lines and the current control driver is provided on the other end side, the pixels and the current control driver can be set apart from each other and the layout area of the optical element in each pixel is not restricted by the current control driver.

0025A display apparatus according to a further aspect of the invention comprises:

0026a optical element which has a pair of electrodes and demonstrates an optical operation according to a current flowing between the pair of electrodes;

0027a first switching element having a control terminal and a current path whose one end is connected to one of the pair of electrodes of the optical element so that a current with a value according to a voltage between the control terminal and the one end of the current path flows in the current path;

0028a power supply line which is connected to the other end of the current path of the first switching element and on which a power supply signal for allowing a drive current to flow in the optical element is output;

0029a scan line on which a scan signal for selecting the optical element is output;

0030a signal line in which a write current flows from the power supply line via the current path of the first switching element;

0031a second switching element which controls a voltage to be applied to the control terminal of the first switching element in accordance with the scan signal on the scan line;

0032a third switching element which controls a current flowing in the signal line in accordance with the scan signal in the scan line;

0033a capacitor which holds a voltage between the control terminal of the first switching element and the one end of the current path of the first switching element; and

0034a current control driver which allows the write current obtained by reducing a current value of a gradation signal by a predetermined current reduction ratio to flow in the signal line.

0035Even in a display apparatus in which the current control active element for an optical element is constituted by using the first switching element, the second switching element and the third switching element, as apparent from the above, the provision of the current control driver which allows the write current to flow in the signal line can bring about an advantage of securing the layout area of the optical element more effectively. Because the first switching element, the second switching element and the third switching element can be driven even if they are N channel transistors, amorphous silicon TFTs for which a P channel transistor with a sufficient effective speed has not been achieved can be adapted, which makes the manufacture of the display apparatus easier.

0036A drive method for display apparatus according to a different aspect of the invention comprises:

0037a current-writing step of allowing a write current obtained by reducing a current value of a gradation signal by a predetermined current reduction ratio to flow to a plurality of pixels via a plurality of signal lines; and

0038a drive current step of allowing a drive current equal in value to the write current to optical elements of the plurality of pixels.

0039Because the write current whose value is smaller than the current value of the gradation signal of image data flows into the signal line in the invention, a circuit which modulates the current to a minute current need not be provided in a pixel.

BRIEF DESCRIPTION OF THE DRAWINGS

0040<figref idref="DRAWINGS">FIG. 1</figref> is a circuit diagram illustrating a specific mode of a display apparatus to which the invention is adapted;

0041<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram showing a plurality of pixels laid out in a matrix form;

0042<figref idref="DRAWINGS">FIG. 3</figref> is an approximately plan view showing the pixels in <figref idref="DRAWINGS">FIG. 2</figref>;

0043<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view along line IV—IV in <figref idref="DRAWINGS">FIG. 3</figref>;

0044<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view along line V—V in <figref idref="DRAWINGS">FIG. 3</figref>;

0045<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view along line VI—VI in <figref idref="DRAWINGS">FIG. 3</figref>;

0046<figref idref="DRAWINGS">FIG. 7</figref> is a diagram showing the current-voltage characteristic of an N channel field effect transistor;

0047<figref idref="DRAWINGS">FIG. 8</figref> is a timing chart illustrating signals in the display apparatus in <figref idref="DRAWINGS">FIG. 1</figref>;

0048<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram illustrating a specific mode of another display apparatus;

0049<figref idref="DRAWINGS">FIG. 10</figref> is a timing chart illustrating signals in the display apparatus in <figref idref="DRAWINGS">FIG. 9</figref>;

0050<figref idref="DRAWINGS">FIG. 11</figref> is a diagram showing an equivalent circuit of a pixel of a liquid crystal display;

0051<figref idref="DRAWINGS">FIG. 12</figref> is a diagram showing an equivalent circuit of a pixel of a voltage-writing display apparatus; and

0052<figref idref="DRAWINGS">FIG. 13</figref> is a diagram showing an equivalent circuit of a pixel of a conventional current-writing display apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0053The following will describe specific modes of the invention referring to the accompanying drawings. It is to be noted however that the scope of the invention is not limited to the illustrated examples.

First Embodiment

0054<figref idref="DRAWINGS">FIG. 1</figref> is a circuit diagram illustrating a display apparatus to which the invention is adapted. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the basic structure of the display apparatus <b>1</b> has an organic EL display panel <b>2</b> which provides color display by an active matrix driving system, and a data driver (gradation signal output means) <b>3</b> which outputs gradation signals, represented by current values corresponding to the gradations of image data, to the organic EL display panel <b>2</b> in parallel.

0055The organic EL display panel <b>2</b> has a basic structure that includes a transparent substrate <b>8</b>, a display section <b>4</b> or the display area on which an image is substantially displayed, a select scan driver <b>5</b> provided around the display section <b>4</b> or in the non-display area, a power-supply scan driver <b>6</b> and a current conversion section <b>7</b>. Those circuits <b>4</b> to <b>7</b> are formed on the transparent substrate <b>8</b>. A current control driver has the current conversion section <b>7</b> and the data driver <b>3</b>.

0056In the display section <b>4</b>, (m×n) pixels P_1,1to P_m,n(m and n being arbitrary natural numbers) are provided on the transparent substrate <b>8</b> in a matrix form, m pixels P_1,jto P_m,j(j being an arbitrary natural number and 1≦j≦n) laid out in the column direction or the vertical direction while n pixels P_i,1to P_i,n(i being an arbitrary natural number and 1≦i≦m) are laid out in the row direction or the horizontal direction. That is, the pixel P_i,jis the pixel that is the i-th one (i.e., the i-th row) from the top in the vertical direction and is the j-th one (i.e., the j-th column) from the left in the horizontal direction.

0057In the display section <b>4</b>, m select scan lines X₁to X_marrayed along the row direction are provided on the transparent substrate <b>8</b> in parallel in the column direction. Further, m power-supply scan lines Z₁to Z_marrayed along the row direction are provided on the transparent substrate <b>8</b> in parallel in the column direction in association with the respective select scan lines X₁to X_m. Each power-supply scan line Z_k(1≦k≦m−1) is laid between the select scan line X_kand the select scan line X_k+1 and the select scan line X_mis laid between the power-supply scan line Z_m−1and the power-supply scan line Z_m. Further, n signal lines Y₁to Y_narrayed along the column direction are provided on the transparent substrate <b>8</b> in parallel in the row direction. Those select scan lines X₁to X_m, the power-supply scan lines Z₁to Z_mand the signal lines Y₁to Y_nare insulated from one another by respective intervening insulating films. The select scan line X₁and the power-supply scan line Z₁are connected to the n pixels P_i,1to P_i,nlaid out in the row direction, the m pixels P_1,jto P_m,jlaid out in the column direction are connected to the signal line Y_j, and the pixel P_i,jis located in an area surrounded by the select scan line X_i, the power-supply scan line Z_iand the signal line Y_j.

0058Each pixel P_i,jwill be discussed next referring to <figref idref="DRAWINGS">FIGS. 2 to 6</figref>. <figref idref="DRAWINGS">FIG. 2</figref> is an equivalent circuit diagram of four adjoining pixels P_i,j, P_i+1,j, P_i,j+1and P_i+1,j+1. <figref idref="DRAWINGS">FIG. 3</figref> is a plan view showing the pixel P_i,jand does not show an oxide insulating film <b>41</b>, a channel protection insulating film <b>45</b>, a common electrode <b>53</b> and so forth, which will be discussed later, for easier understanding. <figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view along line IV—IV in <figref idref="DRAWINGS">FIG. 3</figref>, <figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view along line V—V in <figref idref="DRAWINGS">FIG. 3</figref> and <figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view along line VI—VI in <figref idref="DRAWINGS">FIG. 3</figref>.

0059The pixel P_i,jcomprises an organic EL element E_i,jwhich emits light, and a pixel circuit D_i,jwhich is provided around the organic EL element E_i,jand is comprised of an active element to drive the organic EL element E_i,j. The pixel circuit D_i,jkeeps the luminous brightness of the organic EL element E_i,jconstant for a predetermined period of time by holding the value of the current that flows through the organic EL element E_i,jduring a given luminous period based on signals output from the data driver <b>3</b>, the select scan driver <b>5</b> and the power-supply scan driver <b>6</b>.

0060The organic EL element E_i,jhas a lamination structure comprising a pixel electrode <b>51</b>, an organic EL layer <b>52</b> and a common electrode <b>53</b> laminated on the transparent substrate <b>8</b>. The pixel electrode <b>51</b> serves as an anode. The organic EL layer <b>52</b> has a capability which allows holes and electrons to be injected therein by an electric field and a capability of transporting the holes and electrons. Further, the organic EL layer <b>52</b> has a recombining area which recombines transported holes and electrons and a luminous area which emits light by capturing excitons generated by recombination, and thus serves as a luminous layer in a broad sense. The common electrode <b>53</b> serves as a cathode.

0061The pixel electrode <b>51</b> is patterned in such a way as to be separated into segments for the respective pixels P_i,jwhich are respectively surrounded by the signal lines Y₁to Y_nand the select scan lines X₁to X_m. The pixel electrode <b>51</b> has its periphery covered with an interlayer insulating film <b>54</b> of silicon nitrogen or silicon oxide which covers three transistors <b>21</b>, <b>22</b> and <b>23</b> of each pixel circuit D_i,j, and has its center top portion exposed through a contact hole <b>55</b> formed in the interlayer insulating film <b>54</b>. The interlayer insulating film <b>54</b> may have a first layer of silicon nitrogen or silicon oxide and a second layer comprised of an insulating film of polyimide or the like and formed on the first layer.

0062The pixel electrode <b>51</b> has a conductivity and a transmittivity with respect to visible light. It is preferable that the pixel electrode <b>51</b> should have a relatively high work function to efficiently inject holes into the organic EL layer <b>52</b>. As an example, the pixel electrode <b>51</b> essentially consists of tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In₂O₃), tin oxide (SnO₂) or zinc oxide (ZnO).

0063The organic EL layer <b>52</b> is deposited on each pixel electrode <b>51</b>. The organic EL layer <b>52</b> is also patterned for each pixel P_i,j. While the organic EL layer <b>52</b> contains a luminous material (fluorescent substance) which is an organic compound, the luminous material may be a high polymer material or a low polymer material. The organic EL layer <b>52</b> may have, for example, a double-layer structure which comprises a hole transporting layer <b>52</b>A and a luminous layer <b>52</b>B in a narrow sense, which has a recombining area recombination area where electrons and holes are recombined and a luminous area that emits light by capturing excitons generated by recombination, in the named order from the pixel electrode <b>51</b>, as shown in <figref idref="DRAWINGS">FIG. 4</figref>. Alternatively, the organic EL layer <b>52</b> may have a three-layer structure which comprises a hole transporting layer, a luminous layer in a narrow sense and an electron transporting layer arranged in the named order from the pixel electrode <b>51</b>, or may have a single-layer structure comprising a luminous area in a narrow sense.

0064The organic EL display panel <b>2</b> can provide full color display or multi-color display in which case the organic EL layer <b>52</b> of each of the pixels P_i,1to P_i,nis a luminous area in a broad sense which has a capability of emitting light of, for example, red, green or blue. That is, as the individual pixels P_i,1to P_i,nselectively emit lights of red, green and blue, the display can have the color tone with those colors properly combined.

0065It is desirable that the organic EL layer <b>52</b> be of an electrically neutral organic compound, so that holes and electrons are injected and transported in a well-balanced manner in the organic EL layer <b>52</b>. A substance with an electron transporting capability may be adequately mixed in a luminous area in a narrow sense, a substance with a hole transporting capability may be adequately mixed in a luminous area in a narrow sense or a substance with an electron transporting capability and a substance with a hole transporting capability may be adequately mixed in a luminous area in a narrow sense. Further, a charge transporting layer which is an electron transporting layer or a hole transporting layer may be let function as a recombining area and light emission may be achieved by mixing a fluorescent substance in this charge transporting layer.

0066The common electrode <b>53</b> formed on the organic EL layer <b>52</b> is a single electrode connected to all the pixels P_1,1to P_m,n. The common electrode <b>53</b> may comprise a plurality of electrodes of a stripe pattern connected column by column, such as a common electrode of a stripe pattern which connects a group of pixels P_1,h−1to pixels P_m,h−1(h being an arbitrary natural number and 2≦h≦n) in the column direction, a common electrode of a stripe pattern which connects a group of pixels P_1,hto pixels P_m,h, and so forth. Alternatively, the common electrode <b>53</b> may comprise a plurality of electrodes of a stripe pattern connected row by row, such as a common electrode of a stripe pattern which connects a group of pixels P_g−1,1to pixels P_g−1,n(g being an arbitrary natural number and 2≦g≦n) in the row direction, a common electrode of a stripe pattern which connects a group of pixels P_g,1to pixels P_g,n, and so forth. In either case, the common electrode <b>53</b> is electrically insulated from the select scan line X_i, the signal line Y_jand the power-supply scan line Z_i. The common electrode <b>53</b> is formed of a material having a low work function, e.g., a single material or an alloy which contains at least one of indium, magnesium, calcium, lithium, barium and a rare earth metal. The common electrode <b>53</b> may take a lamination structure which has a lamination of multiple layers of the aforementioned materials; specifically, the lamination structure which has a high-purity barium layer with a low work function provided on the interface side that contacts the organic EL layer <b>52</b> and an aluminum layer provided in such a way as to cover the barium layer or the lamination structure which has a lithium layer and an aluminum layer overlying the lithium layer. In case where the pixel electrode <b>51</b> is a transparent electrode and light emitted from the organic EL layer <b>52</b> of the organic EL display panel <b>2</b> is let go out from the transparent substrate <b>8</b> via the pixel electrode <b>51</b>, it is preferable that the common electrode <b>53</b> should have a light-shielding property with respect to light emitted from the organic EL layer <b>52</b> and it is more preferable that the common electrode <b>53</b> should have a high light reflectance with respect to light emitted from the organic EL layer <b>52</b>.

0067As a forward bias voltage is applied between the pixel electrode <b>51</b> and the common electrode <b>53</b> of the organic EL element E_i,jthat has the aforementioned lamination structure, holes are injected into the organic EL layer <b>52</b> from the pixel electrode <b>51</b> and electrons are injected into the organic EL layer <b>52</b> from the common electrode <b>53</b>. Then, the holes and electrons are transported in the organic EL layer <b>52</b> and are recombined in the organic EL layer <b>52</b> to generate excitons. The excitons excite the organic EL layer <b>52</b> which in turn emit light.

0068The luminous brightness (unit of cd/m²) of the organic EL element E_i,jdepends on the value of the current that flows in the organic EL element E_i,j. To keep the luminous brightness of the organic EL element E_i,jconstant during the luminous period of the organic EL element E_i,jor set the luminous brightness to the one that accords to the current value of a gradation signal output from the data driver <b>3</b>, the pixel circuit D_i,jwhich controls the current value of the organic EL element E_i,jis provided around the organic EL element E_i,jfor each pixel P_i,j.

0069Each pixel circuit D_i,jhas three transistors <b>21</b>, <b>22</b> and <b>23</b> each comprised of an N channel MOS field effect thin film transistor (TFT) and a capacitor <b>24</b>.

0070Each transistor <b>21</b> is an MOS field effect transistor which comprises a gate electrode <b>21</b><i>g</i>, a gate insulating film <b>42</b>, a semiconductor layer <b>43</b>, a source electrode <b>21</b><i>s </i>and a drain electrode <b>21</b><i>d</i>, each transistor <b>22</b> is an MOS field effect transistor which comprises a gate electrode <b>22</b><i>g</i>, a gate insulating film <b>42</b>, a semiconductor layer <b>43</b>, a source electrode <b>22</b><i>s </i>and a drain electrode <b>22</b><i>d</i>, and each transistor <b>23</b> comprises a gate electrode <b>23</b><i>g</i>, a gate insulating film <b>42</b>, a semiconductor layer <b>43</b>, a source electrode <b>23</b><i>s </i>and a drain electrode <b>23</b><i>d. </i>

0071Specifically, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, the transistor <b>21</b> is an inverse staggered transistor which comprises the gate electrode <b>21</b><i>g </i>of aluminum provided on the transparent substrate <b>8</b>, the oxide insulating film <b>41</b> formed by anode oxidation of aluminum in such a way as to cover the gate electrode <b>21</b><i>g</i>, the gate insulating film <b>42</b> of silicon nitride or silicon oxide covering the oxide insulating film <b>41</b>, the semiconductor layer <b>43</b> having an island shape formed on the gate insulating film <b>42</b>, the channel protection insulating film <b>45</b> of silicon nitride formed on the semiconductor layer <b>43</b>, impurity semiconductor layers <b>44</b>, <b>44</b> of n⁺ silicon respectively provided on both ends of the semiconductor layer <b>43</b>, and the source electrode <b>21</b><i>s </i>and the drain electrode <b>21</b><i>d</i>, which are respectively formed on the impurity semiconductor layers <b>44</b>, <b>44</b> and whose materials are selected from chromium, a chromium alloy, aluminum, an aluminum alloy or the like.

0072While the transistor <b>22</b> and the transistor <b>23</b> have the same structures as the transistor <b>21</b>, the shapes and sizes of the transistors <b>21</b>, <b>22</b> and <b>23</b>, the channel width, the channel length and the like of the semiconductor layer <b>43</b> are adequately set in accordance with the functions of the transistors <b>21</b>, <b>22</b> and <b>23</b>.

0073The transistors <b>21</b>, <b>22</b> and <b>23</b> may be formed simultaneously in the same process, in which case the components of each of the transistors <b>21</b>, <b>22</b> and <b>23</b>, such as the gate electrode, the oxide insulating film <b>41</b>, the gate insulating film <b>42</b>, the semiconductor layer <b>43</b>, the impurity semiconductor layers <b>44</b>, <b>44</b>, the source electrode and drain electrode, have the same compositions as those of the other transistors.

0074Although the semiconductor layer <b>43</b> of the transistors <b>21</b>, <b>22</b> and <b>23</b>, if it is made of amorphous silicon, can be driven sufficiently, it may be of polysilicon. The structures of the transistors <b>21</b>, <b>22</b> and <b>23</b> may take a staggered type or a coplanar type instead of the inverse staggered type.

0075Each capacitor <b>24</b> comprises an electrode <b>24</b>A connected to the gate electrode <b>23</b><i>g </i>of the transistor <b>23</b>, an electrode <b>24</b>B connected to the source electrode <b>23</b><i>s </i>of the transistor <b>23</b>, and a dielectric having the gate insulating film <b>42</b> intervened between the electrode <b>24</b>A and the electrode <b>24</b>B, and stores charges between the source electrode <b>23</b><i>s </i>and the drain electrode <b>23</b><i>d </i>of the transistor <b>23</b>.

0076As shown in <figref idref="DRAWINGS">FIG. 2</figref>, each transistor <b>22</b> of the i-th row of pixel circuits D_i,1to D_i,nhas the gate electrode <b>22</b><i>g </i>connected to the select scan line X_iof the i-th row and the drain electrode <b>22</b><i>d </i>connected to the power-supply scan line Z_iof the i-th row. The drain electrode <b>23</b><i>d </i>of each transistor <b>23</b> of the i-th row of pixel circuits D_i,1to D_1,nis connected to the power-supply scan line Z_iof the i-th row. The gate electrode <b>21</b><i>g </i>of each transistor <b>21</b> of the i-th row of pixel circuits D_i,1to D_i,nis connected to the select scan line X_iof the i-th row. The source electrode <b>21</b><i>s </i>of each transistor <b>21</b> of the j-th row of pixel circuits D_1,jto D_m,jis connected to the signal line Y_jof the j-th column.

0077In each of the pixels P_1,1to P_m,n, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the source electrode <b>22</b><i>s </i>of the transistor <b>22</b> is connected to the gate electrode <b>23</b><i>g </i>of the transistor <b>23</b> via a contact hole <b>25</b> formed in the gate insulating film <b>42</b> and connected to one electrode of the capacitor <b>24</b>. The source electrode <b>23</b><i>s </i>of the transistor <b>23</b> is connected to the other electrode of the capacitor <b>24</b> and the drain electrode <b>21</b><i>d </i>of the transistor <b>21</b>. The source electrode <b>23</b><i>s </i>of the transistor <b>23</b>, the other electrode of the capacitor <b>24</b> and the drain electrode <b>21</b><i>d </i>of the transistor <b>21</b> are each connected to the pixel electrode <b>51</b> of the organic EL element E_i,j. The potential of the common electrode <b>53</b> of the organic EL element E_i,jis a reference potential V_SSand is set to 0 (V) in the invention as the common electrodes <b>53</b> of all the organic EL elements E_1,1to E_m,n.

0078Provided between the select scan line X_iand the signal line Y_jand between the power-supply scan line Z_iand the signal line Y_jare a protection film <b>43</b>A formed by patterning the same film as the semiconductor layer <b>43</b> of each of the transistors <b>21</b> to <b>23</b> in addition to the gate insulating film <b>42</b>.

0079As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the signal lines Y₁to Y_nare connected to the current conversion section <b>7</b>. Specifically, the current conversion section <b>7</b> comprises current mirror circuits M₁to M_nwhich have one ends connected to the signal lines Y₁to Y_nand other ends connected to the data driver <b>3</b>. That is, the signal line Y_jof the j-th column is connected to the data driver <b>3</b> via the current mirror circuit M_j.

0080The current mirror circuit M_jcomprises a capacitor <b>30</b> and two MOS transistors <b>31</b> and <b>32</b>. The transistors <b>31</b> and <b>32</b> will be described as N channel field effect transistors in the following description.

0081The gate electrode of the transistor <b>31</b> and the gate electrode of the transistor <b>32</b> are connected together to the output terminal, T_j, of the data driver <b>3</b> and one electrode of the capacitor <b>30</b>. The drain electrode of the transistor <b>31</b> is connected to the output terminal T_jof the data driver <b>3</b> and one electrode of the capacitor <b>30</b>.

0082The drain electrode of the transistor <b>32</b> is connected to the signal line Y_j. The source electrode of the transistor <b>31</b> and the source electrode of the transistor <b>32</b> are connected together to the other electrode of the capacitor <b>30</b>. Further, the source electrode of the transistor <b>31</b> and the source electrode of the transistor <b>32</b> are connected to a low power supply <b>40</b> of a potential V_CCwhich is a constant level. The potential V_CCof the low power supply <b>40</b> is lower than the reference potential V_SSand is lower than a select voltage V_SELECTof, for example, −20 V, which will be discussed later.

0083The transistors <b>31</b> and <b>32</b> are so set as to have a relationship given by the following equation 1. <br /><i>W</i>31<i>/L</i>31<i>>W</i>32<i>/L</i>32  (1)<br /> where W<b>31</b> and L<b>31</b> are the channel width and channel length of the transistor <b>31</b>, and W<b>32</b> and L<b>32</b> are the channel width and channel length of the transistor <b>32</b>. As one example, the relationship given by the equation 1 can be provided by making the channel length L<b>31</b> of the transistor <b>31</b> equal to the channel length L<b>32</b> of the transistor <b>32</b> and making the channel width W<b>31</b> of the transistor <b>31</b> longer than the channel width W<b>32</b> of the transistor <b>32</b>. If the channel resistance of the transistor <b>32</b> is higher than the channel resistance of the transistor <b>31</b>, the transistors <b>31</b> and <b>32</b> may have the same channel length. That is, the channel length L<b>31</b> of the transistor <b>31</b> may be shorter than the channel length L<b>32</b> of the transistor <b>32</b> and the channel width W<b>31</b> of the transistor <b>31</b> may be equal to the channel width W<b>32</b> of the transistor <b>32</b>. Alternatively, the channel length L<b>31</b> of the transistor <b>31</b> may be shorter than the channel length L<b>32</b> of the transistor <b>32</b> and the channel width W<b>31</b> of the transistor <b>31</b> may be greater than the channel width W<b>32</b> of the transistor <b>32</b>. This design can allow the channel resistance of the transistor <b>32</b> to be higher than the channel resistance of the transistor <b>31</b>, e.g., about ten times or twenty times the channel resistance of the transistor <b>31</b>.

0084The data driver <b>3</b> outputs gradation signals represented by current values according to the gradations of image data to the current mirror circuits M₁to M_nin response to a clock signal from an external circuit. As the gradation signal is output from the output terminal T_jof the data driver <b>3</b>, the voltage is applied to the drain electrode and the gate electrode of the transistor <b>31</b>, causing the current to flow between the drain and source of the transistor <b>31</b>. At this time, the current also flows between the drain and source of the transistor <b>32</b>. Because the channel resistance of the transistor <b>32</b> is higher than the channel resistance of the transistor <b>31</b> and the voltage level at the gate electrode of the transistor <b>32</b> is equal to the voltage level at the gate electrode of the transistor <b>31</b>, the value of the drain-source current of the transistor <b>32</b> is smaller than the value of the drain-source current of the transistor <b>31</b>. Specifically, the value of the drain-source current of the transistor <b>32</b> is the ratio of the channel resistance of the transistor <b>32</b> to the channel resistance of the transistor <b>31</b> multiplied by the value of the drain-source current of the transistor <b>31</b>, i.e., the product of the channel resistance ratio and the current value, so that the value of the drain-source current of the transistor <b>32</b> is proportional to the value of the drain-source current of the transistor <b>31</b> and is smaller than the value of the drain-source current of the transistor <b>31</b>. It is therefore possible to easily perform gradation control on the minute current that flows in the transistor <b>32</b>. The ratio of the channel resistance of the transistor <b>32</b> to the channel resistance of the transistor <b>31</b> will be hereinafter called “current reduction ratio”.

0085The select scan lines X₁to X_mare connected to the select scan driver <b>5</b>, and the power-supply scan lines Z₁to Z_mto the power-supply scan driver <b>6</b>.

0086The select scan driver <b>5</b> is a so-called shift register. That is, based on the clock signal from the external circuit, the select scan driver <b>5</b> outputs a scan signal to the select scan lines X₁to X_min order from X₁to X_m(the select scan line X_αcomes next to the select scan line X_m) to thereby sequentially scan and select the select scan lines X₁to X_m.

0087In detail, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, the select scan driver <b>5</b> outputs a high-level ON voltage V_on(sufficiently higher than the reference potential V_SS) to set the transistors <b>21</b> and <b>22</b> on to the select scan lines X₁to X_mduring each select period T_SEand outputs a low-level OFF voltage V_off(equal to or lower than the reference potential V_SS) to set the transistors <b>21</b> and <b>22</b> off to the select scan lines X₁to X_mduring each non-select period T_NSE. For each of the select scan lines X₁to X_m, the select period and the select period are so set as to be alternately repeated and not to overlap each other. Therefore, the period that is given by T_SE+T_NSE=T_SCis one scan period.

0088That is, in the select period T_SEwhere any one, X_i, of the select scan lines X₁to X_i, is selected, the select scan driver <b>5</b> outputs a pulse signal with the ON voltage V_onto the select scan line X_ito turn on the transistors <b>21</b> and <b>22</b> (the transistors <b>21</b> and <b>22</b> of every one of the pixel circuits D_i,1, D_i,2, D_i,3, . . . , and D_i,n) that are connected to the select scan line X_i. As the transistor <b>21</b> is turned on, the current that flows in the signal line Y_jcan flow in the pixel circuit D_i,j. At this time, as the transistors <b>21</b> and <b>22</b> of the select scan lines X₁to X₁₋₁and the select scan lines X₁₊₁to X_m, excluding the select scan line X₁, in the select scan lines X₁to X_mare in the non-select period T_NSE, the OFF voltage V_offis output to render both the transistors <b>21</b> and <b>22</b> off. As the transistors <b>21</b> and <b>22</b> are turned off, the current that flows in the signal line Y_jcannot flow in the pixel circuit D_i,j.

0089In each select period T_SEwhere the select scan lines X₁to X_mare selected, the data driver <b>3</b> outputs the gradation signals from all the output terminals T₁to T_n, and the levels of the gradation signals output from the respective output terminals T₁to T_nare represented by current values based on the gradation luminances.

0090The power-supply scan driver <b>6</b> is a so-called shift register. That is, based on the clock signal from the external circuit, the power-supply scan driver <b>6</b> outputs a scan signal to the power-supply scan lines Z₁to Z_min order from Z₁to Z_m(the power-supply scan line Z₁comes next to the power-supply scan line Z_m) to thereby sequentially scan and select the power-supply scan lines Z₁to Z_m.

0091In detail, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, the power-supply scan driver <b>6</b> outputs a low-level select voltage V_SELECT(equal to or less than the reference potential V_SSbut higher than the potential V_CCof the low power supply <b>40</b>) to the power-supply scan lines Z₁to Z_mduring each select period T_SEand outputs a high-level supply voltage V_ddhigher than the select voltage V_SELECTto the power-supply scan line Z_iduring each non-select period T_NSEfollowing each select period T_SE, i.e., during each luminous period TEM. As the supply voltage V_ddthat is applied during each luminous period T_EMis set higher than the reference potential V_SSand the potential V_CC, the drive current can flow into the organic EL elements E_i,1, E_i, 2; E_i,3, . . . , and E_i,nof the i-th row from the power-supply scan line Z_iif the transistor <b>23</b> of the i-th row is on and the transistor <b>21</b> of the i-th row is off.

0092The supply voltage V_ddwill be discussed below. <figref idref="DRAWINGS">FIG. 7</figref> is a graph showing the current-voltage characteristic of the N channel field effect transistor <b>23</b>. In <figref idref="DRAWINGS">FIG. 7</figref>, the horizontal scale shows the level of the drain-source voltage and the vertical scale shows the value of the drain-source current. In the un-saturation area in the diagram or the area where the level, V_DS, of the source-drain voltage of the transistor <b>23</b> is less than a drain saturation voltage level V_TH(the drain saturation voltage level V_THaccords to the level, V_GS, of the gate-source voltage of the transistor <b>23</b>) given that the gate-source voltage level V_GSis constant, a source-drain current value IDS gets larger as the source-drain voltage level V_DSbecomes larger. Further, in the saturation area in the diagram or the area where the source-drain voltage level V_DSis the drain saturation voltage level V_TH, given that the gate-source voltage level V_GSof the transistor <b>23</b> is constant, the source-drain current value I_DSbecomes approximately constant even if the source-drain voltage level V_DSbecomes larger.

0093In <figref idref="DRAWINGS">FIG. 7</figref>, gate-source voltage levels V_GS0to V_GSMAXhave a relationship of V_GS0=0&lt;V_GS1&lt;V_GS2&lt;V_GS3&lt;V_GS4&lt;V_GSMAX. That is, as apparent from <figref idref="DRAWINGS">FIG. 7</figref>, with the source-drain voltage level V_DSbeing constant, as the gate-source voltage level V_GSincreases the source-drain current value IDS becomes larger in both the un-saturation area and the saturation area. Further, as the gate-source voltage level V_GSincreases, the drain saturation voltage level V_THbecomes greater.

0094It is apparent that a slight change in source-drain voltage level V_DSresults in a change in source-drain current value IDS in the un-saturation area, whereas once the gate-source voltage level V_GSis settled, the source-drain current value IDS is determined specifically.

0095Here, the source-drain current value I_DSwhen the transistor <b>23</b> has the gate-source voltage level V_GSMAXis set to the value of the current that flows between the pixel electrode <b>51</b> and the common electrode <b>53</b> of the organic EL element E_i,jthat emits light with the maximum luminance.

0096Even if the gate-source voltage level V_GSOf the transistor <b>23</b> is at the maximum level V_GSMAX, an equation 2 given below is satisfied so that the transistor <b>23</b> keeps the saturation area. <br /><i>V</i>_dd<i>−V</i>_E<i>−V</i>_SS<i>≧V</i>_THMAX  (2)<br /> where V_Eis the voltage level which gradually increases due to the high resistance of the organic EL element E_i,jduring the luminous life period of the organic EL element E_i,jand is divided to the voltage of the organic EL element E_i,jat the time of the maximum luminance, and V_THMAXis the saturation threshold voltage level between the source and drain of the transistor <b>23</b> at the time of V_GSMAX. The supply voltage V_ddis determined in such a way as to satisfy the equation 2.

0097The following will discuss the display operation of the display apparatus <b>1</b> with the above-described structure and how to drive the display apparatus <b>1</b>.

0098Based on the input clock signal, the select scan driver <b>5</b> sequentially outputs a pulse signal of a high level (ON voltage V_on) to the select scan line X_mof the m-th row from the select scan line X₁of the first row. At the same time, the power-supply scan driver <b>6</b> sequentially outputs a pulse signal of a low level (select voltage V_SELECT) to the power-supply scan line Z_mof the m-th row from the power-supply scan line Z₁of the first row based on the input clock signal. During the select period T_SEof each row, the data driver <b>3</b> outputs current values corresponding to the gradations of image data to the current mirror circuits M₁to M_nfrom all the output terminals T₁to T_nbased on the clock signal.

0099As shown in <figref idref="DRAWINGS">FIG. 8</figref>, in each row, the timing at which the ON signal of the high-level voltage V_onis output to the select scan line X_imatches with the timing at which the charge signal of the low-level voltage V_SELECTis output to the power-supply scan line Z_i, the time length of the ON signal of the high-level voltage V_onis nearly equal to the time length of the charge signal of the low-level voltage V_SELECTand those pulse signals are output during the select period T_SE(between time t_1Sto time t_1Ein the first row). That is, the period in which the voltage V_onoutput from the select scan driver <b>5</b> is synchronous with the period in which the voltage V_SELECToutput from the power-supply scan driver <b>6</b> is shifted. Of the first row to the m-th row, that row in which the ON signal of the high-level V_onis output from the select scan driver <b>5</b> is a so-called selected row, and charges stored in the capacitor <b>24</b> of each of the pixels of that row is newly written while the row is selected.

0100As apparent from the above, as the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> shift the pulse signals sequentially from the first row to the m-th row, the pulse signals are sequentially written in the pixels P_1,1, to P_m,nfrom the first row of pixels P_1,1to P_1,nto the m-th row of pixels P_m,1to P_m,nbased on the gradation signals from the data driver <b>3</b>. As such linear sequential scanning is repeated, an image is displayed on the display section <b>4</b> of the organic EL display panel <b>2</b>.

0101A description will now be given of writing of the gradations of the selected i-th row of pixels P_1,1to P_i,nin one scan period T_SC.

0102In the select period T_SEof the i-th row, as the high-level ON signal is output to the select scan line X_iof the i-th row from the select scan driver <b>5</b>, the transistors <b>21</b> and the transistors <b>22</b> of all the pixel circuits D_i,1to D_i,nconnected to the select scan line X_iare turned on during the select period T_SE. Further, in the select period T_SEof the i-th row, as the low-level charge signal is output to the power-supply scan line Z_iof the i-th row from the power-supply scan driver <b>6</b>, the select voltage V_SELECTequal to or lower than the reference potential V_SSis applied to the power-supply scan line Z_iduring the select period T_SE. As the transistor <b>22</b> is on, the voltage is also applied to the gate electrode <b>23</b><i>g </i>of the transistor <b>23</b>, rendering the transistor <b>23</b> on.

0103The current values of the gradation signals that are output in parallel from the output terminals T₁to T_nof the data driver <b>3</b> during the select period T_SEfor each row are determined based on image data input from the external circuit. The transistor <b>31</b> that has been turned on by the gradation signal causes the current to flow through the path of output terminal T_j→transistor <b>31</b>→low power supply <b>40</b> in each of the current mirror circuits M₁to M_n.

0104The value of the current that flows through the path of output terminal T_j→transistor <b>31</b>→low power supply <b>40</b> accords to the level of the gradation signal. That is, the value of the current that flows through the path of output terminal T_j→transistor <b>31</b>→low power supply <b>40</b> is the same as the current value of the gradation signal. Then, the capacitor <b>30</b> is charged with charges in accordance with the current that flows through the path of output terminal T_j→transistor <b>31</b>→low power supply <b>40</b>. In accordance with the voltage that is charged according to the gradation signal, the transistor <b>32</b> causes the write current to flow between the source and drain. The value of the current that the transistor <b>32</b> attempts to flow at this time is determined by the ratio of the channel resistance of the transistor <b>32</b> to the channel resistance of the transistor <b>31</b>. That is, the value of the current that the transistor <b>32</b> attempts to flow is determined by the current reduction ratio. The individual current mirror circuits M₁to M_nhave the same current reduction ratio.

0105In the select period T_SEof the i-th row, as described above, the transistors <b>21</b>, <b>22</b> and <b>23</b> of every one of the i-th row of pixel circuits D_i,1to D_i,nare on and the voltage level of the power-supply scan line Z_iis the select voltage V_SELECT, the write current that flows in every one of the i-th row of pixel circuits D_i,1to D_i,nflows through the path of power-supply scan line Z_i→transistor <b>23</b>→transistor <b>21</b>→signal lines Y₁to Y_n→each transistor <b>32</b> of the current mirror circuits M₁to M_n→low power supply <b>40</b>. At this time, the value of the write current that likewise flows through the path of power-supply scan line Z_i→transistor <b>23</b>→transistor <b>21</b>→signal lines Y₁to Y_n→each transistor <b>32</b> of the current mirror circuits M₁to M_n→low power supply <b>40</b> in any one of the first column to the n-th column due to the function of the current mirror circuit M_jis the value of the current that flows through the path of output terminal T_j→transistor <b>31</b>→low power supply <b>40</b> multiplied by the current reduction ratio of the current mirror circuit M_j. Provided that the channel lengths of the transistors <b>31</b> and <b>32</b> are set equal to each other and the ratio of the channel width of the transistor <b>31</b> to the channel width of the transistor <b>32</b> is set to 20:1 in each other the In each of the current mirror circuits M₁to M_n, for example, the current reduction ratio becomes 1/20 and the value of the current that flows between the source and drain of the transistor <b>32</b> or the value of the current that flows between the source and drain of the transistor <b>31</b> with respect to the current value of the gradation signal output from the output terminal T_jbecomes 1/20.

0106As apparent from the above, because of the current mirror circuit M_jconnected to the signal line Y_j, the value of the write current of the signal line Y_jdepends on the value of the drain-source current of the transistor <b>31</b> and can be made smaller than the value of the drain-source current of the transistor <b>31</b>. To ensure the organic EL element E_i,jwith the luminous gradation according to image data, it is necessary to supply the organic EL element E_i,jwith a current which has a very small value with a small gradation-originated variation. According to the invention, should the data driver <b>3</b> not be able to supply such a gradation current directly to the organic EL element E_i,j, the value of the currents output from the output terminals T₁to T_nof the data driver <b>3</b> can be modulated to minute values with slight gradation variations by intervening the current conversion section <b>7</b> whose current reduction ratio has been set to a given value beforehand by the design of the transistors <b>31</b> and <b>32</b>, between the data driver <b>3</b> and the individual signal lines Y₁to Y_n. Even if the value of the drain-source current of the transistor <b>31</b> is slightly deviated from the current value that should originally be output due to the occurrence of a leak current in the interconnection between the data driver <b>3</b> and the transistor <b>31</b>, therefore, the deviation of the write current value of the signal line Y_jis suppressed low in proportional to the current reduction ratio, which can in turn suppress the deviation of the luminous gradation of the organic EL element E_i,jas will be discussed later.

0107In the select period T_SEof the i-th row, as described above, in every one of the i-th row of pixel circuits D_i,1to D_i, the write current flows through the path of power-supply scan line Z_i→transistor <b>23</b>→transistor <b>21</b>→signal lines Y₁to Y_n→each transistor <b>32</b> of the current mirror circuits M₁to M_n→low power supply <b>40</b>. The value of the write current that flows in each of those pixel circuits D_i,1to D_i,nis the current value output from the respective one of the output terminals T₁to T_nmultiplied by the current reduction ratio of the associated one of the current mirror circuits M₁to M_nand is the value of the current that flows in the associated one of the organic EL elements E_i,1to E_i,nin the luminous period T_EMto be discussed later.

0108At this time, the other end of the capacitor <b>24</b> of each of the i-th row of pixel circuits D_i,1to D_i,n(the source electrode <b>23</b><i>s </i>of the transistor <b>23</b>) has a potential which corresponds to the current value of the gradation signal output from the data driver <b>3</b> and is equal to or lower than the gate potential of the transistor <b>23</b>. That is, in each of the i-th row of pixel circuits D_i,1to D_i,n, the capacitor <b>24</b> is charged with charges whose quantity accords to the voltage level between the gate electrode <b>23</b><i>g </i>and source electrode <b>23</b><i>s </i>of the transistor and accords to the value of the current that flows in the transistor <b>23</b>. That is, the write current according to the current value of the gradation signal flows between the source and drain of the transistor <b>23</b> and the signal lines Y₁to Y_n, resulting in that the voltage needed to allow the write current of a given current value to flow is applied between the gate electrode <b>23</b><i>g </i>and source electrode <b>23</b><i>s </i>of the transistor <b>23</b> and the capacitor <b>24</b> is charged with charges whose quantity accords to the voltage between the gate electrode <b>23</b><i>g </i>and source electrode <b>23</b><i>s </i>of the transistor <b>23</b>, so that the quantity of charges charged in the capacitor <b>24</b> accords to the value that is obtained by multiplying the current value of the gradation signal by the current reduction ratio. In other words, in the select period T_SE, in each of the i-th row of pixel circuits D_i,1to D_i,n, as the transistors <b>21</b> and <b>22</b> forcibly let the write current whose value is the current value of the gradation signal multiplied by the current reduction ratio flow in the transistor <b>23</b> too, the write current forcibly flows in the transistor <b>23</b> and the write current is forcibly converted to the gate-source voltage between the gate and source where the current flows, and the capacitor <b>24</b> serves to hold the gate-source voltage over a predetermined period.

0109As apparent from the above, at time t_iSwhere the select period T_SEstarts, charges charged in the capacitor <b>24</b> of each of the i-th row of pixel circuits D_i,1to D_i,nhave been refreshed since the previous one scan period T_SCand newly written and the current value of the capacitor <b>24</b> of each of the i-th row of pixel circuits D_i,1to D_i,nhas also been refreshed since the previous one scan period T_SCand newly written.

0110In any one of the i-th row of pixel circuits D_i,1to D_i,n, the potential at any point in the path of transistor <b>23</b>→transistor <b>21</b>→signal line Y_jvaries due to the internal resistances or the like of the transistors <b>21</b>, <b>22</b> and <b>23</b> which change with time. According to the embodiment, however, the value of the write current that flows through the path of transistor <b>23</b>→transistor <b>21</b>→signal line Y_jis forcibly set so as to be the current value of the gradation signal output from the output terminal T_jmultiplied by the current reduction ratio, regardless of changes in the internal resistances of the transistors <b>21</b>, <b>22</b> and <b>23</b>. Even if the internal resistances of the transistors <b>21</b>, <b>22</b> and <b>23</b> change with time, therefore, the value of the write current that flows through the path of transistor <b>23</b>→transistor <b>21</b>→signal line Y_jdoes not depend on changes in the internal resistances of the transistors <b>21</b>, <b>22</b> and <b>23</b>.

0111In the select period T_SEof the i-th row, because the reference potential V_SSis applied to the common electrode <b>53</b> of each of the i-th row of organic EL elements E_i,1to E_i,nand the power-supply scan line Z_iis at the select voltage V_SELECTwhich is equal to or the reference potential V_SS, 0 (V) or the reverse bias voltage is applied to the i-th row of organic EL elements E_i,1to E_i,nso that the current does not flow in the i-th row of organic EL elements E_i,1to E_i,n. Therefore, the current that flows through the transistor <b>23</b> becomes the write current itself which flows in the signal lines Y₁to Y_n.

0112At time t_iEwhere the select period T_SEof the i-th row ends (start time t_iEof the non-select period T_NSE), the high-level ON signal output on the select scan line X_ifrom the select scan driver <b>5</b> ends and the low-level charge signal output on the power-supply scan line Z_ifrom the power-supply scan driver <b>6</b> ends. That is, in the non-select period T_NSEfrom the end time t_iEto the start time t_iSof the next select period T_SE, the select scan driver <b>5</b> applies the OFF signal with the level of the OFF voltage V_offto the gate electrode <b>21</b><i>g </i>of the transistor <b>21</b> and the gate electrode <b>22</b><i>g </i>of the transistor <b>22</b> in each of the i-th row of pixel circuits D_i,1to D_i,nand the power-supply scan driver <b>6</b> applies the forward bias signal with the level of the supply voltage V_ddto the power-supply scan line Z_i.

0113In the non-select period T_NSEof the i-th row, therefore, the transistors <b>21</b> of the i-th row of pixel circuits D_i,1to D_i,nare turned off to cut off the write current that flows into the signal lines Y₁to Y_nfrom the power-supply scan line Z_i(it is to be noted that in the non-select period T_NSEof the i-th row, the write current flows into the signal lines Y₁to Y_nfrom any one of the power-supply scan line Z₁to Z_mexcluding the power-supply scan line Z_i). Further, in the non-select period T_NSEof the i-th row, in any one of the i-th row of pixel circuits D_i,1to D_i,n, even if the transistors <b>21</b> and <b>22</b> are turned off, the charges that have been charged in the capacitor <b>24</b> in the immediately previous select period T_SEare confined by the transistors <b>21</b> and <b>22</b> and the transistor <b>23</b> keeps the drive state according to the charges charged in the capacitor <b>24</b>. That is, in any one of the i-th row of pixel circuits D_i,1to D_i,n, the gate-source voltage V_GSof the transistor <b>23</b> is substantially identical in both the non-select period T_NSEand the immediately previous select period T_SE.

0114Even in the non-select period T_NSEof the i-th row, therefore, the transistors <b>23</b> in the i-th row of pixel circuits D_i,1to D_i,nkeep letting the drive current having the same value as the write current in the immediately previous select period T_SEflow. Because the common electrodes <b>53</b> of the i-th row of organic EL elements E_i,1, to E_i,nhave the reference potential V_SSand the power-supply scan line Z_ihas the supply voltage V_ddhigher than the in the non-select period T_NSEreference potential V_SS, the forward bias voltage is applied to the i-th row of organic EL elements E_i,1to E_i,n. The drive current flows in each of the i-th row of organic EL elements E_i,1to E_i,nbecause of the function of the transistor <b>23</b>, the organic EL elements E_i,1to E_i,nemit lights. In the pixels P_i,1to P_i,nof the i-th row, the gradation signals output from the output terminals T₁to T_nof the data driver <b>3</b> and the drive current equal to the write current that flows in the signal lines Y₁to Y_nin the select period T_SEby the current conversion section <b>7</b> with a given current reduction ratio flow in the organic EL elements E_i,1to E_i,nin the non-select period T_NSE, thus allowing the luminous brightness of the gradations according to image data to be controlled and maintained.

0115That is, in the non-select period T_NSEof the i-th row, in any of the i-th row of pixel circuits D_i,1, to D_i,n, the transistor <b>21</b> serves to electrically cut off between the signal line Y_jand the transistor so as not to let the write current flowing in the signal line Y_jflow in the transistor <b>23</b>, the transistor <b>22</b> serves to trap the charges in the capacitor <b>24</b> to thereby keep the gate-source voltage of the transistor <b>23</b> converted in the select period T_SE, and the transistor <b>23</b> serves to let the drive current with the value according to the held gate-source voltage flow in the organic EL element E_i,j.

0116The values of the drive currents flowing in the organic EL elements E_i,1to E_i,nare the same as the drive currents flowing in the associated transistors <b>23</b> of the pixel circuits D_i,1to D_i,nand thus are the same as the values of the write currents flowing in the associated transistors <b>23</b> of the pixel circuits D_i,1to D_i,n. In the luminous period TEM of the i-th row (i.e., the non-select period T_NSE), the drive currents with such values flow in the i-th row of organic EL elements E_i,1to E_i,nwhich in turn emit lights with the luminous gradations according to the respective drive current values. In the select period T_SEof the i-th row, as mentioned above, the current values of the transistors <b>23</b> of the i-th row of pixel circuits D_i,1to D_i,nbecome the desired values so that the organic EL elements E_i,1to E_i,nare supplied with the desired drive currents and thus keep emitting lights with the desired luminous gradations until the next select period T_SE.

0117The provision of the current mirror circuits M₁to M_non the data driver side of the respective signal lines Y₁to Y_nin the embodiment makes it unnecessary to provide a current mirror circuit for each pixel. This can minimize the number of transistors to be provided pixel by pixel, making it possible to suppress the reduction in the numerical aperture of the pixels and supply minute currents according to the luminous gradations of the organic EL elements E_1,1to E_m,n.

0118The current mirror circuits M₁to M_nallow the write currents whose values are proportional to the current values of the gradation signals flow in the signal lines Y₁to Y_n. Even if the data driver <b>3</b> cannot itself let minute write currents flow, therefore, minute write currents with the adequate values for the luminous brightnesses of the organic EL elements E_1,1to E_m,ncan flow in the signal lines Y_j.

0119Further, the provision of the current mirror circuits M₁to M_nmake the values of the write currents of the signal lines Y₁to Y_nproportional to the current values of the gradation signals from the output terminals T₁to T_n(i.e., the values of the drain-source currents of the transistors <b>31</b>) and smaller than the values of the drain-source currents of the transistors <b>31</b>. Even if the occurrence of a leak current in the data driver <b>3</b> or the like reduces the value of the current flowing from any of the output terminals T₁to T_n(i.e., the drain-source current value of the transistor <b>31</b>), therefore, the reduction in the current value of the associated one of the signal lines Y₁to Y_nbecome smaller so that the drain-source current value does not become significantly small. In other words, even if the leak current reduces the output of the data driver <b>3</b>, it does not significantly affect the current values of the signal lines Y₁to Y_nand the luminous brightnesses of the organic EL elements E_1,1to E_m,ndo not get considerably lower.

Second Embodiment

0120<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram illustrating a display apparatus <b>101</b> of a different mode from the display apparatus <b>1</b> according to the first embodiment. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, the display apparatus <b>101</b> has an organic EL display panel <b>102</b> which provides color display by the active matrix driving system and a shift register <b>103</b>.

0121The organic EL display panel <b>102</b> has a basic structure that includes a transparent substrate <b>8</b>, a display section <b>4</b> or the display area on which an image is substantially displayed, a select scan driver <b>5</b> provided around the display section <b>4</b> or in the non-display area, a power-supply scan driver <b>6</b> and a current conversion section <b>107</b>. Those circuits <b>4</b> to <b>6</b> and <b>107</b> are formed on the transparent substrate <b>8</b>. The display section <b>4</b>, the select scan driver <b>5</b>, the power-supply scan driver <b>6</b> and the transparent substrate <b>8</b> are the same as those of the display apparatus <b>1</b> of the first embodiment. In case of the P⁺ substrate <b>101</b> of the second embodiment, therefore, the timing for voltage application by the select scan driver <b>5</b>, the timing for voltage application by the power-supply scan driver <b>6</b>, the refreshing of the pixels P_1,1to P_m,nand the gradation expression of the pixels P_1,1to P_m,nare the same as those of the display apparatus <b>1</b> of the first embodiment.

0122It is to be noted however that the second embodiment differs from the first embodiment in how to apply the write current; specifically, while the data driver <b>3</b> and the current conversion section <b>7</b> allow the write current to flow in the signal lines Y_αto Y_nin the display apparatus <b>1</b> of the first embodiment, the shift register <b>103</b> and the current conversion section <b>107</b> allow the write current to flow in the signal lines Y₁to Y_n.

0123In the current conversion section <b>107</b>, the current mirror circuits M₁to M_nare provided column by column as in the current conversion section <b>7</b> of the first embodiment, in addition to which first transistors L₁to L_n, second transistors S₁to S_nand third transistors W₁to W_nare provided column by column.

0124The first transistors L₁to L_n, second transistors S₁to S_nand third transistors W₁to W_nare MOS field effect thin film transistors and particularly are a-Si transistors each having an amorphous semiconductor layer, but may be p-Si transistors each having a polysilicon semiconductor layer or integrated circuits of monocrystalline silicon. Further, the first transistors L₁to L_n, second transistors S₁to S_nand third transistors W₁to W_nmay have an inverse staggered type structure or a coplanar structure. The first transistors L₁to L_n, second transistors S₁to S_nand third transistors W₁to W_nwill be described as N channel field effect transistors in the following description.

0125With regard to each column, the current mirror circuit M_jcomprises transistors <b>31</b> and <b>32</b> and a capacitor <b>30</b> as per the first embodiment. The connections and structures of those components <b>30</b> to <b>32</b> are basically the same as those of the first embodiment, but differ in that the drain electrode of the transistor <b>31</b> is connected to the source electrode of the transistor W_j, the gate electrodes of the transistors <b>31</b> and <b>32</b> are connected to the source electrode of the second transistor S_jand the drain electrode of the transistor is connected to the source electrode of the first transistor L_j.

0126The drain electrode of the first transistor L_jis connected to the signal line Y_j. The gate electrodes of the first transistors L₁to L_nare commonly connected to a sync-signal input terminal <b>160</b>.

0127The gate electrode of the second transistor S_jand the gate electrode of the third transistor W_jare connected together to an output terminal R_jof the shift register <b>103</b>. The drain electrodes of the second transistors S₁to S_nand the drain electrodes of the third transistors W₁to W_nare connected together to a common gradation-signal input terminal <b>170</b>.

0128Based on a clock signal from an external circuit, the shift register <b>103</b> shifts and outputs the ON-level pulse signal from the output terminal R₁to the output terminal R_nin order (the output terminal R₁comes next to the output terminal R_n) to thereby sequentially select the current mirror circuits M₁to M_n. One shift period of the shift register <b>103</b> is shorter than one shift period of the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> in such a way that while the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> shift the pulse signal to the (i+1)-th row from the i-th row, the shift register <b>103</b> sequentially shifts the pulse signals of the first column to the n-th column of the (i+1)-th row to the output terminal R_nfrom the output terminal R₁and outputs n ON-level pulse signals.

0129The gradation signals of the first row to the n-th row are sequentially input to the gradation-signal input terminal <b>170</b> in each select period T_SEby the external circuit. When the gradation signal of the i-th row is input from the gradation-signal input terminal <b>170</b>, the current mirror circuits M₁to M_ncauses the write current which is the current value of that gradation signal multiplied by the current reduction ratio to flow between the source and drain of each transistor <b>23</b> of the i-th row and in the signal lines Y₁to Y_n. As the capacitor <b>24</b> holds charges matching with that write current, the drive current whose value is equal to the value of the write current flows between the source and drain of each transistor <b>23</b> and in the organic EL elements E_i,1to E_i,nin the non-select period T_NSE(luminous period T_EM) of the first row, so that the organic EL elements E_i,1to E_i,nemit light with a given luminous brightness. The gradation signal which is input from the gradation-signal input terminal <b>170</b> may be either an analog signal or a digital signal, and is input to the drain electrodes of the second transistors S₁to S_nand the drain electrodes of the third transistors W₁to W_nat the timings at which the ON-level pulse signals from the output terminals R₁to R_nof the shift register <b>103</b> are input. The period of the gradation signal for one row is shorter than the one shift period of the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> in such a way that while the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> shift the pulse signal to the (i+1)-th row from the i-th row, the gradation signals of the organic EL elements E_i+1,1to E_i+1,nare respectively input to the current mirror circuits M₁to M_n.

0130After the shift register <b>103</b> inputs the gradation signal from the gradation-signal input terminal <b>170</b> to the current mirror circuits M₁to M_n, the sync signal is input to the sync-signal input terminal <b>160</b> from the external circuit. The period of the sync signal is the same as one shift period of the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> and the period in which the ON-level sync signal is input is the period in which the select scan driver <b>5</b> and power-supply scan driver <b>6</b> output the ON-level pulse signal. Every time the select scan driver <b>5</b> and the power-supply scan driver <b>6</b> shift the pulse signal, therefore, the sync signal with the ON-level voltage is input to the sync-signal input terminal <b>160</b>.

0131The operation of the display apparatus <b>101</b> with the above-described structure will be explained below.

0132As shown in <figref idref="DRAWINGS">FIG. 8</figref>, the select scan driver <b>5</b> and power-supply scan driver <b>6</b> shift the pulse signal to the first row to the m-th row line by line, as per the first embodiment.

0133As shown in <figref idref="DRAWINGS">FIG. 10</figref>, the shift register <b>103</b> shifts the ON-level pulse signal of the second transistors S₁to S_nand the third transistors W₁to W_nfrom the output terminal R₁to the output terminal R_nbetween the select period T_SEof the (i−1)-th row and the select period T_SEof the i-th row. While the shift register <b>103</b> is shifting the pulse signal, the voltage of the sync-signal input terminal <b>160</b> is at an OFF level (low level).

0134When the shift register <b>103</b> outputs the ON-level pulse signal to the output terminal R_j, the gradation signal for the organic EL element E_i,jis input to the gradation-signal input terminal <b>170</b>. Because the j-th row of second transistors S_jand third transistors W_jare on at this time, the gradation signal for the organic EL element E_i,jis input to the current mirror circuit M_j, rendering the transistor <b>31</b> and transistor <b>32</b> on, and the capacitor <b>30</b> is charged with charges whose quantity accords to the current value of the gradation signal. That is, the second transistor S_jand the third transistor W_jserve to fetch the gradation signal into the current mirror circuit M_jat the time of selecting the j-th row.

0135As the transistor <b>31</b> of the j-th column is turned on, the current flows through the path of gradation-signal input terminal <b>170</b>→third transistor W_j→transistor <b>31</b>→low power supply <b>40</b> in the current mirror circuit M_j, and the capacitor <b>30</b> is charged with the charges.

0136As the voltage of the sync-signal input terminal <b>160</b> has an OFF level at this time, the first transistor L_jis off so that the write current does not flow in the current mirror circuit M_jand the signal line Y_j.

0137When the pulse signal is output to the output terminal R_j+1by the shift register <b>103</b>, the gradation signal for the organic EL element E_i,j+1is input to the gradation-signal input terminal <b>170</b> and the capacitor <b>30</b> of the (j+1)-th column is charged with charges whose quantity accords to the current value of the gradation signal as in the case of the j-th column. Because the transistors S_jand W_jof the j-th row are off at this time, the charges charged in the capacitor <b>30</b> of the j-th column are confined by the transistor S_j, so that the capacitor <b>30</b> of the j-th column allows the transistor <b>31</b> and transistor <b>32</b> of the j-th column to keep the ON state without being affected by the gradation signal of the (j+1)-th column. That is, even when the j-th column is not selected, the transistor S_jserves to keep the gate voltage according to the current value of the gradation signal of the time at which the j-th column is selected.

0138As the shift register <b>103</b> shifts the pulse signal in the above-described manner, the capacitors <b>30</b> of the first column to the n-th column are charged with the charges whose quantity accords to the current value of the gradation signal column by column in the named order.

0139When charging of the capacitor <b>30</b> of the n-th row is completed, the shift register <b>103</b> temporarily stops shifting the pulse signal and when the directly subsequent i-th select period T_SEcomes, the ON-level (high-level) sync signal from the sync-signal input terminal <b>160</b> is input to all columns of first transistors L₁to L_nwhich are in turn rendered on simultaneously. At this time, each capacitor <b>30</b> is charged with the charges according to the gradation signal of each column the transistors <b>31</b> and <b>32</b> of each column allow the write current to flow there according to the charges of the capacitor <b>30</b>. While the write currents flowing in the i-th row of pixel circuits D_i,1to D_i,nflow through the path of power-supply scan line Z_i→individual transistors <b>23</b> of pixel circuits D_i,1to D_i,n→individual transistors <b>21</b> of pixel circuits D_i,1to D_i,n→signal lines Y₁to Y_n→individual first transistors L₁to L_n→individual transistors <b>32</b> of current mirror circuits M₁to M_n→low power supply <b>40</b>, the values of the write currents flowing toward the low power supply <b>40</b> from the power-supply scan line Z_ibecome the current values of the associated gradation signal currents flowing through the path of gradation-signal input terminal <b>170</b>→individual third transistors W₁to W_n→individual transistors <b>31</b> of current mirror circuits M₁to M_n→low power supply <b>40</b> multiplied by the current reduction ratios of the current mirror circuits M₁to M_n.

0140In the subsequent non-select period T_NSEof the i-th row, the drive currents whose values are the values of the gradation signal currents multiplied by the current reduction ratios flow in the transistors <b>23</b> of the pixel circuits D_i,1to D_i,nand the organic EL elements E_i,1to E_i,nas per the first embodiment, so that the display section <b>4</b> emit light with the gradation brightnesses that match with the drive currents of the i-th row of organic EL elements E_i,1to E_i,n.

0141As the first half of the non-select period T_NSEof the i-th row becomes the shift period of the (i+1)-th row, the sync-signal input terminal <b>160</b> becomes off level (low level) then, the shift register <b>103</b> sequentially outputs the (i+1)-th row of pulse signals to the output terminals R₁to R_nand the gradation signals for presenting display with the gradation brightnesses of the (i+1)-th row of organic EL elements E_i+1,1to E_i+1,nare written in the current mirror circuits M₁to M_n, respectively.

0142Because the current mirror circuits M₁to M_nare also provided outside the display section <b>4</b> in the second embodiment, it is unnecessary to provide a current mirror circuit in a pixel, thereby making it possible to suppress a reduction in the ratio of the luminous area of the pixel to the non-luminous area. Because the current mirror circuit is not provided pixel by pixel, it is possible to suppress the reduction in production yield and reduce the probability of an in-plane variation in the characteristics of the current mirror circuits. Because of the provision of the current mirror circuit M_j, even if the write current value slightly deviates from the current value that should originally be output to the gradation-signal input terminal <b>170</b> or the like, the deviation of the write current value of the signal line Y_jis suppressed small according to the deviation of the luminous gradation of the organic EL element E_i,jcan thus be suppressed.

0143The present invention is not limited to the above-described embodiments, but may be modified in various forms and subjected to various design changes within the scope of the invention.

0144In the display apparatus <b>1</b> or <b>101</b>, the gradation brightness of the pixel P_i,jis designated by the value of the so-called sink current which is the current drawn out into the signal line Y_jfrom the pixel P_i,j. However, the gradation brightness of the pixel P_i,jmay be designated by the value of the current flowing to the pixel P_i,jfrom the signal line Y_j. In this case, a current mirror circuit is also provided for each signal line to allow the current which is proportional to, and is smaller than, the current value of the gradation signal from the data driver to flow into the signal line.

0145While the active drive circuit for the pixel P_i,jmay be adequately changed, such as using, for example, an MIM element in place of a TFT, it is desirable provide, around the organic EL element, a pixel circuit set in such a way as to hold charges which match with the write current by enforcing the write current flowing in the signal line when the scan line is selected to flow in the pixel circuit and then let the drive current with a value equal to the value of the write current flow in the pixel circuit and organic EL element with the help of the held charges.

0146Although the pixel circuit D_i,jdoes not let the write current flow in the organic EL element E_i,jin the select period T_SEin each embodiment discussed above, the pixel circuit may be so designed as to allow the write current to flow in the organic EL element E_i,jeven in the select period T_SEin which case the value of the drive current allowed to flow in the organic EL element E_i,jin the non-select period T_NSEby the pixel circuit is the same as the value of the write current flowing in the pixel circuit in the immediately previous select period T_SE. The pixel circuit may not comprise three transistors but may comprise four or more transistors as long as it has a capability to allow the drive current with a value equal to the value of the write current in the select period T_SEto flow in the organic. EL element E_i,jin the non-select period T_NSE. It is however desirable that the pixel circuit should comprise fewer transistors.

0147Although the light irradiated from the organic EL element E_i,jis output from the underlying pixel electrode <b>51</b> in the embodiments discussed above, the invention is not limited to this particular design but the common electrode <b>53</b> above the organic EL layer <b>52</b> may be made light transmittive so that light is output from above the organic EL layer <b>52</b>. It is preferable then that the pixel electrode <b>51</b> below the organic EL layer <b>52</b> should be light reflective but may be light transmittive if a non-transmittive or reflective layer is provided below the pixel electrode <b>51</b>.

0148Although the pixel electrode <b>51</b> serves as the anode electrode and the common electrode <b>53</b> serves as the cathode in the above-described embodiments, the pixel electrode <b>51</b> and the common electrode <b>53</b> may be made to serve as the cathode electrode and the anode, respectively.

0149While the current mirror circuits M₁to M_nof each column are provided with the second transistors S₁to S_nand third transistors W₁to W_nrespectively in the second embodiment, the second transistor and the third transistor may be replaced with a single transistor. That is, the j-th column may be provided with a single transistor whose gate is connected to the output terminal R_jof the shift register <b>103</b>, whose drain is connected to the gradation-signal input terminal <b>170</b> and whose source is connected to one electrode of the capacitor <b>30</b>, the drain and gate of the transistor <b>31</b> and the gate of the transistor <b>32</b>, thereby reducing the number of required transistors.

0150Although an organic EL element is used as a luminous element in the above-described embodiments, a luminous element in use may be of the type that does not allow the current to flow when the reverse bias voltage is applied but allow the current to flow when the forward bias voltage is applied and emit light with the brightness according to the size of the flowing current. For example, an LED (Light Emitting Diode) or the like may serve as a luminous element instead of an organic EL element.

0151As the current control driver is not provided pixel by pixel but connected to the signal line, it is possible to minimize the number of elements provided on a pixel. This increases the ratio of the luminous area of the pixel to the non-luminous area and can thus provide a high-definition display with a high numerical aperture.

0152As the write current whose value is proportional to the current value of the gradation signal is allows to flow in the signal line by the current control driver, the write current having the adequate value can be let flow in the signal line even the range of the current value of the gradation signal from the gradation signal output means is beyond the range of the value of the drive current flowing in the luminous element.

0153The write current whose value is proportional to and smaller than the current value of the gradation signal flows in the signal line, so that even when noise occurs in the gradation signal due to the leak current, the current control driver can suppress the noise and is not affected considerably.