Impedance controller and impedance control method

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 2004-0000517, filed on Jan. 6, 2004 that we incorporate by reference.

BACKGROUND

1. Technical Field

The invention relates to a semiconductor device and, more particularly, to an impedance controller for impedance matching with an external device.

2. Discussion of the Related Art

A variety of semiconductor devices, such as microcomputers, memory devices and the like, are used to construct a variety of electrical products. In most cases, the semiconductor devices have input/output pins for receiving and transmitting external data, an output circuit for providing internal data to external devices, and the like. A semiconductor device may provide internal data to other semiconductor devices using a transmission line. In this case, the output impedance of the input/output pins and the impedance of the transmission line must be matched to optimize signal transmission.

One method for realizing impedance matching is to design a system with output impedance matching transmission line impedance and terminating an input to minimize reflective waves. In this method, however, an impedance difference arises due to temperature variations, process changes, and other operating environment characteristics that differ from the design environment. A need exists, therefore, for a device that provides constant impedance regardless of environmental changes. For this reason, some have devised a programmable impedance controller (PIC) capable of sensing transmission line characteristic impedance and providing relevant information to the output circuit. The PIC performs impedance matching according to an external resistor resistance when the resistor is connected to the system by a user. In addition, the controller matches internal to external impedance by actively updating a digital code in a certain period relative to environmental changes, e.g., changes in voltage and temperature.

One example of a conventional PIC is disclosed in U.S. Pat. No. 6,573,746 to Nam-Seog Kim et al. The '746 patent claims priority to Korean Patent No. 10-0394586 entitled Impedance Control Circuit, both the '746 patent and the Korean '586 patent are assigned to Samsung Electronic Co., Ltd.

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a PIC. Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the PIC includes a current mirror section CUR for converting an external impedance RQ connected through a pad ZQ PAD (e.g., a chip pad), to a current I. Up and down detectors UPDET <b>16</b> and DNDET <b>15</b> include a transistor array that is programmed to have the same up and down impedance as the external impedance RQ. Up and down selectors UPSEL <b>18</b> and DNSEL <b>17</b> compare outputs from the detectors <b>15</b> and <b>16</b> to a reference voltage to control outputs of counters <b>12</b> and <b>14</b>. The counters <b>12</b> and <b>14</b> generate digital impedance codes. A register IMPREG <b>20</b> stores the impedance codes and a code transmitter TRANS <b>21</b> serially transmits the impedance codes.

The PIC operates as follows. The current mirror section converts the external impedance RQ, connected with the pad ZQ PAD, to the current I as follows. The comparator <b>10</b>, which is a component of the current mirror section CUR, compares a node voltage VZQ at the pad ZQ PAD to a reference voltage VREF to control a gate voltage of a PMOS transistor M<b>0</b>. If the node voltage VZQ is larger than the reference voltage VREF, the output from the comparator <b>10</b> increases, and in turn, an amount of a current flowing through the PMOS transistor M<b>0</b> decreases. Since all the current flowing through the PMOS transistor M<b>0</b> flows through the external impedance RQ, the node voltage VZQ will lower below a previous value. On the contrary, if the node voltage VZQ is smaller than the reference voltage VREF, the output of the comparator <b>10</b> decreases and, in turn, the amount of the current flowing through the PMOS transistor M<b>0</b> increases. Since all the current flowing through the PMOS transistor M<b>0</b> flows through the external impedance RQ, the node voltage VZQ will increase over the previous value. Through this process, the gate voltage of the PMOS transistor is controlled so that the node voltage VZQ has a value of VDDQ/2. At this time, the current I flowing through the PMOS transistor becomes VDDQ/2RQ.

The current I is also supplied to the up and down detectors <b>15</b> and <b>16</b> via the current mirror. The current I is duplicated and delivered to the down detector <b>15</b> by a PMOS transistor M<b>3</b>. Further, the same current I is duplicated and delivered to the up detector <b>16</b> by a PMOS transistor M<b>1</b>, a NMOS transistor M<b>2</b>, and a NMOS transistor M<b>4</b>.

A bias condition of the up and down detectors must be the same as the external impedance RQ so that the up and down detectors <b>15</b> and <b>16</b> have the same impedance as the external impedance RQ. In other words, when the up and down detectors <b>15</b> and <b>16</b> have output voltages UCUR and DCUR at VDDQ/2 and the current at VDDQ/2RQ, the up and down detectors <b>15</b> and <b>16</b> would have the same impedance as the external impedance RQ.

The comparators <b>11</b> and <b>13</b> compare the output voltage UCUR and DCUR from the up and down detectors <b>15</b> and <b>16</b> with the reference voltage VREF, e.g., VDDQ/2, to determine whether to increase or decrease the size of a transistor array that constitute the up and down detectors <b>15</b> and <b>16</b>.

The outputs from the comparators <b>11</b> and <b>13</b> are delivered to first and second counters <b>12</b> and <b>14</b>. The counters <b>12</b> and <b>14</b> generate impedance codes to program the up and down detectors <b>15</b> and <b>16</b>.

The impedance codes outputted from the counters <b>12</b> and <b>14</b> are also sent to the up and down detectors <b>15</b> and <b>16</b> to control the size of the transistor array.

Thereafter, the output voltages UCUR and DCUR from the up and down detectors <b>15</b> and <b>16</b> are compared back to the reference voltage VREF by the comparators <b>11</b> and <b>13</b>. This comparison result is sent to the counters <b>12</b> and <b>14</b>.

The above-described impedance controller makes the output voltages UCUR and DCUR from up and down detectors <b>15</b> and <b>16</b> be VDDQ/2 through such series of processes so that the impedance of the up and down detectors <b>15</b> and <b>16</b> is the same as the external impedance RQ.

The selectors <b>17</b> and <b>18</b> serve to detect a dithering phenomenon and store the same impedance code as the external impedance RQ in the register <b>20</b>. The dithering phenomenon may indicate when the output voltages UCUR and DCUR output from the detectors <b>15</b> and <b>16</b>, respectively, are not exactly obtained as VDDQ/2 but have an amplitude with a quantization error. The quantization error may be based on the oscillating voltage VDDQ/2. The dithering phenomenon implies that since the impedance of the up and down detectors in the impedance controller is made as two values most similar to the external impedance RQ, the values must be detected to select an optimal one of two impedance codes.

The impedance codes stored in the register <b>20</b> by the selectors <b>17</b> and <b>18</b> are transmitted by the code transmitter <b>21</b>, thus adjusting the output impedance.

<figref idref="DRAWINGS">FIGS. 2 and 3</figref> illustrate graphs showing impedance codes and impedance resolution for different external impedances in the impedance controller of <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates a graph of impedance codes according to impedance values, where an X axis denotes an impedance code and a Y axis denotes an impedance value. <figref idref="DRAWINGS">FIG. 2</figref> demonstrates that when the external impedance is DDR<b>1</b> (50Ω) and DDR<b>3</b> (25Ω), an impedance code (i.e., 20) at the impedance value, DDR<b>3</b> (25Ω), is larger than an impedance code (i.e., 10) at DDR<b>1</b> (50Ω).

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a graph showing impedance codes and impedance resolution for respective external impedances, where an X axis denotes an impedance code and a Y axis denotes impedance resolution. It can be seen that when the external impedance is DDR<b>1</b> (50Ω) and DDR<b>3</b> (25Ω), the impedance resolutions dependent on the impedance code significantly differ as 40 and 30 at the impedance values, DDR<b>3</b> (25%) and DDR<b>1</b> (50%). In other words, if the controller is designed to meet both 50Ω and 25Ω, which correspond to DDR<b>1</b> and DDR<b>3</b>, respectively, the DDR<b>3</b> has impedance resolution of about 2% while the DDR<b>1</b> has impedance resolution of about 4.4%.

Because a range of the impedance is determined by controlling the size of the transistor array that constitutes the detectors, the impedance resolution is high when the size of the transistor array is large and is low when the size of the transistor array is small. A problem arises that, when the impedance controller is applied to two systems having different external impedance, there exists a large difference in impedance resolution between the two systems. Another problem may be that the impedance code varies depending on change in processes, which affects the impedance resolution.

Accordingly a need remains for an improved impedance controller and an impedance control method.

SUMMARY OF THE INVENTION

An object of the invention to provide an improved impedance controller and an impedance control method.

It is another object of the invention to provide an impedance controller and an impedance control method capable of achieving the same impedance resolution even for different external impedances.

It is yet another object of the invention to provide an impedance controller and an impedance control method capable of achieving constant impedance irrespective of changes in external environments, such as changes in operation temperature, process, or the like.

It is yet another object of the invention to provide an impedance controller and impedance control method capable of achieving the same resolution without modifying a circuit in several systems having different external impedances.

In an embodiment, the impedance controller comprises a current mirror section to generate an impedance current. At least one detector that includes a transistor array and an impedance corresponding to the impedance current, the at least one detector operating responsive to a code generator. And an at least one code generator to generate a first code to adjust a gate voltage of the transistor array by comparing an output of the at least one detector to a reference voltage and to generate a second code to adjust a size of the transistor array by comparing the output from the at least one detector to the reference voltage.

The at least one detector may comprise a pull-up detector and a pull-down detector and the at least one code generator comprises a pull-up code generator to control the pull-up detector and a pull-down code generator to control the pull-down detector.

The current mirror section may include an external resistor connected between a ground and a pad, a comparator to generate an impedance control voltage by comparing a voltage at the pad to the reference voltage, a PMOS transistor to apply an impedance current corresponding to the impedance control voltage to the pad, and a current mirror to duplicate the impedance current at the pull-up and pull-down detectors.

The current mirror may include NMOS and PMOS transistors.

The pull-up code generator may include a first comparator to compare an output of the pull-up detector and the reference voltage, a first counter to generate the first and second codes responsive to the first comparator, a first reference ladder to adjust a gate voltage of the transistor array by selecting a node voltage from nodes in a plurality of resistors serially interconnected between a constant-voltage source and the ground responsive to the first code, a first dithering detector to generate a control signal that locks the first code responsive to the pull-up detector detecting a first state and to generate an update control signal responsive to the pull-up detector detecting a second state, and a first register to store the second code responsive to the update control signal.

The pull-down code generator may include a second comparator to compare the pull-down detector output and the reference voltage, a second counter to generate the first and second codes responsive to an output from the second comparator, a second reference ladder to adjust the gate voltage of the transistor array by selecting a node from nodes in a plurality of resistors serially interconnected between the constant-voltage source and the ground responsive to the first code, a second dithering detector to generate a second control signal that locks the first code responsive to the pull-down detector detecting a third state and to generate a second update control signal responsive to the pull-down detector detecting a fourth state, and a second register to store the second code responsive to the second update control signal.

The impedance controller may include a code transmitter to transmit the second code stored in the first register.

The impedance controller may include a code transmitter to transmit the second code stored in the second register.

A constant voltage applied by the constant-voltage source may be a power supply voltage.

The reference voltage may have a level of half a constant-source voltage.

In another embodiment, an impedance control method comprises digitally coding a current corresponding to an impedance control voltage, controlling a detector to have an impedance corresponding to the current, and generating an impedance code corresponding to the current to control a size of a transistor array.

The method may further comprise transmitting the impedance code after generating the impedance code.

Generating the impedance code may include adjusting a gate voltage of the transistor array by selecting a node voltage from a node in a plurality of serially interconnected resistors and generating the impedance code may include applying the node voltage to a gate of the transistor array responsive to the impedance code.

The reference voltage may have a level of half a constant-voltage source or half a power supply voltage.

In yet another embodiment, an impedance control method comprises generating an impedance control voltage by comparing a pad voltage at a pad connected with an external setup resistor to a reference voltage, digitally coding an impedance current corresponding to the impedance control voltage, generating first and second codes by comparing an output voltage to the reference voltage, adjusting a gate voltage of a transistor array responsive to the first code, effecting a first feedback process by comparing the output voltage and the reference voltage until the output voltage is substantially a voltage corresponding to the impedance current responsive to the first code, and effecting a second feedback process by comparing the output voltage and the reference voltage until the output voltage is substantially the voltage corresponding to the impedance current responsive to the second code.

Adjusting the gate voltage may include adjusting the gate voltage by selecting a node voltage from a plurality of nodes associated with a plurality of serially connected resistors responsive to the first code, the plurality of resistors being connected between ground and a constant-voltage source.

The method may further comprise setting the reference voltage to a level of half the constant voltage of the constant-voltage source or a power supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings.

<figref idref="DRAWINGS">FIG. 1</figref> is a schematic block diagram of a conventional impedance controller.

<figref idref="DRAWINGS">FIG. 2</figref> shows a graph of an impedance code according to <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 3</figref> shows a graph illustrating impedance resolution according to <figref idref="DRAWINGS">FIG. 1</figref>.

<figref idref="DRAWINGS">FIG. 4</figref> is a schematic block diagram of an impedance controller according to an exemplary embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> is a detailed block diagram of a pull-down code generator of <figref idref="DRAWINGS">FIG. 4</figref>.

<figref idref="DRAWINGS">FIG. 6</figref> is a detailed block diagram of a reference ladder and a pull-down detector of <figref idref="DRAWINGS">FIG. 5</figref>.

<figref idref="DRAWINGS">FIG. 7</figref> is an operational timing diagram of <figref idref="DRAWINGS">FIG. 5</figref>,

<figref idref="DRAWINGS">FIGS. 8 and 10</figref> show graphs illustrating impedance codes according to <figref idref="DRAWINGS">FIG. 4</figref>.

<figref idref="DRAWINGS">FIGS. 9 and 11</figref> show graphs illustrating an impedance resolution according to <figref idref="DRAWINGS">FIG. 4</figref>.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the invention will be described with reference to <figref idref="DRAWINGS">FIGS. 4 to 11</figref> only with the intention of assisting those skilled in the art in thoroughly understanding the invention.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a schematic block diagram of an impedance controller according to an exemplary embodiment of the invention.

Referring to <figref idref="DRAWINGS">FIG. 4</figref>, the impedance controller includes a current mirror section CUR for generating an impedance current I. Pull-up and pull-down detectors <b>110</b> and <b>120</b> include an array of transistors and controlled by codes that control a gate voltage or a size of the transistor array. Pull-up and pull-down code generators <b>130</b> and <b>140</b> generate codes that control the pull-up and pull-down detectors <b>110</b> and <b>120</b>, respectively. And a code transmitter <b>150</b> transmits an impedance code corresponding to the impedance current. The impedance controller includes a clock generator <b>160</b> to generate a clock used for the impedance controller.

The current mirror section CUR includes an external resistor RQ connected between a ground and a chip pad ZQ PAD and having resistance corresponding to an external impedance. A comparator <b>101</b> compares a voltage VZQ at the pad ZQ PAD to a reference voltage VREF to output an impedance control voltage UPX. A PMOS transistor M<b>100</b> connected between a constant-voltage source VDDQ and the pad ZQ PAD receives the impedance control voltage UPX from the comparator <b>101</b> at a gate and applies an impedance current I corresponding to the impedance control voltage UPX, to the pad. A current mirror of NMOS transistors M<b>102</b> and M<b>104</b> duplicates the current I that is in the PMOS transistor M<b>100</b> and applies the duplicated current I to the pull-up detector <b>110</b>. And a current mirror of PMOS transistors M<b>101</b> and M<b>103</b> duplicates the current I that is in the PMOS transistor M<b>100</b> and applies the duplicated current I to the pull-down detector <b>120</b>.

The pull-up and pull-down detectors <b>110</b> and <b>120</b> include an array of transistors. The gate voltage and size of the array of transistors may be controlled by the relevant pull-up and pull-down code generators <b>130</b> and <b>140</b> so that the detectors <b>110</b> and <b>120</b> have the same impedance as the external impedance RQ.

The pull-up and pull-down code generators <b>130</b> and <b>140</b> compare the output node voltages UCUR and DCUR from the pull-up and the pull-down detectors <b>110</b> and <b>120</b> to a reference voltage VDDQ/2 to determine whether to increase or decrease the impedance of the pull-up and pull-down detectors <b>110</b> and <b>120</b>. If the output node voltages DCUR and UCUR from the pull-up and pull-down detectors <b>110</b> and <b>120</b>, respectively, cause a dithering phenomenon due to the digital control, the respective code generators send a gate voltage adjustment code and an impedance code to the code transmitter <b>150</b>.

The code transmitter <b>150</b> synchronizes the gate voltage code and the impedance code received from the code generators <b>130</b> and <b>140</b> to a transmission clock, and transmits the codes in series.

The clock generator <b>160</b> generates the clock that will be used in the impedance controller.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a detailed block diagram of the pull-down code generator <b>140</b>, and <figref idref="DRAWINGS">FIG. 6</figref> illustrates a block diagram of a reference ladder <b>161</b> and the pull-down detector <b>120</b>.

As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the pull-down code generator <b>140</b> includes a comparator <b>166</b> to compare the output of the pull-down detector to the reference voltage. A counter <b>165</b> generates a first code for adjusting the gate voltage of the transistor array <b>124</b> of the pull-down detector <b>120</b>, and a second code for controlling the array size selector <b>122</b> to adjust the size of the transistor array <b>124</b> in response to the output from the comparator <b>166</b>. A register N-bit Reg (A) <b>162</b> stores the first code therein and a register N-bit Reg (B) <b>163</b> stores the second code therein. A reference ladder <b>161</b> adjusts the gate voltage of the transistor array <b>124</b> of the pull-down detector <b>120</b>, in response to the first code. A dithering detector <b>164</b> generates a control signal <b>1</b>st Lock for locking the first code when the output from the pull-down detector <b>120</b> adjusted by the reference ladder <b>161</b> is close to or matches the impedance current. A control signal Update gets updated when the output from the pull-down detector <b>120</b> adjusted by the second code output is close to or matches the impedance current. And a register N-bit Reg (D) <b>171</b> stores the second code therein in response to the update control signal Update and a register N-bit Reg (C) <b>170</b> stores the first locked code.

As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the reference ladder <b>161</b> that is a component of the pull-down code generator <b>140</b>, adjusts a gate voltage by selecting a node voltage from nodes in a plurality of resistors connected in series between the constant-voltage source VDDQ and a ground and by connecting the selected node voltage to the gate of the transistor array <b>124</b> of the pull-down detector <b>120</b> in response to the first code received from the register <b>162</b>.

The constant voltage VDDQ that is generated from the above-described constant-voltage source may have a level of the power supply voltage, and the reference voltage VREF may have a level VDDQ/2, which is half the constant voltage.

<figref idref="DRAWINGS">FIG. 7</figref> illustrates an operational timing diagram of the pull-down code generator <b>140</b>.

Hereinafter, the operation of the impedance controller according to an exemplary embodiment of the invention will be described with reference to <figref idref="DRAWINGS">FIGS. 2 to 7</figref>.

First, the current mirror section CUR converts the external impedance RQ, connected to the pad ZQ PAD, to a current in the following process.

The comparator <b>101</b> compares the node voltage VZQ at the pad ZQ PAD to the reference voltage VREF to control the gate voltage of the PMOS transistor M<b>100</b>. If the node voltage VZQ is larger than the reference voltage VREF, the output of the comparator <b>101</b> increases and the amount of a current flowing through the PMOS transistor M<b>100</b>, in turn, decreases. Since all current flowing through the PMOS transistor M<b>100</b> flows through the external impedance RQ, the node voltage VZQ lowers below the previous value. On the contrary, if the node voltage VZQ is smaller than the reference voltage VREF, the output of the comparator <b>101</b> lowers and in turn the amount of the current flowing through the PMOS transistor M<b>100</b> increases. Since all the current flowing through the PMOS transistor M<b>100</b> flows through the external impedance RQ, the node voltage VZQ will become higher than a previous value. Through this process, the gate voltage of the PMOS transistor M<b>100</b> is controlled so that the node voltage VZQ has a value of VDDQ/2. At this time, the current I flowing through the PMOS transistor becomes VDDQ/2RQ.

The current I is duplicated and delivered to the pull-down detector <b>120</b> by the PMOS transistor M<b>103</b>. Further, the current I is duplicated and delivered to the pull-up detector <b>110</b> by the PMOS transistors M<b>101</b> and the NMOS transistors M<b>102</b> and M<b>104</b>.

The pull-down detector <b>120</b> is controlled by the pull-down code generator <b>140</b> to have an impedance corresponding to the delivered current I. The register <b>163</b>, which stores the second code, namely, the impedance code from the pull-down code generator <b>140</b>, maintains a previously stored initial value. The size of the transistor array <b>124</b> of the pull-down detector <b>120</b> is maintained by the array size selector <b>122</b> and the initial value of the second code, and the resultant output voltage DCUR from the pull-down detector is sent to the comparator <b>166</b>.

The comparator <b>166</b> operates with the clock signal COMP_CK, compares the reference voltage to the output DCUR from the pull-down detector <b>120</b>, and sends the output COMP_O from the comparator <b>166</b> to the counter <b>165</b>. The counter <b>165</b> is synchronized to the clock signal CNT_CK and samples the output of the comparator <b>166</b>. For example, if the output DCUR of the pull-down detector <b>120</b> is larger than the reference voltage VREF, the output from the comparator <b>166</b> becomes a logical value ‘1’, and the logical value is sent to the counter <b>165</b> to increase the subsequent output from the counter <b>165</b>. Further, if the output DCUR of the pull-down detector <b>120</b> is smaller than the reference voltage VREF, the output of the comparator <b>166</b> becomes a logical value ‘0’ and this logical value is sent to the counter <b>165</b> to decrease the subsequent output of the counter <b>165</b>.

The increased or decreased output of the counter <b>165</b> is stored in the register <b>162</b> by the sampling clock signal SAM_CK, and the first code stored in the register <b>162</b> controls the reference ladder <b>161</b> to adjust the gate voltage of the transistor array <b>124</b>, which is applied to the pull-down detector. For example, the increasing output of the counter <b>165</b> increases the voltage that is delivered to the pull-down detector <b>120</b>. The increasing input voltage to the pull-down detector <b>120</b> increases the amount of the current relative to the same size of the array of transistors, which serves to lower the output from the pull-down detector <b>120</b>.

The output from the pull-down detector <b>120</b> is compared to a reference voltage by the comparator <b>166</b>. This first feedback process continues until the dithering phenomenon occurs.

If the dithering phenomenon occurs, the output DCUR from the pull-down detector <b>120</b> is close to the VDDQ/2 and the dithering detector <b>164</b> generates a control signal <b>1</b>st Lock, which locks the first code, and an update signal Update. The first code outputted from the counter <b>165</b> is stored in the register <b>170</b>. This feedback process adjusts the gate voltage of the transistor array, <b>124</b> of the pull-down detector <b>120</b>.

Once the dithering phenomenon firstly occurs, a logic ‘high’ state remains after the control signal <b>1</b>st Lock, which locks the first code, is activated, and accordingly, the reference ladder <b>161</b>, the register <b>162</b> and the register <b>170</b>, which operates in the state where the control signal that locks the first code is inactive, does not operate any more.

The second feedback process is a process of creating a desired impedance code by adjusting the size of the transistor array <b>124</b> of the pull-down detector <b>120</b> with respect to the gate voltage determined after the above-mentioned operation is completed.

After the gate voltage is determined, the output from the counter <b>165</b> is connected to and is stored in the register <b>163</b>. The register <b>163</b> stores impedance codes. The impedance codes, namely, the second code stored in the register <b>163</b> controls the array size selector <b>122</b> to adjust the size of the transistor array <b>124</b> of the pull-down detector <b>120</b> to thereby change the output DCUR from the pull-down detector.

The comparator <b>166</b> compares the output DCUR from the pull-down detector <b>120</b> to the reference voltage, and sends the resultant output to the counter <b>165</b>. The counter <b>165</b> then generates the second code to adjust the output DCUR from the pull-down detector <b>120</b>. This feedback process continues until a second dithering phenomenon occurs. At this time, an impedance code created through the second feedback process does not greatly deviate from the initial value since the dithering phenomenon is already occurring with respect to the initial value of the impedance code through the first feedback process. If the second dithering phenomenon occurs, the dithering detector <b>164</b> generates the data control signal Update and stores it in the impedance code register <b>171</b> to send the output from the counter <b>165</b> to the code transmitter <b>150</b>. After the control signal <b>1</b>st Lock that locks the first code changes to ‘high,’ the register <b>171</b> stores a new impedance code in response to the update control signal Update received whenever the dithering phenomenon occurs.

Although above-described configuration and operation have been primarily described in connection with the pull-down detector <b>120</b> and the pull-down code generator <b>140</b>, it will be apparent to those skilled in the art that the configuration and operation of the pull-up detector <b>110</b> and the pull-up code generator <b>130</b> are identical or similar to those described above.

With the above-described impedance controller, similar or the same impedance code is created irrespective of the external impedance value through such series of processes, which allows constant impedance resolution to be achieved with respect to a variety of external impedances. Further, if different external impedances are required according to systems, it is possible to maintain impedance resolution uniform by automatically maintaining only the gate voltage of the transistor arrays of the detectors <b>110</b> and <b>120</b>.

<figref idref="DRAWINGS">FIGS. 8 to 11</figref> illustrate graphs showing impedance codes and impedance resolution for different external impedances in the impedance controller according to the above-described exemplary embodiment of the invention.

<figref idref="DRAWINGS">FIGS. 8 and 10</figref> illustrate graphs showing impedance codes depending on change in impedance values, where an X axis denotes an impedance code and a Y axis denotes an impedance value. <figref idref="DRAWINGS">FIGS. 9 and 11</figref> illustrate graphs showing a relationship between an impedance code and impedance resolution for external impedance, where an X axis denotes an impedance code and a Y axis denotes impedance resolution.

As shown in <figref idref="DRAWINGS">FIGS. 8 to 11</figref>, it will be appreciated that in the invention, both have impedance resolutions <b>200</b> and <b>400</b> of 2.5% irrespective of DDR (150Ω) or DDR<b>3</b> (25Ω) since the impedance is automatically controlled depending on the external impedance value. Further, it will be appreciated that similar impedance codes <b>100</b> and <b>300</b> are achieved. With the impedance controller according to the above-described exemplary embodiment of the invention, more improved impedance resolution can be achieved by changing the initial values of the registers <b>162</b> and <b>163</b>.

Since the exemplary embodiments have been only illustrated by way of example with reference to the accompanying drawings to assist in thoroughly understanding the invention, it should not be construed as limiting the invention. Further, it will be apparent to those skilled in the art that a variety of changes and modifications may be made to the invention departing from the scope and spirit of the invention. For example, it will be apparent that the internal configuration of the circuit may be modified and internal components of the circuit may be substituted by other equivalents, if necessary.

As described above, with the impedance controller according to the invention, the same impedance resolution can be achieved even for different external impedances, and constant impedance can be achieved irrespective of changes in an external environment, such as changes in temperature, process, and the like. Further, with the impedance controller, the same impedance resolution can be achieved without modifying a circuit in several systems having different external impedance.