Circuits for transistor testing

TECHNICAL FIELD

0001This application claims the benefit of the Korean Application No. P2003-0096992, filed on Dec. 24, 2003, which is hereby incorporated by reference.

0002The present disclosure relates generally to circuits and, more particularly, to circuits for transistor testing.

BACKGROUND

0003Generally, a degradation degree of a transistor can be determined by measuring a drain current that results from voltages applied to a gate and drain.

0004<figref idref="DRAWINGS">FIG. 1</figref> is an equivalent circuit of a test circuit for measuring a degradation degree of a transistor according to a related art. Referring to <figref idref="DRAWINGS">FIG. 1</figref>, in a test circuit for measuring a degradation degree of a transistor, prescribed voltages, e.g., 2 volts (V) and 4V, are applied to gate and drain electrodes, respectively. After applying an electrical stress to a transistor, a drain current as a device parameter of the transistor is detected to measure a degree of device degradation.

0005After completion of measuring the device parameter of the transistor for one electrical stress condition, a separate electrical stress condition, e.g., 5V drain voltage and 2.5V gate voltage, is applied to another transistor. A new drain current is then detected using a probe card to measure the degradation degree.

0006Thus, the degradation degree and lifetime of each transistor are measured by sequentially measuring drain currents of a plurality of transistors by applying the entire electrical stress conditions to be measured, respectively.

0007However, in case of measuring lifetimes of transistors by the test circuit in <figref idref="DRAWINGS">FIG. 1</figref>, the degradation degree should be measured in a manner of applying one electrical stress of one condition to one transistor each. Hence, it takes a considerable time (at least 3 hours) to find a time for seeking 10% drain saturation current (IDSAT) for each stress condition.

0008Moreover, because the device degradation of transistor should be measured under various conditions to measure an accurate lifetime of transistor, the time needed increases with the number of devices to be tested.

BRIEF DESCRIPTION OF THE DRAWINGS

0009<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of an equivalent circuit of a known test circuit for measuring a degradation degree of a transistor.

0010<figref idref="DRAWINGS">FIG. 2</figref> a diagram of an equivalent circuit of an example disclosed test circuit capable of measuring degradation degrees of a plurality of transistors simultaneously.

DETAILED DESCRIPTION

0011Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a disclosed circuit <b>100</b> for transistor test includes gate pads G<b>1</b> to G<b>4</b>, source pads S<b>1</b> to S<b>4</b>, drain pads D<b>1</b> to D<b>4</b>, and substrate pads B<b>1</b> to B<b>4</b> connected to gate electrodes, source electrodes, drain electrodes, and substrate electrodes of four transistors (devices under test) DUT<b>1</b> to DUT<b>4</b>, respectively. A gate pulse pad Gp and gate bulk pad Bp for are provided for applying specific voltages to the gate and drain electrodes of the four transistors, respectively. A connecting line L<b>1</b> connecting the gate pulse and gate bulk pads Gp and Bp to each other is provided with resistors R<b>1</b> to R<b>3</b> between the gates of the respective transistors, and resistors R<b>4</b> to R<b>7</b> inserted between the connecting line L<b>1</b> and the drain electrodes, respectively.

0012Specifically, the gate pulse pad Gp and the gate bulk pad Bp are connected by the connecting line L<b>1</b>. The connecting line L<b>1</b> includes nodes N<b>1</b> to N<b>4</b> connected to the gate electrodes of the transistors, respectively, the resistor R<b>1</b> connected between the nodes N<b>1</b> and N<b>2</b>, the resistor R<b>2</b> connected between the nodes N<b>2</b> and N<b>3</b>, and the resistor R<b>3</b> connected between the nodes N<b>3</b> and N<b>4</b>. Further, the connecting line L<b>1</b> is connected to the drain of the transistor DUT<b>1</b> via the resistor R<b>4</b>, the drain of the transistor DUT<b>2</b> via the resistor R<b>5</b>, the drain of the transistor DUT<b>3</b> via the resistor R<b>6</b>, and the drain of the transistor DUT<b>4</b> via the resistor R<b>7</b>.

0013Hence, by applying a specific voltage difference between the pads Gp and Bp, prescribed voltages are applied to the gate and drain electrodes of the transistors DUT<b>1</b> to DUT<b>4</b>, respectively.

0014An operation of the example circuit of <figref idref="DRAWINGS">FIG. 2</figref> is explained as follows.

0015First of all, prescribed voltage differences occur between the nodes N<b>1</b> to N<b>4</b> by the resistors R<b>1</b> to R<b>3</b>, respectively, whereby different voltages are applied to the gate electrodes of the transistors DUT<b>1</b> to DUT<b>4</b>, respectively. For instance, if 4.0V is applied to the pad Gp to generate 0.2V differences between the nodes N<b>1</b> to N<b>4</b>, respectively, 4.0V is applied to the gate electrode of the transistor DUT<b>1</b>, 3.8V is applied to the gate electrode of the transistor DUT<b>2</b>, 3.6V is applied to the gate electrode of the transistor DUT<b>3</b>, and 3.4V is applied to the gate electrode of the transistor DUT<b>4</b>.

0016Prescribed voltage differences occur between the nodes N<b>1</b> to N<b>4</b> and the drain electrodes of the transistors DUT<b>1</b> to DUT<b>4</b> by the resistors R<b>4</b> to R<b>7</b>, respectively, whereby different voltages are applied to the drain electrodes of the transistors DUT<b>1</b> to DUT<b>4</b>, respectively. For instance, if 4.0V is applied to the pad Gp to generate 2V differences between the nodes and the drain electrodes of the transistors, a voltage of the node N<b>1</b> is 4.0V and a voltage of the drain electrode of the transistor DUT<b>1</b> is 2.0V by the resistor R<b>4</b>. A voltage of 1.8V is applied to the drain electrode of the transistor DUT<b>2</b>, 1.6V is applied to the drain electrode of the transistor DUT<b>3</b>, and 1.4V is applied to the drain electrode of the transistor DUT<b>4</b>. In doing so, the substrate pads B<b>1</b> to B<b>4</b> and the source pads S<b>1</b> to S<b>4</b> are grounded.

0017Thus, by applying different stresses to the gate and drain electrodes of the transistors, respectively, drain currents as a device parameter may be measured. Namely, parameters indicating device characteristics such as saturation current IDSAT, threshold voltage Vth and the like are measured for each of the transistors DUT<b>1</b> to DUT<b>4</b>.

0018Specifically, the degradation degree of the transistor can be measured by detecting the saturation drain current. The saturation drain current needs to be measured at an operational voltage Vop. In its measurement condition, a drain voltage Vd is equal to the operational voltage Vop, a gate voltage is equal to the operational voltage Vop, a source voltage 0V, and a substrate bulk voltage is 0V. For instance, while each of the source and substrate pads S<b>1</b> and B<b>1</b> of the transistor DUT<b>1</b> has 0V, the drain current is measured after applying the operational voltage to the gate and drain pads G<b>1</b> and D<b>1</b>.

0019In the same manner, the drain current of each the transistors DUT<b>2</b> to DUT<b>4</b> is measured as a time function. Subsequently, the measured value is compared to an initial value. A reduction rate is found to measure a lifetime of the device.

0020The degree of degradation is analyzed into a percentage (%) that represents a variation according to a time for initial values of the drain current and threshold voltage of the corresponding transistor.

0021The lifetime is measured in a manner of setting a criterion to a value (time) of 10% degradation for each stress condition. The saturation current is a function of the threshold voltage. The threshold voltage means a voltage at which a strong inversion takes place. The value of the threshold voltage can be measured in a drain current to gate voltage curve.

0022As described above, the degradation degrees of a plurality of transistors can be simultaneously measured using one test circuit, whereby the degradation degree and lifetime of the transistor can be quickly and efficiently estimated.

0023Accordingly, as disclosed herein, if the stress corresponding to one condition (maximum gate and drain voltages) is applied, the separate stress conditions are applied to a plurality of transistors, respectively to enable the simultaneous measurements for the degradation degrees of the transistors for the entire conditions. Therefore, the disclosed system simultaneously measures various devices with the time taken for measuring one transistor in the related art method to reduce time loss, thereby raising work efficiency.

0024The resistors are connected to generate specific voltage drops of the gate or drain electrodes of the transistors, respectively, whereby the various test circuits may be implemented.

0025As disclosed herein, a transistor testing circuit enables electrical stresses of separate conditions to be applied simultaneously to a plurality of transistors, respectively.

0026According to one example, a transistor test circuit may include a plurality of contact pads connectable to a plurality of terminals of a plurality of transistors, a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively, and a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.

0027As disclosed herein, a plurality of the contact pads include a gate pulse pad and a gate bulk pad for applying a maximum voltage to be applied to the gate of each of the transistors. In one example, voltage differences between the voltages applied to the gates of a plurality of the transistors are equal to each other. Additionally, voltage differences between the voltages applied to the drains of a plurality of the transistors may be equal to each other.

0028In another example, an integrated circuit may include a plurality of transistors and a test circuit for measuring degradation degrees of a plurality of the transistors. Such a test circuit may include a plurality of contact pads connectable to a plurality of terminals of a plurality of the transistors, a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively, and a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively. A plurality of the contact pads may include a gate pulse pad and a gate bulk pad for applying a maximum voltage to be applied to the gate of each of the transistors. In such an arrangement, voltage differences between the voltages applied to the gates of a plurality of the transistors are equal to each other. Additionally, voltage differences between the voltages applied to the drains of a plurality of the transistors may be equal to each other.

0029This application claims the benefit of the Korean Application No. P2003-0096992 filed on Dec. 24, 2003, which is hereby incorporated by reference.

0030Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.