Wiring design method and system for electronic wiring boards

BACKGROUND OF THE INVENTION

The present invention relates to a wiring design system and method, and more particularly to a wiring design system and method which is advantageous when applied to electronic wiring boards having various wiring restrictions, wherein the system and method shows a rough wiring plan at the floor plan stage so as to complete a wiring design satisfying the wiring restrictions in a short period of time.

Attempts have been made to automate the design of wiring on electronic wiring boards using a computer system.

Description will be made below of problems with prior art wiring design techniques with reference to <figref idref="DRAWINGS">FIG. 12</figref>.

<figref idref="DRAWINGS">FIG. 12</figref> is a schematic diagram showing an example of how to lay out signal (line) groups having proximity wiring restrictions.

Generally, the wiring on an electronic wiring board is designed under various wiring restrictions since each signal varies in its characteristics and interference occurs between the wires.

For example, if signals on a wiring board have different distance restrictions with respect to their neighboring signals, the wiring density may decrease depending on the arrangement of the wiring paths.

<figref idref="DRAWINGS">FIG. 12</figref> shows distance restrictions (denoted by reference numeral <b>1203</b>) between neighboring parallel lines, in which a (minimum) distance is set between each combination of two signal groups. That is, for example, a wire belonging to the signal group groupA and that belonging to the signal group groupB must be spaced 4 units or more apart. It should be noted that a signal group is a group consisting of (signal) wires having the same characteristics.

If wires of the signal group groupA and the signal group groupB have a positional relationship as shown in a wiring state <b>1201</b> (in <figref idref="DRAWINGS">FIG. 12</figref>), their wiring restrictions prevent them from being densely arranged.

To overcome this problem, the wires of the same signal group may be disposed adjacent to one another to achieve a dense wiring arrangement; for example, a signal (wire) <b>1204</b> of the signal group groupA may be disposed next to a signal (wire) <b>1206</b> of the same group, as shown in a wiring state <b>1202</b> (in <figref idref="DRAWINGS">FIG. 12</figref>).

Increased speed of semiconductor integrated circuits has made it necessary to match the characteristics of a plurality of signals, which requires that their wiring lengths and wiring paths be made as equal as possible.

To accomplish this, the technique disclosed in Japanese Laid-Open Patent Publication No. 2002-124571 uses the concept of virtual wiring. This technique generates detailed wiring from rough wiring by dividing the virtual wiring. In virtual wiring, a plurality of nets which must be made equal in their characteristics are grouped together and handled as a single virtual net.

SUMMARY OF THE INVENTION

The above patent publication describes that the above technique can make effectively equal characteristics (such as wiring length, wiring capacity, wiring path, and wiring pattern) of a plurality of nets which must be made equal in their characteristics.

However, the technique may entail the problem of increased wiring length or increased wiring space, depending on how parts are arranged on the wiring board.

Description will be made below of problems arising when parts block wiring on a wiring board with reference to <figref idref="DRAWINGS">FIGS. 13A to 13D</figref>.

<figref idref="DRAWINGS">FIGS. 13A to 13D</figref> are schematic diagrams illustrating wiring patterns formed when parts block wiring on a wiring board.

Referring to <figref idref="DRAWINGS">FIG. 13A</figref>, let us consider how to find a path for signal lines (indicated by reference numeral <b>1303</b>) between two parts <b>1301</b> and <b>1302</b>. The characteristics of the signal lines must be substantially equal.

The conventional technique will draw the virtual net <b>1305</b> shown in <figref idref="DRAWINGS">FIG. 13B</figref> and then determine a path based on this virtual net.

However, since parts <b>1304</b> disposed between the parts <b>1301</b> and <b>1302</b> constitute an obstacle to the wiring, the above path determining method using the virtual net <b>1305</b> will come up with the wiring path <b>1306</b> shown in <figref idref="DRAWINGS">FIG. 13C</figref> which detours around the parts <b>1304</b>.

This results in increased wiring length and increased wiring space, making it necessary to increase the area of the wiring board.

Therefore, the wiring design system preferably generates the wiring paths <b>1307</b> shown in <figref idref="DRAWINGS">FIG. 13D</figref> which run in a bundle before and after meeting the parts <b>1304</b> but separate at these parts so as to pass between them.

Further, another problem is that increased speed and increased density of semiconductor circuits have introduced various wiring restrictions. Floor plans have become important in designing wiring which satisfies these restrictions. A floor plan is a process of roughly drawing a wiring plan and a parts layout before the structure of the wiring board and the detailed wiring are designed. Thus, it is necessary to review the wiring restrictions and each possible wiring pattern in the early wiring design stage.

With the conventional technique, however, it is necessary to prepare information equivalent to that required for detailed wiring design, and furthermore preparation for checking each possible wiring pattern requires time and man-hours. Reviewing and modifying a floor plan also take a considerable amount of time since wiring information on each signal must be handled separately. Therefore, it is necessary to provide a system which draws a floor plan based on simple but practical information to considerably reduce the preparation period and which handles signals as a signal group to reduce the man-hours need to review and modify the floor plan.

The present invention has been devised to solve the above problems. It is, therefore, an object of the present invention to provide a wiring design system and method which is advantageous when applied to wiring boards having various wiring restrictions, wherein the system and method shows a rough wiring plan at the floor plan stage so as to complete a wiring design satisfying the wiring restrictions in a short period of time while evaluating the congestion degree of the wiring.

The present invention handles related signals such as those on a bus as a signal group, and first try to find a path for the signal group as a whole, that is, to ensure a wiring area for all signals in the group. If the above step has not been able to find a single wiring area for accommodating all signals in the signal group due to an obstacle, etc., then the present invention divides the signal group into smaller groups and try to find paths for them again.

At that time, the wiring paths for neighboring divided groups are designed to have the same shape so that these groups have the same wiring pattern.

When a (rough) wiring path has been specified for one of the signals in the signal group using simple information, the present invention regards it as being also applied to all other signals in the group and try to find a path for each signal, giving priority to the specified area (wiring path).

Further, the present invention first draws a rough wiring path based on temporary simple information and then evaluates the degree of congestion. The present invention gradually increases the accuracy of the information as the design progresses, replacing previous information with more practical information. At that time, only wiring sections for which no path has yet been determined due to insufficient information are subjected to reexamination (using more detailed information).

With this arrangement, the wiring design system of the present invention can find suitable wiring paths for signals (signal lines) that must be made equal in their characteristics, which is also advantageous in increasing the density of the wiring board. Furthermore, it is possible to design a floor plan taking account of the wiring restrictions and each possible wiring pattern on the wiring board in the early wiring board design stage.

BRIEF DESCRIPTION OF DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing the configuration of a wiring design system according to the present invention.

<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram showing examples of the information contained in a path specification information file <b>104</b>.

<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart showing the details of path search processing.

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating path search processing using a recommended path according to the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> includes <figref idref="DRAWINGS">FIGS. 5A to 5E</figref> which are diagrams illustrating path search processing according to the present invention, wherein a signal group is divided into smaller groups which run adjacent to one another.

<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a procedure for determining a wiring path for a signal group.

<figref idref="DRAWINGS">FIG. 7</figref> is a schematic diagram illustrating processing flow in a wiring design system according to a first embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8</figref> is a schematic diagram illustrating processing flow in a wiring design system according to a second embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 9</figref> is a schematic diagram illustrating processing flow in a wiring design system according to a third embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10</figref> is a schematic diagram illustrating processing flow in a wiring design system according to a fourth embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 11</figref> is a schematic diagram illustrating processing flow in a wiring design system according to a fifth embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 12</figref> is a schematic diagram showing an example of how to lay out signal (line) groups having proximity wiring restrictions.

<figref idref="DRAWINGS">FIG. 13</figref> includes <figref idref="DRAWINGS">FIGS. 13A to 13D</figref> which are diagrams illustrating wiring patterns formed when parts block wiring on a wiring board.

DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described below with reference to <figref idref="DRAWINGS">FIGS. 1 to 11</figref>.

First of all, description will be made of the configuration of a wiring design system according to the present invention with reference to <figref idref="DRAWINGS">FIGS. 1 to 3</figref>.

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram showing the configuration of a wiring design system according to the present invention.

<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram showing examples of the information contained in a path specification information file <b>104</b>.

<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart showing the details of path search processing.

As shown in <figref idref="DRAWINGS">FIG. 1</figref>, an input processing section <b>107</b> of a wiring design system <b>101</b> receives input files such as a net information file <b>102</b>, a signal group information file <b>103</b>, a path specification information file <b>104</b>, a layout specification information file <b>105</b>, and a wiring restriction information file <b>106</b>.

These input files are input to a wiring processing section <b>108</b> and used to change parts on the wiring board or to design wiring paths.

Output information is output through an output processing section <b>115</b> as output files such as a wiring path information file <b>116</b>, a congestion degree evaluation file <b>117</b>, and a layout information file <b>118</b>.

It should be noted that the net information file <b>102</b> contains logical connection information on parts on the wiring board. The signal group information file <b>103</b> contains specification information on signal groups to be wired. A signal group is a concept used to handle a plurality of wires as a group, for example, as a bus. The path specification information file <b>104</b> contains rough specification information on wiring paths. The wiring restriction information <b>106</b> contains information on wiring restrictions such as those on wiring lengths and distances between neighboring signals.

The wiring path information file <b>116</b> contains wiring path information generated by the wiring processing section <b>108</b>. The congestion degree evaluation file <b>117</b> contains the results of evaluating the congestion degrees of wiring paths based on generated wiring path information. The layout information file <b>118</b> contains parts layout information.

The path specification information in the path specification information file <b>104</b> may have the structure shown in <figref idref="DRAWINGS">FIG. 2</figref>. The path specification information specifies paths which signal groups should follow whenever appropriate. Each piece of path specification information includes information on a (signal) line, for example, a signal group name or a signal name, a start point, an end point, and a layer name, as shown in Table <b>201</b>. Or it may include a signal group name or a signal name, two coordinates in a specified wiring area, and a layer number.

It should be noted that a signal group name and a signal name are the names of a signal group and a signal handled by a wiring design system of the present invention to design wiring. Any coordinate system can be used if it allows the wiring design system to easily design wiring. The layer name and the layer number are employed since multilayer wiring is formed.

Description will be made below of the details of the processing performed by the wiring processing section <b>108</b> of a wiring design system according to the present invention.

At step S<b>01</b>, the wiring processing section <b>108</b> selects a signal group for which no path has yet been found, based on information obtained from the input processing section <b>107</b>. Then, the wiring processing section <b>108</b> searches for a path for the selected signal group at step S<b>02</b>.

After completing the path search, the wiring processing section <b>108</b> determines at step S<b>03</b> whether there is another signal group for which no path has yet been found. If so, the above processing (steps S<b>01</b> to S<b>03</b>) is repeated.

If, on the other hand, there is no other signal group for which no path has yet been found, then at step S<b>04</b> the wiring processing section <b>108</b> evaluates the wiring, such as checking its degree of congestion or determining whether the wiring meets the wiring restrictions.

Step S<b>05</b> determines whether the degree of congestion is high or there is any restriction which is not met. If it is determined that the degree of congestion is high or there is a restriction which is not met, the wiring processing section <b>108</b> changes the parts layout and the wiring path(s) at step S<b>06</b>. After that, the above processing (steps S<b>01</b> to S<b>05</b>) is repeated.

If, on the other hand, it is determined that the degree of congestion is not high and there is no restriction which is not met, the wiring processing section <b>108</b> determines at step S<b>07</b> whether the signal group can be divided into smaller groups. If it is determined that the signal group can be divided and the division threshold value is larger than the division limit value, the wiring processing section <b>108</b> reduce the division threshold value at step S<b>08</b>. At step S<b>09</b>, the wiring processing section <b>108</b> sets the found path as a recommended path. Then, the above processing is repeated. It should be noted that a division limit value is an externally supplied parameter for limiting the division operation.

If, on the other hand, the signal group cannot be divided or the division threshold value is smaller than the division limit value, the wiring processing section <b>108</b> supplies necessary information to the output processing section <b>115</b> which then takes over the processing.

Description will be made below of the details of the path search processing at step S<b>02</b> with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

First of all, the wiring processing section <b>108</b> sets the recommended path on the wiring board at step S<b>301</b>. A recommended path is a path which wiring should follow whenever appropriate and is specified by the path specification information <b>104</b>. With the recommended path, it is possible to design desirable wiring considering the parts layout conditions on the wiring board. How to specify a recommended path will be described later in detail.

Then, the wiring processing section <b>108</b> divides the signal group into smaller groups at step S<b>302</b>. A signal group consists of signals whose wires are handled as a group. The wiring design systems of the present invention use signal groups as wiring units. At step S<b>302</b>, the signal group is divided such that neighboring signals in the signal group belong to the same group whenever possible. One of the characteristics of the present invention is in its method of dividing this signal group, as described later using specific examples. It should be noted that it may be arranged that differential signals in a pair always belong to the same group. The differential signals in a pair always have opposite levels and are effective in reducing external noise produced when signals are transmitted through wires at high speed. These differential signals need be transmitted adjacent to each other.

Then, the wiring processing section <b>108</b> determines at step S<b>303</b> whether the number of signals in the signal group is larger than the division threshold value. If it is determined that the number of signals in the signal group is larger than the division threshold value, the signal group is further divided so that the number of signals is equal to or less than the division threshold value at step S<b>304</b>.

After that, one group is selected at step S<b>305</b>.

Then, the wiring processing section <b>108</b> searches for a path for the selected group at step S<b>306</b>. In the path search at step S<b>306</b>, priority is given to the recommended path. If it is determined at step S<b>307</b> that a wiring path has been found and its capacity is within a limit, the wiring processing section <b>108</b> sets the found wiring path as a recommended path at step S<b>310</b> so that paths adjacent to the found path can be searched for other groups within the signal group. It should be noted that step S<b>310</b> will be further described later using specific examples.

If it is determined at step S<b>307</b> that no wiring path has been found or the capacity of the found wiring path is over the limit, then the wiring processing section <b>108</b> determines at step S<b>308</b> whether the signal group can be divided.

If the group can be divided, the wiring processing section <b>108</b> divides it at step S<b>309</b> and then repeats the above processing starting with step S<b>305</b>. The group can be (or should be) divided, for example, when the resultant smaller groups are small enough to pass between parts blocking them (the original group cannot pass since it includes a large number of signals), or when the degree of congestion can be reduced through the division.

If, on the other hand, the group cannot be divided, the wiring processing section <b>108</b> sets the found wiring path as a new recommended path at step S<b>310</b>.

After step S<b>310</b>, the wiring processing section <b>108</b> determines at step S<b>311</b> whether there is any group for which no path has yet been found. If yes, the wiring processing section <b>108</b> repeats the above processing starting with step S<b>305</b>. If no, the processing ends.

Description will be made below of path search processing using a recommended path in which a signal group is divided into smaller groups and of a technique for determining a wiring path according to a wiring design method of the present invention with reference to <figref idref="DRAWINGS">FIGS. 4 to 6</figref>.

<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating path search processing using a recommended path according to the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> includes <figref idref="DRAWINGS">FIGS. 5A to 5E</figref> which are diagrams illustrating path search processing according to the present invention, wherein a signal group is divided into smaller groups which run adjacent to one another.

<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a procedure for determining a wiring path for a signal group.

First of all, with reference to <figref idref="DRAWINGS">FIG. 4</figref>, description will be made of how to find a wiring path by specifying a recommended path as described above at step S<b>301</b> of the flowchart shown in <figref idref="DRAWINGS">FIG. 3</figref>.

Assume, for example, that parts <b>502</b> and <b>503</b> are mounted on a wiring board <b>501</b>, and a signal group <b>504</b> is set between the parts <b>502</b> and <b>503</b>.

To generate a desirable wiring pattern or to provide a base for that, a recommended path <b>505</b> is set for the signal group <b>504</b> from a path specification information file <b>506</b>. This arrangement makes the changes to the wiring explicit.

The recommended path <b>505</b> is generated based on the path specification information stored in the path specification information file <b>506</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>. A recommended path is a path which the signal group <b>504</b> should follow whenever appropriate. Each recommended path has a certain width so that all nets (signals) within the signal group can follow the path alongside of one another, as indicated by a recommended path <b>507</b> in <figref idref="DRAWINGS">FIG. 4</figref>. Thus, the path search processing generates a path which follows the recommended path <b>507</b> whenever appropriate, as indicated by a wiring path <b>508</b> in <figref idref="DRAWINGS">FIG. 4</figref>.

With reference to <figref idref="DRAWINGS">FIGS. 5A to 5E</figref>, description will be made below of how to arrange the wiring paths for groups obtained as a result of dividing a signal group at step S<b>309</b> of the flowchart shown in <figref idref="DRAWINGS">FIG. 3</figref> so that they run adjacent to one another.

Assume, for example, that a signal group <b>603</b> is set between parts <b>601</b> and <b>602</b> which sandwich a plurality of parts <b>604</b>, as shown in <figref idref="DRAWINGS">FIG. 5A</figref>.

In such a case, it is not possible to set a single straight path accommodating the entire signal group <b>603</b> since the path must detour around the parts <b>604</b>, which is not desirable in terms of wiring design. Therefore, the signal group <b>603</b> is divided into smaller groups such that they can pass between the parts <b>604</b>, and then paths for them are searched for, as follows.

First, as shown in <figref idref="DRAWINGS">FIG. 5B</figref>, a wiring path <b>605</b> for one of the groups is determined which passes between two parts <b>604</b>. Then, the wiring path <b>605</b> is widened and registered as a recommended path <b>606</b> (step S<b>310</b> in <figref idref="DRAWINGS">FIG. 3</figref>), as shown in <figref idref="DRAWINGS">FIG. 5C</figref>. A wiring path <b>607</b> for another one of the groups is determined such that it runs within the recommended path, as shown in <figref idref="DRAWINGS">FIG. 5D</figref>.

The above arrangement (in which the wiring path <b>605</b> is widened and registered as a new recommended path) allows the next path to run adjacent to the wiring path <b>605</b> (that is, it can be disposed close to the target part <b>604</b>).

The above processing is repeated, thereby determining a wiring path <b>608</b>, as shown in <figref idref="DRAWINGS">FIG. 5E</figref>.

Description will be made below of a procedure for determining a wiring path for a signal group with reference to <figref idref="DRAWINGS">FIG. 6</figref>.

Assume, for example, that parts <b>703</b>, <b>704</b>, and <b>705</b> are mounted on a wiring board <b>710</b>, and connection lines for a single signal group are set between the parts <b>703</b> and <b>704</b> as connection information <b>706</b>, <b>707</b>, <b>708</b>, and <b>709</b>.

Net information <b>701</b> and path specification information <b>702</b> on the wiring board <b>710</b> are input to the wiring design system <b>400</b>.

The wiring design system <b>400</b> searches for a path for the signal group or for each group obtained as a result of dividing the signal group, generating wiring paths <b>711</b> and <b>712</b>. After that, the wiring design system <b>400</b> generates detailed wiring paths <b>713</b>, <b>714</b>, <b>715</b>, and <b>716</b> based on the path for the signal group or for each group. Thus, the wiring design system <b>400</b> determines appropriate paths by dividing a signal group into smaller groups and finding a path for each group (even for each signal).

Lastly, after determining the wiring paths, the wiring design system <b>400</b> outputs a congestion degree evaluation file <b>717</b> and a wiring path information file <b>718</b>.

A first embodiment of the present invention will be described below with reference to <figref idref="DRAWINGS">FIG. 7</figref>.

<figref idref="DRAWINGS">FIG. 7</figref> is a schematic diagram illustrating processing flow in a wiring design system according to the first embodiment of the present invention.

The present embodiment generates an optimum wiring design by changing the parts layout and setting a recommended path based on evaluation of the degree of congestion.

According to the present embodiment, net information <b>401</b> on a wiring board <b>402</b> indicates that parts <b>403</b>, <b>404</b>, <b>406</b>, <b>407</b>, <b>409</b>, and <b>410</b> are mounted on the wiring board <b>402</b>, as shown in the upper-left corner of <figref idref="DRAWINGS">FIG. 7</figref>.

Connection lines for one signal-group are set between the parts <b>403</b> and <b>404</b> as connection information <b>405</b>. Likewise, connection lines for another signal group are set between the parts <b>406</b> and <b>407</b> as connection information <b>408</b>. Further, connection lines for still another signal group are set between the parts <b>409</b> and <b>410</b> as connection information <b>411</b>.

The wiring design system <b>400</b> receives these pieces of information and determines or ensures wiring paths for the signals in each signal group, thus generating wiring paths <b>412</b>, <b>413</b>, <b>414</b>, and <b>415</b>. The wiring design system <b>400</b> then evaluates the wiring and obtains a congestion degree evaluation result <b>416</b>. The degree of congestion is obtained by dividing the entire wiring area into small regions by horizontal and vertical dividing lines at equal intervals and then measuring the amount of wiring in each small region. At this point, the wiring design system <b>400</b> can output a congestion degree evaluation file <b>417</b>, which contains the results of evaluating the congestion degrees of wiring paths, and a wiring path information file <b>418</b>, which contains information on determined wiring paths.

The congestion degree evaluation result <b>416</b> indicates that the wiring paths <b>413</b>, <b>414</b>, and <b>415</b> run very close to one another, that is, the congestion degree of the determined wiring paths is partially high.

To solve this problem, the parts layout and the wiring paths are modified as follows. After reviewing the parts layout, the parts <b>409</b> and <b>410</b> are moved in the directions indicated by arrows <b>420</b> and <b>421</b>, respectively.

Further, a recommended path <b>424</b> is set for the signal group <b>405</b> to modify the wiring path.

These measures are expected to reduce the congestion degree of the center portion of the wiring board. Then, the wiring design system <b>400</b> searches for wiring paths for the signal groups again using wiring path information <b>419</b>, which includes information on the above changes in the parts layout and on the new recommended path.

As a result, the wiring design system <b>400</b> obtains new wiring paths <b>425</b>, <b>426</b>, and <b>427</b>. The wiring design system <b>400</b> then evaluates the wiring thus generated and obtains a congestion degree evaluation result <b>428</b>. At this point, the wiring design system <b>400</b> can generate a new congestion degree evaluation file <b>429</b> and a new wiring specification information file <b>430</b>. The above processing is repeated until no portion of the wiring board is too high in the degree of congestion.

A second embodiment of the present invention will be described below with reference to <figref idref="DRAWINGS">FIG. 8</figref>.

<figref idref="DRAWINGS">FIG. 8</figref> is a schematic diagram illustrating processing flow in a wiring design system according to the second embodiment of the present invention.

The present embodiment designs wiring by considering restrictions on wiring lengths and on distances between neighboring wires.

Assume, for example, that parts <b>802</b> and <b>803</b> are mounted on a wiring board <b>808</b>, and signals <b>804</b>, <b>805</b>, <b>806</b>, and <b>807</b> are set between the parts <b>802</b> and <b>803</b>. The signals <b>804</b> and <b>805</b> belong to one signal group, while the signals <b>806</b> and <b>807</b> belong to another signal group.

Furthermore, the wiring board has wiring restrictions. Specifically, a wiring restriction information file <b>812</b> contains neighboring wire restriction information <b>810</b> and wiring length restriction information <b>811</b>. The neighboring wire restriction information <b>810</b> indicates restrictions on wiring distances between neighboring signal groups, while the wiring length restriction information <b>811</b> indicates restrictions on the wiring length tolerance and the wiring length for each signal group. Since these pieces of information are registered only for each signal group, a signal group information file <b>809</b> is prepared as a table for associating each signal with a signal group (listing each signal name and its corresponding signal group name).

Here, assume that the signals <b>804</b> and <b>805</b> belong to a signal group grpA and the signals <b>806</b> and <b>807</b> belong to a signal group grpB. Further, the neighboring wire restriction information <b>810</b> and the wiring length restriction information <b>811</b> indicate, for example, that the signal groups grpA and grpB should be spaced 1.27 mm or more apart, the wiring length tolerance of each signal wire in the signal group grpA is <img file="US7143385B2_D0001.tif" /> 3 mm, and the wiring length restriction on the signal group grpA is 50 mm or less.

The wiring design system receives the net information file <b>801</b>, the signal group information file <b>809</b>, and the wiring restriction information file <b>812</b> which contain information on the wiring board <b>808</b>.

Based on the neighboring wire restriction information <b>810</b>, the wiring design system <b>400</b> generates wiring paths <b>813</b> and <b>814</b> which meet the restrictions on the wiring distances between neighboring signal groups. Then, the wiring design system <b>400</b> searches for a wiring path for each signal in each signal group based on the wiring paths <b>813</b> and <b>814</b> for the signal groups, generating the wiring paths <b>815</b> and <b>816</b> (which belong to the wiring path <b>813</b>) and the wiring paths <b>817</b> and <b>818</b> (which belong to the wiring path <b>814</b>) such that that these generated wiring paths satisfy the neighboring wire restriction information <b>810</b> and the wiring length restriction information <b>811</b>.

After that, the wiring design system <b>400</b> outputs a congestion degree evaluation file <b>819</b> and a wiring path information file <b>820</b>.

A third embodiment of the present invention will be described below with reference to <figref idref="DRAWINGS">FIG. 9</figref>.

<figref idref="DRAWINGS">FIG. 9</figref> is a schematic diagram illustrating processing flow in a wiring design system according to the third embodiment of the present invention.

The present embodiment first generates “temporary wiring” based on temporary information and then changes it into “actual wiring”. The present embodiment is advantageous when it takes a long time to determine a final parts layout, wiring, etc. on a wiring board.

That is, the wiring design system receives rough information about the wiring board, connections between the parts, and the pin assignments and the layout of parts on the wiring board, and then determines a temporary optimum parts layout and temporary optimum wiring at this point based on the rough information. After that, the wiring design system breaks down the arrangement using detailed information obtained from the temporary optimum parts layout and temporary optimum wiring described above so as to generate a detailed parts layout and detailed wiring.

According to the present embodiment, “temporary information” files for wiring design are input to the wiring design system <b>400</b>.

A temporary wiring board information file <b>901</b> roughly defines the size of the wiring board. A reserved area information file <b>902</b> specifies regions reserved for logic circuit parts, etc. on the wiring board.

A temporary parts information file <b>903</b> contains information on temporary parts which are used to prepare information on the number and the positions of the pins of each actual part to be mounted on the wiring board. The temporary net information file <b>904</b> contains information roughly indicating the numbers of connections between parts, that is, connection information before information on the pins is taken into account. A temporary layout information file <b>905</b> roughly defines the layout position of each part.

The wiring design system <b>400</b> generates a temporary optimum wiring design based on the input rough information. Then, the wiring design system <b>400</b> outputs a congestion degree evaluation file <b>915</b>, a wiring path information file <b>916</b>, and a layout information file <b>917</b> as a result of evaluating the degree of wiring congestion.

Thus, the above temporary information files are input to the wiring design system <b>400</b>. This allows the wiring design system <b>400</b> to obtain information about a temporary part <b>906</b> (whose pin positions are only roughly specified on a temporary wiring board), a part <b>907</b> (which is an actual part), a reserved area <b>908</b>, a temporary part <b>906</b>, and signal groups <b>909</b>, <b>910</b>, and <b>911</b> set between the temporary part <b>906</b> and the actual part <b>907</b>.

It should be noted that “temporary part” refers to a part which has not been fully specified, while “actual part” refers to a part which has been fully specified.

As shown in the left-hand side of <figref idref="DRAWINGS">FIG. 9</figref>, the part <b>906</b> is a temporary part, as described above, and its size and the number and the positions of its pins have not been fully specified. The part <b>907</b> is an actual part, as described above. Furthermore, the reserved area <b>908</b> is set on the wiring board.

In this case, the wiring design system <b>400</b> searches for a wiring path on the assumption that all pins of the temporary part <b>906</b> are disposed at its center. In the path search processing, the wiring design system <b>400</b> generates wiring paths <b>912</b>, <b>913</b>, and <b>914</b> obtained as a result of avoiding passage through the reserved area <b>908</b> whenever possible. Further, when the wiring between the temporary part <b>906</b> and the actual part <b>907</b> is designed, it is assumed that the terminals of the temporary part <b>906</b> are disposed at its center.

Thus, the wiring design system <b>400</b> generates an appropriate parts layout and appropriate wiring paths based on the temporary information, producing a congestion degree evaluation file <b>915</b>, a wiring path information file <b>916</b>, and a layout information file <b>917</b>. As the design progresses, the wiring design system <b>400</b> generates actual information. The wiring design system <b>400</b> replaces the temporary information files with the corresponding actual information files such as an actual wiring board information file <b>918</b>, an actual parts information file <b>919</b>, an actual connection information file <b>920</b>, and an actual layout information file <b>922</b>, one after another, to increase the accuracy of the wiring design. Furthermore, the wiring design system <b>400</b> receives a path specification information file <b>921</b> created based on the wiring path information file <b>916</b> generated using the temporary information files. The wiring design system <b>400</b> also receives an actual layout information file <b>922</b> created based on the information in the layout information file <b>917</b>, actual wiring board information, and actual parts information.

The actual connection information file <b>920</b> contains wiring information including the actual pin positions of parts.

The actual layout information file <b>922</b> specifies actual parts layouts and corresponds to the reserved area information file <b>902</b> and the temporary layout information file <b>905</b>.

It should be noted that the path specification information file <b>921</b> specifies paths to be initially used for path search processing and is created based on wiring information generated using the temporary information.

The parts <b>923</b> and <b>907</b> and the parts <b>927</b> to <b>929</b> are mounted on the actual wiring board. Signal groups <b>924</b>, <b>925</b>, and <b>926</b> are set between the parts <b>923</b> and <b>907</b>, while signals groups <b>930</b> and <b>931</b> are set between the parts <b>927</b> and <b>928</b> and between the parts <b>928</b> and <b>929</b>.

The reserved area <b>908</b> has been replaced by the area in which the parts <b>927</b> to <b>929</b> are disposed. The wiring design system <b>400</b> searches for paths between the parts <b>923</b> and <b>907</b> using as recommended paths the wiring paths <b>912</b>, <b>913</b>, and <b>914</b> generated at the previous step. The wiring design system <b>400</b> also determine the positions of the pins of a part <b>932</b>, to which the recommended paths have not yet been connected.

The wiring design system <b>400</b> then designs (detailed) wiring using the results of wiring based on the temporary information, generating wiring paths <b>933</b>, <b>934</b>, and <b>935</b> obtained after determining the actual pin positions of the part.

The wiring design system <b>400</b> searches for appropriate paths for the new parts <b>927</b> to <b>929</b> and, as a result, generates wiring paths <b>936</b> and <b>937</b>.

After completing the wiring design, the wiring design system outputs a congestion degree evaluation file <b>938</b>, a wiring path information file <b>939</b>, and a layout information file <b>940</b>. Thus, the present embodiment makes it possible to roughly design wiring based on rough information and check it in the floor plan stage (early design stage) before generating detailed wiring. The rough wiring (temporary wiring) is effectively used to generate actual wiring on an actual wiring board.

A fourth embodiment of the present invention will be described below with reference to <figref idref="DRAWINGS">FIG. 10</figref>.

<figref idref="DRAWINGS">FIG. 10</figref> is a schematic diagram illustrating processing flow in a wiring design system according to the fourth embodiment of the present invention.

The present embodiment makes it possible to design wiring by considering information about capacitors and power cut lines on an electronic wiring board.

Assume, for example, that parts <b>1002</b>, <b>1003</b>, and <b>1004</b> are mounted on a wiring board <b>1009</b>. Between the parts <b>1002</b> and <b>1003</b> are disposed connection lines for one signal group defined as connection information <b>1005</b> and <b>1006</b> and connection lines for another signal group defined as connection information <b>1007</b> and <b>1008</b>.

A capacitor information file <b>1010</b> is also defined which contains information on the required number of capacitors for each voltage type for each part. For example, the part <b>1002</b> requires 6 capacitors of VG1 voltage type and 2 capacitors of VG2 voltage type.

Further, a table <b>1012</b> is defined which lists each signal and its voltage type. This table indicates, for example, that the signals <b>1005</b> and <b>1006</b> should be set in an area to which a voltage of VG1 type is supplied.

Still further, a power cut line information file <b>1011</b> is defined which contains rough information on power cut lines on the wiring board. A power cut line indicates a border between voltage types supplied to the wiring board.

The wiring design system <b>400</b> of the present embodiment receives net information <b>1001</b> specifying the wiring board, the capacitor information file <b>1010</b>, the power cut line information file <b>1011</b>, and the table <b>1012</b> for listing each signal and its voltage type.

The wiring design system <b>400</b> then arranges the required number of capacitors around each target part according to a rough power cut line by use of the capacitor information file <b>1010</b>. After that, the wiring design system <b>400</b> corrects the power cut line based on the capacitor arrangement, producing a power cut line <b>1014</b>. Then, wiring design system <b>400</b> determines wiring paths based on the resultant arrangement.

At that time, the wiring design system <b>400</b> generates signal wires above and below the power cut line such that they do not cross the power cut line. Then, the wiring design system <b>400</b> shifts and thereby corrects the power cut line again based on the congestion degree of the obtained wiring paths <b>1015</b>, <b>1016</b>, and <b>1017</b>. After that, the wiring design system <b>400</b> outputs a congestion degree evaluation file <b>1018</b>, a wiring path information file <b>1019</b>, and a corrected power cut line information file <b>1020</b>. Thus, the present embodiment can design the power supply portion, including capacitors and power cut lines, and the wiring portion at the same time, thereby completing the floor plan and the power design in a short period of time.

A fifth embodiment of the present invention will be described below with reference to <figref idref="DRAWINGS">FIG. 11</figref>.

<figref idref="DRAWINGS">FIG. 11</figref> is a schematic diagram illustrating processing flow in a wiring design system according to the fifth embodiment of the present invention.

The present embodiment changes the pin assignments of parts in wiring design.

Assume, for example, that parts <b>1102</b> and <b>1103</b> are mounted on a wiring board <b>1108</b>. Between the parts <b>1102</b> and <b>1103</b> are disposed connection lines for one signal group defined as connection information <b>1104</b> and <b>1105</b> and connection lines for another signal group defined as connection information <b>1106</b> and <b>1107</b>.

The wiring design system <b>400</b> of the present embodiment receives a net information file <b>1101</b> specifying the wiring board <b>1108</b> and performs path search processing. As a result, the wiring design system <b>400</b> generates wiring paths <b>1109</b> and <b>1110</b>, and then evaluates their lengths. In the evaluation, if there is a path whose wiring length and Manhattan length (the shortest path between parts formed using horizontal and vertical lines) considerably differ from each other, as shown in table <b>1111</b> (listing the results of evaluating the roundabout lengths), the wiring design system <b>400</b> reviews the pin assignments. It should be noted that the wiring design system <b>400</b> may employ another pin assignment evaluation method instead and if the evaluation result indicates that there is a problem with the wiring design, the wiring design system <b>400</b> may review the pin assignments.

In the example of <figref idref="DRAWINGS">FIG. 11</figref>, a signal group grpB has a very long roundabout length (7).

Therefore, the wiring design system <b>400</b> performs path search processing again after replacing the part <b>1002</b> by a part <b>1113</b> with new pin assignment <b>1114</b>. As a result, the wiring design system <b>400</b> generates wiring paths <b>1115</b> and <b>1116</b>, and then evaluates their lengths. In the evaluation, if there is no path whose wiring length and Manhattan length considerably differ from each other, as shown in the table <b>1118</b> (listing the results of evaluating the roundabout lengths), the wiring design system <b>400</b> ends the path search processing, outputting pin assignment change information <b>1119</b>, a congestion degree evaluation file <b>1120</b>, and a wiring path information file <b>1121</b>.

The present invention can provide a wiring design system and method which is advantageous when applied to wiring boards having various wiring restrictions, wherein the system and method shows a rough wiring plan at the floor plan stage so as complete a wiring design satisfying the wiring restrictions in a short period of time while evaluating the congestion degree of the wiring.